drivers/tty/serial/rk_serial.c

   1 /*\r
   2  * Driver for RK-UART controller.\r
   3  * Based on drivers/tty/serial/8250.c\r
   4  *\r
   5  * Copyright (C) 2011 Rochchip.\r
   6  *\r
   7  * This program is free software; you can redistribute it and/or modify\r
   8  * it under the terms of the GNU General Public License as published by\r
   9  * the Free Software Foundation; either version 2 of the License, or\r
  10 \r
  11  * (at your option) any later version.\r
  12  *\r
  13  * Author: hhb@rock-chips.com\r
  14  * Date: 2011.06.18\r
  15  */\r
  16 \r
  17 #ifndef CONFIG_SERIAL_RK_CONSOLE\r
  18 #if defined(CONFIG_SERIAL_RK29_CONSOLE)\r
  19 #define CONFIG_SERIAL_RK_CONSOLE\r
  20 #endif\r
  21 #endif\r
  22 \r
  23 #if defined(CONFIG_SERIAL_RK_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)\r
  24 #define SUPPORT_SYSRQ\r
  25 #endif\r
  26 \r
  27 #include <linux/module.h>\r
  28 #include <linux/ioport.h>\r
  29 #include <linux/init.h>\r
  30 #include <linux/console.h>\r
  31 #include <linux/sysrq.h>\r
  32 #include <linux/delay.h>\r
  33 #include <linux/platform_device.h>\r
  34 #include <linux/tty.h>\r
  35 #include <linux/ratelimit.h>\r
  36 #include <linux/tty_flip.h>\r
  37 #include <linux/serial_reg.h>\r
  38 #include <linux/serial_core.h>\r
  39 #include <linux/serial.h>\r
  40 #include <linux/nmi.h>\r
  41 #include <linux/mutex.h>\r
  42 #include <linux/slab.h>\r
  43 #include <linux/clk.h>\r
  44 #include <linux/timer.h>\r
  45 #include <linux/workqueue.h>\r
  46 #include <linux/dma-mapping.h>\r
  47 \r
  48 #include <asm/io.h>\r
  49 #include <asm/irq.h>\r
  50 \r
  51 /*\r
  52 *                        Driver Version Note\r
  53 *\r
  54 *v0.0 : this driver is 2.6.32 kernel driver;\r
  55 *v0.1 : this driver is 3.0.8 kernel driver;\r
  56 *v1.0 : 2012-08-09\r
  57 *               1.modify dma dirver;\r
  58 *               2.enable Programmable THRE Interrupt Mode, so we can just judge ((up->iir & 0x0f) == 0x02) when transmit\r
  59 *               3.reset uart and set it to loopback state to ensure setting baud rate sucessfully \r
  60 *v1.1 : 2012-08-23\r
  61 *               1. dma driver:make "when tx dma is only enable" work functionally  \r
  62 *v1.2 : 2012-08-28\r
  63 *               1. dma driver:serial rx use new dma interface  rk29_dma_enqueue_ring \r
  64 *v1.3 : 2012-12-14\r
  65 *               1. When enable Programmable THRE Interrupt Mode, in lsr register, only UART_LSR_TEMT means transmit empty, but\r
  66                  UART_LSR_THRE doesn't. So, the macro BOTH_EMPTY should be replaced with UART_LSR_TEMT.\r
  67 */\r
  68 #define VERSION_AND_TIME  "rk_serial.c v1.3 2012-12-14"\r
  69 \r
  70 #define PORT_RK         90\r
  71 #define UART_USR        0x1F    /* UART Status Register */\r
  72 #define UART_USR_BUSY (1)\r
  73 #define UART_IER_PTIME  0x80    /* Programmable THRE Interrupt Mode Enable */\r
  74 #define UART_LSR_RFE    0x80    /* receive fifo error */\r
  75 #define UART_SRR                0x22    /* software reset register */\r
  76 #define UART_RESET              0x01\r
  77 \r
  78 \r
  79 //#define BOTH_EMPTY    (UART_LSR_TEMT | UART_LSR_THRE)\r
  80 \r
  81 #define UART_NR 4   //uart port number\r
  82 \r
  83 \r
  84 /* configurate whether the port transmit-receive by DMA in menuconfig*/\r
  85 #define OPEN_DMA      1\r
  86 #define CLOSE_DMA     0\r
  87 \r
  88 #define TX_DMA (1)\r
  89 #define RX_DMA (2)\r
  90 \r
  91 #ifdef CONFIG_UART0_DMA_RK29 \r
  92 #define UART0_USE_DMA CONFIG_UART0_DMA_RK29\r
  93 #else\r
  94 #define UART0_USE_DMA CLOSE_DMA\r
  95 #endif\r
  96 #ifdef CONFIG_UART1_DMA_RK29\r
  97 #define UART1_USE_DMA CONFIG_UART1_DMA_RK29\r
  98 #else\r
  99 #define UART1_USE_DMA CLOSE_DMA\r
 100 #endif\r
 101 #ifdef CONFIG_UART2_DMA_RK29\r
 102 #define UART2_USE_DMA CONFIG_UART2_DMA_RK29\r
 103 #else\r
 104 #define UART2_USE_DMA CLOSE_DMA\r
 105 #endif\r
 106 #ifdef CONFIG_UART3_DMA_RK29\r
 107 #define UART3_USE_DMA CONFIG_UART3_DMA_RK29\r
 108 #else\r
 109 #define UART3_USE_DMA CLOSE_DMA\r
 110 #endif\r
 111 \r
 112 #define USE_TIMER    1           // use timer for dma transport\r
 113 #define POWER_MANEGEMENT 1\r
 114 #define RX_TIMEOUT              (3000*3)  //uint ms\r
 115 #define DMA_TX_TRRIGE_LEVEL 128\r
 116 #define SERIAL_CIRC_CNT_TO_END(xmit)   CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)\r
 117 \r
 118 \r
 119 #define USE_DMA (UART0_USE_DMA | UART1_USE_DMA | UART2_USE_DMA | UART3_USE_DMA)\r
 120 #if USE_DMA\r
 121 #ifdef CONFIG_ARCH_RK29\r
 122 #include <mach/dma-pl330.h>\r
 123 #else\r
 124 #include <plat/dma-pl330.h>\r
 125 #endif\r
 126 #endif\r
 127 \r
 128 \r
 129 \r
 130 static struct uart_driver serial_rk_reg;\r
 131 \r
 132 /*\r
 133  * Debugging.\r
 134  */\r
 135 #ifdef CONFIG_ARCH_RK29\r
 136 #define DBG_PORT 1   //DBG_PORT which uart is used to print log message\r
 137 #else\r
 138 #define DBG_PORT -1   //DBG_PORT which uart is used to print log message\r
 139 #endif\r
 140 #ifdef CONFIG_SERIAL_CORE_CONSOLE\r
 141 #define uart_console(port)      ((port)->cons && (port)->cons->index == (port)->line)\r
 142 #else\r
 143 #define uart_console(port)      (0)\r
 144 #endif\r
 145 \r
 146 \r
 147 extern void printascii(const char *);\r
 148 static void dbg(const char *fmt, ...)\r
 149 {\r
 150         va_list va;\r
 151         char buff[256];\r
 152 \r
 153         va_start(va, fmt);\r
 154         vsprintf(buff, fmt, va);\r
 155         va_end(va);\r
 156 \r
 157         printascii(buff);\r
 158 }\r
 159 \r
 160 //enable log output\r
 161 #define DEBUG 1\r
 162 static int log_port = -1;\r
 163 module_param(log_port, int, S_IRUGO|S_IWUSR);\r
 164 \r
 165 #if DEBUG\r
 166 #define DEBUG_INTR(fmt...)      if (up->port.line == log_port && !uart_console(&up->port)) dbg(fmt)\r
 167 #else\r
 168 #define DEBUG_INTR(fmt...)      do { } while (0)\r
 169 #endif\r
 170 \r
 171 \r
 172 #if USE_DMA\r
 173 /* added by hhb@rock-chips.com for uart dma transfer */\r
 174 \r
 175 struct rk_uart_dma {\r
 176         u32 use_dma;            //1:used\r
 177         enum dma_ch rx_dmach;\r
 178         enum dma_ch tx_dmach;\r
 179 \r
 180         //receive and transfer buffer\r
 181         char * rx_buffer;    //visual memory\r
 182         char * tx_buffer;\r
 183         dma_addr_t rx_phy_addr;  //physical memory\r
 184         dma_addr_t tx_phy_addr;\r
 185         u32 rb_size;             //buffer size\r
 186         u32 tb_size;\r
 187 \r
 188         //regard the rx buffer as a circular buffer\r
 189         u32 rb_head;\r
 190         u32 rb_tail;\r
 191         u32 rx_size;\r
 192 \r
 193         spinlock_t              tx_lock;\r
 194         spinlock_t              rx_lock;\r
 195 \r
 196         char tx_dma_inited;   //1:dma tx channel has been init\r
 197         char rx_dma_inited;      //1:dma rx channel has been init\r
 198         char tx_dma_used;        //1:dma tx is working\r
 199         char rx_dma_used;    //1:dma rx is working\r
 200 \r
 201         /* timer to poll activity on rx dma */\r
 202         char use_timer;\r
 203         int      rx_timeout;\r
 204         struct timer_list rx_timer;\r
 205 };\r
 206 #endif\r
 207 \r
 208 struct uart_rk_port {\r
 209         struct uart_port        port;\r
 210         struct platform_device  *pdev;\r
 211         struct clk              *clk;\r
 212         struct clk              *pclk;\r
 213         unsigned int            tx_loadsz;      /* transmit fifo load size */\r
 214         unsigned char           ier;\r
 215         unsigned char           lcr;\r
 216         unsigned char           mcr;\r
 217         unsigned char           iir;\r
 218         unsigned char           fcr;\r
 219         /*\r
 220          * Some bits in registers are cleared on a read, so they must\r
 221          * be saved whenever the register is read but the bits will not\r
 222          * be immediately processed.\r
 223          */\r
 224 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS\r
 225         unsigned char           lsr_saved_flags;\r
 226 #if 0\r
 227 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA\r
 228         unsigned char           msr_saved_flags;\r
 229 #endif\r
 230 \r
 231         char                    name[12];\r
 232         char                    fifo[64];\r
 233         char                    fifo_size;\r
 234         unsigned long           port_activity;\r
 235         struct work_struct uart_work;\r
 236         struct work_struct uart_work_rx;\r
 237         struct workqueue_struct *uart_wq;\r
 238 #if USE_DMA\r
 239         struct rk_uart_dma *dma;\r
 240 #endif\r
 241 };\r
 242 \r
 243 #if USE_DMA\r
 244 static void serial_rk_release_dma_tx(struct uart_port *port);\r
 245 static int serial_rk_start_tx_dma(struct uart_port *port);\r
 246 //static void serial_rk_rx_timeout(unsigned long uart);\r
 247 static void serial_rk_release_dma_rx(struct uart_port *port);\r
 248 static int serial_rk_start_rx_dma(struct uart_port *port);\r
 249 #else\r
 250 static inline int serial_rk_start_tx_dma(struct uart_port *port) { return 0; }\r
 251 #endif\r
 252 static int serial_rk_startup(struct uart_port *port);\r
 253 \r
 254 static inline unsigned int serial_in(struct uart_rk_port *up, int offset)\r
 255 {\r
 256         offset = offset << 2;\r
 257         return __raw_readb(up->port.membase + offset);\r
 258 }\r
 259 \r
 260 /* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */\r
 261 static inline void dwapb_save_out_value(struct uart_rk_port *up, int offset,\r
 262                                         unsigned char value)\r
 263 {\r
 264         if (offset == UART_LCR)\r
 265                 up->lcr = value;\r
 266 }\r
 267 \r
 268 /* Read the IER to ensure any interrupt is cleared before returning from ISR. */\r
 269 static inline void dwapb_check_clear_ier(struct uart_rk_port *up, int offset)\r
 270 {\r
 271         if (offset == UART_TX || offset == UART_IER)\r
 272                 serial_in(up, UART_IER);\r
 273 }\r
 274 \r
 275 static inline void serial_out(struct uart_rk_port *up, int offset, unsigned char value)\r
 276 {\r
 277         dwapb_save_out_value(up, offset, value);\r
 278         __raw_writeb(value, up->port.membase + (offset << 2));\r
 279         if (offset != UART_TX)\r
 280                 dsb();\r
 281         dwapb_check_clear_ier(up, offset);\r
 282 }\r
 283 \r
 284 /* Uart divisor latch read */\r
 285 static inline int serial_dl_read(struct uart_rk_port *up)\r
 286 {\r
 287         return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;\r
 288 }\r
 289 \r
 290 /* Uart divisor latch write */\r
 291 static int serial_dl_write(struct uart_rk_port *up, unsigned int value)\r
 292 {\r
 293         unsigned int tmout = 100;\r
 294 \r
 295         while(!(serial_in(up, UART_LCR) & UART_LCR_DLAB)){\r
 296                 if (--tmout == 0){\r
 297                         if(up->port.line != DBG_PORT)\r
 298                                 dbg("set serial.%d baudrate fail with DLAB not set\n", up->port.line);\r
 299                         return -1;\r
 300                 }\r
 301         }\r
 302 \r
 303         tmout = 15000;\r
 304         while(serial_in(up, UART_USR) & UART_USR_BUSY){\r
 305                 if (--tmout == 0){\r
 306                         if(up->port.line != DBG_PORT)\r
 307                                 dbg("set serial.%d baudrate timeout\n", up->port.line);\r
 308                         return -1;\r
 309                 }\r
 310                 udelay(1);\r
 311         }\r
 312 \r
 313         serial_out(up, UART_DLL, value & 0xff);\r
 314         serial_out(up, UART_DLM, value >> 8 & 0xff);\r
 315 \r
 316         return 0;\r
 317 \r
 318 }\r
 319 \r
 320 static int serial_lcr_write(struct uart_rk_port *up, unsigned char value)\r
 321 {\r
 322         unsigned int tmout = 15000;\r
 323 \r
 324         while(serial_in(up, UART_USR) & UART_USR_BUSY){\r
 325                 if (--tmout == 0){\r
 326                         if(up->port.line != DBG_PORT)\r
 327                                 dbg("set serial.%d lc r = 0x%02x timeout\n", up->port.line, value);\r
 328                         return -1;\r
 329                 }\r
 330                 udelay(1);\r
 331         }\r
 332 \r
 333         serial_out(up, UART_LCR, value);\r
 334 \r
 335         return 0;\r
 336 }\r
 337 \r
 338 static inline void serial_rk_enable_ier_thri(struct uart_rk_port *up)\r
 339 {\r
 340         if (!(up->ier & UART_IER_THRI)) {\r
 341                 up->ier |= UART_IER_THRI;\r
 342                 serial_out(up, UART_IER, up->ier);\r
 343         }\r
 344 }\r
 345 \r
 346 \r
 347 static inline void serial_rk_disable_ier_thri(struct uart_rk_port *up)\r
 348 {\r
 349         if (up->ier & UART_IER_THRI) {\r
 350                 up->ier &= ~UART_IER_THRI;\r
 351                 serial_out(up, UART_IER, up->ier);\r
 352         }\r
 353 }\r
 354 \r
 355 static int rk29_uart_dump_register(struct uart_rk_port *up){\r
 356 \r
 357         unsigned int reg_value = 0;\r
 358 \r
 359         reg_value = serial_in(up, UART_IER);\r
 360         dbg("UART_IER = 0x%0x\n", reg_value);\r
 361         reg_value = serial_in(up, UART_IIR);\r
 362         dbg("UART_IIR = 0x%0x\n", reg_value);\r
 363     reg_value = serial_in(up, UART_LSR);\r
 364     dbg("UART_LSR = 0x%0x\n", reg_value);\r
 365     reg_value = serial_in(up, UART_MSR);\r
 366     dbg("UART_MSR = 0x%0x\n", reg_value);\r
 367     reg_value = serial_in(up, UART_MCR);\r
 368     dbg("UART_MCR = 0x%0x\n", reg_value);\r
 369     reg_value = serial_in(up, 0x21);\r
 370     dbg("UART_RFL = 0x%0x\n", reg_value);\r
 371     reg_value = serial_in(up, UART_LCR);\r
 372     dbg("UART_LCR = 0x%0x\n", reg_value);\r
 373         return 0;\r
 374 \r
 375 }\r
 376 \r
 377 /*\r
 378  * FIFO support.\r
 379  */\r
 380 static void serial_rk_clear_fifos(struct uart_rk_port *up)\r
 381 {\r
 382         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);\r
 383         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |\r
 384                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);\r
 385         serial_out(up, UART_FCR, 0);\r
 386 }\r
 387 \r
 388 static inline void __stop_tx(struct uart_rk_port *p)\r
 389 {\r
 390         if (p->ier & UART_IER_THRI) {\r
 391                 p->ier &= ~UART_IER_THRI;\r
 392                 serial_out(p, UART_IER, p->ier);\r
 393         }\r
 394 }\r
 395 \r
 396 static void serial_rk_stop_tx(struct uart_port *port)\r
 397 {\r
 398         struct uart_rk_port *up =\r
 399                 container_of(port, struct uart_rk_port, port);\r
 400 #if USE_DMA\r
 401         struct rk_uart_dma *uart_dma = up->dma;\r
 402         if(uart_dma->use_dma & TX_DMA){\r
 403                 serial_rk_release_dma_tx(port);\r
 404         }\r
 405 #endif\r
 406         __stop_tx(up);\r
 407 \r
 408 }\r
 409 \r
 410 \r
 411 static void serial_rk_start_tx(struct uart_port *port)\r
 412 {\r
 413         struct uart_rk_port *up =\r
 414                 container_of(port, struct uart_rk_port, port);\r
 415 \r
 416 #if USE_DMA\r
 417         if(up->dma->use_dma & TX_DMA) {\r
 418                 if(!up->dma->tx_dma_used)\r
 419                         serial_rk_enable_ier_thri(up);\r
 420         }else {\r
 421                 serial_rk_enable_ier_thri(up);\r
 422         }\r
 423 #else\r
 424         serial_rk_enable_ier_thri(up);\r
 425 #endif\r
 426 }\r
 427 \r
 428 \r
 429 static void serial_rk_stop_rx(struct uart_port *port)\r
 430 {\r
 431         struct uart_rk_port *up =\r
 432                 container_of(port, struct uart_rk_port, port);\r
 433 #if USE_DMA\r
 434         struct rk_uart_dma *uart_dma = up->dma;\r
 435         if(uart_dma->use_dma & RX_DMA){\r
 436                 serial_rk_release_dma_rx(port);\r
 437         }\r
 438 #endif\r
 439         up->ier &= ~UART_IER_RLSI;\r
 440         up->port.read_status_mask &= ~UART_LSR_DR;\r
 441         serial_out(up, UART_IER, up->ier);\r
 442 }\r
 443 \r
 444 \r
 445 static void serial_rk_enable_ms(struct uart_port *port)\r
 446 {\r
 447         /* no MSR capabilities */\r
 448 #if 0\r
 449         struct uart_rk_port *up =\r
 450                 container_of(port, struct uart_rk_port, port);\r
 451 \r
 452         dev_dbg(port->dev, "%s\n", __func__);\r
 453         up->ier |= UART_IER_MSI;\r
 454         serial_out(up, UART_IER, up->ier);\r
 455 #endif\r
 456 }\r
 457 \r
 458 \r
 459 #if USE_DMA\r
 460 /*\r
 461  * Start transmitting by dma.\r
 462  */\r
 463 #define DMA_SERIAL_BUFFER_SIZE     UART_XMIT_SIZE\r
 464 \r
 465 /* added by hhb@rock-chips.com  for uart dma transfer*/\r
 466 static struct rk_uart_dma rk29_uart_ports_dma[] = {\r
 467                 {UART0_USE_DMA, DMACH_UART0_RX, DMACH_UART0_TX},\r
 468                 {UART1_USE_DMA, DMACH_UART1_RX, DMACH_UART1_TX},\r
 469                 {UART2_USE_DMA, DMACH_UART2_RX, DMACH_UART2_TX},\r
 470                 {UART3_USE_DMA, DMACH_UART3_RX, DMACH_UART3_TX},\r
 471 };\r
 472 \r
 473 \r
 474 /* DMAC PL330 add by hhb@rock-chips.com */\r
 475 static struct rk29_dma_client rk29_uart_dma_client = {\r
 476         .name = "rk-uart-dma",\r
 477 };\r
 478 \r
 479 /*TX*/\r
 480 \r
 481 static void serial_rk_release_dma_tx(struct uart_port *port)\r
 482 {\r
 483         struct uart_rk_port *up =\r
 484                         container_of(port, struct uart_rk_port, port);\r
 485         struct rk_uart_dma *uart_dma = up->dma;\r
 486         if(!port){\r
 487                 return;\r
 488         }\r
 489         if(uart_dma && uart_dma->tx_dma_inited) {\r
 490                 rk29_dma_free(uart_dma->tx_dmach, &rk29_uart_dma_client);\r
 491                 uart_dma->tx_dma_inited = 0;\r
 492                 uart_dma->tx_dma_used = 0;\r
 493         }\r
 494 }\r
 495 \r
 496 /*this function will be called every time after rk29_dma_enqueue() be invoked*/\r
 497 static void serial_rk_dma_txcb(void *buf, int size, enum rk29_dma_buffresult result) {\r
 498         struct uart_port *port = buf;\r
 499         struct uart_rk_port *up = container_of(port, struct uart_rk_port, port);\r
 500         struct circ_buf *xmit = &port->state->xmit;\r
 501 \r
 502         if(result != RK29_RES_OK){\r
 503                 printk(">>>>%s:%d result:%d\n", __func__, __LINE__, result);\r
 504                 up->dma->tx_dma_used = 0;\r
 505                 return;\r
 506         }\r
 507 \r
 508         //spin_lock(&(up->dma->rx_lock));\r
 509         xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);\r
 510         port->icount.tx += size;\r
 511         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)\r
 512                 uart_write_wakeup(&up->port);\r
 513 \r
 514         //spin_lock(&(up->dma->tx_lock));\r
 515         up->dma->tx_dma_used = 0;\r
 516         //spin_unlock(&(up->dma->tx_lock));\r
 517         serial_rk_enable_ier_thri(up);\r
 518         up->port_activity = jiffies;\r
 519 //      dev_info(up->port.dev, "s:%d\n", size);\r
 520 }\r
 521 \r
 522 static int serial_rk_init_dma_tx(struct uart_port *port) {\r
 523 \r
 524         struct uart_rk_port *up =\r
 525                                 container_of(port, struct uart_rk_port, port);\r
 526         struct rk_uart_dma *uart_dma = up->dma;\r
 527 \r
 528         if(!port || !uart_dma){\r
 529                 dev_info(up->port.dev, "serial_rk_init_dma_tx fail\n");\r
 530                 return -1;\r
 531         }\r
 532 \r
 533         if(uart_dma->tx_dma_inited) {\r
 534                 return 0;\r
 535         }\r
 536 \r
 537         if (rk29_dma_request(uart_dma->tx_dmach, &rk29_uart_dma_client, NULL) == -EBUSY) {\r
 538                 dev_info(up->port.dev, "rk29_dma_request tx fail\n");\r
 539                 return -1;\r
 540         }\r
 541 \r
 542         if (rk29_dma_set_buffdone_fn(uart_dma->tx_dmach, serial_rk_dma_txcb)) {\r
 543                 dev_info(up->port.dev, "rk29_dma_set_buffdone_fn tx fail\n");\r
 544                 return -1;\r
 545         }\r
 546         \r
 547         if (rk29_dma_devconfig(uart_dma->tx_dmach, RK29_DMASRC_MEM, (unsigned long)(port->iobase + UART_TX))) {\r
 548                 dev_info(up->port.dev, "rk29_dma_devconfig tx fail\n");\r
 549                 return -1;\r
 550         }\r
 551         \r
 552         if (rk29_dma_config(uart_dma->tx_dmach, 1, 16)) {\r
 553                 dev_info(up->port.dev, "rk29_dma_config tx fail\n");\r
 554                 return -1;\r
 555         }\r
 556 \r
 557         uart_dma->tx_dma_inited = 1;\r
 558         dev_info(up->port.dev, "serial_rk_init_dma_tx sucess\n");\r
 559         return 0;\r
 560 \r
 561 }\r
 562 \r
 563 static int serial_rk_start_tx_dma(struct uart_port *port)\r
 564 {\r
 565         int count = 0;\r
 566         struct circ_buf *xmit = &port->state->xmit;\r
 567         struct uart_rk_port *up = container_of(port, struct uart_rk_port, port);\r
 568         struct rk_uart_dma *uart_dma = up->dma;\r
 569 \r
 570         if(!uart_dma->use_dma)\r
 571                 goto err_out;\r
 572 \r
 573         if(-1 == serial_rk_init_dma_tx(port))\r
 574                 goto err_out;\r
 575 \r
 576         if (1 == uart_dma->tx_dma_used)\r
 577                 return 1;\r
 578 \r
 579 //      spin_lock(&(uart_dma->tx_lock));\r
 580         __stop_tx(up);\r
 581 \r
 582         count = SERIAL_CIRC_CNT_TO_END(xmit);\r
 583         count -= count%16;\r
 584         if(count >= DMA_TX_TRRIGE_LEVEL) {\r
 585                 if (rk29_dma_enqueue(uart_dma->tx_dmach, port, uart_dma->tx_phy_addr + xmit->tail , count)) {\r
 586                         goto err_out;\r
 587                 }\r
 588                 rk29_dma_ctrl(uart_dma->tx_dmach, RK29_DMAOP_START);\r
 589                 up->dma->tx_dma_used = 1;\r
 590         }\r
 591 //      spin_unlock(&(uart_dma->tx_lock));\r
 592         return 1;\r
 593 err_out:\r
 594         dev_info(up->port.dev, "-serial_rk_start_tx_dma-error-\n");\r
 595         return -1;\r
 596 }\r
 597 \r
 598 \r
 599 \r
 600 /*RX*/\r
 601 static void serial_rk_dma_rxcb(void *buf, int size, enum rk29_dma_buffresult result) {\r
 602 \r
 603         //printk(">>%s:%d\n", __func__, result);\r
 604 }\r
 605 \r
 606 static void serial_rk_release_dma_rx(struct uart_port *port)\r
 607 {\r
 608         struct uart_rk_port *up =\r
 609                                 container_of(port, struct uart_rk_port, port);\r
 610         struct rk_uart_dma *uart_dma = up->dma;\r
 611         \r
 612         if(!port){\r
 613                 return;\r
 614         }\r
 615         \r
 616         if(uart_dma && uart_dma->rx_dma_inited) {\r
 617                 del_timer(&uart_dma->rx_timer);\r
 618                 rk29_dma_free(uart_dma->rx_dmach, &rk29_uart_dma_client);\r
 619                 uart_dma->rb_tail = 0;\r
 620                 uart_dma->rx_dma_inited = 0;\r
 621                 uart_dma->rx_dma_used = 0;\r
 622         }\r
 623 }\r
 624 \r
 625 \r
 626 static int serial_rk_init_dma_rx(struct uart_port *port) {\r
 627 \r
 628         struct uart_rk_port *up =\r
 629                                 container_of(port, struct uart_rk_port, port);\r
 630         struct rk_uart_dma *uart_dma = up->dma;\r
 631 \r
 632         if(!port || !uart_dma){\r
 633                 dev_info(up->port.dev, "serial_rk_init_dma_rx: port fail\n");\r
 634                 return -1;\r
 635         }\r
 636 \r
 637         if(uart_dma->rx_dma_inited) {\r
 638                 return 0;\r
 639         }\r
 640 \r
 641         if (rk29_dma_request(uart_dma->rx_dmach, &rk29_uart_dma_client, NULL) == -EBUSY) {\r
 642                 dev_info(up->port.dev, "rk29_dma_request fail rx \n");\r
 643                 return -1;\r
 644         }\r
 645 \r
 646         if (rk29_dma_set_buffdone_fn(uart_dma->rx_dmach, serial_rk_dma_rxcb)) {\r
 647                 dev_info(up->port.dev, "rk29_dma_set_buffdone_fn rx fail\n");\r
 648                 return -1;\r
 649         }\r
 650 \r
 651         if (rk29_dma_devconfig(uart_dma->rx_dmach, RK29_DMASRC_HW, (unsigned long)(port->iobase + UART_RX))) {\r
 652                 dev_info(up->port.dev, "rk29_dma_devconfig rx fail\n");\r
 653                 return -1;\r
 654         }\r
 655 \r
 656         if (rk29_dma_config(uart_dma->rx_dmach, 1, 1)) {\r
 657                 dev_info(up->port.dev, "rk29_dma_config rx fail 1 1 \n");\r
 658                 return -1;\r
 659         }\r
 660 \r
 661         //rk29_dma_setflags(uart_dma->rx_dmach, RK29_DMAF_CIRCULAR);\r
 662 \r
 663         uart_dma->rx_dma_inited = 1;\r
 664         dev_info(up->port.dev, "serial_rk_init_dma_rx sucess\n");\r
 665         return 0;\r
 666 \r
 667 }\r
 668 \r
 669 static int serial_rk_start_rx_dma(struct uart_port *port)\r
 670 {\r
 671         struct uart_rk_port *up =\r
 672                                 container_of(port, struct uart_rk_port, port);\r
 673         struct rk_uart_dma *uart_dma = up->dma;\r
 674         if(!uart_dma->use_dma)\r
 675                 return 0;\r
 676 \r
 677         if(uart_dma->rx_dma_used == 1)\r
 678                 return 0;\r
 679 \r
 680         if(-1 == serial_rk_init_dma_rx(port)){\r
 681                 dev_info(up->port.dev, "*******serial_rk_init_dma_rx*******error*******\n");\r
 682                 return -1;\r
 683         }\r
 684         \r
 685 #if 0   \r
 686                 if (rk29_dma_enqueue(uart_dma->rx_dmach, (void *)up, uart_dma->rx_phy_addr,\r
 687                                 uart_dma->rb_size/2)) {\r
 688                         dev_info(up->port.dev, "*******rk29_dma_enqueue fail*****\n");\r
 689                         return -1;\r
 690                 }\r
 691 \r
 692                 if (rk29_dma_enqueue(uart_dma->rx_dmach, (void *)up,\r
 693                                 uart_dma->rx_phy_addr+uart_dma->rb_size/2, uart_dma->rb_size/2)) {\r
 694                         dev_info(up->port.dev, "*******rk29_dma_enqueue fail*****\n");\r
 695                         return -1;\r
 696                 }\r
 697 \r
 698 #else\r
 699         rk29_dma_enqueue_ring(uart_dma->rx_dmach, (void *)up, uart_dma->rx_phy_addr, uart_dma->rb_size/4, 4, false);\r
 700 #endif\r
 701         rk29_dma_ctrl(uart_dma->rx_dmach, RK29_DMAOP_START);\r
 702         uart_dma->rx_dma_used = 1;\r
 703         if(uart_dma->use_timer == 1){\r
 704                 mod_timer(&uart_dma->rx_timer, jiffies + msecs_to_jiffies(uart_dma->rx_timeout));\r
 705         }\r
 706         up->port_activity = jiffies;\r
 707         return 1;\r
 708 }\r
 709 \r
 710 static void serial_rk_update_rb_addr(struct uart_rk_port *up){\r
 711         dma_addr_t current_pos = 0;\r
 712         dma_addr_t rx_current_pos = 0;\r
 713         struct rk_uart_dma *uart_dma = up->dma;\r
 714         //spin_lock(&(up->dma->rx_lock));\r
 715         uart_dma->rx_size = 0;\r
 716         if(uart_dma->rx_dma_used == 1){\r
 717                 rk29_dma_getposition(uart_dma->rx_dmach, &current_pos, &rx_current_pos);\r
 718                 uart_dma->rb_head = (rx_current_pos - uart_dma->rx_phy_addr);\r
 719                 uart_dma->rx_size = CIRC_CNT(uart_dma->rb_head, uart_dma->rb_tail, uart_dma->rb_size);\r
 720         }\r
 721         //spin_unlock(&(up->dma->rx_lock));\r
 722 }\r
 723 \r
 724 static void serial_rk_report_dma_rx(unsigned long uart)\r
 725 {\r
 726         int count, flip = 0;\r
 727         struct uart_rk_port *up = (struct uart_rk_port *)uart;\r
 728         struct rk_uart_dma *uart_dma = up->dma;\r
 729 \r
 730         if(!uart_dma->rx_dma_used || !up->port.state->port.tty)\r
 731                 return;\r
 732 \r
 733         serial_rk_update_rb_addr(up);\r
 734 \r
 735         while(1) {\r
 736                 count = CIRC_CNT_TO_END(uart_dma->rb_head, uart_dma->rb_tail, uart_dma->rb_size);\r
 737                 if(count <= 0)\r
 738                         break;\r
 739                 up->port.icount.rx += count;\r
 740                 flip = tty_insert_flip_string(up->port.state->port.tty, uart_dma->rx_buffer\r
 741                                 + uart_dma->rb_tail, count);\r
 742                 tty_flip_buffer_push(up->port.state->port.tty);\r
 743                 uart_dma->rb_tail = (uart_dma->rb_tail + count) & (uart_dma->rb_size - 1);\r
 744                 up->port_activity = jiffies;\r
 745         }\r
 746 \r
 747         //if (uart_dma->rx_size > 0)\r
 748         //      printk("rx_size:%d ADDR:%x\n", uart_dma->rx_size, uart_dma->rb_head);\r
 749 \r
 750         if(uart_dma->use_timer == 1){\r
 751                 mod_timer(&uart_dma->rx_timer, jiffies + msecs_to_jiffies(uart_dma->rx_timeout));\r
 752         }\r
 753 \r
 754 }\r
 755 #if 0\r
 756 static void serial_rk_rx_timeout(unsigned long uart)\r
 757 {\r
 758         struct uart_rk_port *up = (struct uart_rk_port *)uart;\r
 759 \r
 760         serial_rk_report_dma_rx(up);\r
 761         //queue_work(up->uart_wq, &up->uart_work);\r
 762 }\r
 763 \r
 764 static void serial_rk_report_revdata_workfunc(struct work_struct *work)\r
 765 {\r
 766         struct uart_rk_port *up =\r
 767                                 container_of(work, struct uart_rk_port, uart_work);\r
 768 \r
 769         serial_rk_report_dma_rx((unsigned long)up);\r
 770 \r
 771         //spin_lock(&(up->dma->rx_lock));\r
 772 \r
 773         if(up->port.state->port.tty && up->dma->use_timer != 1 && up->fifo_size > 0){\r
 774 \r
 775                 tty_insert_flip_string(up->port.state->port.tty, up->fifo, up->fifo_size);\r
 776                 tty_flip_buffer_push(up->port.state->port.tty);\r
 777                 up->port.icount.rx += up->fifo_size;\r
 778                 up->ier |= UART_IER_RDI;\r
 779                 serial_out(up, UART_IER, up->ier);\r
 780         }\r
 781 \r
 782         //spin_unlock(&(up->dma->rx_lock));\r
 783 \r
 784 }\r
 785 \r
 786 \r
 787 static void serial_rk_start_dma_rx(struct work_struct *work)\r
 788 {\r
 789         struct uart_rk_port *up =\r
 790                                         container_of(work, struct uart_rk_port, uart_work_rx);\r
 791 \r
 792         //mod_timer(&up->dma->rx_timer, jiffies + msecs_to_jiffies(up->dma->rx_timeout));\r
 793         //rk29_dma_ctrl(up->dma->rx_dmach, RK29_DMAOP_START);\r
 794         //serial_rk_start_rx_dma(&up->port);\r
 795 \r
 796 }\r
 797 #endif\r
 798 \r
 799 #endif /* USE_DMA */\r
 800 \r
 801 \r
 802 static void\r
 803 receive_chars(struct uart_rk_port *up, unsigned int *status)\r
 804 {\r
 805         struct tty_struct *tty = up->port.state->port.tty;\r
 806         unsigned char ch, lsr = *status;\r
 807         int max_count = 256;\r
 808         char flag;\r
 809 \r
 810         do {\r
 811                 if (likely(lsr & UART_LSR_DR)){\r
 812                         ch = serial_in(up, UART_RX);\r
 813                 }\r
 814                 else\r
 815                         /*\r
 816                          * Intel 82571 has a Serial Over Lan device that will\r
 817                          * set UART_LSR_BI without setting UART_LSR_DR when\r
 818                          * it receives a break. To avoid reading from the\r
 819                          * receive buffer without UART_LSR_DR bit set, we\r
 820                          * just force the read character to be 0\r
 821                          */\r
 822                         ch = 0;\r
 823 \r
 824                 flag = TTY_NORMAL;\r
 825                 up->port.icount.rx++;\r
 826 \r
 827                 lsr |= up->lsr_saved_flags;\r
 828                 up->lsr_saved_flags = 0;\r
 829 \r
 830                 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {\r
 831                         /*\r
 832                          * For statistics only\r
 833                          */\r
 834                         if (lsr & UART_LSR_BI) {\r
 835                                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);\r
 836                                 up->port.icount.brk++;\r
 837                                 /*\r
 838                                  * We do the SysRQ and SAK checking\r
 839                                  * here because otherwise the break\r
 840                                  * may get masked by ignore_status_mask\r
 841                                  * or read_status_mask.\r
 842                                  */\r
 843                                 if (uart_handle_break(&up->port))\r
 844                                         goto ignore_char;\r
 845                         } else if (lsr & UART_LSR_PE)\r
 846                                 up->port.icount.parity++;\r
 847                         else if (lsr & UART_LSR_FE)\r
 848                                 up->port.icount.frame++;\r
 849                         if (lsr & UART_LSR_OE)\r
 850                                 up->port.icount.overrun++;\r
 851 \r
 852 \r
 853                         /*\r
 854                          * Mask off conditions which should be ignored.\r
 855                          */\r
 856                         lsr &= up->port.read_status_mask;\r
 857 \r
 858                         if (lsr & UART_LSR_BI) {\r
 859                                 DEBUG_INTR("handling break....");\r
 860                                 flag = TTY_BREAK;\r
 861                         } else if (lsr & UART_LSR_PE)\r
 862                                 flag = TTY_PARITY;\r
 863                         else if (lsr & UART_LSR_FE)\r
 864                                 flag = TTY_FRAME;\r
 865                 }\r
 866                 if (uart_handle_sysrq_char(&up->port, ch))\r
 867                         goto ignore_char;\r
 868 \r
 869                 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);\r
 870 \r
 871 ignore_char:\r
 872                 lsr = serial_in(up, UART_LSR);\r
 873         } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));\r
 874         spin_unlock(&up->port.lock);\r
 875         tty_flip_buffer_push(tty);\r
 876         spin_lock(&up->port.lock);\r
 877         *status = lsr;\r
 878 }\r
 879 \r
 880 static void transmit_chars(struct uart_rk_port *up)\r
 881 {\r
 882         struct circ_buf *xmit = &up->port.state->xmit;\r
 883         int count;\r
 884 \r
 885         if (up->port.x_char) {\r
 886                 serial_out(up, UART_TX, up->port.x_char);\r
 887                 up->port.icount.tx++;\r
 888                 up->port.x_char = 0;\r
 889                 return;\r
 890         }\r
 891         if (uart_tx_stopped(&up->port)) {\r
 892                 __stop_tx(up);\r
 893                 return;\r
 894         }\r
 895         if (uart_circ_empty(xmit)) {\r
 896                 __stop_tx(up);\r
 897                 return;\r
 898         }\r
 899 #if USE_DMA\r
 900         //hhb\r
 901         if(up->dma->use_dma & TX_DMA){\r
 902                 if(SERIAL_CIRC_CNT_TO_END(xmit) >= DMA_TX_TRRIGE_LEVEL){\r
 903                         serial_rk_start_tx_dma(&up->port);\r
 904                         return;\r
 905                 }\r
 906         }\r
 907 #endif\r
 908         count = up->port.fifosize - serial_in(up , 0x20);\r
 909         do {\r
 910                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);\r
 911                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);\r
 912                 up->port.icount.tx++;\r
 913                 if (uart_circ_empty(xmit))\r
 914                         break;\r
 915         } while (--count > 0);\r
 916 \r
 917         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)\r
 918                 uart_write_wakeup(&up->port);\r
 919 \r
 920         DEBUG_INTR("THRE...");\r
 921 #if USE_DMA\r
 922         up->port_activity = jiffies;\r
 923 #endif\r
 924         if (uart_circ_empty(xmit))\r
 925                 __stop_tx(up);\r
 926 }\r
 927 \r
 928 static unsigned int check_modem_status(struct uart_rk_port *up)\r
 929 {\r
 930         unsigned int status = serial_in(up, UART_MSR);\r
 931 \r
 932 #if 0\r
 933         status |= up->msr_saved_flags;\r
 934         up->msr_saved_flags = 0;\r
 935         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&\r
 936             up->port.state != NULL) {\r
 937                 if (status & UART_MSR_TERI)\r
 938                         up->port.icount.rng++;\r
 939                 if (status & UART_MSR_DDSR)\r
 940                         up->port.icount.dsr++;\r
 941                 if (status & UART_MSR_DDCD)\r
 942                         uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);\r
 943                 if (status & UART_MSR_DCTS)\r
 944                         uart_handle_cts_change(&up->port, status & UART_MSR_CTS);\r
 945 \r
 946                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);\r
 947         }\r
 948 #endif\r
 949 \r
 950         return status;\r
 951 }\r
 952 \r
 953 \r
 954 /*\r
 955  * This handles the interrupt from one port.\r
 956  */\r
 957 static void serial_rk_handle_port(struct uart_rk_port *up)\r
 958 {\r
 959         unsigned int status;\r
 960         unsigned long flags;\r
 961         spin_lock_irqsave(&up->port.lock, flags);\r
 962 \r
 963         /* reading UART_LSR can automatically clears PE FE OE bits, except receive fifo error bit*/\r
 964         status = serial_in(up, UART_LSR);\r
 965 \r
 966         DEBUG_INTR("status = %x...\n", status);\r
 967 #if USE_DMA\r
 968         /* DMA mode enable */\r
 969         if(up->dma->use_dma) {\r
 970 \r
 971                 if (status & UART_LSR_RFE) {\r
 972                         if(up->port.line != DBG_PORT){\r
 973                                 dev_info(up->port.dev, "error:lsr=0x%x\n", status);\r
 974                                 status = serial_in(up, UART_LSR);\r
 975                                 DEBUG_INTR("error:lsr=0x%x\n", status);\r
 976                         }\r
 977                 }\r
 978 \r
 979                 if (status & 0x02) {\r
 980                         if(up->port.line != DBG_PORT){\r
 981                                 dev_info(up->port.dev, "error:lsr=0x%x\n", status);\r
 982                                 status = serial_in(up, UART_LSR);\r
 983                                 DEBUG_INTR("error:lsr=0x%x\n", status);\r
 984                         }\r
 985                 }\r
 986 \r
 987                 if(!(up->dma->use_dma & RX_DMA)) {\r
 988                         if (status & (UART_LSR_DR | UART_LSR_BI)) {\r
 989                                 receive_chars(up, &status);\r
 990                         }\r
 991                 }\r
 992 \r
 993                 if ((up->iir & 0x0f) == 0x02) {\r
 994                         transmit_chars(up);\r
 995                 }\r
 996         } else \r
 997 #endif\r
 998         {   //dma mode disable\r
 999 \r
1000                 /*\r
1001                  * when uart receive a serial of data which doesn't have stop bit and so on, that causes frame error,and\r
1002                  * set UART_LSR_RFE to one,what is worse,we couldn't read the data in the receive fifo. So if\r
1003                  * wo don't clear this bit and reset the receive fifo, the received data available interrupt would\r
1004                  * occur continuously.  added by hhb@rock-chips.com 2011-08-05\r
1005                  */\r
1006 \r
1007                 if (status & UART_LSR_RFE) {\r
1008                         if(up->port.line != DBG_PORT){\r
1009                                 dev_info(up->port.dev, "error:lsr=0x%x\n", status);\r
1010                                 status = serial_in(up, UART_LSR);\r
1011                                 DEBUG_INTR("error:lsr=0x%x\n", status);\r
1012                                 rk29_uart_dump_register(up);\r
1013                         }\r
1014                 }\r
1015 \r
1016                 if (status & (UART_LSR_DR | UART_LSR_BI)) {\r
1017                         receive_chars(up, &status);\r
1018                 }\r
1019                 check_modem_status(up);\r
1020                 //hhb@rock-chips.com when FIFO and THRE mode both are enabled,and FIFO TX empty trigger is set to larger than 1,\r
1021                 //,we need to add ((up->iir & 0x0f) == 0x02) to transmit_chars,because when entering interrupt,the FIFO and THR\r
1022                 //might not be 1.\r
1023                 if ((up->iir & 0x0f) == 0x02) {\r
1024                         transmit_chars(up);\r
1025                 }\r
1026         }\r
1027         spin_unlock_irqrestore(&up->port.lock, flags);\r
1028 }\r
1029 \r
1030 /*\r
1031  * This is the serial driver's interrupt routine.\r
1032  */\r
1033 \r
1034 static irqreturn_t serial_rk_interrupt(int irq, void *dev_id)\r
1035 {\r
1036         struct uart_rk_port *up = dev_id;\r
1037         int handled = 0;\r
1038         unsigned int iir;\r
1039 \r
1040         iir = serial_in(up, UART_IIR);\r
1041 \r
1042         DEBUG_INTR("%s(%d) iir = 0x%02x\n", __func__, irq, iir);\r
1043         up->iir = iir;\r
1044 \r
1045         if (!(iir & UART_IIR_NO_INT)) {\r
1046                 serial_rk_handle_port(up);\r
1047                 handled = 1;\r
1048         } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {\r
1049 \r
1050                 /* The DesignWare APB UART has an Busy Detect (0x07)\r
1051                  * interrupt meaning an LCR write attempt occured while the\r
1052                  * UART was busy. The interrupt must be cleared by reading\r
1053                  * the UART status register (USR) and the LCR re-written. */\r
1054 \r
1055                 if(!(serial_in(up, UART_USR) & UART_USR_BUSY)){\r
1056                         serial_out(up, UART_LCR, up->lcr);\r
1057                 }\r
1058                 handled = 1;\r
1059                 dbg("the serial.%d is busy\n", up->port.line);\r
1060         }\r
1061         DEBUG_INTR("end(%d).\n", handled);\r
1062 \r
1063         return IRQ_RETVAL(handled);\r
1064 }\r
1065 \r
1066 static unsigned int serial_rk_tx_empty(struct uart_port *port)\r
1067 {\r
1068         struct uart_rk_port *up =\r
1069                 container_of(port, struct uart_rk_port, port);\r
1070         unsigned long flags;\r
1071         unsigned int lsr;\r
1072 \r
1073         dev_dbg(port->dev, "%s\n", __func__);\r
1074         spin_lock_irqsave(&up->port.lock, flags);\r
1075         lsr = serial_in(up, UART_LSR);\r
1076         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;\r
1077         spin_unlock_irqrestore(&up->port.lock, flags);\r
1078 \r
1079         return (lsr & UART_LSR_TEMT) == UART_LSR_TEMT ? TIOCSER_TEMT : 0;\r
1080 }\r
1081 \r
1082 static unsigned int serial_rk_get_mctrl(struct uart_port *port)\r
1083 {\r
1084         struct uart_rk_port *up =\r
1085                 container_of(port, struct uart_rk_port, port);\r
1086         unsigned int status;\r
1087         unsigned int ret;\r
1088 \r
1089         status = check_modem_status(up);\r
1090 \r
1091         ret = 0;\r
1092         if (status & UART_MSR_DCD)\r
1093                 ret |= TIOCM_CAR;\r
1094         if (status & UART_MSR_RI)\r
1095                 ret |= TIOCM_RNG;\r
1096         if (status & UART_MSR_DSR)\r
1097                 ret |= TIOCM_DSR;\r
1098         if (status & UART_MSR_CTS)\r
1099                 ret |= TIOCM_CTS;\r
1100         dev_dbg(port->dev, "%s 0x%08x\n", __func__, ret);\r
1101         return ret;\r
1102 }\r
1103 \r
1104 static void serial_rk_set_mctrl(struct uart_port *port, unsigned int mctrl)\r
1105 {\r
1106         struct uart_rk_port *up =\r
1107                 container_of(port, struct uart_rk_port, port);\r
1108         unsigned char mcr = 0;\r
1109 \r
1110         dev_dbg(port->dev, "+%s\n", __func__);\r
1111         if (mctrl & TIOCM_RTS)\r
1112                 mcr |= UART_MCR_RTS;\r
1113         if (mctrl & TIOCM_DTR)\r
1114                 mcr |= UART_MCR_DTR;\r
1115         if (mctrl & TIOCM_OUT1)\r
1116                 mcr |= UART_MCR_OUT1;\r
1117         if (mctrl & TIOCM_OUT2)\r
1118                 mcr |= UART_MCR_OUT2;\r
1119         if (mctrl & TIOCM_LOOP)\r
1120                 mcr |= UART_MCR_LOOP;\r
1121 \r
1122         mcr |= up->mcr;\r
1123 \r
1124         serial_out(up, UART_MCR, mcr);\r
1125         dev_dbg(port->dev, "-serial.%d %s mcr: 0x%02x\n", port->line, __func__, mcr);\r
1126 }\r
1127 \r
1128 static void serial_rk_break_ctl(struct uart_port *port, int break_state)\r
1129 {\r
1130         struct uart_rk_port *up =\r
1131                 container_of(port, struct uart_rk_port, port);\r
1132         unsigned long flags;\r
1133 \r
1134         dev_dbg(port->dev, "+%s\n", __func__);\r
1135         spin_lock_irqsave(&up->port.lock, flags);\r
1136         if (break_state == -1)\r
1137                 up->lcr |= UART_LCR_SBC;\r
1138         else\r
1139                 up->lcr &= ~UART_LCR_SBC;\r
1140         serial_lcr_write(up, up->lcr);\r
1141         spin_unlock_irqrestore(&up->port.lock, flags);\r
1142         dev_dbg(port->dev, "-%s lcr: 0x%02x\n", __func__, up->lcr);\r
1143 }\r
1144 \r
1145 #if defined(CONFIG_SERIAL_RK_CONSOLE) || defined(CONFIG_CONSOLE_POLL)\r
1146 /*\r
1147  *      Wait for transmitter & holding register to empty\r
1148  */\r
1149 static void wait_for_xmitr(struct uart_rk_port *up, int bits)\r
1150 {\r
1151         unsigned int status, tmout = 10000;\r
1152 \r
1153         /* Wait up to 10ms for the character(s) to be sent. */\r
1154         for (;;) {\r
1155                 status = serial_in(up, UART_LSR);\r
1156 \r
1157                 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;\r
1158 \r
1159                 if ((status & bits) == bits)\r
1160                         break;\r
1161                 if (--tmout == 0)\r
1162                         break;\r
1163                 udelay(1);\r
1164         }\r
1165 }\r
1166 #endif\r
1167 \r
1168 #ifdef CONFIG_CONSOLE_POLL\r
1169 /*\r
1170  * Console polling routines for writing and reading from the uart while\r
1171  * in an interrupt or debug context.\r
1172  */\r
1173 \r
1174 static int serial_rk_get_poll_char(struct uart_port *port)\r
1175 {\r
1176         struct uart_rk_port *up =\r
1177                 container_of(port, struct uart_rk_port, port);\r
1178         unsigned char lsr = serial_in(up, UART_LSR);\r
1179 \r
1180         while (!(lsr & UART_LSR_DR))\r
1181                 lsr = serial_in(up, UART_LSR);\r
1182 \r
1183         return serial_in(up, UART_RX);\r
1184 }\r
1185 \r
1186 static void serial_rk_put_poll_char(struct uart_port *port,\r
1187                          unsigned char c)\r
1188 {\r
1189         unsigned int ier;\r
1190         struct uart_rk_port *up =\r
1191                 container_of(port, struct uart_rk_port, port);\r
1192 \r
1193         /*\r
1194          *      First save the IER then disable the interrupts\r
1195          */\r
1196         ier = serial_in(up, UART_IER);\r
1197         serial_out(up, UART_IER, 0);\r
1198 \r
1199         wait_for_xmitr(up, UART_LSR_TEMT);\r
1200         /*\r
1201          *      Send the character out.\r
1202          *      If a LF, also do CR...\r
1203          */\r
1204         serial_out(up, UART_TX, c);\r
1205         if (c == 10) {\r
1206                 wait_for_xmitr(up, UART_LSR_TEMT);\r
1207                 serial_out(up, UART_TX, 13);\r
1208         }\r
1209 \r
1210         /*\r
1211          *      Finally, wait for transmitter to become empty\r
1212          *      and restore the IER\r
1213          */\r
1214         wait_for_xmitr(up, UART_LSR_TEMT);\r
1215         serial_out(up, UART_IER, ier);\r
1216 }\r
1217 \r
1218 #endif /* CONFIG_CONSOLE_POLL */\r
1219 \r
1220 static int serial_rk_startup(struct uart_port *port)\r
1221 {\r
1222         struct uart_rk_port *up =\r
1223                 container_of(port, struct uart_rk_port, port);\r
1224         unsigned long flags;\r
1225         int retval, fifosize = 0;\r
1226         \r
1227 \r
1228         dev_dbg(port->dev, "%s\n", __func__);\r
1229 \r
1230         /*\r
1231          * Allocate the IRQ\r
1232          */\r
1233         retval = request_irq(up->port.irq, serial_rk_interrupt, up->port.irqflags,\r
1234                                 up->name, up);\r
1235         if (retval)\r
1236                 return retval;\r
1237 \r
1238         up->mcr = 0;\r
1239 \r
1240         clk_enable(up->pclk);\r
1241         clk_enable(up->clk);  // enable the config uart clock\r
1242 \r
1243         /*\r
1244          * Clear the FIFO buffers and disable them.\r
1245          * (they will be reenabled in set_termios())\r
1246          */\r
1247         serial_rk_clear_fifos(up);\r
1248 \r
1249         //read uart fifo size  hhb@rock-chips.com\r
1250         fifosize = __raw_readl(up->port.membase + 0xf4);\r
1251         up->port.fifosize = ((fifosize >> 16) & 0xff) << 4;\r
1252         if(up->port.fifosize <= 0)\r
1253                 up->port.fifosize = 32;\r
1254         //printk("fifo size:%d :%08x\n", up->port.fifosize, fifosize);\r
1255 \r
1256         /*\r
1257          * Clear the interrupt registers.\r
1258          */\r
1259         (void) serial_in(up, UART_LSR);\r
1260         (void) serial_in(up, UART_RX);\r
1261         (void) serial_in(up, UART_IIR);\r
1262         (void) serial_in(up, UART_MSR);\r
1263         (void) serial_in(up, UART_USR);\r
1264 \r
1265         /*\r
1266          * Now, initialize the UART\r
1267          */\r
1268         serial_lcr_write(up, UART_LCR_WLEN8 | UART_LCR_EPAR);\r
1269 \r
1270         spin_lock_irqsave(&up->port.lock, flags);\r
1271 \r
1272         /*\r
1273          * Most PC uarts need OUT2 raised to enable interrupts.\r
1274          */\r
1275 //      up->port.mctrl |= TIOCM_OUT2;\r
1276 \r
1277         serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1278 \r
1279         spin_unlock_irqrestore(&up->port.lock, flags);\r
1280 \r
1281         /*\r
1282          * Clear the interrupt registers again for luck, and clear the\r
1283          * saved flags to avoid getting false values from polling\r
1284          * routines or the previous session.\r
1285          */\r
1286         (void) serial_in(up, UART_LSR);\r
1287         (void) serial_in(up, UART_RX);\r
1288         (void) serial_in(up, UART_IIR);\r
1289         (void) serial_in(up, UART_MSR);\r
1290         (void) serial_in(up, UART_USR);\r
1291         up->lsr_saved_flags = 0;\r
1292 #if 0\r
1293         up->msr_saved_flags = 0;\r
1294 #endif\r
1295 #if USE_DMA\r
1296         if (up->dma->use_dma & TX_DMA) {\r
1297                 if(up->port.state->xmit.buf != up->dma->tx_buffer){\r
1298                         free_page((unsigned long)up->port.state->xmit.buf);\r
1299                         up->port.state->xmit.buf = up->dma->tx_buffer;\r
1300                 }\r
1301         } else \r
1302 #endif\r
1303         {\r
1304                 up->ier = 0;\r
1305                 serial_out(up, UART_IER, up->ier);\r
1306         }\r
1307 \r
1308         /*\r
1309          * Finally, enable interrupts.  Note: Modem status interrupts\r
1310          * are set via set_termios(), which will be occurring imminently\r
1311          * anyway, so we don't enable them here.\r
1312          */\r
1313 \r
1314         return 0;\r
1315 }\r
1316 \r
1317 \r
1318 static void serial_rk_shutdown(struct uart_port *port)\r
1319 {\r
1320         struct uart_rk_port *up =\r
1321                 container_of(port, struct uart_rk_port, port);\r
1322         unsigned long flags;\r
1323 \r
1324         dev_dbg(port->dev, "%s\n", __func__);\r
1325         /*\r
1326          * Disable interrupts from this port\r
1327          */\r
1328         up->ier = 0;\r
1329         serial_out(up, UART_IER, 0);\r
1330 \r
1331         spin_lock_irqsave(&up->port.lock, flags);\r
1332 //      up->port.mctrl &= ~TIOCM_OUT2;\r
1333         serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1334         spin_unlock_irqrestore(&up->port.lock, flags);\r
1335 \r
1336         /*\r
1337          * Disable break condition and FIFOs\r
1338          */\r
1339         serial_lcr_write(up, serial_in(up, UART_LCR) & ~UART_LCR_SBC);\r
1340         serial_rk_clear_fifos(up);\r
1341 \r
1342         /*\r
1343          * Read data port to reset things, and then free the irq\r
1344          */\r
1345         (void) serial_in(up, UART_RX);\r
1346 #if USE_DMA\r
1347         //if (up->dma->use_dma & TX_DMA)\r
1348         //      up->port.state->xmit.buf = NULL;\r
1349 #endif\r
1350         free_irq(up->port.irq, up);\r
1351         clk_disable(up->clk);\r
1352         clk_disable(up->pclk);\r
1353 }\r
1354 \r
1355 static void\r
1356 serial_rk_set_termios(struct uart_port *port, struct ktermios *termios,\r
1357                       struct ktermios *old)\r
1358 {\r
1359         struct uart_rk_port *up =\r
1360                 container_of(port, struct uart_rk_port, port);\r
1361         unsigned char cval = 0, fcr = 0, mcr = 0;\r
1362         unsigned long flags;\r
1363         unsigned int baud, quot;\r
1364         dev_dbg(port->dev, "+%s\n", __func__);\r
1365 \r
1366         switch (termios->c_cflag & CSIZE) {\r
1367         case CS5:\r
1368                 cval = UART_LCR_WLEN5;\r
1369                 break;\r
1370         case CS6:\r
1371                 cval = UART_LCR_WLEN6;\r
1372                 break;\r
1373         case CS7:\r
1374                 cval = UART_LCR_WLEN7;\r
1375                 break;\r
1376         case CS8:\r
1377         default:\r
1378                 cval = UART_LCR_WLEN8;\r
1379                 break;\r
1380         }\r
1381 \r
1382         if (termios->c_cflag & CSTOPB){\r
1383                 cval |= UART_LCR_STOP;\r
1384         }\r
1385         if (termios->c_cflag & PARENB){\r
1386                 cval |= UART_LCR_PARITY;\r
1387         }\r
1388         if (!(termios->c_cflag & PARODD)){\r
1389                 cval |= UART_LCR_EPAR;\r
1390         }\r
1391 #ifdef CMSPAR\r
1392         if (termios->c_cflag & CMSPAR)\r
1393                 cval |= UART_LCR_SPAR;\r
1394 #endif\r
1395 \r
1396 \r
1397         /*\r
1398          * Ask the core to calculate the divisor for us.\r
1399          */\r
1400         baud = uart_get_baud_rate(port, termios, old,\r
1401                                   port->uartclk / 16 / 0xffff,\r
1402                                   port->uartclk / 16);\r
1403 \r
1404         quot = uart_get_divisor(port, baud);\r
1405         //dev_info(up->port.dev, "uartclk:%d\n", port->uartclk/16);\r
1406         //dev_info(up->port.dev, "baud:%d\n", baud);\r
1407         //dev_info(up->port.dev, "quot:%d\n", quot);\r
1408 \r
1409         if (baud < 2400){\r
1410                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;\r
1411         }\r
1412         else{\r
1413                 fcr = UART_FCR_ENABLE_FIFO;\r
1414 #if USE_DMA\r
1415                 //added by hhb@rock-chips.com\r
1416                 if(up->dma->use_dma & TX_DMA){\r
1417                         fcr |= UART_FCR_T_TRIG_01;\r
1418                 } else\r
1419 #endif\r
1420                 {\r
1421                         fcr |= UART_FCR_T_TRIG_01;\r
1422                 }\r
1423 \r
1424 #if USE_DMA\r
1425                 //added by hhb@rock-chips.com\r
1426                 if(up->dma->use_dma & RX_DMA){  \r
1427                         fcr |= UART_FCR_R_TRIG_00;\r
1428                 } else\r
1429 #endif\r
1430                 {\r
1431                         if (termios->c_cflag & CRTSCTS)\r
1432                                 fcr |= UART_FCR_R_TRIG_11;\r
1433                         else\r
1434                                 fcr |= UART_FCR_R_TRIG_00;\r
1435                 }\r
1436         }\r
1437 \r
1438         /*\r
1439          * MCR-based auto flow control.  When AFE is enabled, RTS will be\r
1440          * deasserted when the receive FIFO contains more characters than\r
1441          * the trigger, or the MCR RTS bit is cleared.  In the case where\r
1442          * the remote UART is not using CTS auto flow control, we must\r
1443          * have sufficient FIFO entries for the latency of the remote\r
1444          * UART to respond.  IOW, at least 32 bytes of FIFO.\r
1445          */\r
1446         up->mcr &= ~UART_MCR_AFE;\r
1447         if (termios->c_cflag & CRTSCTS){\r
1448                 up->mcr |= UART_MCR_AFE;\r
1449         }\r
1450 \r
1451         /*\r
1452          * Ok, we're now changing the port state.  Do it with\r
1453          * interrupts disabled.\r
1454          */\r
1455         spin_lock_irqsave(&up->port.lock, flags);\r
1456 \r
1457         /*\r
1458          * Update the per-port timeout.\r
1459          */\r
1460         uart_update_timeout(port, termios->c_cflag, baud);\r
1461 \r
1462         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;\r
1463         if (termios->c_iflag & INPCK)\r
1464                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;\r
1465         if (termios->c_iflag & (BRKINT | PARMRK))\r
1466                 up->port.read_status_mask |= UART_LSR_BI;\r
1467 \r
1468         /*\r
1469          * Characteres to ignore\r
1470          */\r
1471         up->port.ignore_status_mask = 0;\r
1472         if (termios->c_iflag & IGNPAR)\r
1473                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;\r
1474         if (termios->c_iflag & IGNBRK) {\r
1475                 up->port.ignore_status_mask |= UART_LSR_BI;\r
1476                 /*\r
1477                  * If we're ignoring parity and break indicators,\r
1478                  * ignore overruns too (for real raw support).\r
1479                  */\r
1480                 if (termios->c_iflag & IGNPAR)\r
1481                         up->port.ignore_status_mask |= UART_LSR_OE;\r
1482         }\r
1483 \r
1484         /*\r
1485          * ignore all characters if CREAD is not set\r
1486          */\r
1487         if ((termios->c_cflag & CREAD) == 0)\r
1488                 up->port.ignore_status_mask |= UART_LSR_DR;\r
1489 \r
1490         /*\r
1491          * CTS flow control flag and modem status interrupts\r
1492          */\r
1493         up->ier &= ~UART_IER_MSI;\r
1494 #if 0\r
1495         if (UART_ENABLE_MS(&up->port, termios->c_cflag))\r
1496                 up->ier |= UART_IER_MSI;\r
1497 #endif\r
1498 \r
1499         //to avoid uart busy when set baud rate  hhb@rock-chips.com\r
1500         serial_out(up, UART_SRR, UART_RESET);\r
1501         mcr = serial_in(up, UART_MCR);\r
1502         serial_out(up, UART_MCR, mcr | 0x10);  //loopback mode\r
1503         \r
1504         up->lcr = cval;                         /* Save LCR */\r
1505         /* set DLAB */\r
1506         if(serial_lcr_write(up, cval | UART_LCR_DLAB)) {\r
1507                 if(up->port.line != DBG_PORT)\r
1508                         dbg("serial.%d set DLAB fail\n", up->port.line);\r
1509                 serial_out(up, UART_SRR, UART_RESET);\r
1510                 goto fail;\r
1511         }\r
1512 \r
1513         /* set uart baud rate */\r
1514         if(serial_dl_write(up, quot)) {\r
1515                 if(up->port.line != DBG_PORT)\r
1516                         dbg("serial.%d set dll fail\n", up->port.line);\r
1517                 serial_out(up, UART_SRR, UART_RESET);\r
1518                 goto fail;\r
1519         }\r
1520 \r
1521         /* reset DLAB */\r
1522         if(serial_lcr_write(up, cval)) {\r
1523                 if(up->port.line != DBG_PORT)\r
1524                         dbg("serial.%d reset DLAB fail\n", up->port.line);\r
1525                 serial_out(up, UART_SRR, UART_RESET);\r
1526                 goto fail;\r
1527         }\r
1528         else {\r
1529                 serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1530                 up->fcr = fcr;\r
1531                 serial_out(up, UART_FCR, up->fcr);              /* set fcr */\r
1532                 up->ier = 0;\r
1533                 //start serial receive data\r
1534 #if USE_DMA\r
1535                 if (up->dma->use_dma) {\r
1536                         up->ier |= UART_IER_RLSI;\r
1537                         up->ier |= UART_IER_PTIME;   //Programmable THRE Interrupt Mode Enable\r
1538                         if (up->dma->use_dma & RX_DMA)\r
1539                                 serial_rk_start_rx_dma(&up->port);\r
1540                         else\r
1541                                 up->ier |= UART_IER_RDI;\r
1542                 } else\r
1543 #endif\r
1544                 {\r
1545                         //  not use dma receive\r
1546                         up->ier |= UART_IER_RDI;\r
1547                         up->ier |= UART_IER_RLSI;\r
1548                         if(up->port.line != DBG_PORT)\r
1549                                 up->ier |= UART_IER_PTIME;   //Programmable THRE Interrupt Mode Enable\r
1550 \r
1551                 }\r
1552                 serial_out(up, UART_IER, up->ier);\r
1553         }\r
1554         \r
1555         spin_unlock_irqrestore(&up->port.lock, flags);\r
1556 \r
1557         /* Don't rewrite B0 */\r
1558         if (tty_termios_baud_rate(termios))\r
1559                 tty_termios_encode_baud_rate(termios, baud, baud);\r
1560         dev_dbg(port->dev, "-%s baud %d\n", __func__, baud);\r
1561         return;\r
1562 \r
1563 fail:\r
1564         spin_unlock_irqrestore(&up->port.lock, flags);\r
1565 \r
1566 }\r
1567 \r
1568 #if 0\r
1569 static void\r
1570 serial_rk_set_ldisc(struct uart_port *port, int new)\r
1571 {\r
1572         if (new == N_PPS) {\r
1573                 port->flags |= UPF_HARDPPS_CD;\r
1574                 serial_rk_enable_ms(port);\r
1575         } else\r
1576                 port->flags &= ~UPF_HARDPPS_CD;\r
1577 }\r
1578 #endif\r
1579 \r
1580 static void\r
1581 serial_rk_pm(struct uart_port *port, unsigned int state,\r
1582               unsigned int oldstate)\r
1583 {\r
1584         struct uart_rk_port *up =\r
1585                 container_of(port, struct uart_rk_port, port);\r
1586 \r
1587         dev_dbg(port->dev, "%s: %s\n", __func__, state ? "disable" : "enable");\r
1588         if (state) {\r
1589                 clk_disable(up->clk);\r
1590                 clk_disable(up->pclk);\r
1591         } else {\r
1592                 clk_enable(up->pclk);\r
1593                 clk_enable(up->clk);\r
1594         }\r
1595 }\r
1596 \r
1597 static void serial_rk_release_port(struct uart_port *port)\r
1598 {\r
1599         dev_dbg(port->dev, "%s\n", __func__);\r
1600 }\r
1601 \r
1602 static int serial_rk_request_port(struct uart_port *port)\r
1603 {\r
1604         dev_dbg(port->dev, "%s\n", __func__);\r
1605         return 0;\r
1606 }\r
1607 \r
1608 static void serial_rk_config_port(struct uart_port *port, int flags)\r
1609 {\r
1610         dev_dbg(port->dev, "%s\n", __func__);\r
1611         port->type = PORT_RK;\r
1612 }\r
1613 \r
1614 static int\r
1615 serial_rk_verify_port(struct uart_port *port, struct serial_struct *ser)\r
1616 {\r
1617         /* we don't want the core code to modify any port params */\r
1618         dev_dbg(port->dev, "%s\n", __func__);\r
1619         return -EINVAL;\r
1620 }\r
1621 \r
1622 static const char *\r
1623 serial_rk_type(struct uart_port *port)\r
1624 {\r
1625         struct uart_rk_port *up =\r
1626                 container_of(port, struct uart_rk_port, port);\r
1627 \r
1628         dev_dbg(port->dev, "%s: %s\n", __func__, up->name);\r
1629         return up->name;\r
1630 }\r
1631 \r
1632 static struct uart_ops serial_rk_pops = {\r
1633         .tx_empty       = serial_rk_tx_empty,\r
1634         .set_mctrl      = serial_rk_set_mctrl,\r
1635         .get_mctrl      = serial_rk_get_mctrl,\r
1636         .stop_tx        = serial_rk_stop_tx,\r
1637         .start_tx       = serial_rk_start_tx,\r
1638         .stop_rx        = serial_rk_stop_rx,\r
1639         .enable_ms      = serial_rk_enable_ms,\r
1640         .break_ctl      = serial_rk_break_ctl,\r
1641         .startup        = serial_rk_startup,\r
1642         .shutdown       = serial_rk_shutdown,\r
1643         .set_termios    = serial_rk_set_termios,\r
1644 #if 0\r
1645         .set_ldisc      = serial_rk_set_ldisc,\r
1646 #endif\r
1647         .pm             = serial_rk_pm,\r
1648         .type           = serial_rk_type,\r
1649         .release_port   = serial_rk_release_port,\r
1650         .request_port   = serial_rk_request_port,\r
1651         .config_port    = serial_rk_config_port,\r
1652         .verify_port    = serial_rk_verify_port,\r
1653 #ifdef CONFIG_CONSOLE_POLL\r
1654         .poll_get_char = serial_rk_get_poll_char,\r
1655         .poll_put_char = serial_rk_put_poll_char,\r
1656 #endif\r
1657 };\r
1658 \r
1659 #ifdef CONFIG_SERIAL_RK_CONSOLE\r
1660 \r
1661 static struct uart_rk_port *serial_rk_console_ports[UART_NR];\r
1662 \r
1663 static void serial_rk_console_putchar(struct uart_port *port, int ch)\r
1664 {\r
1665         struct uart_rk_port *up =\r
1666                 container_of(port, struct uart_rk_port, port);\r
1667 \r
1668         wait_for_xmitr(up, UART_LSR_THRE);\r
1669         serial_out(up, UART_TX, ch);\r
1670 }\r
1671 \r
1672 /*\r
1673  *      Print a string to the serial port trying not to disturb\r
1674  *      any possible real use of the port...\r
1675  *\r
1676  *      The console_lock must be held when we get here.\r
1677  */\r
1678 static void\r
1679 serial_rk_console_write(struct console *co, const char *s, unsigned int count)\r
1680 {\r
1681         struct uart_rk_port *up = serial_rk_console_ports[co->index];\r
1682         unsigned long flags;\r
1683         unsigned int ier;\r
1684         int locked = 1;\r
1685 \r
1686         touch_nmi_watchdog();\r
1687 \r
1688         local_irq_save(flags);\r
1689         if (up->port.sysrq) {\r
1690                 /* serial_rk_handle_port() already took the lock */\r
1691                 locked = 0;\r
1692         } else if (oops_in_progress) {\r
1693                 locked = spin_trylock(&up->port.lock);\r
1694         } else\r
1695                 spin_lock(&up->port.lock);\r
1696 \r
1697         /*\r
1698          *      First save the IER then disable the interrupts\r
1699          */\r
1700         ier = serial_in(up, UART_IER);\r
1701 \r
1702         serial_out(up, UART_IER, 0);\r
1703 \r
1704         uart_console_write(&up->port, s, count, serial_rk_console_putchar);\r
1705 \r
1706         /*\r
1707          *      Finally, wait for transmitter to become empty\r
1708          *      and restore the IER\r
1709          */\r
1710         wait_for_xmitr(up, UART_LSR_TEMT);\r
1711         serial_out(up, UART_IER, ier);\r
1712 \r
1713 #if 0\r
1714         /*\r
1715          *      The receive handling will happen properly because the\r
1716          *      receive ready bit will still be set; it is not cleared\r
1717          *      on read.  However, modem control will not, we must\r
1718          *      call it if we have saved something in the saved flags\r
1719          *      while processing with interrupts off.\r
1720          */\r
1721         if (up->msr_saved_flags)\r
1722                 check_modem_status(up);\r
1723 #endif\r
1724 \r
1725         if (locked)\r
1726                 spin_unlock(&up->port.lock);\r
1727         local_irq_restore(flags);\r
1728 }\r
1729 \r
1730 static int __init serial_rk_console_setup(struct console *co, char *options)\r
1731 {\r
1732         struct uart_rk_port *up;\r
1733         int baud = 115200;\r
1734         int bits = 8;\r
1735         int parity = 'n';\r
1736         int flow = 'n';\r
1737 \r
1738         if (unlikely(co->index >= UART_NR || co->index < 0))\r
1739                 return -ENODEV;\r
1740 \r
1741         if (serial_rk_console_ports[co->index] == NULL)\r
1742                 return -ENODEV;\r
1743         up = serial_rk_console_ports[co->index];\r
1744 \r
1745         if (options)\r
1746                 uart_parse_options(options, &baud, &parity, &bits, &flow);\r
1747 \r
1748         return uart_set_options(&up->port, co, baud, parity, bits, flow);\r
1749 }\r
1750 \r
1751 static struct console serial_rk_console = {\r
1752         .name           = "ttyS",\r
1753         .write          = serial_rk_console_write,\r
1754         .device         = uart_console_device,\r
1755         .setup          = serial_rk_console_setup,\r
1756         .flags          = CON_PRINTBUFFER | CON_ANYTIME,\r
1757         .index          = -1,\r
1758         .data           = &serial_rk_reg,\r
1759 };\r
1760 \r
1761 static void serial_rk_add_console_port(struct uart_rk_port *up)\r
1762 {\r
1763         serial_rk_console_ports[up->pdev->id] = up;\r
1764 }\r
1765 \r
1766 #define SERIAL_CONSOLE  &serial_rk_console\r
1767 #else\r
1768 #define SERIAL_CONSOLE  NULL\r
1769 \r
1770 static inline void serial_rk_add_console_port(struct uart_rk_port *up)\r
1771 {}\r
1772 \r
1773 #endif\r
1774 \r
1775 static struct uart_driver serial_rk_reg = {\r
1776         .owner                  = THIS_MODULE,\r
1777         .driver_name            = "rk29_serial",\r
1778         .dev_name               = "ttyS",\r
1779         .major                  = TTY_MAJOR,\r
1780         .minor                  = 64,\r
1781         .cons                   = SERIAL_CONSOLE,\r
1782         .nr                     = UART_NR,\r
1783 };\r
1784 \r
1785 static int __devinit serial_rk_probe(struct platform_device *pdev)\r
1786 {\r
1787         struct uart_rk_port     *up;\r
1788         struct resource         *mem;\r
1789         int irq;\r
1790         int ret = -ENOSPC;\r
1791         \r
1792         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1793         if (!mem) {\r
1794                 dev_err(&pdev->dev, "no mem resource?\n");\r
1795                 return -ENODEV;\r
1796         }\r
1797 \r
1798         irq = platform_get_irq(pdev, 0);\r
1799         if (irq < 0) {\r
1800                 dev_err(&pdev->dev, "no irq resource?\n");\r
1801                 return irq;\r
1802         }\r
1803 \r
1804         if (!request_mem_region(mem->start, (mem->end - mem->start) + 1,\r
1805                                 pdev->dev.driver->name)) {\r
1806                 dev_err(&pdev->dev, "memory region already claimed\n");\r
1807                 return -EBUSY;\r
1808         }\r
1809 \r
1810         up = kzalloc(sizeof(*up), GFP_KERNEL);\r
1811         if (up == NULL) {\r
1812                 ret = -ENOMEM;\r
1813                 goto do_release_region;\r
1814         }\r
1815 \r
1816         sprintf(up->name, "rk29_serial.%d", pdev->id);\r
1817         up->pdev = pdev;\r
1818         up->pclk = clk_get(&pdev->dev, "pclk_uart");\r
1819         up->clk = clk_get(&pdev->dev, "uart");\r
1820         if (unlikely(IS_ERR(up->clk))) {\r
1821                 ret = PTR_ERR(up->clk);\r
1822                 goto do_free;\r
1823         }\r
1824         up->tx_loadsz = 30;\r
1825 #if USE_DMA\r
1826         up->dma = &rk29_uart_ports_dma[pdev->id];\r
1827 #endif\r
1828         up->port.dev = &pdev->dev;\r
1829         up->port.type = PORT_RK;\r
1830         up->port.irq = irq;\r
1831         up->port.iotype = UPIO_DWAPB;\r
1832 \r
1833         up->port.regshift = 2;\r
1834         //fifo size default is 32, but it will be updated later when start_up\r
1835         up->port.fifosize = 32;\r
1836         up->port.ops = &serial_rk_pops;\r
1837         up->port.line = pdev->id;\r
1838         up->port.iobase = mem->start;\r
1839         up->port.membase = ioremap_nocache(mem->start, mem->end - mem->start + 1);\r
1840         if (!up->port.membase) {\r
1841                 ret = -ENOMEM;\r
1842                 goto do_put_clk;\r
1843         }\r
1844         up->port.mapbase = mem->start;\r
1845         up->port.irqflags = IRQF_DISABLED;\r
1846         up->port.uartclk = clk_get_rate(up->clk);\r
1847 \r
1848 #if USE_DMA\r
1849         /* set dma config */\r
1850         pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);\r
1851         if(up->dma->use_dma & RX_DMA) {\r
1852                 //timer\r
1853                 up->dma->use_timer = USE_TIMER;\r
1854                 up->dma->rx_timer.function = serial_rk_report_dma_rx;\r
1855                 up->dma->rx_timer.data = (unsigned long)up;\r
1856                 up->dma->rx_timeout = 10;\r
1857                 up->dma->rx_timer.expires = jiffies + msecs_to_jiffies(up->dma->rx_timeout);\r
1858                 init_timer(&up->dma->rx_timer);\r
1859 \r
1860                 //rx buffer\r
1861                 up->dma->rb_size =  UART_XMIT_SIZE*2;\r
1862                 up->dma->rx_buffer = dmam_alloc_coherent(up->port.dev, up->dma->rb_size,\r
1863                                 &up->dma->rx_phy_addr, DMA_MEMORY_MAP);\r
1864                 up->dma->rb_tail = 0;\r
1865 \r
1866                 if(!up->dma->rx_buffer){\r
1867                         dev_info(up->port.dev, "dmam_alloc_coherent dma_rx_buffer fail\n");\r
1868                 }\r
1869                 else {\r
1870                         dev_info(up->port.dev, "dma_rx_buffer 0x%08x\n", (unsigned) up->dma->rx_buffer);\r
1871                         dev_info(up->port.dev, "dma_rx_phy 0x%08x\n", (unsigned)up->dma->rx_phy_addr);\r
1872                 }\r
1873 \r
1874                 // work queue\r
1875                 //INIT_WORK(&up->uart_work, serial_rk_report_revdata_workfunc);\r
1876                 //INIT_WORK(&up->uart_work_rx, serial_rk_start_dma_rx);\r
1877                 //up->uart_wq = create_singlethread_workqueue("uart_workqueue");\r
1878                 up->dma->rx_dma_used = 0;\r
1879                 spin_lock_init(&(up->dma->rx_lock));\r
1880                 serial_rk_init_dma_rx(&up->port);\r
1881         }\r
1882 \r
1883         if(up->dma->use_dma & TX_DMA){\r
1884                 //tx buffer\r
1885                 up->dma->tb_size = UART_XMIT_SIZE;\r
1886                 up->dma->tx_buffer = dmam_alloc_coherent(up->port.dev, up->dma->tb_size,\r
1887                                 &up->dma->tx_phy_addr, DMA_MEMORY_MAP);\r
1888                 if(!up->dma->tx_buffer){\r
1889                         dev_info(up->port.dev, "dmam_alloc_coherent dma_tx_buffer fail\n");\r
1890                 }\r
1891                 else{\r
1892                         dev_info(up->port.dev, "dma_tx_buffer 0x%08x\n", (unsigned) up->dma->tx_buffer);\r
1893                         dev_info(up->port.dev, "dma_tx_phy 0x%08x\n", (unsigned) up->dma->tx_phy_addr);\r
1894                 }\r
1895                 spin_lock_init(&(up->dma->tx_lock));\r
1896                 serial_rk_init_dma_tx(&up->port);\r
1897         }\r
1898 \r
1899 #endif\r
1900         serial_rk_add_console_port(up);\r
1901         ret = uart_add_one_port(&serial_rk_reg, &up->port);\r
1902         if (ret != 0)\r
1903                 goto do_iounmap;\r
1904 \r
1905         platform_set_drvdata(pdev, up);\r
1906         dev_info(&pdev->dev, "membase 0x%08x\n", (unsigned) up->port.membase);\r
1907 \r
1908         return 0;\r
1909 \r
1910 do_iounmap:\r
1911         iounmap(up->port.membase);\r
1912         up->port.membase = NULL;\r
1913 do_put_clk:\r
1914         clk_put(up->clk);\r
1915         clk_put(up->pclk);\r
1916 do_free:\r
1917         kfree(up);\r
1918 do_release_region:\r
1919         release_mem_region(mem->start, (mem->end - mem->start) + 1);\r
1920         return ret;\r
1921 }\r
1922 \r
1923 static int __devexit serial_rk_remove(struct platform_device *pdev)\r
1924 {\r
1925         struct uart_rk_port *up = platform_get_drvdata(pdev);\r
1926 \r
1927         platform_set_drvdata(pdev, NULL);\r
1928         if (up) {\r
1929                 struct resource *mem;\r
1930                 destroy_workqueue(up->uart_wq);\r
1931                 uart_remove_one_port(&serial_rk_reg, &up->port);\r
1932                 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1933                 iounmap(up->port.membase);\r
1934                 up->port.membase = NULL;\r
1935                 clk_put(up->clk);\r
1936                 clk_put(up->pclk);\r
1937                 kfree(up);\r
1938                 release_mem_region(mem->start, (mem->end - mem->start) + 1);\r
1939         }\r
1940 \r
1941         return 0;\r
1942 }\r
1943 \r
1944 static int serial_rk_suspend(struct platform_device *dev, pm_message_t state)\r
1945 {\r
1946         struct uart_rk_port *up = platform_get_drvdata(dev);\r
1947 \r
1948         if (up && up->port.line != DBG_PORT && POWER_MANEGEMENT){\r
1949                 uart_suspend_port(&serial_rk_reg, &up->port);\r
1950         }\r
1951         if(up->port.line == DBG_PORT && POWER_MANEGEMENT){\r
1952                 serial_rk_pm(&up->port, 1, 0);\r
1953         }\r
1954 \r
1955         return 0;\r
1956 }\r
1957 \r
1958 static int serial_rk_resume(struct platform_device *dev)\r
1959 {\r
1960         struct uart_rk_port *up = platform_get_drvdata(dev);\r
1961 \r
1962         if (up && up->port.line != DBG_PORT && POWER_MANEGEMENT){\r
1963                 uart_resume_port(&serial_rk_reg, &up->port);\r
1964         }\r
1965         if(up->port.line == DBG_PORT && POWER_MANEGEMENT){\r
1966                 serial_rk_pm(&up->port, 0, 1);\r
1967         }\r
1968         return 0;\r
1969 }\r
1970 \r
1971 static struct platform_driver serial_rk_driver = {\r
1972         .probe          = serial_rk_probe,\r
1973         .remove         = __devexit_p(serial_rk_remove),\r
1974         .suspend        = serial_rk_suspend,\r
1975         .resume         = serial_rk_resume,\r
1976         .driver         = {\r
1977 #if defined(CONFIG_ARCH_RK29)\r
1978                 .name   = "rk29_serial",\r
1979 #elif defined(CONFIG_SERIAL_RK2818)\r
1980                 .name   = "rk2818_serial",\r
1981 #else\r
1982                 .name   = "rk_serial",\r
1983 #endif\r
1984                 .owner  = THIS_MODULE,\r
1985         },\r
1986 };\r
1987 \r
1988 static int __init serial_rk_init(void)\r
1989 {\r
1990         int ret;\r
1991         //hhb@rock-chips.com\r
1992         printk("%s\n", VERSION_AND_TIME);\r
1993 \r
1994         ret = uart_register_driver(&serial_rk_reg);\r
1995         if (ret)\r
1996                 return ret;\r
1997 \r
1998         ret = platform_driver_register(&serial_rk_driver);\r
1999         if (ret != 0)\r
2000                 uart_unregister_driver(&serial_rk_reg);\r
2001 \r
2002         return ret;\r
2003 }\r
2004 \r
2005 static void __exit serial_rk_exit(void)\r
2006 {\r
2007         platform_driver_unregister(&serial_rk_driver);\r
2008         uart_unregister_driver(&serial_rk_reg);\r
2009 }\r
2010 \r
2011 module_init(serial_rk_init);\r
2012 module_exit(serial_rk_exit);\r
2013 \r
2014 MODULE_LICENSE("GPL");\r
2015 MODULE_DESCRIPTION("RK UART driver");\r
2016 \r