drivers/tty/serial/rk_serial.c

   1 /*\r
   2  * Driver for RK-UART controller.\r
   3  * Based on drivers/tty/serial/8250.c\r
   4  *\r
   5  * Copyright (C) 2011 Rochchip.\r
   6  *\r
   7  * This program is free software; you can redistribute it and/or modify\r
   8  * it under the terms of the GNU General Public License as published by\r
   9  * the Free Software Foundation; either version 2 of the License, or\r
  10 \r
  11  * (at your option) any later version.\r
  12  *\r
  13  * Author: hhb@rock-chips.com\r
  14  * Date: 2011.06.18\r
  15  */\r
  16 \r
  17 #ifndef CONFIG_SERIAL_RK_CONSOLE\r
  18 #if defined(CONFIG_SERIAL_RK29_CONSOLE)\r
  19 #define CONFIG_SERIAL_RK_CONSOLE\r
  20 #endif\r
  21 #endif\r
  22 \r
  23 #if defined(CONFIG_SERIAL_RK_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)\r
  24 #define SUPPORT_SYSRQ\r
  25 #endif\r
  26 \r
  27 #include <linux/module.h>\r
  28 #include <linux/ioport.h>\r
  29 #include <linux/init.h>\r
  30 #include <linux/console.h>\r
  31 #include <linux/sysrq.h>\r
  32 #include <linux/delay.h>\r
  33 #include <linux/platform_device.h>\r
  34 #include <linux/tty.h>\r
  35 #include <linux/ratelimit.h>\r
  36 #include <linux/tty_flip.h>\r
  37 #include <linux/serial_reg.h>\r
  38 #include <linux/serial_core.h>\r
  39 #include <linux/serial.h>\r
  40 #include <linux/nmi.h>\r
  41 #include <linux/mutex.h>\r
  42 #include <linux/slab.h>\r
  43 #include <linux/clk.h>\r
  44 #include <linux/timer.h>\r
  45 #include <linux/workqueue.h>\r
  46 #include <linux/dma-mapping.h>\r
  47 \r
  48 #include <asm/io.h>\r
  49 #include <asm/irq.h>\r
  50 \r
  51 /*\r
  52 *                        Driver Version Note\r
  53 *\r
  54 *v0.0 : this driver is 2.6.32 kernel driver;\r
  55 *v0.1 : this driver is 3.0.8 kernel driver;\r
  56 *v1.0 : 2012-08-09\r
  57 *               1.modify dma dirver;\r
  58 *               2.enable Programmable THRE Interrupt Mode, so we can just judge ((up->iir & 0x0f) == 0x02) when transmit\r
  59 *               3.reset uart and set it to loopback state to ensure setting baud rate sucessfully \r
  60 *v1.1 : 2012-08-23\r
  61 *               1. dma driver:make "when tx dma is only enable" work functionally  \r
  62 *v1.2 : 2012-08-28\r
  63 *               1. dma driver:serial rx use new dma interface  rk29_dma_enqueue_ring \r
  64 *v1.3 : 2012-12-14\r
  65 *               1. When enable Programmable THRE Interrupt Mode, in lsr register, only UART_LSR_TEMT means transmit empty, but\r
  66                  UART_LSR_THRE doesn't. So, the macro BOTH_EMPTY should be replaced with UART_LSR_TEMT.\r
  67 *v1.4 : 2013-04-16\r
  68 *               1.fix bug dma buffer free error\r
  69 *v1.5 : 2013-10-17\r
  70 *               1.in some case, set uart rx as gpio interrupt to wake up arm, when arm suspends \r
  71 */\r
  72 #define VERSION_AND_TIME  "rk_serial.c v1.5 2013-10-17"\r
  73 \r
  74 #define PORT_RK         90\r
  75 #define UART_USR        0x1F    /* UART Status Register */\r
  76 #define UART_USR_BUSY (1)\r
  77 #define UART_IER_PTIME  0x80    /* Programmable THRE Interrupt Mode Enable */\r
  78 #define UART_LSR_RFE    0x80    /* receive fifo error */\r
  79 #define UART_SRR                0x22    /* software reset register */\r
  80 #define UART_RESET              0x01\r
  81 \r
  82 \r
  83 //#define BOTH_EMPTY    (UART_LSR_TEMT | UART_LSR_THRE)\r
  84 \r
  85 #define UART_NR 4   //uart port number\r
  86 \r
  87 \r
  88 /* configurate whether the port transmit-receive by DMA in menuconfig*/\r
  89 #define OPEN_DMA      1\r
  90 #define CLOSE_DMA     0\r
  91 \r
  92 #define TX_DMA (1)\r
  93 #define RX_DMA (2)\r
  94 \r
  95 #ifdef CONFIG_UART0_DMA_RK29 \r
  96 #define UART0_USE_DMA CONFIG_UART0_DMA_RK29\r
  97 #else\r
  98 #define UART0_USE_DMA CLOSE_DMA\r
  99 #endif\r
 100 #ifdef CONFIG_UART1_DMA_RK29\r
 101 #define UART1_USE_DMA CONFIG_UART1_DMA_RK29\r
 102 #else\r
 103 #define UART1_USE_DMA CLOSE_DMA\r
 104 #endif\r
 105 #ifdef CONFIG_UART2_DMA_RK29\r
 106 #define UART2_USE_DMA CONFIG_UART2_DMA_RK29\r
 107 #else\r
 108 #define UART2_USE_DMA CLOSE_DMA\r
 109 #endif\r
 110 #ifdef CONFIG_UART3_DMA_RK29\r
 111 #define UART3_USE_DMA CONFIG_UART3_DMA_RK29\r
 112 #else\r
 113 #define UART3_USE_DMA CLOSE_DMA\r
 114 #endif\r
 115 \r
 116 //serial wake up \r
 117 #ifdef CONFIG_UART0_WAKEUP_RK29 \r
 118 #define UART0_USE_WAKEUP CONFIG_UART0_WAKEUP_RK29\r
 119 #else\r
 120 #define UART0_USE_WAKEUP 0\r
 121 #endif\r
 122 #ifdef CONFIG_UART1_WAKEUP_RK29\r
 123 #define UART1_USE_WAKEUP CONFIG_UART1_WAKEUP_RK29\r
 124 #else\r
 125 #define UART1_USE_WAKEUP 0\r
 126 #endif\r
 127 #ifdef CONFIG_UART2_WAKEUP_RK29\r
 128 #define UART2_USE_WAKEUP CONFIG_UART2_WAKEUP_RK29\r
 129 #else\r
 130 #define UART2_USE_WAKEUP 0\r
 131 #endif\r
 132 #ifdef CONFIG_UART3_WAKEUP_RK29\r
 133 #define UART3_USE_WAKEUP CONFIG_UART3_WAKEUP_RK29\r
 134 #else\r
 135 #define UART3_USE_WAKEUP 0\r
 136 #endif\r
 137 \r
 138 \r
 139 \r
 140 #define USE_TIMER    1           // use timer for dma transport\r
 141 #define POWER_MANEGEMENT 1\r
 142 #define RX_TIMEOUT              (3000*3)  //uint ms\r
 143 #define DMA_TX_TRRIGE_LEVEL 128\r
 144 #define SERIAL_CIRC_CNT_TO_END(xmit)   CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)\r
 145 \r
 146 \r
 147 #define USE_DMA (UART0_USE_DMA | UART1_USE_DMA | UART2_USE_DMA | UART3_USE_DMA)\r
 148 #define USE_WAKEUP (UART0_USE_WAKEUP | UART1_USE_WAKEUP | UART2_USE_WAKEUP | UART3_USE_WAKEUP)\r
 149 \r
 150 #if USE_DMA\r
 151 #ifdef CONFIG_ARCH_RK29\r
 152 #include <mach/dma-pl330.h>\r
 153 #else\r
 154 #include <plat/dma-pl330.h>\r
 155 #endif\r
 156 #endif\r
 157 \r
 158 #if USE_WAKEUP\r
 159 #include <mach/iomux.h>\r
 160 #include <linux/wakelock.h>\r
 161 #endif\r
 162 \r
 163 \r
 164 \r
 165 static struct uart_driver serial_rk_reg;\r
 166 \r
 167 /*\r
 168  * Debugging.\r
 169  */\r
 170 #ifdef CONFIG_ARCH_RK29\r
 171 #define DBG_PORT 1   //DBG_PORT which uart is used to print log message\r
 172 #else\r
 173 #ifndef CONFIG_RK_DEBUG_UART   //DBG_PORT which uart is used to print log message\r
 174 #define DBG_PORT 2\r
 175 #else\r
 176 #define DBG_PORT CONFIG_RK_DEBUG_UART\r
 177 #endif\r
 178 #endif\r
 179 \r
 180 #ifdef CONFIG_SERIAL_CORE_CONSOLE\r
 181 #define uart_console(port)      ((port)->cons && (port)->cons->index == (port)->line)\r
 182 #else\r
 183 #define uart_console(port)      (0)\r
 184 #endif\r
 185 \r
 186 \r
 187 extern void printascii(const char *);\r
 188 static void dbg(const char *fmt, ...)\r
 189 {\r
 190         va_list va;\r
 191         char buff[256];\r
 192 \r
 193         va_start(va, fmt);\r
 194         vsprintf(buff, fmt, va);\r
 195         va_end(va);\r
 196 \r
 197 #if defined(CONFIG_DEBUG_LL) || defined(CONFIG_RK_EARLY_PRINTK)\r
 198         printascii(buff);\r
 199 #endif\r
 200 }\r
 201 \r
 202 //enable log output\r
 203 #define DEBUG 0\r
 204 static int log_port = -1;\r
 205 module_param(log_port, int, S_IRUGO|S_IWUSR);\r
 206 \r
 207 #if DEBUG\r
 208 #define DEBUG_INTR(fmt...)      if (up->port.line == log_port && !uart_console(&up->port)) dbg(fmt)\r
 209 #else\r
 210 #define DEBUG_INTR(fmt...)      do { } while (0)\r
 211 #endif\r
 212 \r
 213 \r
 214 #if USE_DMA\r
 215 /* added by hhb@rock-chips.com for uart dma transfer */\r
 216 \r
 217 struct rk_uart_dma {\r
 218         u32 use_dma;            //1:used\r
 219         enum dma_ch rx_dmach;\r
 220         enum dma_ch tx_dmach;\r
 221 \r
 222         //receive and transfer buffer\r
 223         char * rx_buffer;    //visual memory\r
 224         char * tx_buffer;\r
 225         dma_addr_t rx_phy_addr;  //physical memory\r
 226         dma_addr_t tx_phy_addr;\r
 227         u32 rb_size;             //buffer size\r
 228         u32 tb_size;\r
 229 \r
 230         //regard the rx buffer as a circular buffer\r
 231         u32 rb_head;\r
 232         u32 rb_tail;\r
 233         u32 rx_size;\r
 234 \r
 235         spinlock_t              tx_lock;\r
 236         spinlock_t              rx_lock;\r
 237 \r
 238         char tx_dma_inited;   //1:dma tx channel has been init\r
 239         char rx_dma_inited;      //1:dma rx channel has been init\r
 240         char tx_dma_used;        //1:dma tx is working\r
 241         char rx_dma_used;    //1:dma rx is working\r
 242 \r
 243         /* timer to poll activity on rx dma */\r
 244         char use_timer;\r
 245         int      rx_timeout;\r
 246         struct timer_list rx_timer;\r
 247 };\r
 248 #endif\r
 249 \r
 250 #if USE_WAKEUP  \r
 251 struct uart_wake_up {\r
 252         unsigned int enable;\r
 253         unsigned int rx_mode;\r
 254         unsigned int tx_mode;\r
 255         unsigned int rx_pin;\r
 256         char rx_pin_name[32];\r
 257         unsigned int tx_pin;\r
 258         unsigned int rx_irq;\r
 259         char rx_irq_name[32];\r
 260         struct wake_lock wakelock;\r
 261         char wakelock_name[32];\r
 262 };\r
 263 #endif\r
 264 \r
 265 struct uart_rk_port {\r
 266         struct uart_port        port;\r
 267         struct platform_device  *pdev;\r
 268         struct clk              *clk;\r
 269         struct clk              *pclk;\r
 270         unsigned int            tx_loadsz;      /* transmit fifo load size */\r
 271         unsigned char           ier;\r
 272         unsigned char           lcr;\r
 273         unsigned char           mcr;\r
 274         unsigned char           iir;\r
 275         unsigned char           fcr;\r
 276         /*\r
 277          * Some bits in registers are cleared on a read, so they must\r
 278          * be saved whenever the register is read but the bits will not\r
 279          * be immediately processed.\r
 280          */\r
 281 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS\r
 282         unsigned char           lsr_saved_flags;\r
 283 #if 0\r
 284 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA\r
 285         unsigned char           msr_saved_flags;\r
 286 #endif\r
 287 \r
 288         char                    name[16];\r
 289         char                    fifo[64];\r
 290         char                    fifo_size;\r
 291         unsigned long           port_activity;\r
 292         struct work_struct uart_work;\r
 293         struct work_struct uart_work_rx;\r
 294         struct workqueue_struct *uart_wq;\r
 295 #if USE_DMA\r
 296         struct rk_uart_dma *dma;\r
 297 #endif\r
 298 #if USE_WAKEUP\r
 299         struct uart_wake_up *wakeup;\r
 300 #endif\r
 301 };\r
 302 \r
 303 #if USE_DMA\r
 304 static void serial_rk_release_dma_tx(struct uart_port *port);\r
 305 static int serial_rk_start_tx_dma(struct uart_port *port);\r
 306 //static void serial_rk_rx_timeout(unsigned long uart);\r
 307 static void serial_rk_release_dma_rx(struct uart_port *port);\r
 308 static int serial_rk_start_rx_dma(struct uart_port *port);\r
 309 #else\r
 310 static inline int serial_rk_start_tx_dma(struct uart_port *port) { return 0; }\r
 311 #endif\r
 312 static int serial_rk_startup(struct uart_port *port);\r
 313 \r
 314 static inline unsigned int serial_in(struct uart_rk_port *up, int offset)\r
 315 {\r
 316         offset = offset << 2;\r
 317 \r
 318         return __raw_readb(up->port.membase + offset);\r
 319 }\r
 320 \r
 321 /* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */\r
 322 static inline void dwapb_save_out_value(struct uart_rk_port *up, int offset,\r
 323                                         unsigned char value)\r
 324 {\r
 325         if (offset == UART_LCR)\r
 326                 up->lcr = value;\r
 327 }\r
 328 \r
 329 /* Read the IER to ensure any interrupt is cleared before returning from ISR. */\r
 330 static inline void dwapb_check_clear_ier(struct uart_rk_port *up, int offset)\r
 331 {\r
 332         if (offset == UART_TX || offset == UART_IER)\r
 333                 serial_in(up, UART_IER);\r
 334 }\r
 335 \r
 336 static inline void serial_out(struct uart_rk_port *up, int offset, unsigned char value)\r
 337 {\r
 338         dwapb_save_out_value(up, offset, value);\r
 339         __raw_writeb(value, up->port.membase + (offset << 2));\r
 340         if (offset != UART_TX)\r
 341                 dsb();\r
 342         dwapb_check_clear_ier(up, offset);\r
 343 }\r
 344 \r
 345 /* Uart divisor latch read */\r
 346 static inline int serial_dl_read(struct uart_rk_port *up)\r
 347 {\r
 348         return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;\r
 349 }\r
 350 \r
 351 /* Uart divisor latch write */\r
 352 static int serial_dl_write(struct uart_rk_port *up, unsigned int value)\r
 353 {\r
 354         unsigned int tmout = 100;\r
 355 \r
 356         while(!(serial_in(up, UART_LCR) & UART_LCR_DLAB)){\r
 357                 if (--tmout == 0){\r
 358                         if(up->port.line != DBG_PORT)\r
 359                                 dbg("set serial.%d baudrate fail with DLAB not set\n", up->port.line);\r
 360                         return -1;\r
 361                 }\r
 362         }\r
 363 \r
 364         tmout = 15000;\r
 365         while(serial_in(up, UART_USR) & UART_USR_BUSY){\r
 366                 if (--tmout == 0){\r
 367                         if(up->port.line != DBG_PORT)\r
 368                                 dbg("set serial.%d baudrate timeout\n", up->port.line);\r
 369                         return -1;\r
 370                 }\r
 371                 udelay(1);\r
 372         }\r
 373 \r
 374         serial_out(up, UART_DLL, value & 0xff);\r
 375         serial_out(up, UART_DLM, value >> 8 & 0xff);\r
 376 \r
 377         return 0;\r
 378 \r
 379 }\r
 380 \r
 381 static int serial_lcr_write(struct uart_rk_port *up, unsigned char value)\r
 382 {\r
 383         unsigned int tmout = 15000;\r
 384 \r
 385         while(serial_in(up, UART_USR) & UART_USR_BUSY){\r
 386                 if (--tmout == 0){\r
 387                         if(up->port.line != DBG_PORT)\r
 388                                 dbg("set serial.%d lc r = 0x%02x timeout\n", up->port.line, value);\r
 389                         return -1;\r
 390                 }\r
 391                 udelay(1);\r
 392         }\r
 393 \r
 394         serial_out(up, UART_LCR, value);\r
 395 \r
 396         return 0;\r
 397 }\r
 398 \r
 399 static inline void serial_rk_enable_ier_thri(struct uart_rk_port *up)\r
 400 {\r
 401         if (!(up->ier & UART_IER_THRI)) {\r
 402                 up->ier |= UART_IER_THRI;\r
 403                 serial_out(up, UART_IER, up->ier);\r
 404         }\r
 405 }\r
 406 \r
 407 \r
 408 static inline void serial_rk_disable_ier_thri(struct uart_rk_port *up)\r
 409 {\r
 410         if (up->ier & UART_IER_THRI) {\r
 411                 up->ier &= ~UART_IER_THRI;\r
 412                 serial_out(up, UART_IER, up->ier);\r
 413         }\r
 414 }\r
 415 \r
 416 static int rk29_uart_dump_register(struct uart_rk_port *up){\r
 417 \r
 418         unsigned int reg_value = 0;\r
 419 \r
 420         reg_value = serial_in(up, UART_IER);\r
 421         dbg("UART_IER = 0x%0x\n", reg_value);\r
 422         reg_value = serial_in(up, UART_IIR);\r
 423         dbg("UART_IIR = 0x%0x\n", reg_value);\r
 424     reg_value = serial_in(up, UART_LSR);\r
 425     dbg("UART_LSR = 0x%0x\n", reg_value);\r
 426     reg_value = serial_in(up, UART_MSR);\r
 427     dbg("UART_MSR = 0x%0x\n", reg_value);\r
 428     reg_value = serial_in(up, UART_MCR);\r
 429     dbg("UART_MCR = 0x%0x\n", reg_value);\r
 430     reg_value = serial_in(up, 0x21);\r
 431     dbg("UART_RFL = 0x%0x\n", reg_value);\r
 432     reg_value = serial_in(up, UART_LCR);\r
 433     dbg("UART_LCR = 0x%0x\n", reg_value);\r
 434         return 0;\r
 435 \r
 436 }\r
 437 \r
 438 /*\r
 439  * FIFO support.\r
 440  */\r
 441 static void serial_rk_clear_fifos(struct uart_rk_port *up)\r
 442 {\r
 443         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);\r
 444         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |\r
 445                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);\r
 446         serial_out(up, UART_FCR, 0);\r
 447 }\r
 448 \r
 449 static inline void __stop_tx(struct uart_rk_port *p)\r
 450 {\r
 451         if (p->ier & UART_IER_THRI) {\r
 452                 p->ier &= ~UART_IER_THRI;\r
 453                 serial_out(p, UART_IER, p->ier);\r
 454         }\r
 455 }\r
 456 \r
 457 static void serial_rk_stop_tx(struct uart_port *port)\r
 458 {\r
 459         struct uart_rk_port *up =\r
 460                 container_of(port, struct uart_rk_port, port);\r
 461 #if USE_DMA\r
 462         struct rk_uart_dma *uart_dma = up->dma;\r
 463         if(uart_dma->use_dma & TX_DMA){\r
 464                 serial_rk_release_dma_tx(port);\r
 465         }\r
 466 #endif\r
 467         __stop_tx(up);\r
 468 \r
 469 }\r
 470 \r
 471 \r
 472 static void serial_rk_start_tx(struct uart_port *port)\r
 473 {\r
 474         struct uart_rk_port *up =\r
 475                 container_of(port, struct uart_rk_port, port);\r
 476 \r
 477 #if USE_DMA\r
 478         if(up->dma->use_dma & TX_DMA) {\r
 479                 if(!up->dma->tx_dma_used)\r
 480                         serial_rk_enable_ier_thri(up);\r
 481         }else {\r
 482                 serial_rk_enable_ier_thri(up);\r
 483         }\r
 484 #else\r
 485         serial_rk_enable_ier_thri(up);\r
 486 #endif\r
 487 }\r
 488 \r
 489 \r
 490 static void serial_rk_stop_rx(struct uart_port *port)\r
 491 {\r
 492         struct uart_rk_port *up =\r
 493                 container_of(port, struct uart_rk_port, port);\r
 494 #if USE_DMA\r
 495         struct rk_uart_dma *uart_dma = up->dma;\r
 496         if(uart_dma->use_dma & RX_DMA){\r
 497                 serial_rk_release_dma_rx(port);\r
 498         }\r
 499 #endif\r
 500         up->ier &= ~UART_IER_RLSI;\r
 501         up->port.read_status_mask &= ~UART_LSR_DR;\r
 502         serial_out(up, UART_IER, up->ier);\r
 503 }\r
 504 \r
 505 \r
 506 static void serial_rk_enable_ms(struct uart_port *port)\r
 507 {\r
 508         /* no MSR capabilities */\r
 509 #if 0\r
 510         struct uart_rk_port *up =\r
 511                 container_of(port, struct uart_rk_port, port);\r
 512 \r
 513         dev_dbg(port->dev, "%s\n", __func__);\r
 514         up->ier |= UART_IER_MSI;\r
 515         serial_out(up, UART_IER, up->ier);\r
 516 #endif\r
 517 }\r
 518 \r
 519 #if USE_WAKEUP\r
 520 static struct uart_wake_up rk29_uart_ports_wakeup[] = {\r
 521                 {UART0_USE_WAKEUP, UART0_SIN, UART0_SOUT},\r
 522                 {UART1_USE_WAKEUP, UART1_SIN, UART1_SOUT},\r
 523                 {UART2_USE_WAKEUP, UART2_SIN, UART2_SOUT},\r
 524                 {UART3_USE_WAKEUP, UART3_SIN, UART3_SOUT},\r
 525 };\r
 526 #endif\r
 527 \r
 528 #if USE_DMA\r
 529 /*\r
 530  * Start transmitting by dma.\r
 531  */\r
 532 #define DMA_SERIAL_BUFFER_SIZE     UART_XMIT_SIZE\r
 533 \r
 534 /* added by hhb@rock-chips.com  for uart dma transfer*/\r
 535 static struct rk_uart_dma rk29_uart_ports_dma[] = {\r
 536                 {UART0_USE_DMA, DMACH_UART0_RX, DMACH_UART0_TX},\r
 537                 {UART1_USE_DMA, DMACH_UART1_RX, DMACH_UART1_TX},\r
 538                 {UART2_USE_DMA, DMACH_UART2_RX, DMACH_UART2_TX},\r
 539                 {UART3_USE_DMA, DMACH_UART3_RX, DMACH_UART3_TX},\r
 540 };\r
 541 \r
 542 \r
 543 /* DMAC PL330 add by hhb@rock-chips.com */\r
 544 static struct rk29_dma_client rk29_uart_dma_client = {\r
 545         .name = "rk-uart-dma",\r
 546 };\r
 547 \r
 548 /*TX*/\r
 549 \r
 550 static void serial_rk_release_dma_tx(struct uart_port *port)\r
 551 {\r
 552         struct uart_rk_port *up =\r
 553                         container_of(port, struct uart_rk_port, port);\r
 554         struct rk_uart_dma *uart_dma = up->dma;\r
 555         if(!port){\r
 556                 return;\r
 557         }\r
 558         if(uart_dma && uart_dma->tx_dma_inited) {\r
 559                 rk29_dma_free(uart_dma->tx_dmach, &rk29_uart_dma_client);\r
 560                 uart_dma->tx_dma_inited = 0;\r
 561                 uart_dma->tx_dma_used = 0;\r
 562         }\r
 563 }\r
 564 \r
 565 /*this function will be called every time after rk29_dma_enqueue() be invoked*/\r
 566 static void serial_rk_dma_txcb(void *buf, int size, enum rk29_dma_buffresult result) {\r
 567         struct uart_port *port = buf;\r
 568         struct uart_rk_port *up = container_of(port, struct uart_rk_port, port);\r
 569         struct circ_buf *xmit = &port->state->xmit;\r
 570 \r
 571         if(result != RK29_RES_OK){\r
 572                 printk(">>>>%s:%d result:%d\n", __func__, __LINE__, result);\r
 573                 up->dma->tx_dma_used = 0;\r
 574                 return;\r
 575         }\r
 576 \r
 577         //spin_lock(&(up->dma->rx_lock));\r
 578         xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);\r
 579         port->icount.tx += size;\r
 580         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)\r
 581                 uart_write_wakeup(&up->port);\r
 582 \r
 583         //spin_lock(&(up->dma->tx_lock));\r
 584         up->dma->tx_dma_used = 0;\r
 585         //spin_unlock(&(up->dma->tx_lock));\r
 586         serial_rk_enable_ier_thri(up);\r
 587         up->port_activity = jiffies;\r
 588 //      dev_info(up->port.dev, "s:%d\n", size);\r
 589 }\r
 590 \r
 591 static int serial_rk_init_dma_tx(struct uart_port *port) {\r
 592 \r
 593         struct uart_rk_port *up =\r
 594                                 container_of(port, struct uart_rk_port, port);\r
 595         struct rk_uart_dma *uart_dma = up->dma;\r
 596 \r
 597         if(!port || !uart_dma){\r
 598                 dev_info(up->port.dev, "serial_rk_init_dma_tx fail\n");\r
 599                 return -1;\r
 600         }\r
 601 \r
 602         if(uart_dma->tx_dma_inited) {\r
 603                 return 0;\r
 604         }\r
 605 \r
 606         if (rk29_dma_request(uart_dma->tx_dmach, &rk29_uart_dma_client, NULL) == -EBUSY) {\r
 607                 dev_info(up->port.dev, "rk29_dma_request tx fail\n");\r
 608                 return -1;\r
 609         }\r
 610 \r
 611         if (rk29_dma_set_buffdone_fn(uart_dma->tx_dmach, serial_rk_dma_txcb)) {\r
 612                 dev_info(up->port.dev, "rk29_dma_set_buffdone_fn tx fail\n");\r
 613                 return -1;\r
 614         }\r
 615         \r
 616         if (rk29_dma_devconfig(uart_dma->tx_dmach, RK29_DMASRC_MEM, (unsigned long)(port->iobase + UART_TX))) {\r
 617                 dev_info(up->port.dev, "rk29_dma_devconfig tx fail\n");\r
 618                 return -1;\r
 619         }\r
 620         \r
 621         if (rk29_dma_config(uart_dma->tx_dmach, 1, 16)) {\r
 622                 dev_info(up->port.dev, "rk29_dma_config tx fail\n");\r
 623                 return -1;\r
 624         }\r
 625 \r
 626         uart_dma->tx_dma_inited = 1;\r
 627         dev_info(up->port.dev, "serial_rk_init_dma_tx sucess\n");\r
 628         return 0;\r
 629 \r
 630 }\r
 631 \r
 632 static int serial_rk_start_tx_dma(struct uart_port *port)\r
 633 {\r
 634         int count = 0;\r
 635         struct circ_buf *xmit = &port->state->xmit;\r
 636         struct uart_rk_port *up = container_of(port, struct uart_rk_port, port);\r
 637         struct rk_uart_dma *uart_dma = up->dma;\r
 638 \r
 639         if(!uart_dma->use_dma)\r
 640                 goto err_out;\r
 641 \r
 642         if(-1 == serial_rk_init_dma_tx(port))\r
 643                 goto err_out;\r
 644 \r
 645         if (1 == uart_dma->tx_dma_used)\r
 646                 return 1;\r
 647 \r
 648 //      spin_lock(&(uart_dma->tx_lock));\r
 649         __stop_tx(up);\r
 650 \r
 651         count = SERIAL_CIRC_CNT_TO_END(xmit);\r
 652         count -= count%16;\r
 653         if(count >= DMA_TX_TRRIGE_LEVEL) {\r
 654                 if (rk29_dma_enqueue(uart_dma->tx_dmach, port, uart_dma->tx_phy_addr + xmit->tail , count)) {\r
 655                         goto err_out;\r
 656                 }\r
 657                 rk29_dma_ctrl(uart_dma->tx_dmach, RK29_DMAOP_START);\r
 658                 up->dma->tx_dma_used = 1;\r
 659         }\r
 660 //      spin_unlock(&(uart_dma->tx_lock));\r
 661         return 1;\r
 662 err_out:\r
 663         dev_info(up->port.dev, "-serial_rk_start_tx_dma-error-\n");\r
 664         return -1;\r
 665 }\r
 666 \r
 667 \r
 668 \r
 669 /*RX*/\r
 670 static void serial_rk_dma_rxcb(void *buf, int size, enum rk29_dma_buffresult result) {\r
 671 \r
 672         //printk(">>%s:%d\n", __func__, result);\r
 673 }\r
 674 \r
 675 static void serial_rk_release_dma_rx(struct uart_port *port)\r
 676 {\r
 677         struct uart_rk_port *up =\r
 678                                 container_of(port, struct uart_rk_port, port);\r
 679         struct rk_uart_dma *uart_dma = up->dma;\r
 680         \r
 681         if(!port){\r
 682                 return;\r
 683         }\r
 684         \r
 685         if(uart_dma && uart_dma->rx_dma_inited) {\r
 686                 del_timer(&uart_dma->rx_timer);\r
 687                 rk29_dma_free(uart_dma->rx_dmach, &rk29_uart_dma_client);\r
 688                 uart_dma->rb_tail = 0;\r
 689                 uart_dma->rx_dma_inited = 0;\r
 690                 uart_dma->rx_dma_used = 0;\r
 691         }\r
 692 }\r
 693 \r
 694 \r
 695 static int serial_rk_init_dma_rx(struct uart_port *port) {\r
 696 \r
 697         struct uart_rk_port *up =\r
 698                                 container_of(port, struct uart_rk_port, port);\r
 699         struct rk_uart_dma *uart_dma = up->dma;\r
 700 \r
 701         if(!port || !uart_dma){\r
 702                 dev_info(up->port.dev, "serial_rk_init_dma_rx: port fail\n");\r
 703                 return -1;\r
 704         }\r
 705 \r
 706         if(uart_dma->rx_dma_inited) {\r
 707                 return 0;\r
 708         }\r
 709 \r
 710         if (rk29_dma_request(uart_dma->rx_dmach, &rk29_uart_dma_client, NULL) == -EBUSY) {\r
 711                 dev_info(up->port.dev, "rk29_dma_request fail rx \n");\r
 712                 return -1;\r
 713         }\r
 714 \r
 715         if (rk29_dma_set_buffdone_fn(uart_dma->rx_dmach, serial_rk_dma_rxcb)) {\r
 716                 dev_info(up->port.dev, "rk29_dma_set_buffdone_fn rx fail\n");\r
 717                 return -1;\r
 718         }\r
 719 \r
 720         if (rk29_dma_devconfig(uart_dma->rx_dmach, RK29_DMASRC_HW, (unsigned long)(port->iobase + UART_RX))) {\r
 721                 dev_info(up->port.dev, "rk29_dma_devconfig rx fail\n");\r
 722                 return -1;\r
 723         }\r
 724 \r
 725         if (rk29_dma_config(uart_dma->rx_dmach, 1, 1)) {\r
 726                 dev_info(up->port.dev, "rk29_dma_config rx fail 1 1 \n");\r
 727                 return -1;\r
 728         }\r
 729 \r
 730         //rk29_dma_setflags(uart_dma->rx_dmach, RK29_DMAF_CIRCULAR);\r
 731 \r
 732         uart_dma->rx_dma_inited = 1;\r
 733         dev_info(up->port.dev, "serial_rk_init_dma_rx sucess\n");\r
 734         return 0;\r
 735 \r
 736 }\r
 737 \r
 738 static int serial_rk_start_rx_dma(struct uart_port *port)\r
 739 {\r
 740         struct uart_rk_port *up =\r
 741                                 container_of(port, struct uart_rk_port, port);\r
 742         struct rk_uart_dma *uart_dma = up->dma;\r
 743         if(!uart_dma->use_dma)\r
 744                 return 0;\r
 745 \r
 746         if(uart_dma->rx_dma_used == 1)\r
 747                 return 0;\r
 748 \r
 749         if(-1 == serial_rk_init_dma_rx(port)){\r
 750                 dev_info(up->port.dev, "*******serial_rk_init_dma_rx*******error*******\n");\r
 751                 return -1;\r
 752         }\r
 753         \r
 754 #if 0   \r
 755                 if (rk29_dma_enqueue(uart_dma->rx_dmach, (void *)up, uart_dma->rx_phy_addr,\r
 756                                 uart_dma->rb_size/2)) {\r
 757                         dev_info(up->port.dev, "*******rk29_dma_enqueue fail*****\n");\r
 758                         return -1;\r
 759                 }\r
 760 \r
 761                 if (rk29_dma_enqueue(uart_dma->rx_dmach, (void *)up,\r
 762                                 uart_dma->rx_phy_addr+uart_dma->rb_size/2, uart_dma->rb_size/2)) {\r
 763                         dev_info(up->port.dev, "*******rk29_dma_enqueue fail*****\n");\r
 764                         return -1;\r
 765                 }\r
 766 \r
 767 #else\r
 768         rk29_dma_enqueue_ring(uart_dma->rx_dmach, (void *)up, uart_dma->rx_phy_addr, uart_dma->rb_size/4, 4, false);\r
 769 #endif\r
 770         rk29_dma_ctrl(uart_dma->rx_dmach, RK29_DMAOP_START);\r
 771         uart_dma->rx_dma_used = 1;\r
 772         if(uart_dma->use_timer == 1){\r
 773                 mod_timer(&uart_dma->rx_timer, jiffies + msecs_to_jiffies(uart_dma->rx_timeout));\r
 774         }\r
 775         up->port_activity = jiffies;\r
 776         return 1;\r
 777 }\r
 778 \r
 779 static void serial_rk_update_rb_addr(struct uart_rk_port *up){\r
 780         dma_addr_t current_pos = 0;\r
 781         dma_addr_t rx_current_pos = 0;\r
 782         struct rk_uart_dma *uart_dma = up->dma;\r
 783         //spin_lock(&(up->dma->rx_lock));\r
 784         uart_dma->rx_size = 0;\r
 785         if(uart_dma->rx_dma_used == 1){\r
 786                 rk29_dma_getposition(uart_dma->rx_dmach, &current_pos, &rx_current_pos);\r
 787                 uart_dma->rb_head = (rx_current_pos - uart_dma->rx_phy_addr);\r
 788                 uart_dma->rx_size = CIRC_CNT(uart_dma->rb_head, uart_dma->rb_tail, uart_dma->rb_size);\r
 789         }\r
 790         //spin_unlock(&(up->dma->rx_lock));\r
 791 }\r
 792 \r
 793 static void serial_rk_report_dma_rx(unsigned long uart)\r
 794 {\r
 795         int count, flip = 0;\r
 796         struct uart_rk_port *up = (struct uart_rk_port *)uart;\r
 797         struct rk_uart_dma *uart_dma = up->dma;\r
 798 \r
 799         if(!uart_dma->rx_dma_used || !up->port.state->port.tty)\r
 800                 return;\r
 801 \r
 802         serial_rk_update_rb_addr(up);\r
 803 \r
 804         while(1) {\r
 805                 count = CIRC_CNT_TO_END(uart_dma->rb_head, uart_dma->rb_tail, uart_dma->rb_size);\r
 806                 if(count <= 0)\r
 807                         break;\r
 808                 up->port.icount.rx += count;\r
 809                 flip = tty_insert_flip_string(up->port.state->port.tty, uart_dma->rx_buffer\r
 810                                 + uart_dma->rb_tail, count);\r
 811                 tty_flip_buffer_push(up->port.state->port.tty);\r
 812                 uart_dma->rb_tail = (uart_dma->rb_tail + count) & (uart_dma->rb_size - 1);\r
 813                 up->port_activity = jiffies;\r
 814         }\r
 815 \r
 816         //if (uart_dma->rx_size > 0)\r
 817         //      printk("rx_size:%d ADDR:%x\n", uart_dma->rx_size, uart_dma->rb_head);\r
 818 \r
 819         if(uart_dma->use_timer == 1){\r
 820                 mod_timer(&uart_dma->rx_timer, jiffies + msecs_to_jiffies(uart_dma->rx_timeout));\r
 821         }\r
 822 \r
 823 }\r
 824 #if 0\r
 825 static void serial_rk_rx_timeout(unsigned long uart)\r
 826 {\r
 827         struct uart_rk_port *up = (struct uart_rk_port *)uart;\r
 828 \r
 829         serial_rk_report_dma_rx(up);\r
 830         //queue_work(up->uart_wq, &up->uart_work);\r
 831 }\r
 832 \r
 833 static void serial_rk_report_revdata_workfunc(struct work_struct *work)\r
 834 {\r
 835         struct uart_rk_port *up =\r
 836                                 container_of(work, struct uart_rk_port, uart_work);\r
 837 \r
 838         serial_rk_report_dma_rx((unsigned long)up);\r
 839 \r
 840         //spin_lock(&(up->dma->rx_lock));\r
 841 \r
 842         if(up->port.state->port.tty && up->dma->use_timer != 1 && up->fifo_size > 0){\r
 843 \r
 844                 tty_insert_flip_string(up->port.state->port.tty, up->fifo, up->fifo_size);\r
 845                 tty_flip_buffer_push(up->port.state->port.tty);\r
 846                 up->port.icount.rx += up->fifo_size;\r
 847                 up->ier |= UART_IER_RDI;\r
 848                 serial_out(up, UART_IER, up->ier);\r
 849         }\r
 850 \r
 851         //spin_unlock(&(up->dma->rx_lock));\r
 852 \r
 853 }\r
 854 \r
 855 \r
 856 static void serial_rk_start_dma_rx(struct work_struct *work)\r
 857 {\r
 858         struct uart_rk_port *up =\r
 859                                         container_of(work, struct uart_rk_port, uart_work_rx);\r
 860 \r
 861         //mod_timer(&up->dma->rx_timer, jiffies + msecs_to_jiffies(up->dma->rx_timeout));\r
 862         //rk29_dma_ctrl(up->dma->rx_dmach, RK29_DMAOP_START);\r
 863         //serial_rk_start_rx_dma(&up->port);\r
 864 \r
 865 }\r
 866 #endif\r
 867 \r
 868 #endif /* USE_DMA */\r
 869 \r
 870 \r
 871 static void\r
 872 receive_chars(struct uart_rk_port *up, unsigned int *status)\r
 873 {\r
 874         struct tty_struct *tty = up->port.state->port.tty;\r
 875         unsigned char ch, lsr = *status;\r
 876         int max_count = 256;\r
 877         char flag;\r
 878 \r
 879         do {\r
 880                 if (likely(lsr & UART_LSR_DR)){\r
 881                         ch = serial_in(up, UART_RX);\r
 882                 }\r
 883                 else\r
 884                         /*\r
 885                          * Intel 82571 has a Serial Over Lan device that will\r
 886                          * set UART_LSR_BI without setting UART_LSR_DR when\r
 887                          * it receives a break. To avoid reading from the\r
 888                          * receive buffer without UART_LSR_DR bit set, we\r
 889                          * just force the read character to be 0\r
 890                          */\r
 891                         ch = 0;\r
 892 \r
 893                 flag = TTY_NORMAL;\r
 894                 up->port.icount.rx++;\r
 895 \r
 896                 lsr |= up->lsr_saved_flags;\r
 897                 up->lsr_saved_flags = 0;\r
 898 \r
 899                 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {\r
 900                         /*\r
 901                          * For statistics only\r
 902                          */\r
 903                         if (lsr & UART_LSR_BI) {\r
 904                                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);\r
 905                                 up->port.icount.brk++;\r
 906                                 /*\r
 907                                  * We do the SysRQ and SAK checking\r
 908                                  * here because otherwise the break\r
 909                                  * may get masked by ignore_status_mask\r
 910                                  * or read_status_mask.\r
 911                                  */\r
 912                                 if (uart_handle_break(&up->port))\r
 913                                         goto ignore_char;\r
 914                         } else if (lsr & UART_LSR_PE)\r
 915                                 up->port.icount.parity++;\r
 916                         else if (lsr & UART_LSR_FE)\r
 917                                 up->port.icount.frame++;\r
 918                         if (lsr & UART_LSR_OE)\r
 919                                 up->port.icount.overrun++;\r
 920 \r
 921 \r
 922                         /*\r
 923                          * Mask off conditions which should be ignored.\r
 924                          */\r
 925                         lsr &= up->port.read_status_mask;\r
 926 \r
 927                         if (lsr & UART_LSR_BI) {\r
 928                                 DEBUG_INTR("handling break....");\r
 929                                 flag = TTY_BREAK;\r
 930                         } else if (lsr & UART_LSR_PE)\r
 931                                 flag = TTY_PARITY;\r
 932                         else if (lsr & UART_LSR_FE)\r
 933                                 flag = TTY_FRAME;\r
 934                 }\r
 935                 if (uart_handle_sysrq_char(&up->port, ch))\r
 936                         goto ignore_char;\r
 937 \r
 938                 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);\r
 939 \r
 940 ignore_char:\r
 941                 lsr = serial_in(up, UART_LSR);\r
 942         } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));\r
 943         spin_unlock(&up->port.lock);\r
 944         tty_flip_buffer_push(tty);\r
 945         spin_lock(&up->port.lock);\r
 946         *status = lsr;\r
 947 }\r
 948 \r
 949 static void transmit_chars(struct uart_rk_port *up)\r
 950 {\r
 951         struct circ_buf *xmit = &up->port.state->xmit;\r
 952         int count;\r
 953 \r
 954         if (up->port.x_char) {\r
 955                 serial_out(up, UART_TX, up->port.x_char);\r
 956                 up->port.icount.tx++;\r
 957                 up->port.x_char = 0;\r
 958                 return;\r
 959         }\r
 960         if (uart_tx_stopped(&up->port)) {\r
 961                 __stop_tx(up);\r
 962                 return;\r
 963         }\r
 964         if (uart_circ_empty(xmit)) {\r
 965                 __stop_tx(up);\r
 966                 return;\r
 967         }\r
 968 #if USE_DMA\r
 969         //hhb\r
 970         if(up->dma->use_dma & TX_DMA){\r
 971                 if(SERIAL_CIRC_CNT_TO_END(xmit) >= DMA_TX_TRRIGE_LEVEL){\r
 972                         serial_rk_start_tx_dma(&up->port);\r
 973                         return;\r
 974                 }\r
 975         }\r
 976 #endif\r
 977         count = up->port.fifosize - serial_in(up , 0x20);\r
 978         do {\r
 979                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);\r
 980                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);\r
 981                 up->port.icount.tx++;\r
 982                 if (uart_circ_empty(xmit))\r
 983                         break;\r
 984         } while (--count > 0);\r
 985 \r
 986         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)\r
 987                 uart_write_wakeup(&up->port);\r
 988 \r
 989         DEBUG_INTR("THRE...");\r
 990 #if USE_DMA\r
 991         up->port_activity = jiffies;\r
 992 #endif\r
 993         if (uart_circ_empty(xmit))\r
 994                 __stop_tx(up);\r
 995 }\r
 996 \r
 997 static unsigned int check_modem_status(struct uart_rk_port *up)\r
 998 {\r
 999         unsigned int status = serial_in(up, UART_MSR);\r
1000 \r
1001 #if 0\r
1002         status |= up->msr_saved_flags;\r
1003         up->msr_saved_flags = 0;\r
1004         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&\r
1005             up->port.state != NULL) {\r
1006                 if (status & UART_MSR_TERI)\r
1007                         up->port.icount.rng++;\r
1008                 if (status & UART_MSR_DDSR)\r
1009                         up->port.icount.dsr++;\r
1010                 if (status & UART_MSR_DDCD)\r
1011                         uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);\r
1012                 if (status & UART_MSR_DCTS)\r
1013                         uart_handle_cts_change(&up->port, status & UART_MSR_CTS);\r
1014 \r
1015                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);\r
1016         }\r
1017 #endif\r
1018 \r
1019         return status;\r
1020 }\r
1021 \r
1022 \r
1023 /*\r
1024  * This handles the interrupt from one port.\r
1025  */\r
1026 static void serial_rk_handle_port(struct uart_rk_port *up)\r
1027 {\r
1028         unsigned int status;\r
1029         unsigned long flags;\r
1030         spin_lock_irqsave(&up->port.lock, flags);\r
1031 \r
1032         /* reading UART_LSR can automatically clears PE FE OE bits, except receive fifo error bit*/\r
1033         status = serial_in(up, UART_LSR);\r
1034 \r
1035         DEBUG_INTR("status = %x...\n", status);\r
1036 #if USE_DMA\r
1037         /* DMA mode enable */\r
1038         if(up->dma->use_dma) {\r
1039 \r
1040                 if (status & UART_LSR_RFE) {\r
1041                         if(up->port.line != DBG_PORT){\r
1042                                 dev_info(up->port.dev, "error:lsr=0x%x\n", status);\r
1043                                 status = serial_in(up, UART_LSR);\r
1044                                 DEBUG_INTR("error:lsr=0x%x\n", status);\r
1045                         }\r
1046                 }\r
1047 \r
1048                 if (status & 0x02) {\r
1049                         if(up->port.line != DBG_PORT){\r
1050                                 dev_info(up->port.dev, "error:lsr=0x%x\n", status);\r
1051                                 status = serial_in(up, UART_LSR);\r
1052                                 DEBUG_INTR("error:lsr=0x%x\n", status);\r
1053                         }\r
1054                 }\r
1055 \r
1056                 if(!(up->dma->use_dma & RX_DMA)) {\r
1057                         if (status & (UART_LSR_DR | UART_LSR_BI)) {\r
1058                                 receive_chars(up, &status);\r
1059                         }\r
1060                 }\r
1061 \r
1062                 if ((up->iir & 0x0f) == 0x02) {\r
1063                         transmit_chars(up);\r
1064                 }\r
1065         } else \r
1066 #endif\r
1067         {   //dma mode disable\r
1068 \r
1069                 /*\r
1070                  * when uart receive a serial of data which doesn't have stop bit and so on, that causes frame error,and\r
1071                  * set UART_LSR_RFE to one,what is worse,we couldn't read the data in the receive fifo. So if\r
1072                  * wo don't clear this bit and reset the receive fifo, the received data available interrupt would\r
1073                  * occur continuously.  added by hhb@rock-chips.com 2011-08-05\r
1074                  */\r
1075 \r
1076                 if (status & UART_LSR_RFE) {\r
1077                         if(up->port.line != DBG_PORT){\r
1078                                 dev_info(up->port.dev, "error:lsr=0x%x\n", status);\r
1079                                 status = serial_in(up, UART_LSR);\r
1080                                 DEBUG_INTR("error:lsr=0x%x\n", status);\r
1081                                 rk29_uart_dump_register(up);\r
1082                         }\r
1083                 }\r
1084 \r
1085                 if (status & (UART_LSR_DR | UART_LSR_BI)) {\r
1086                         receive_chars(up, &status);\r
1087                 }\r
1088                 check_modem_status(up);\r
1089                 //hhb@rock-chips.com when FIFO and THRE mode both are enabled,and FIFO TX empty trigger is set to larger than 1,\r
1090                 //,we need to add ((up->iir & 0x0f) == 0x02) to transmit_chars,because when entering interrupt,the FIFO and THR\r
1091                 //might not be 1.\r
1092                 if ((up->iir & 0x0f) == 0x02) {\r
1093                         transmit_chars(up);\r
1094                 }\r
1095         }\r
1096         spin_unlock_irqrestore(&up->port.lock, flags);\r
1097 }\r
1098 \r
1099 /*\r
1100  * This is the serial driver's interrupt routine.\r
1101  */\r
1102 \r
1103 static irqreturn_t serial_rk_interrupt(int irq, void *dev_id)\r
1104 {\r
1105         struct uart_rk_port *up = dev_id;\r
1106         int handled = 0;\r
1107         unsigned int iir;\r
1108 \r
1109         iir = serial_in(up, UART_IIR);\r
1110 \r
1111         DEBUG_INTR("%s(%d) iir = 0x%02x\n", __func__, irq, iir);\r
1112         up->iir = iir;\r
1113 \r
1114         if (!(iir & UART_IIR_NO_INT)) {\r
1115                 serial_rk_handle_port(up);\r
1116                 handled = 1;\r
1117         } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {\r
1118 \r
1119                 /* The DesignWare APB UART has an Busy Detect (0x07)\r
1120                  * interrupt meaning an LCR write attempt occured while the\r
1121                  * UART was busy. The interrupt must be cleared by reading\r
1122                  * the UART status register (USR) and the LCR re-written. */\r
1123 \r
1124                 if(!(serial_in(up, UART_USR) & UART_USR_BUSY)){\r
1125                         serial_out(up, UART_LCR, up->lcr);\r
1126                 }\r
1127                 handled = 1;\r
1128                 dbg("the serial.%d is busy\n", up->port.line);\r
1129         }\r
1130         DEBUG_INTR("end(%d).\n", handled);\r
1131 \r
1132         return IRQ_RETVAL(handled);\r
1133 }\r
1134 \r
1135 static unsigned int serial_rk_tx_empty(struct uart_port *port)\r
1136 {\r
1137         struct uart_rk_port *up =\r
1138                 container_of(port, struct uart_rk_port, port);\r
1139         unsigned long flags;\r
1140         unsigned int lsr;\r
1141 \r
1142         dev_dbg(port->dev, "%s\n", __func__);\r
1143         spin_lock_irqsave(&up->port.lock, flags);\r
1144         lsr = serial_in(up, UART_LSR);\r
1145         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;\r
1146         spin_unlock_irqrestore(&up->port.lock, flags);\r
1147 \r
1148         return (lsr & UART_LSR_TEMT) == UART_LSR_TEMT ? TIOCSER_TEMT : 0;\r
1149 }\r
1150 \r
1151 static unsigned int serial_rk_get_mctrl(struct uart_port *port)\r
1152 {\r
1153         struct uart_rk_port *up =\r
1154                 container_of(port, struct uart_rk_port, port);\r
1155         unsigned int status;\r
1156         unsigned int ret;\r
1157 \r
1158         status = check_modem_status(up);\r
1159 \r
1160         ret = 0;\r
1161         if (status & UART_MSR_DCD)\r
1162                 ret |= TIOCM_CAR;\r
1163         if (status & UART_MSR_RI)\r
1164                 ret |= TIOCM_RNG;\r
1165         if (status & UART_MSR_DSR)\r
1166                 ret |= TIOCM_DSR;\r
1167         if (status & UART_MSR_CTS)\r
1168                 ret |= TIOCM_CTS;\r
1169         dev_dbg(port->dev, "%s 0x%08x\n", __func__, ret);\r
1170         return ret;\r
1171 }\r
1172 \r
1173 static void serial_rk_set_mctrl(struct uart_port *port, unsigned int mctrl)\r
1174 {\r
1175         struct uart_rk_port *up =\r
1176                 container_of(port, struct uart_rk_port, port);\r
1177         unsigned char mcr = 0;\r
1178 \r
1179         dev_dbg(port->dev, "+%s\n", __func__);\r
1180         if (mctrl & TIOCM_RTS)\r
1181                 mcr |= UART_MCR_RTS;\r
1182         if (mctrl & TIOCM_DTR)\r
1183                 mcr |= UART_MCR_DTR;\r
1184         if (mctrl & TIOCM_OUT1)\r
1185                 mcr |= UART_MCR_OUT1;\r
1186         if (mctrl & TIOCM_OUT2)\r
1187                 mcr |= UART_MCR_OUT2;\r
1188         if (mctrl & TIOCM_LOOP)\r
1189                 mcr |= UART_MCR_LOOP;\r
1190 \r
1191         mcr |= up->mcr;\r
1192 \r
1193         serial_out(up, UART_MCR, mcr);\r
1194         dev_dbg(port->dev, "-serial.%d %s mcr: 0x%02x\n", port->line, __func__, mcr);\r
1195 }\r
1196 \r
1197 static void serial_rk_break_ctl(struct uart_port *port, int break_state)\r
1198 {\r
1199         struct uart_rk_port *up =\r
1200                 container_of(port, struct uart_rk_port, port);\r
1201         unsigned long flags;\r
1202 \r
1203         dev_dbg(port->dev, "+%s\n", __func__);\r
1204         spin_lock_irqsave(&up->port.lock, flags);\r
1205         if (break_state == -1)\r
1206                 up->lcr |= UART_LCR_SBC;\r
1207         else\r
1208                 up->lcr &= ~UART_LCR_SBC;\r
1209         serial_lcr_write(up, up->lcr);\r
1210         spin_unlock_irqrestore(&up->port.lock, flags);\r
1211         dev_dbg(port->dev, "-%s lcr: 0x%02x\n", __func__, up->lcr);\r
1212 }\r
1213 \r
1214 #if defined(CONFIG_SERIAL_RK_CONSOLE) || defined(CONFIG_CONSOLE_POLL)\r
1215 /*\r
1216  *      Wait for transmitter & holding register to empty\r
1217  */\r
1218 static void wait_for_xmitr(struct uart_rk_port *up, int bits)\r
1219 {\r
1220         unsigned int status, tmout = 10000;\r
1221 \r
1222         /* Wait up to 10ms for the character(s) to be sent. */\r
1223         for (;;) {\r
1224                 status = serial_in(up, UART_LSR);\r
1225 \r
1226                 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;\r
1227 \r
1228                 if ((status & bits) == bits)\r
1229                         break;\r
1230                 if (--tmout == 0)\r
1231                         break;\r
1232                 udelay(1);\r
1233         }\r
1234 }\r
1235 #endif\r
1236 \r
1237 #ifdef CONFIG_CONSOLE_POLL\r
1238 /*\r
1239  * Console polling routines for writing and reading from the uart while\r
1240  * in an interrupt or debug context.\r
1241  */\r
1242 \r
1243 static int serial_rk_get_poll_char(struct uart_port *port)\r
1244 {\r
1245         struct uart_rk_port *up =\r
1246                 container_of(port, struct uart_rk_port, port);\r
1247         unsigned char lsr = serial_in(up, UART_LSR);\r
1248 \r
1249         while (!(lsr & UART_LSR_DR))\r
1250                 lsr = serial_in(up, UART_LSR);\r
1251 \r
1252         return serial_in(up, UART_RX);\r
1253 }\r
1254 \r
1255 static void serial_rk_put_poll_char(struct uart_port *port,\r
1256                          unsigned char c)\r
1257 {\r
1258         unsigned int ier;\r
1259         struct uart_rk_port *up =\r
1260                 container_of(port, struct uart_rk_port, port);\r
1261 \r
1262         /*\r
1263          *      First save the IER then disable the interrupts\r
1264          */\r
1265         ier = serial_in(up, UART_IER);\r
1266         serial_out(up, UART_IER, 0);\r
1267 \r
1268         wait_for_xmitr(up, UART_LSR_TEMT);\r
1269         /*\r
1270          *      Send the character out.\r
1271          *      If a LF, also do CR...\r
1272          */\r
1273         serial_out(up, UART_TX, c);\r
1274         if (c == 10) {\r
1275                 wait_for_xmitr(up, UART_LSR_TEMT);\r
1276                 serial_out(up, UART_TX, 13);\r
1277         }\r
1278 \r
1279         /*\r
1280          *      Finally, wait for transmitter to become empty\r
1281          *      and restore the IER\r
1282          */\r
1283         wait_for_xmitr(up, UART_LSR_TEMT);\r
1284         serial_out(up, UART_IER, ier);\r
1285 }\r
1286 \r
1287 #endif /* CONFIG_CONSOLE_POLL */\r
1288 \r
1289 static int serial_rk_startup(struct uart_port *port)\r
1290 {\r
1291         struct uart_rk_port *up =\r
1292                 container_of(port, struct uart_rk_port, port);\r
1293         unsigned long flags;\r
1294         int retval, fifosize = 0;\r
1295         \r
1296 \r
1297         dev_dbg(port->dev, "%s\n", __func__);\r
1298 \r
1299         /*\r
1300          * Allocate the IRQ\r
1301          */\r
1302         retval = request_irq(up->port.irq, serial_rk_interrupt, up->port.irqflags,\r
1303                                 up->name, up);\r
1304         if (retval)\r
1305                 return retval;\r
1306 \r
1307         up->mcr = 0;\r
1308 \r
1309         clk_enable(up->pclk);\r
1310         clk_enable(up->clk);  // enable the config uart clock\r
1311 \r
1312         /*\r
1313          * Clear the FIFO buffers and disable them.\r
1314          * (they will be reenabled in set_termios())\r
1315          */\r
1316         serial_rk_clear_fifos(up);\r
1317 \r
1318         //read uart fifo size  hhb@rock-chips.com\r
1319         fifosize = __raw_readl(up->port.membase + 0xf4);\r
1320         up->port.fifosize = ((fifosize >> 16) & 0xff) << 4;\r
1321         if(up->port.fifosize <= 0)\r
1322                 up->port.fifosize = 32;\r
1323         //printk("fifo size:%d :%08x\n", up->port.fifosize, fifosize);\r
1324 \r
1325         /*\r
1326          * Clear the interrupt registers.\r
1327          */\r
1328         (void) serial_in(up, UART_LSR);\r
1329         (void) serial_in(up, UART_RX);\r
1330         (void) serial_in(up, UART_IIR);\r
1331         (void) serial_in(up, UART_MSR);\r
1332         (void) serial_in(up, UART_USR);\r
1333 \r
1334         /*\r
1335          * Now, initialize the UART\r
1336          */\r
1337         serial_lcr_write(up, UART_LCR_WLEN8 | UART_LCR_EPAR);\r
1338 \r
1339         spin_lock_irqsave(&up->port.lock, flags);\r
1340 \r
1341         /*\r
1342          * Most PC uarts need OUT2 raised to enable interrupts.\r
1343          */\r
1344 //      up->port.mctrl |= TIOCM_OUT2;\r
1345 \r
1346         serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1347 \r
1348         spin_unlock_irqrestore(&up->port.lock, flags);\r
1349 \r
1350         /*\r
1351          * Clear the interrupt registers again for luck, and clear the\r
1352          * saved flags to avoid getting false values from polling\r
1353          * routines or the previous session.\r
1354          */\r
1355         (void) serial_in(up, UART_LSR);\r
1356         (void) serial_in(up, UART_RX);\r
1357         (void) serial_in(up, UART_IIR);\r
1358         (void) serial_in(up, UART_MSR);\r
1359         (void) serial_in(up, UART_USR);\r
1360         up->lsr_saved_flags = 0;\r
1361 #if 0\r
1362         up->msr_saved_flags = 0;\r
1363 #endif\r
1364 #if USE_DMA\r
1365         if (up->dma->use_dma & TX_DMA) {\r
1366                 if(up->port.state->xmit.buf != up->dma->tx_buffer){\r
1367                         free_page((unsigned long)up->port.state->xmit.buf);\r
1368                         up->port.state->xmit.buf = up->dma->tx_buffer;\r
1369                 }\r
1370         } else \r
1371 #endif\r
1372         {\r
1373                 up->ier = 0;\r
1374                 serial_out(up, UART_IER, up->ier);\r
1375         }\r
1376 \r
1377         /*\r
1378          * Finally, enable interrupts.  Note: Modem status interrupts\r
1379          * are set via set_termios(), which will be occurring imminently\r
1380          * anyway, so we don't enable them here.\r
1381          */\r
1382 \r
1383         return 0;\r
1384 }\r
1385 \r
1386 \r
1387 static void serial_rk_shutdown(struct uart_port *port)\r
1388 {\r
1389         struct uart_rk_port *up =\r
1390                 container_of(port, struct uart_rk_port, port);\r
1391         unsigned long flags;\r
1392 \r
1393         dev_dbg(port->dev, "%s\n", __func__);\r
1394         /*\r
1395          * Disable interrupts from this port\r
1396          */\r
1397         up->ier = 0;\r
1398         serial_out(up, UART_IER, 0);\r
1399 \r
1400         spin_lock_irqsave(&up->port.lock, flags);\r
1401 //      up->port.mctrl &= ~TIOCM_OUT2;\r
1402         serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1403         spin_unlock_irqrestore(&up->port.lock, flags);\r
1404 \r
1405         /*\r
1406          * Disable break condition and FIFOs\r
1407          */\r
1408         serial_lcr_write(up, serial_in(up, UART_LCR) & ~UART_LCR_SBC);\r
1409         serial_rk_clear_fifos(up);\r
1410 \r
1411         /*\r
1412          * Read data port to reset things, and then free the irq\r
1413          */\r
1414         (void) serial_in(up, UART_RX);\r
1415 #if USE_DMA\r
1416         if (up->dma->use_dma & TX_DMA)\r
1417                 up->port.state->xmit.buf = NULL;\r
1418 #endif\r
1419         free_irq(up->port.irq, up);\r
1420         clk_disable(up->clk);\r
1421         clk_disable(up->pclk);\r
1422 }\r
1423 \r
1424 static void\r
1425 serial_rk_set_termios(struct uart_port *port, struct ktermios *termios,\r
1426                       struct ktermios *old)\r
1427 {\r
1428         struct uart_rk_port *up =\r
1429                 container_of(port, struct uart_rk_port, port);\r
1430         unsigned char cval = 0, fcr = 0, mcr = 0;\r
1431         unsigned long flags;\r
1432         unsigned int baud, quot;\r
1433         dev_dbg(port->dev, "+%s\n", __func__);\r
1434 \r
1435         switch (termios->c_cflag & CSIZE) {\r
1436         case CS5:\r
1437                 cval = UART_LCR_WLEN5;\r
1438                 break;\r
1439         case CS6:\r
1440                 cval = UART_LCR_WLEN6;\r
1441                 break;\r
1442         case CS7:\r
1443                 cval = UART_LCR_WLEN7;\r
1444                 break;\r
1445         case CS8:\r
1446         default:\r
1447                 cval = UART_LCR_WLEN8;\r
1448                 break;\r
1449         }\r
1450 \r
1451         if (termios->c_cflag & CSTOPB){\r
1452                 cval |= UART_LCR_STOP;\r
1453         }\r
1454         if (termios->c_cflag & PARENB){\r
1455                 cval |= UART_LCR_PARITY;\r
1456         }\r
1457         if (!(termios->c_cflag & PARODD)){\r
1458                 cval |= UART_LCR_EPAR;\r
1459         }\r
1460 #ifdef CMSPAR\r
1461         if (termios->c_cflag & CMSPAR)\r
1462                 cval |= UART_LCR_SPAR;\r
1463 #endif\r
1464 \r
1465 \r
1466         /*\r
1467          * Ask the core to calculate the divisor for us.\r
1468          */\r
1469         baud = uart_get_baud_rate(port, termios, old,\r
1470                                   port->uartclk / 16 / 0xffff,\r
1471                                   port->uartclk / 16);\r
1472 \r
1473         quot = uart_get_divisor(port, baud);\r
1474         //dev_info(up->port.dev, "uartclk:%d\n", port->uartclk/16);\r
1475         //dev_info(up->port.dev, "baud:%d\n", baud);\r
1476         //dev_info(up->port.dev, "quot:%d\n", quot);\r
1477 \r
1478         if (baud < 2400){\r
1479                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;\r
1480         }\r
1481         else{\r
1482                 fcr = UART_FCR_ENABLE_FIFO;\r
1483 #if USE_DMA\r
1484                 //added by hhb@rock-chips.com\r
1485                 if(up->dma->use_dma & TX_DMA){\r
1486                         fcr |= UART_FCR_T_TRIG_01;\r
1487                 } else\r
1488 #endif\r
1489                 {\r
1490                         fcr |= UART_FCR_T_TRIG_01;\r
1491                 }\r
1492 \r
1493 #if USE_DMA\r
1494                 //added by hhb@rock-chips.com\r
1495                 if(up->dma->use_dma & RX_DMA){  \r
1496                         fcr |= UART_FCR_R_TRIG_00;\r
1497                 } else\r
1498 #endif\r
1499                 {\r
1500                         if (termios->c_cflag & CRTSCTS)\r
1501                                 fcr |= UART_FCR_R_TRIG_11;\r
1502                         else\r
1503                                 fcr |= UART_FCR_R_TRIG_00;\r
1504                 }\r
1505         }\r
1506 \r
1507         /*\r
1508          * MCR-based auto flow control.  When AFE is enabled, RTS will be\r
1509          * deasserted when the receive FIFO contains more characters than\r
1510          * the trigger, or the MCR RTS bit is cleared.  In the case where\r
1511          * the remote UART is not using CTS auto flow control, we must\r
1512          * have sufficient FIFO entries for the latency of the remote\r
1513          * UART to respond.  IOW, at least 32 bytes of FIFO.\r
1514          */\r
1515         up->mcr &= ~UART_MCR_AFE;\r
1516         if (termios->c_cflag & CRTSCTS){\r
1517                 up->mcr |= UART_MCR_AFE;\r
1518         }\r
1519 \r
1520         /*\r
1521          * Ok, we're now changing the port state.  Do it with\r
1522          * interrupts disabled.\r
1523          */\r
1524         spin_lock_irqsave(&up->port.lock, flags);\r
1525 \r
1526         /*\r
1527          * Update the per-port timeout.\r
1528          */\r
1529         uart_update_timeout(port, termios->c_cflag, baud);\r
1530 \r
1531         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;\r
1532         if (termios->c_iflag & INPCK)\r
1533                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;\r
1534         if (termios->c_iflag & (BRKINT | PARMRK))\r
1535                 up->port.read_status_mask |= UART_LSR_BI;\r
1536 \r
1537         /*\r
1538          * Characteres to ignore\r
1539          */\r
1540         up->port.ignore_status_mask = 0;\r
1541         if (termios->c_iflag & IGNPAR)\r
1542                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;\r
1543         if (termios->c_iflag & IGNBRK) {\r
1544                 up->port.ignore_status_mask |= UART_LSR_BI;\r
1545                 /*\r
1546                  * If we're ignoring parity and break indicators,\r
1547                  * ignore overruns too (for real raw support).\r
1548                  */\r
1549                 if (termios->c_iflag & IGNPAR)\r
1550                         up->port.ignore_status_mask |= UART_LSR_OE;\r
1551         }\r
1552 \r
1553         /*\r
1554          * ignore all characters if CREAD is not set\r
1555          */\r
1556         if ((termios->c_cflag & CREAD) == 0)\r
1557                 up->port.ignore_status_mask |= UART_LSR_DR;\r
1558 \r
1559         /*\r
1560          * CTS flow control flag and modem status interrupts\r
1561          */\r
1562         up->ier &= ~UART_IER_MSI;\r
1563 #if 0\r
1564         if (UART_ENABLE_MS(&up->port, termios->c_cflag))\r
1565                 up->ier |= UART_IER_MSI;\r
1566 #endif\r
1567 \r
1568         //to avoid uart busy when set baud rate  hhb@rock-chips.com\r
1569         serial_out(up, UART_SRR, UART_RESET);\r
1570         mcr = serial_in(up, UART_MCR);\r
1571         serial_out(up, UART_MCR, mcr | 0x10);  //loopback mode\r
1572         \r
1573         up->lcr = cval;                         /* Save LCR */\r
1574         /* set DLAB */\r
1575         if(serial_lcr_write(up, cval | UART_LCR_DLAB)) {\r
1576                 if(up->port.line != DBG_PORT)\r
1577                         dbg("serial.%d set DLAB fail\n", up->port.line);\r
1578                 serial_out(up, UART_SRR, UART_RESET);\r
1579                 goto fail;\r
1580         }\r
1581 \r
1582         /* set uart baud rate */\r
1583         if(serial_dl_write(up, quot)) {\r
1584                 if(up->port.line != DBG_PORT)\r
1585                         dbg("serial.%d set dll fail\n", up->port.line);\r
1586                 serial_out(up, UART_SRR, UART_RESET);\r
1587                 goto fail;\r
1588         }\r
1589 \r
1590         /* reset DLAB */\r
1591         if(serial_lcr_write(up, cval)) {\r
1592                 if(up->port.line != DBG_PORT)\r
1593                         dbg("serial.%d reset DLAB fail\n", up->port.line);\r
1594                 serial_out(up, UART_SRR, UART_RESET);\r
1595                 goto fail;\r
1596         }\r
1597         else {\r
1598                 serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1599                 up->fcr = fcr;\r
1600                 serial_out(up, UART_FCR, up->fcr);              /* set fcr */\r
1601                 up->ier = 0;\r
1602                 //start serial receive data\r
1603 #if USE_DMA\r
1604                 if (up->dma->use_dma) {\r
1605                         up->ier |= UART_IER_RLSI;\r
1606                         up->ier |= UART_IER_PTIME;   //Programmable THRE Interrupt Mode Enable\r
1607                         if (up->dma->use_dma & RX_DMA)\r
1608                                 serial_rk_start_rx_dma(&up->port);\r
1609                         else\r
1610                                 up->ier |= UART_IER_RDI;\r
1611                 } else\r
1612 #endif\r
1613                 {\r
1614                         //  not use dma receive\r
1615                         up->ier |= UART_IER_RDI;\r
1616                         up->ier |= UART_IER_RLSI;\r
1617                         if(up->port.line != DBG_PORT)\r
1618                                 up->ier |= UART_IER_PTIME;   //Programmable THRE Interrupt Mode Enable\r
1619 \r
1620                 }\r
1621                 serial_out(up, UART_IER, up->ier);\r
1622         }\r
1623         \r
1624         spin_unlock_irqrestore(&up->port.lock, flags);\r
1625 \r
1626         /* Don't rewrite B0 */\r
1627         if (tty_termios_baud_rate(termios))\r
1628                 tty_termios_encode_baud_rate(termios, baud, baud);\r
1629         dev_dbg(port->dev, "-%s baud %d\n", __func__, baud);\r
1630         return;\r
1631 \r
1632 fail:\r
1633         spin_unlock_irqrestore(&up->port.lock, flags);\r
1634 \r
1635 }\r
1636 \r
1637 #if 0\r
1638 static void\r
1639 serial_rk_set_ldisc(struct uart_port *port, int new)\r
1640 {\r
1641         if (new == N_PPS) {\r
1642                 port->flags |= UPF_HARDPPS_CD;\r
1643                 serial_rk_enable_ms(port);\r
1644         } else\r
1645                 port->flags &= ~UPF_HARDPPS_CD;\r
1646 }\r
1647 #endif\r
1648 \r
1649 static void\r
1650 serial_rk_pm(struct uart_port *port, unsigned int state,\r
1651               unsigned int oldstate)\r
1652 {\r
1653         struct uart_rk_port *up =\r
1654                 container_of(port, struct uart_rk_port, port);\r
1655 \r
1656         dev_dbg(port->dev, "%s: %s\n", __func__, state ? "disable" : "enable");\r
1657         if (state) {\r
1658                 clk_disable(up->clk);\r
1659                 clk_disable(up->pclk);\r
1660         } else {\r
1661                 clk_enable(up->pclk);\r
1662                 clk_enable(up->clk);\r
1663         }\r
1664 }\r
1665 \r
1666 static void serial_rk_release_port(struct uart_port *port)\r
1667 {\r
1668         dev_dbg(port->dev, "%s\n", __func__);\r
1669 }\r
1670 \r
1671 static int serial_rk_request_port(struct uart_port *port)\r
1672 {\r
1673         dev_dbg(port->dev, "%s\n", __func__);\r
1674         return 0;\r
1675 }\r
1676 \r
1677 static void serial_rk_config_port(struct uart_port *port, int flags)\r
1678 {\r
1679         dev_dbg(port->dev, "%s\n", __func__);\r
1680         port->type = PORT_RK;\r
1681 }\r
1682 \r
1683 static int\r
1684 serial_rk_verify_port(struct uart_port *port, struct serial_struct *ser)\r
1685 {\r
1686         /* we don't want the core code to modify any port params */\r
1687         dev_dbg(port->dev, "%s\n", __func__);\r
1688         return -EINVAL;\r
1689 }\r
1690 \r
1691 static const char *\r
1692 serial_rk_type(struct uart_port *port)\r
1693 {\r
1694         struct uart_rk_port *up =\r
1695                 container_of(port, struct uart_rk_port, port);\r
1696 \r
1697         dev_dbg(port->dev, "%s: %s\n", __func__, up->name);\r
1698         return up->name;\r
1699 }\r
1700 \r
1701 static struct uart_ops serial_rk_pops = {\r
1702         .tx_empty       = serial_rk_tx_empty,\r
1703         .set_mctrl      = serial_rk_set_mctrl,\r
1704         .get_mctrl      = serial_rk_get_mctrl,\r
1705         .stop_tx        = serial_rk_stop_tx,\r
1706         .start_tx       = serial_rk_start_tx,\r
1707         .stop_rx        = serial_rk_stop_rx,\r
1708         .enable_ms      = serial_rk_enable_ms,\r
1709         .break_ctl      = serial_rk_break_ctl,\r
1710         .startup        = serial_rk_startup,\r
1711         .shutdown       = serial_rk_shutdown,\r
1712         .set_termios    = serial_rk_set_termios,\r
1713 #if 0\r
1714         .set_ldisc      = serial_rk_set_ldisc,\r
1715 #endif\r
1716         .pm             = serial_rk_pm,\r
1717         .type           = serial_rk_type,\r
1718         .release_port   = serial_rk_release_port,\r
1719         .request_port   = serial_rk_request_port,\r
1720         .config_port    = serial_rk_config_port,\r
1721         .verify_port    = serial_rk_verify_port,\r
1722 #ifdef CONFIG_CONSOLE_POLL\r
1723         .poll_get_char = serial_rk_get_poll_char,\r
1724         .poll_put_char = serial_rk_put_poll_char,\r
1725 #endif\r
1726 };\r
1727 \r
1728 #ifdef CONFIG_SERIAL_RK_CONSOLE\r
1729 \r
1730 static struct uart_rk_port *serial_rk_console_ports[UART_NR];\r
1731 \r
1732 static void serial_rk_console_putchar(struct uart_port *port, int ch)\r
1733 {\r
1734         struct uart_rk_port *up =\r
1735                 container_of(port, struct uart_rk_port, port);\r
1736 \r
1737         wait_for_xmitr(up, UART_LSR_THRE);\r
1738         serial_out(up, UART_TX, ch);\r
1739 }\r
1740 \r
1741 /*\r
1742  *      Print a string to the serial port trying not to disturb\r
1743  *      any possible real use of the port...\r
1744  *\r
1745  *      The console_lock must be held when we get here.\r
1746  */\r
1747 static void\r
1748 serial_rk_console_write(struct console *co, const char *s, unsigned int count)\r
1749 {\r
1750         struct uart_rk_port *up = serial_rk_console_ports[co->index];\r
1751         unsigned long flags;\r
1752         unsigned int ier;\r
1753         int locked = 1;\r
1754 \r
1755         touch_nmi_watchdog();\r
1756 \r
1757         local_irq_save(flags);\r
1758         if (up->port.sysrq) {\r
1759                 /* serial_rk_handle_port() already took the lock */\r
1760                 locked = 0;\r
1761         } else if (oops_in_progress) {\r
1762                 locked = spin_trylock(&up->port.lock);\r
1763         } else\r
1764                 spin_lock(&up->port.lock);\r
1765 \r
1766         /*\r
1767          *      First save the IER then disable the interrupts\r
1768          */\r
1769         ier = serial_in(up, UART_IER);\r
1770 \r
1771         serial_out(up, UART_IER, 0);\r
1772 \r
1773         uart_console_write(&up->port, s, count, serial_rk_console_putchar);\r
1774 \r
1775         /*\r
1776          *      Finally, wait for transmitter to become empty\r
1777          *      and restore the IER\r
1778          */\r
1779         wait_for_xmitr(up, UART_LSR_TEMT);\r
1780         serial_out(up, UART_IER, ier);\r
1781 \r
1782 #if 0\r
1783         /*\r
1784          *      The receive handling will happen properly because the\r
1785          *      receive ready bit will still be set; it is not cleared\r
1786          *      on read.  However, modem control will not, we must\r
1787          *      call it if we have saved something in the saved flags\r
1788          *      while processing with interrupts off.\r
1789          */\r
1790         if (up->msr_saved_flags)\r
1791                 check_modem_status(up);\r
1792 #endif\r
1793 \r
1794         if (locked)\r
1795                 spin_unlock(&up->port.lock);\r
1796         local_irq_restore(flags);\r
1797 }\r
1798 \r
1799 static int __init serial_rk_console_setup(struct console *co, char *options)\r
1800 {\r
1801         struct uart_rk_port *up;\r
1802         int baud = 115200;\r
1803         int bits = 8;\r
1804         int parity = 'n';\r
1805         int flow = 'n';\r
1806 \r
1807         if (unlikely(co->index >= UART_NR || co->index < 0))\r
1808                 return -ENODEV;\r
1809 \r
1810         if (serial_rk_console_ports[co->index] == NULL)\r
1811                 return -ENODEV;\r
1812         up = serial_rk_console_ports[co->index];\r
1813 \r
1814         if (options)\r
1815                 uart_parse_options(options, &baud, &parity, &bits, &flow);\r
1816 \r
1817         return uart_set_options(&up->port, co, baud, parity, bits, flow);\r
1818 }\r
1819 \r
1820 static struct console serial_rk_console = {\r
1821         .name           = "ttyS",\r
1822         .write          = serial_rk_console_write,\r
1823         .device         = uart_console_device,\r
1824         .setup          = serial_rk_console_setup,\r
1825         .flags          = CON_PRINTBUFFER | CON_ANYTIME,\r
1826         .index          = -1,\r
1827         .data           = &serial_rk_reg,\r
1828 };\r
1829 \r
1830 static void serial_rk_add_console_port(struct uart_rk_port *up)\r
1831 {\r
1832         serial_rk_console_ports[up->pdev->id] = up;\r
1833 }\r
1834 \r
1835 #define SERIAL_CONSOLE  &serial_rk_console\r
1836 #else\r
1837 #define SERIAL_CONSOLE  NULL\r
1838 \r
1839 static inline void serial_rk_add_console_port(struct uart_rk_port *up)\r
1840 {}\r
1841 \r
1842 #endif\r
1843 \r
1844 static struct uart_driver serial_rk_reg = {\r
1845         .owner                  = THIS_MODULE,\r
1846         .driver_name            = "rk29_serial",\r
1847         .dev_name               = "ttyS",\r
1848         .major                  = TTY_MAJOR,\r
1849         .minor                  = 64,\r
1850         .cons                   = SERIAL_CONSOLE,\r
1851         .nr                     = UART_NR,\r
1852 };\r
1853 #if USE_WAKEUP\r
1854 static irqreturn_t serial_rk_wakeup_handler(int irq, void *dev) {\r
1855         struct uart_rk_port *up = dev;\r
1856         struct uart_wake_up *wakeup = up->wakeup;\r
1857         if(wakeup->enable == 1) {\r
1858                 iomux_set(wakeup->rx_mode);\r
1859                 wake_lock_timeout(&wakeup->wakelock, 3 * HZ);\r
1860         }    \r
1861         return 0;\r
1862 }\r
1863 \r
1864 static int serial_rk_setup_wakeup_irq(struct uart_rk_port *up)\r
1865 {\r
1866         int ret = 0;\r
1867         struct uart_wake_up *wakeup = up->wakeup;\r
1868 \r
1869         if(wakeup->enable == 1) {\r
1870                 memset(wakeup->wakelock_name, 0, 32);\r
1871                 sprintf(wakeup->wakelock_name, "serial.%d_wakelock", up->port.line);\r
1872                 wake_lock_init(&wakeup->wakelock, WAKE_LOCK_SUSPEND, wakeup->wakelock_name);\r
1873                 memset(wakeup->rx_pin_name, 0, 32);             \r
1874                 sprintf(wakeup->rx_pin_name, "UART%d_SIN", up->port.line);\r
1875                 wakeup->rx_pin = iomux_mode_to_gpio(wakeup->rx_mode);\r
1876                 ret = gpio_request(wakeup->rx_pin, wakeup->rx_pin_name);\r
1877                 if (ret) {\r
1878                         printk("request %s fail ! \n", wakeup->rx_pin_name);\r
1879                     return ret;\r
1880                 }\r
1881                 gpio_direction_input(wakeup->rx_pin);\r
1882                 wakeup->rx_irq = gpio_to_irq(wakeup->rx_pin);\r
1883                 memset(wakeup->rx_irq_name, 0, 32);\r
1884                 sprintf(wakeup->rx_irq_name, "serial.%d_wake_up_irq", up->port.line);\r
1885                 ret = request_irq(wakeup->rx_irq, serial_rk_wakeup_handler, IRQF_TRIGGER_FALLING, wakeup->rx_irq_name, up);\r
1886                 if(ret < 0) {\r
1887                         printk("%s request fail\n", wakeup->rx_irq_name);\r
1888                     return ret;\r
1889                 }\r
1890                 disable_irq_nosync(wakeup->rx_irq);\r
1891                 enable_irq_wake(wakeup->rx_irq);\r
1892                 iomux_set(wakeup->rx_mode);\r
1893         }\r
1894         return ret;\r
1895 }\r
1896 \r
1897 static int serial_rk_enable_wakeup_irq(struct uart_rk_port *up) {\r
1898         struct uart_wake_up *wakeup = up->wakeup;\r
1899         if(wakeup->enable == 1) {\r
1900                 iomux_set(wakeup->rx_mode & 0xfff0);\r
1901                 enable_irq(wakeup->rx_irq);\r
1902         }\r
1903     return 0;\r
1904 }\r
1905 \r
1906 static int serial_rk_disable_wakeup_irq(struct uart_rk_port *up) {\r
1907         struct uart_wake_up *wakeup = up->wakeup;\r
1908         if(wakeup->enable == 1) {\r
1909                 disable_irq_nosync(wakeup->rx_irq);\r
1910                 iomux_set(wakeup->rx_mode);\r
1911         }\r
1912     return 0;\r
1913 }\r
1914 \r
1915 static int serial_rk_remove_wakeup_irq(struct uart_rk_port *up) {\r
1916         struct uart_wake_up *wakeup = up->wakeup;\r
1917         if(wakeup->enable == 1) {\r
1918                 //disable_irq_nosync(wakeup->rx_irq);\r
1919                 free_irq(wakeup->rx_irq, NULL);\r
1920                 gpio_free(wakeup->rx_pin);\r
1921                 wake_lock_destroy(&wakeup->wakelock);\r
1922         }\r
1923     return 0;\r
1924 }\r
1925 #endif\r
1926 \r
1927 \r
1928 \r
1929 static int __devinit serial_rk_probe(struct platform_device *pdev)\r
1930 {\r
1931         struct uart_rk_port     *up;\r
1932         struct resource         *mem;\r
1933         int irq;\r
1934         int ret = -ENOSPC;\r
1935         \r
1936         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1937         if (!mem) {\r
1938                 dev_err(&pdev->dev, "no mem resource?\n");\r
1939                 return -ENODEV;\r
1940         }\r
1941 \r
1942         irq = platform_get_irq(pdev, 0);\r
1943         if (irq < 0) {\r
1944                 dev_err(&pdev->dev, "no irq resource?\n");\r
1945                 return irq;\r
1946         }\r
1947 \r
1948         if (!request_mem_region(mem->start, (mem->end - mem->start) + 1,\r
1949                                 pdev->dev.driver->name)) {\r
1950                 dev_err(&pdev->dev, "memory region already claimed\n");\r
1951                 return -EBUSY;\r
1952         }\r
1953 \r
1954         up = kzalloc(sizeof(*up), GFP_KERNEL);\r
1955         if (up == NULL) {\r
1956                 ret = -ENOMEM;\r
1957                 goto do_release_region;\r
1958         }\r
1959 \r
1960         sprintf(up->name, "rk29_serial.%d", pdev->id);\r
1961         up->pdev = pdev;\r
1962         up->pclk = clk_get(&pdev->dev, "pclk_uart");\r
1963         up->clk = clk_get(&pdev->dev, "uart");\r
1964         if (unlikely(IS_ERR(up->clk))) {\r
1965                 ret = PTR_ERR(up->clk);\r
1966                 goto do_free;\r
1967         }\r
1968         up->tx_loadsz = 30;\r
1969 #if USE_DMA\r
1970         up->dma = &rk29_uart_ports_dma[pdev->id];\r
1971 #endif\r
1972 #if USE_WAKEUP\r
1973         up->wakeup = &rk29_uart_ports_wakeup[pdev->id];\r
1974 #endif\r
1975         up->port.dev = &pdev->dev;\r
1976         up->port.type = PORT_RK;\r
1977         up->port.irq = irq;\r
1978         up->port.iotype = UPIO_DWAPB;\r
1979 \r
1980         up->port.regshift = 2;\r
1981         //fifo size default is 32, but it will be updated later when start_up\r
1982         up->port.fifosize = 32;\r
1983         up->port.ops = &serial_rk_pops;\r
1984         up->port.line = pdev->id;\r
1985         up->port.iobase = mem->start;\r
1986         up->port.membase = ioremap_nocache(mem->start, mem->end - mem->start + 1);\r
1987         if (!up->port.membase) {\r
1988                 ret = -ENOMEM;\r
1989                 goto do_put_clk;\r
1990         }\r
1991         up->port.mapbase = mem->start;\r
1992         up->port.irqflags = IRQF_DISABLED;\r
1993         up->port.uartclk = clk_get_rate(up->clk);\r
1994 \r
1995 #if USE_DMA\r
1996         /* set dma config */\r
1997         pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);\r
1998         if(up->dma->use_dma & RX_DMA) {\r
1999                 //timer\r
2000                 up->dma->use_timer = USE_TIMER;\r
2001                 up->dma->rx_timer.function = serial_rk_report_dma_rx;\r
2002                 up->dma->rx_timer.data = (unsigned long)up;\r
2003                 up->dma->rx_timeout = 10;\r
2004                 up->dma->rx_timer.expires = jiffies + msecs_to_jiffies(up->dma->rx_timeout);\r
2005                 init_timer(&up->dma->rx_timer);\r
2006 \r
2007                 //rx buffer\r
2008                 up->dma->rb_size =  UART_XMIT_SIZE*2;\r
2009                 up->dma->rx_buffer = dmam_alloc_coherent(up->port.dev, up->dma->rb_size,\r
2010                                 &up->dma->rx_phy_addr, DMA_MEMORY_MAP);\r
2011                 up->dma->rb_tail = 0;\r
2012 \r
2013                 if(!up->dma->rx_buffer){\r
2014                         dev_info(up->port.dev, "dmam_alloc_coherent dma_rx_buffer fail\n");\r
2015                 }\r
2016                 else {\r
2017                         dev_info(up->port.dev, "dma_rx_buffer 0x%08x\n", (unsigned) up->dma->rx_buffer);\r
2018                         dev_info(up->port.dev, "dma_rx_phy 0x%08x\n", (unsigned)up->dma->rx_phy_addr);\r
2019                 }\r
2020 \r
2021                 // work queue\r
2022                 //INIT_WORK(&up->uart_work, serial_rk_report_revdata_workfunc);\r
2023                 //INIT_WORK(&up->uart_work_rx, serial_rk_start_dma_rx);\r
2024                 //up->uart_wq = create_singlethread_workqueue("uart_workqueue");\r
2025                 up->dma->rx_dma_used = 0;\r
2026                 spin_lock_init(&(up->dma->rx_lock));\r
2027                 serial_rk_init_dma_rx(&up->port);\r
2028         }\r
2029 \r
2030         if(up->dma->use_dma & TX_DMA){\r
2031                 //tx buffer\r
2032                 up->dma->tb_size = UART_XMIT_SIZE;\r
2033                 up->dma->tx_buffer = dmam_alloc_coherent(up->port.dev, up->dma->tb_size,\r
2034                                 &up->dma->tx_phy_addr, DMA_MEMORY_MAP);\r
2035                 if(!up->dma->tx_buffer){\r
2036                         dev_info(up->port.dev, "dmam_alloc_coherent dma_tx_buffer fail\n");\r
2037                 }\r
2038                 else{\r
2039                         dev_info(up->port.dev, "dma_tx_buffer 0x%08x\n", (unsigned) up->dma->tx_buffer);\r
2040                         dev_info(up->port.dev, "dma_tx_phy 0x%08x\n", (unsigned) up->dma->tx_phy_addr);\r
2041                 }\r
2042                 spin_lock_init(&(up->dma->tx_lock));\r
2043                 serial_rk_init_dma_tx(&up->port);\r
2044         }\r
2045 \r
2046 #endif\r
2047         serial_rk_add_console_port(up);\r
2048         ret = uart_add_one_port(&serial_rk_reg, &up->port);\r
2049         if (ret != 0)\r
2050                 goto do_iounmap;\r
2051 \r
2052         platform_set_drvdata(pdev, up);\r
2053         dev_info(&pdev->dev, "membase 0x%08x\n", (unsigned) up->port.membase);\r
2054 #if USE_WAKEUP\r
2055         serial_rk_setup_wakeup_irq(up); \r
2056 #endif\r
2057         return 0;\r
2058 \r
2059 do_iounmap:\r
2060         iounmap(up->port.membase);\r
2061         up->port.membase = NULL;\r
2062 do_put_clk:\r
2063         clk_put(up->clk);\r
2064         clk_put(up->pclk);\r
2065 do_free:\r
2066         kfree(up);\r
2067 do_release_region:\r
2068         release_mem_region(mem->start, (mem->end - mem->start) + 1);\r
2069         return ret;\r
2070 }\r
2071 \r
2072 static int __devexit serial_rk_remove(struct platform_device *pdev)\r
2073 {\r
2074         struct uart_rk_port *up = platform_get_drvdata(pdev);\r
2075 \r
2076         platform_set_drvdata(pdev, NULL);\r
2077         if (up) {\r
2078                 struct resource *mem;\r
2079                 destroy_workqueue(up->uart_wq);\r
2080                 uart_remove_one_port(&serial_rk_reg, &up->port);\r
2081                 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
2082                 iounmap(up->port.membase);\r
2083                 up->port.membase = NULL;\r
2084                 clk_put(up->clk);\r
2085                 clk_put(up->pclk);\r
2086                 kfree(up);\r
2087                 release_mem_region(mem->start, (mem->end - mem->start) + 1);\r
2088         }\r
2089 #if USE_WAKEUP\r
2090     serial_rk_remove_wakeup_irq(up);\r
2091 #endif\r
2092         return 0;\r
2093 }\r
2094 \r
2095 static int serial_rk_suspend(struct platform_device *dev, pm_message_t state)\r
2096 {\r
2097         struct uart_rk_port *up = platform_get_drvdata(dev);\r
2098 \r
2099         if (up && up->port.line != DBG_PORT && POWER_MANEGEMENT){\r
2100                 uart_suspend_port(&serial_rk_reg, &up->port);\r
2101         }\r
2102         if(up->port.line == DBG_PORT && POWER_MANEGEMENT){\r
2103                 serial_rk_pm(&up->port, 1, 0);\r
2104         }\r
2105 #if USE_WAKEUP\r
2106     serial_rk_enable_wakeup_irq(up);\r
2107 #endif\r
2108         return 0;\r
2109 }\r
2110 \r
2111 static int serial_rk_resume(struct platform_device *dev)\r
2112 {\r
2113         struct uart_rk_port *up = platform_get_drvdata(dev);\r
2114 #if USE_WAKEUP\r
2115     serial_rk_disable_wakeup_irq(up);\r
2116 #endif\r
2117         if (up && up->port.line != DBG_PORT && POWER_MANEGEMENT){\r
2118                 uart_resume_port(&serial_rk_reg, &up->port);\r
2119         }\r
2120         if(up->port.line == DBG_PORT && POWER_MANEGEMENT){\r
2121                 serial_rk_pm(&up->port, 0, 1);\r
2122         }\r
2123         return 0;\r
2124 }\r
2125 \r
2126 static struct platform_driver serial_rk_driver = {\r
2127         .probe          = serial_rk_probe,\r
2128         .remove         = __devexit_p(serial_rk_remove),\r
2129         .suspend        = serial_rk_suspend,\r
2130         .resume         = serial_rk_resume,\r
2131         .driver         = {\r
2132 #if defined(CONFIG_ARCH_RK29)\r
2133                 .name   = "rk29_serial",\r
2134 #elif defined(CONFIG_SERIAL_RK2818)\r
2135                 .name   = "rk2818_serial",\r
2136 #else\r
2137                 .name   = "rk_serial",\r
2138 #endif\r
2139                 .owner  = THIS_MODULE,\r
2140         },\r
2141 };\r
2142 \r
2143 static int __init serial_rk_init(void)\r
2144 {\r
2145         int ret;\r
2146         //hhb@rock-chips.com\r
2147         printk("%s\n", VERSION_AND_TIME);\r
2148 \r
2149         ret = uart_register_driver(&serial_rk_reg);\r
2150         if (ret)\r
2151                 return ret;\r
2152 \r
2153         ret = platform_driver_register(&serial_rk_driver);\r
2154         if (ret != 0)\r
2155                 uart_unregister_driver(&serial_rk_reg);\r
2156 \r
2157         return ret;\r
2158 }\r
2159 \r
2160 static void __exit serial_rk_exit(void)\r
2161 {\r
2162         platform_driver_unregister(&serial_rk_driver);\r
2163         uart_unregister_driver(&serial_rk_reg);\r
2164 }\r
2165 \r
2166 module_init(serial_rk_init);\r
2167 module_exit(serial_rk_exit);\r
2168 \r
2169 MODULE_LICENSE("GPL");\r
2170 MODULE_DESCRIPTION("RK UART driver");\r
2171 \r