2 * Driver for RK-UART controller.
\r
3 * Based on drivers/tty/serial/8250.c
\r
5 * Copyright (C) 2011 Rochchip.
\r
7 * This program is free software; you can redistribute it and/or modify
\r
8 * it under the terms of the GNU General Public License as published by
\r
9 * the Free Software Foundation; either version 2 of the License, or
\r
11 * (at your option) any later version.
\r
13 * Author: hhb@rock-chips.com
\r
17 #if defined(CONFIG_SERIAL_ROCKCHIP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
\r
18 #define SUPPORT_SYSRQ
\r
21 #include <linux/module.h>
\r
22 #include <linux/ioport.h>
\r
23 #include <linux/init.h>
\r
24 #include <linux/console.h>
\r
25 #include <linux/sysrq.h>
\r
26 #include <linux/delay.h>
\r
27 #include <linux/platform_device.h>
\r
28 #include <linux/tty.h>
\r
29 #include <linux/ratelimit.h>
\r
30 #include <linux/tty_flip.h>
\r
31 #include <linux/serial_reg.h>
\r
32 #include <linux/serial_core.h>
\r
33 #include <linux/serial.h>
\r
34 #include <linux/nmi.h>
\r
35 #include <linux/mutex.h>
\r
36 #include <linux/slab.h>
\r
37 #include <linux/clk.h>
\r
38 #include <linux/timer.h>
\r
39 #include <linux/workqueue.h>
\r
40 #include <linux/dma-mapping.h>
\r
42 #include <asm/irq.h>
\r
44 #include <linux/dmaengine.h>
\r
47 #include <linux/of.h>
\r
52 * Driver Version Note
\r
54 *v0.0 : this driver is 2.6.32 kernel driver;
\r
55 *v0.1 : this driver is 3.0.8 kernel driver;
\r
57 * 1.modify dma dirver;
\r
58 * 2.enable Programmable THRE Interrupt Mode, so we can just judge ((up->iir & 0x0f) == 0x02) when transmit
\r
59 * 3.reset uart and set it to loopback state to ensure setting baud rate sucessfully
\r
61 * 1. dma driver:make "when tx dma is only enable" work functionally
\r
63 * 1. dma driver:serial rx use new dma interface rk29_dma_enqueue_ring
\r
65 * 1. When enable Programmable THRE Interrupt Mode, in lsr register, only UART_LSR_TEMT means transmit empty, but
\r
66 UART_LSR_THRE doesn't. So, the macro BOTH_EMPTY should be replaced with UART_LSR_TEMT.
\r
68 * 1.fix bug dma buffer free error
\r
70 * 1.in some case, set uart rx as gpio interrupt to wake up arm, when arm suspends
\r
72 migrate to kernel3.10,and fit device tree
\r
74 DMA use new interfaces, and use some interfaces with devm_ prefix
\r
76 * 1.clear receive time out interrupt request in irq handler
\r
78 #define VERSION_AND_TIME "rk_serial.c v1.8 2014-03-04"
\r
81 #define UART_USR 0x1F /* UART Status Register */
\r
82 #define UART_USR_TX_FIFO_EMPTY 0x04 /* Transmit FIFO empty */
\r
83 #define UART_USR_TX_FIFO_NOT_FULL 0x02 /* Transmit FIFO not full */
\r
84 #define UART_USR_BUSY (1)
\r
85 #define UART_IER_PTIME 0x80 /* Programmable THRE Interrupt Mode Enable */
\r
86 #define UART_LSR_RFE 0x80 /* receive fifo error */
\r
87 #define UART_SRR 0x22 /* software reset register */
\r
88 #define UART_SFE 0x26 /* Shadow FIFO Enable */
\r
89 #define UART_RESET 0x01
\r
92 //#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
\r
93 #define UART_NR 5 //uart port number
\r
96 /* configurate whether the port transmit-receive by DMA in menuconfig*/
\r
102 #define DMA_SERIAL_BUFFER_SIZE (UART_XMIT_SIZE*2)
\r
103 #define CONFIG_CLOCK_CTRL 1
\r
105 #ifdef CONFIG_UART0_WAKEUP_RK29
\r
106 #define UART0_USE_WAKEUP CONFIG_UART0_WAKEUP_RK29
\r
108 #define UART0_USE_WAKEUP 0
\r
110 #ifdef CONFIG_UART1_WAKEUP_RK29
\r
111 #define UART1_USE_WAKEUP CONFIG_UART1_WAKEUP_RK29
\r
113 #define UART1_USE_WAKEUP 0
\r
115 #ifdef CONFIG_UART2_WAKEUP_RK29
\r
116 #define UART2_USE_WAKEUP CONFIG_UART2_WAKEUP_RK29
\r
118 #define UART2_USE_WAKEUP 0
\r
120 #ifdef CONFIG_UART3_WAKEUP_RK29
\r
121 #define UART3_USE_WAKEUP CONFIG_UART3_WAKEUP_RK29
\r
123 #define UART3_USE_WAKEUP 0
\r
126 #define USE_TIMER 1 // use timer for dma transport
\r
127 #define POWER_MANEGEMENT 1
\r
128 #define RX_TIMEOUT (3000*3) //uint ms
\r
129 #define DMA_TX_TRRIGE_LEVEL 128
\r
130 #define SERIAL_CIRC_CNT_TO_END(xmit) CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)
\r
132 #define USE_DMA OPEN_DMA
\r
134 #define USE_WAKEUP (UART0_USE_WAKEUP | UART1_USE_WAKEUP | UART2_USE_WAKEUP | UART3_USE_WAKEUP)
\r
137 #include <mach/iomux.h>
\r
138 #include <linux/wakelock.h>
\r
143 static struct uart_driver serial_rk_reg;
\r
148 #ifdef CONFIG_ARCH_RK29
\r
149 #define DBG_PORT 1 //DBG_PORT which uart is used to print log message
\r
151 #ifndef CONFIG_RK_DEBUG_UART //DBG_PORT which uart is used to print log message
\r
154 #define DBG_PORT CONFIG_RK_DEBUG_UART
\r
158 #ifdef CONFIG_SERIAL_CORE_CONSOLE
\r
159 #define uart_console(port) ((port)->cons && (port)->cons->index == (port)->line)
\r
161 #define uart_console(port) (0)
\r
165 extern void printascii(const char *);
\r
166 static void dbg(const char *fmt, ...)
\r
172 vsprintf(buff, fmt, va);
\r
175 #if defined(CONFIG_DEBUG_LL) || defined(CONFIG_RK_EARLY_PRINTK)
\r
180 //enable log output
\r
182 static int log_port = -1;
\r
183 module_param(log_port, int, S_IRUGO|S_IWUSR);
\r
186 #define DEBUG_INTR(fmt...) if (up->port.line == log_port && !uart_console(&up->port)) dbg(fmt)
\r
188 #define DEBUG_INTR(fmt...) do { } while (0)
\r
193 /* added by hhb@rock-chips.com for uart dma transfer */
\r
195 struct rk_uart_dma {
\r
196 u32 use_dma; //1:used
\r
197 //enum dma_ch rx_dmach;
\r
198 //enum dma_ch tx_dmach;
\r
200 //receive and transfer buffer
\r
201 char * rx_buffer; //visual memory
\r
203 dma_addr_t rx_phy_addr; //physical memory
\r
204 dma_addr_t tx_phy_addr;
\r
205 u32 rb_size; //buffer size
\r
208 //regard the rx buffer as a circular buffer
\r
213 spinlock_t tx_lock;
\r
214 spinlock_t rx_lock;
\r
216 char tx_dma_inited; //1:dma tx channel has been init
\r
217 char rx_dma_inited; //1:dma rx channel has been init
\r
218 char tx_dma_used; //1:dma tx is working
\r
219 char rx_dma_used; //1:dma rx is working
\r
221 /* timer to poll activity on rx dma */
\r
224 struct timer_list rx_timer;
\r
226 struct dma_chan *dma_chan_rx, *dma_chan_tx;
\r
227 struct scatterlist rx_sgl, tx_sgl;
\r
228 unsigned int rx_bytes, tx_bytes;
\r
233 struct uart_wake_up {
\r
234 unsigned int enable;
\r
235 unsigned int rx_mode;
\r
236 unsigned int tx_mode;
\r
237 unsigned int rx_pin;
\r
238 char rx_pin_name[32];
\r
239 unsigned int tx_pin;
\r
240 unsigned int rx_irq;
\r
241 char rx_irq_name[32];
\r
242 struct wake_lock wakelock;
\r
243 char wakelock_name[32];
\r
248 struct of_rk_serial {
\r
250 unsigned int use_dma;
\r
251 unsigned int uartclk;
\r
256 struct uart_rk_port {
\r
257 struct uart_port port;
\r
258 struct platform_device *pdev;
\r
261 unsigned int tx_loadsz; /* transmit fifo load size */
\r
268 * Some bits in registers are cleared on a read, so they must
\r
269 * be saved whenever the register is read but the bits will not
\r
270 * be immediately processed.
\r
272 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
\r
273 unsigned char lsr_saved_flags;
\r
275 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
\r
276 unsigned char msr_saved_flags;
\r
282 unsigned long port_activity;
\r
283 struct work_struct uart_work;
\r
284 struct work_struct uart_work_rx;
\r
285 struct workqueue_struct *uart_wq;
\r
286 struct rk_uart_dma *dma;
\r
288 struct uart_wake_up *wakeup;
\r
293 static void serial_rk_release_dma_tx(struct uart_rk_port *up);
\r
294 static int serial_rk_start_dma_tx(struct uart_rk_port *up);
\r
295 //static void serial_rk_rx_timeout(unsigned long uart);
\r
296 static void serial_rk_release_dma_rx(struct uart_rk_port *up);
\r
297 static int serial_rk_start_dma_rx(struct uart_rk_port *up);
\r
298 static void serial_rk_stop_dma_tx(struct uart_rk_port *up);
\r
299 static void serial_rk_stop_dma_rx(struct uart_rk_port *up);
\r
302 static inline int serial_rk_start_tx_dma(struct uart_port *port) { return 0; }
\r
304 static int serial_rk_startup(struct uart_port *port);
\r
306 static inline unsigned int serial_in(struct uart_rk_port *up, int offset)
\r
308 offset = offset << 2;
\r
310 return __raw_readl(up->port.membase + offset);
\r
313 /* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */
\r
314 static inline void dwapb_save_out_value(struct uart_rk_port *up, int offset,
\r
315 unsigned char value)
\r
317 if (offset == UART_LCR)
\r
321 /* Read the IER to ensure any interrupt is cleared before returning from ISR. */
\r
322 static inline void dwapb_check_clear_ier(struct uart_rk_port *up, int offset)
\r
324 if (offset == UART_TX || offset == UART_IER)
\r
325 serial_in(up, UART_IER);
\r
328 static inline void serial_out(struct uart_rk_port *up, int offset, unsigned char value)
\r
330 dwapb_save_out_value(up, offset, value);
\r
331 __raw_writel(value, up->port.membase + (offset << 2));
\r
332 if (offset != UART_TX)
\r
334 dwapb_check_clear_ier(up, offset);
\r
337 /* Uart divisor latch read */
\r
338 static inline int serial_dl_read(struct uart_rk_port *up)
\r
340 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
\r
343 /* Uart divisor latch write */
\r
344 static int serial_dl_write(struct uart_rk_port *up, unsigned int value)
\r
346 unsigned int tmout = 100;
\r
348 while(!(serial_in(up, UART_LCR) & UART_LCR_DLAB)){
\r
350 if(up->port.line != DBG_PORT)
\r
351 dbg("set serial.%d baudrate fail with DLAB not set\n", up->port.line);
\r
357 while(serial_in(up, UART_USR) & UART_USR_BUSY){
\r
359 if(up->port.line != DBG_PORT)
\r
360 dbg("set serial.%d baudrate timeout\n", up->port.line);
\r
366 serial_out(up, UART_DLL, value & 0xff);
\r
367 serial_out(up, UART_DLM, value >> 8 & 0xff);
\r
373 static int serial_lcr_write(struct uart_rk_port *up, unsigned char value)
\r
375 unsigned int tmout = 15000;
\r
377 while(serial_in(up, UART_USR) & UART_USR_BUSY){
\r
379 if(up->port.line != DBG_PORT)
\r
380 dbg("set serial.%d lc r = 0x%02x timeout\n", up->port.line, value);
\r
386 serial_out(up, UART_LCR, value);
\r
391 static inline void serial_rk_enable_ier_thri(struct uart_rk_port *up)
\r
393 if (!(up->ier & UART_IER_THRI)) {
\r
394 up->ier |= UART_IER_THRI;
\r
395 serial_out(up, UART_IER, up->ier);
\r
400 static inline void serial_rk_disable_ier_thri(struct uart_rk_port *up)
\r
402 if (up->ier & UART_IER_THRI) {
\r
403 up->ier &= ~UART_IER_THRI;
\r
404 serial_out(up, UART_IER, up->ier);
\r
408 static int rk29_uart_dump_register(struct uart_rk_port *up){
\r
410 unsigned int reg_value = 0;
\r
412 reg_value = serial_in(up, UART_IER);
\r
413 dbg("UART_IER = 0x%0x\n", reg_value);
\r
414 reg_value = serial_in(up, UART_IIR);
\r
415 dbg("UART_IIR = 0x%0x\n", reg_value);
\r
416 reg_value = serial_in(up, UART_LSR);
\r
417 dbg("UART_LSR = 0x%0x\n", reg_value);
\r
418 reg_value = serial_in(up, UART_MSR);
\r
419 dbg("UART_MSR = 0x%0x\n", reg_value);
\r
420 reg_value = serial_in(up, UART_MCR);
\r
421 dbg("UART_MCR = 0x%0x\n", reg_value);
\r
422 reg_value = serial_in(up, 0x21);
\r
423 dbg("UART_RFL = 0x%0x\n", reg_value);
\r
424 reg_value = serial_in(up, UART_LCR);
\r
425 dbg("UART_LCR = 0x%0x\n", reg_value);
\r
433 static void serial_rk_clear_fifos(struct uart_rk_port *up)
\r
435 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
\r
436 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
\r
437 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
\r
438 serial_out(up, UART_FCR, 0);
\r
441 static inline void __stop_tx(struct uart_rk_port *p)
\r
443 if (p->ier & UART_IER_THRI) {
\r
444 p->ier &= ~UART_IER_THRI;
\r
445 serial_out(p, UART_IER, p->ier);
\r
449 static void serial_rk_stop_tx(struct uart_port *port)
\r
451 struct uart_rk_port *up =
\r
452 container_of(port, struct uart_rk_port, port);
\r
454 struct rk_uart_dma *uart_dma = up->dma;
\r
455 if(uart_dma->use_dma & TX_DMA){
\r
456 serial_rk_stop_dma_tx(up);
\r
463 static void serial_rk_start_tx(struct uart_port *port)
\r
465 struct uart_rk_port *up =
\r
466 container_of(port, struct uart_rk_port, port);
\r
469 if(up->dma->use_dma & TX_DMA) {
\r
470 if(!up->dma->tx_dma_used)
\r
471 serial_rk_enable_ier_thri(up);
\r
473 serial_rk_enable_ier_thri(up);
\r
476 serial_rk_enable_ier_thri(up);
\r
481 static void serial_rk_stop_rx(struct uart_port *port)
\r
483 struct uart_rk_port *up =
\r
484 container_of(port, struct uart_rk_port, port);
\r
486 struct rk_uart_dma *uart_dma = up->dma;
\r
487 if(uart_dma->use_dma & RX_DMA){
\r
488 serial_rk_stop_dma_rx(up);
\r
491 up->ier &= ~UART_IER_RLSI;
\r
492 up->port.read_status_mask &= ~UART_LSR_DR;
\r
493 serial_out(up, UART_IER, up->ier);
\r
497 static void serial_rk_enable_ms(struct uart_port *port)
\r
499 /* no MSR capabilities */
\r
501 struct uart_rk_port *up =
\r
502 container_of(port, struct uart_rk_port, port);
\r
504 dev_dbg(port->dev, "%s\n", __func__);
\r
505 up->ier |= UART_IER_MSI;
\r
506 serial_out(up, UART_IER, up->ier);
\r
511 static struct uart_wake_up rk29_uart_ports_wakeup[] = {
\r
512 {UART0_USE_WAKEUP, UART0_SIN, UART0_SOUT},
\r
513 {UART1_USE_WAKEUP, UART1_SIN, UART1_SOUT},
\r
514 {UART2_USE_WAKEUP, UART2_SIN, UART2_SOUT},
\r
515 {UART3_USE_WAKEUP, UART3_SIN, UART3_SOUT},
\r
520 /* DMAC PL330 add by hhb@rock-chips.com */
\r
522 static void serial_rk_stop_dma_tx(struct uart_rk_port *up)
\r
524 struct rk_uart_dma *uart_dma = up->dma;
\r
526 if(uart_dma && uart_dma->tx_dma_used) {
\r
527 dmaengine_terminate_all(uart_dma->dma_chan_tx);
\r
528 uart_dma->tx_dma_used = 0;
\r
532 static void serial_rk_release_dma_tx(struct uart_rk_port *up)
\r
534 struct rk_uart_dma *uart_dma = up->dma;
\r
536 if(uart_dma && uart_dma->tx_dma_inited) {
\r
537 serial_rk_stop_dma_tx(up);
\r
538 dma_release_channel(uart_dma->dma_chan_tx);
\r
539 uart_dma->dma_chan_tx = NULL;
\r
540 uart_dma->tx_dma_inited = 0;
\r
544 static void dma_tx_callback(void *data)
\r
546 struct uart_port *port = data;
\r
547 struct uart_rk_port *up = container_of(port, struct uart_rk_port, port);
\r
548 struct circ_buf *xmit = &port->state->xmit;
\r
549 struct rk_uart_dma *uart_dma = up->dma;
\r
550 struct scatterlist *sgl = &uart_dma->tx_sgl;
\r
552 dma_unmap_sg(up->port.dev, sgl, 1, DMA_TO_DEVICE);
\r
554 xmit->tail = (xmit->tail + uart_dma->tx_bytes) & (UART_XMIT_SIZE - 1);
\r
555 port->icount.tx += uart_dma->tx_bytes;
\r
556 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
\r
557 uart_write_wakeup(port);
\r
559 //spin_lock(&(up->dma->tx_lock));
\r
560 uart_dma->tx_dma_used = 0;
\r
561 //spin_unlock(&(up->dma->tx_lock));
\r
562 serial_rk_enable_ier_thri(up);
\r
563 up->port_activity = jiffies;
\r
564 // dev_info(up->port.dev, "s:%d\n", size);
\r
567 static int serial_rk_init_dma_tx(struct uart_rk_port *up) {
\r
569 struct dma_slave_config slave_config;
\r
570 struct uart_port *port = &up->port;
\r
571 struct rk_uart_dma *uart_dma = up->dma;
\r
575 dev_info(up->port.dev, "serial_rk_init_dma_tx fail\n");
\r
579 if(uart_dma->tx_dma_inited) {
\r
583 uart_dma->dma_chan_tx = dma_request_slave_channel(port->dev, "tx");
\r
584 if (!uart_dma->dma_chan_tx) {
\r
585 dev_err(port->dev, "cannot get the TX DMA channel!\n");
\r
589 slave_config.direction = DMA_MEM_TO_DEV;
\r
590 slave_config.dst_addr = port->mapbase + UART_TX;
\r
591 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
\r
592 slave_config.dst_maxburst = 16;
\r
593 ret = dmaengine_slave_config(uart_dma->dma_chan_tx, &slave_config);
\r
595 dev_err(port->dev, "error in TX dma configuration.");
\r
599 uart_dma->tx_dma_inited = 1;
\r
600 dev_info(port->dev, "serial_rk_init_dma_tx sucess\n");
\r
604 static int serial_rk_start_dma_tx(struct uart_rk_port *up)
\r
607 struct uart_port *port = &up->port;
\r
608 struct circ_buf *xmit = &port->state->xmit;
\r
609 struct rk_uart_dma *uart_dma = up->dma;
\r
610 struct scatterlist *sgl = &uart_dma->tx_sgl;
\r
611 struct dma_async_tx_descriptor *desc;
\r
614 if(!uart_dma->use_dma)
\r
617 if(-1 == serial_rk_init_dma_tx(up))
\r
620 if (1 == uart_dma->tx_dma_used)
\r
623 // spin_lock(&(uart_dma->tx_lock));
\r
626 count = SERIAL_CIRC_CNT_TO_END(xmit);
\r
628 if(count >= DMA_TX_TRRIGE_LEVEL) {
\r
629 uart_dma->tx_bytes = count;
\r
630 sg_init_one(sgl, uart_dma->tx_buffer + xmit->tail, count);
\r
631 ret = dma_map_sg(port->dev, sgl, 1, DMA_TO_DEVICE);
\r
634 dev_err(port->dev, "DMA mapping error for TX.\n");
\r
637 desc = dmaengine_prep_slave_sg(uart_dma->dma_chan_tx, sgl, 1,
\r
638 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
\r
641 dev_err(port->dev, "We cannot prepare for the TX slave dma!\n");
\r
644 desc->callback = dma_tx_callback;
\r
645 desc->callback_param = port;
\r
646 dmaengine_submit(desc);
\r
647 dma_async_issue_pending(uart_dma->dma_chan_tx);
\r
648 uart_dma->tx_dma_used = 1;
\r
650 // spin_unlock(&(uart_dma->tx_lock));
\r
653 dev_info(up->port.dev, "-serial_rk_start_dma_tx-error-\n");
\r
661 static void serial_rk_dma_rxcb(void *buf, int size, enum rk29_dma_buffresult result) {
\r
663 //printk(">>%s:%d\n", __func__, result);
\r
667 static void serial_rk_stop_dma_rx(struct uart_rk_port *up)
\r
669 struct rk_uart_dma *uart_dma = up->dma;
\r
671 if(uart_dma && uart_dma->rx_dma_used) {
\r
672 del_timer(&uart_dma->rx_timer);
\r
673 dmaengine_terminate_all(uart_dma->dma_chan_rx);
\r
674 uart_dma->rb_tail = 0;
\r
675 uart_dma->rx_dma_used = 0;
\r
680 static void serial_rk_release_dma_rx(struct uart_rk_port *up)
\r
682 struct rk_uart_dma *uart_dma = up->dma;
\r
684 if(uart_dma && uart_dma->rx_dma_inited) {
\r
685 serial_rk_stop_dma_rx(up);
\r
686 dma_release_channel(uart_dma->dma_chan_rx);
\r
687 uart_dma->dma_chan_rx = NULL;
\r
688 uart_dma->rx_dma_inited = 0;
\r
693 static int serial_rk_init_dma_rx(struct uart_rk_port *up)
\r
696 struct uart_port *port = &up->port;
\r
697 struct dma_slave_config slave_config;
\r
698 struct rk_uart_dma *uart_dma = up->dma;
\r
701 dev_info(port->dev, "serial_rk_init_dma_rx: port fail\n");
\r
705 if(uart_dma->rx_dma_inited) {
\r
709 uart_dma->dma_chan_rx = dma_request_slave_channel(port->dev, "rx");
\r
710 if (!uart_dma->dma_chan_rx) {
\r
711 dev_err(port->dev, "cannot get the DMA channel.\n");
\r
715 slave_config.direction = DMA_DEV_TO_MEM;
\r
716 slave_config.src_addr = port->mapbase + UART_RX;
\r
717 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
\r
718 slave_config.src_maxburst = 1;
\r
719 ret = dmaengine_slave_config(uart_dma->dma_chan_rx, &slave_config);
\r
721 dev_err(port->dev, "error in RX dma configuration.\n");
\r
725 uart_dma->rx_dma_inited = 1;
\r
726 dev_info(port->dev, "serial_rk_init_dma_rx sucess\n");
\r
730 static int serial_rk_start_dma_rx(struct uart_rk_port *up)
\r
732 struct uart_port *port = &up->port;
\r
733 struct rk_uart_dma *uart_dma = up->dma;
\r
734 struct dma_async_tx_descriptor *desc;
\r
736 if(!uart_dma->use_dma)
\r
739 if(uart_dma->rx_dma_used == 1)
\r
742 if(-1 == serial_rk_init_dma_rx(up)){
\r
743 dev_info(up->port.dev, "*******serial_rk_init_dma_rx*******error*******\n");
\r
746 desc = dmaengine_prep_dma_cyclic(uart_dma->dma_chan_rx, uart_dma->rx_phy_addr, uart_dma->rb_size, uart_dma->rb_size/2,DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
\r
749 dev_err(port->dev, "We cannot prepare for the RX slave dma!\n");
\r
753 //desc->callback = dma_rx_callback;
\r
754 //desc->callback_param = port;
\r
755 dev_dbg(port->dev, "RX: prepare for the DMA.\n");
\r
756 dmaengine_submit(desc);
\r
757 dma_async_issue_pending(uart_dma->dma_chan_rx);
\r
759 uart_dma->rx_dma_used = 1;
\r
760 if(uart_dma->use_timer == 1){
\r
761 mod_timer(&uart_dma->rx_timer, jiffies + msecs_to_jiffies(uart_dma->rx_timeout));
\r
763 up->port_activity = jiffies;
\r
767 static void serial_rk_update_rb_addr(struct uart_rk_port *up)
\r
769 struct rk_uart_dma *uart_dma = up->dma;
\r
770 struct dma_tx_state state;
\r
771 //spin_lock(&(up->dma->rx_lock));
\r
772 uart_dma->rx_size = 0;
\r
773 if(uart_dma->rx_dma_used == 1) {
\r
774 dmaengine_tx_status(uart_dma->dma_chan_rx, (dma_cookie_t)0, &state);
\r
775 uart_dma->rb_head = (state.residue - uart_dma->rx_phy_addr);
\r
776 uart_dma->rx_size = CIRC_CNT(uart_dma->rb_head, uart_dma->rb_tail, uart_dma->rb_size);
\r
778 //spin_unlock(&(up->dma->rx_lock));
\r
781 static void serial_rk_report_dma_rx(unsigned long uart)
\r
783 int count, flip = 0;
\r
784 struct uart_rk_port *up = (struct uart_rk_port *)uart;
\r
785 struct uart_port *port = &up->port;
\r
786 struct rk_uart_dma *uart_dma = up->dma;
\r
788 if(!uart_dma->rx_dma_used || !port->state->port.tty)
\r
791 serial_rk_update_rb_addr(up);
\r
792 //if (uart_dma->rx_size > 0)
\r
793 // printk("rx_size:%d ADDR:%x\n", uart_dma->rx_size, uart_dma->rb_head);
\r
795 count = CIRC_CNT_TO_END(uart_dma->rb_head, uart_dma->rb_tail, uart_dma->rb_size);
\r
798 port->icount.rx += count;
\r
799 flip = tty_insert_flip_string(&port->state->port, uart_dma->rx_buffer
\r
800 + uart_dma->rb_tail, count);
\r
801 tty_flip_buffer_push(&port->state->port);
\r
802 uart_dma->rb_tail = (uart_dma->rb_tail + count) & (uart_dma->rb_size - 1);
\r
803 up->port_activity = jiffies;
\r
806 if(uart_dma->use_timer == 1)
\r
807 mod_timer(&uart_dma->rx_timer, jiffies + msecs_to_jiffies(uart_dma->rx_timeout));
\r
809 #endif /* USE_DMA */
\r
813 receive_chars(struct uart_rk_port *up, unsigned int *status)
\r
815 struct tty_struct *tty = up->port.state->port.tty;
\r
816 unsigned char ch, lsr = *status;
\r
817 int max_count = 256;
\r
821 if (likely(lsr & UART_LSR_DR)){
\r
822 ch = serial_in(up, UART_RX);
\r
826 * Intel 82571 has a Serial Over Lan device that will
\r
827 * set UART_LSR_BI without setting UART_LSR_DR when
\r
828 * it receives a break. To avoid reading from the
\r
829 * receive buffer without UART_LSR_DR bit set, we
\r
830 * just force the read character to be 0
\r
835 up->port.icount.rx++;
\r
837 lsr |= up->lsr_saved_flags;
\r
838 up->lsr_saved_flags = 0;
\r
840 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
\r
842 * For statistics only
\r
844 if (lsr & UART_LSR_BI) {
\r
845 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
\r
846 up->port.icount.brk++;
\r
848 * We do the SysRQ and SAK checking
\r
849 * here because otherwise the break
\r
850 * may get masked by ignore_status_mask
\r
851 * or read_status_mask.
\r
853 if (uart_handle_break(&up->port))
\r
855 } else if (lsr & UART_LSR_PE)
\r
856 up->port.icount.parity++;
\r
857 else if (lsr & UART_LSR_FE)
\r
858 up->port.icount.frame++;
\r
859 if (lsr & UART_LSR_OE)
\r
860 up->port.icount.overrun++;
\r
864 * Mask off conditions which should be ignored.
\r
866 lsr &= up->port.read_status_mask;
\r
868 if (lsr & UART_LSR_BI) {
\r
869 DEBUG_INTR("handling break....");
\r
871 } else if (lsr & UART_LSR_PE)
\r
873 else if (lsr & UART_LSR_FE)
\r
876 if (uart_handle_sysrq_char(&up->port, ch))
\r
879 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
\r
882 lsr = serial_in(up, UART_LSR);
\r
883 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
\r
884 spin_unlock(&up->port.lock);
\r
885 tty_flip_buffer_push(tty->port);
\r
886 spin_lock(&up->port.lock);
\r
890 static void transmit_chars(struct uart_rk_port *up)
\r
892 struct circ_buf *xmit = &up->port.state->xmit;
\r
895 if (up->port.x_char) {
\r
896 serial_out(up, UART_TX, up->port.x_char);
\r
897 up->port.icount.tx++;
\r
898 up->port.x_char = 0;
\r
901 if (uart_tx_stopped(&up->port)) {
\r
905 if (uart_circ_empty(xmit)) {
\r
911 if(up->dma->use_dma & TX_DMA){
\r
912 if(SERIAL_CIRC_CNT_TO_END(xmit) >= DMA_TX_TRRIGE_LEVEL){
\r
913 serial_rk_start_dma_tx(up);
\r
918 count = up->port.fifosize - serial_in(up , 0x20);
\r
920 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
\r
921 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
\r
922 up->port.icount.tx++;
\r
923 if (uart_circ_empty(xmit))
\r
925 } while (--count > 0);
\r
927 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
\r
928 uart_write_wakeup(&up->port);
\r
930 DEBUG_INTR("THRE...");
\r
932 up->port_activity = jiffies;
\r
934 if (uart_circ_empty(xmit))
\r
938 static unsigned int check_modem_status(struct uart_rk_port *up)
\r
940 unsigned int status = serial_in(up, UART_MSR);
\r
943 status |= up->msr_saved_flags;
\r
944 up->msr_saved_flags = 0;
\r
945 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
\r
946 up->port.state != NULL) {
\r
947 if (status & UART_MSR_TERI)
\r
948 up->port.icount.rng++;
\r
949 if (status & UART_MSR_DDSR)
\r
950 up->port.icount.dsr++;
\r
951 if (status & UART_MSR_DDCD)
\r
952 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
\r
953 if (status & UART_MSR_DCTS)
\r
954 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
\r
956 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
\r
965 * This handles the interrupt from one port.
\r
967 static void serial_rk_handle_port(struct uart_rk_port *up)
\r
969 unsigned int status;
\r
970 unsigned long flags;
\r
971 spin_lock_irqsave(&up->port.lock, flags);
\r
973 /* reading UART_LSR can automatically clears PE FE OE bits, except receive fifo error bit*/
\r
974 status = serial_in(up, UART_LSR);
\r
976 DEBUG_INTR("status = %x...\n", status);
\r
978 /* DMA mode enable */
\r
979 if(up->dma->use_dma) {
\r
981 if (status & UART_LSR_RFE) {
\r
982 if(up->port.line != DBG_PORT){
\r
983 dev_info(up->port.dev, "error:lsr=0x%x\n", status);
\r
984 status = serial_in(up, UART_LSR);
\r
985 DEBUG_INTR("error:lsr=0x%x\n", status);
\r
989 if (status & 0x02) {
\r
990 if(up->port.line != DBG_PORT){
\r
991 dev_info(up->port.dev, "error:lsr=0x%x\n", status);
\r
992 status = serial_in(up, UART_LSR);
\r
993 DEBUG_INTR("error:lsr=0x%x\n", status);
\r
997 if(!(up->dma->use_dma & RX_DMA)) {
\r
998 if (status & (UART_LSR_DR | UART_LSR_BI)) {
\r
999 receive_chars(up, &status);
\r
1000 } else if ((up->iir & 0x0f) == 0x0c) {
\r
1001 serial_in(up, UART_RX);
\r
1005 if ((up->iir & 0x0f) == 0x02) {
\r
1006 transmit_chars(up);
\r
1010 { //dma mode disable
\r
1013 * when uart receive a serial of data which doesn't have stop bit and so on, that causes frame error,and
\r
1014 * set UART_LSR_RFE to one,what is worse,we couldn't read the data in the receive fifo. So if
\r
1015 * wo don't clear this bit and reset the receive fifo, the received data available interrupt would
\r
1016 * occur continuously. added by hhb@rock-chips.com 2011-08-05
\r
1019 if (status & UART_LSR_RFE) {
\r
1020 if(up->port.line != DBG_PORT){
\r
1021 dev_info(up->port.dev, "error:lsr=0x%x\n", status);
\r
1022 status = serial_in(up, UART_LSR);
\r
1023 DEBUG_INTR("error:lsr=0x%x\n", status);
\r
1024 rk29_uart_dump_register(up);
\r
1028 if (status & (UART_LSR_DR | UART_LSR_BI)) {
\r
1029 receive_chars(up, &status);
\r
1030 } else if ((up->iir & 0x0f) == 0x0c) {
\r
1031 serial_in(up, UART_RX);
\r
1033 check_modem_status(up);
\r
1034 //hhb@rock-chips.com when FIFO and THRE mode both are enabled,and FIFO TX empty trigger is set to larger than 1,
\r
1035 //,we need to add ((up->iir & 0x0f) == 0x02) to transmit_chars,because when entering interrupt,the FIFO and THR
\r
1037 if ((up->iir & 0x0f) == 0x02) {
\r
1038 transmit_chars(up);
\r
1041 spin_unlock_irqrestore(&up->port.lock, flags);
\r
1045 * This is the serial driver's interrupt routine.
\r
1048 static irqreturn_t serial_rk_interrupt(int irq, void *dev_id)
\r
1050 struct uart_rk_port *up = dev_id;
\r
1054 iir = serial_in(up, UART_IIR);
\r
1056 DEBUG_INTR("%s(%d) iir = 0x%02x\n", __func__, irq, iir);
\r
1059 if (!(iir & UART_IIR_NO_INT)) {
\r
1060 serial_rk_handle_port(up);
\r
1062 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
\r
1064 /* The DesignWare APB UART has an Busy Detect (0x07)
\r
1065 * interrupt meaning an LCR write attempt occured while the
\r
1066 * UART was busy. The interrupt must be cleared by reading
\r
1067 * the UART status register (USR) and the LCR re-written. */
\r
1069 if(!(serial_in(up, UART_USR) & UART_USR_BUSY)){
\r
1070 serial_out(up, UART_LCR, up->lcr);
\r
1073 dbg("the serial.%d is busy\n", up->port.line);
\r
1075 DEBUG_INTR("end(%d).\n", handled);
\r
1077 return IRQ_RETVAL(handled);
\r
1080 static unsigned int serial_rk_tx_empty(struct uart_port *port)
\r
1082 struct uart_rk_port *up =
\r
1083 container_of(port, struct uart_rk_port, port);
\r
1084 unsigned long flags;
\r
1087 dev_dbg(port->dev, "%s\n", __func__);
\r
1088 spin_lock_irqsave(&up->port.lock, flags);
\r
1089 lsr = serial_in(up, UART_LSR);
\r
1090 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
\r
1091 spin_unlock_irqrestore(&up->port.lock, flags);
\r
1093 return (lsr & UART_LSR_TEMT) == UART_LSR_TEMT ? TIOCSER_TEMT : 0;
\r
1096 static unsigned int serial_rk_get_mctrl(struct uart_port *port)
\r
1098 struct uart_rk_port *up =
\r
1099 container_of(port, struct uart_rk_port, port);
\r
1100 unsigned int status;
\r
1103 status = check_modem_status(up);
\r
1106 if (status & UART_MSR_DCD)
\r
1108 if (status & UART_MSR_RI)
\r
1110 if (status & UART_MSR_DSR)
\r
1112 if (status & UART_MSR_CTS)
\r
1114 dev_dbg(port->dev, "%s 0x%08x\n", __func__, ret);
\r
1118 static void serial_rk_set_mctrl(struct uart_port *port, unsigned int mctrl)
\r
1120 struct uart_rk_port *up =
\r
1121 container_of(port, struct uart_rk_port, port);
\r
1122 unsigned char mcr = 0;
\r
1124 dev_dbg(port->dev, "+%s\n", __func__);
\r
1125 if (mctrl & TIOCM_RTS)
\r
1126 mcr |= UART_MCR_RTS;
\r
1127 if (mctrl & TIOCM_DTR)
\r
1128 mcr |= UART_MCR_DTR;
\r
1129 if (mctrl & TIOCM_OUT1)
\r
1130 mcr |= UART_MCR_OUT1;
\r
1131 if (mctrl & TIOCM_OUT2)
\r
1132 mcr |= UART_MCR_OUT2;
\r
1133 if (mctrl & TIOCM_LOOP)
\r
1134 mcr |= UART_MCR_LOOP;
\r
1138 serial_out(up, UART_MCR, mcr);
\r
1139 dev_dbg(port->dev, "-serial.%d %s mcr: 0x%02x\n", port->line, __func__, mcr);
\r
1142 static void serial_rk_break_ctl(struct uart_port *port, int break_state)
\r
1144 struct uart_rk_port *up =
\r
1145 container_of(port, struct uart_rk_port, port);
\r
1146 unsigned long flags;
\r
1148 dev_dbg(port->dev, "+%s\n", __func__);
\r
1149 spin_lock_irqsave(&up->port.lock, flags);
\r
1150 if (break_state == -1)
\r
1151 up->lcr |= UART_LCR_SBC;
\r
1153 up->lcr &= ~UART_LCR_SBC;
\r
1154 serial_lcr_write(up, up->lcr);
\r
1155 spin_unlock_irqrestore(&up->port.lock, flags);
\r
1156 dev_dbg(port->dev, "-%s lcr: 0x%02x\n", __func__, up->lcr);
\r
1159 #if defined(CONFIG_SERIAL_ROCKCHIP_CONSOLE) || defined(CONFIG_CONSOLE_POLL)
\r
1161 * Wait for transmitter & holding register to empty
\r
1163 static void wait_for_xmitr(struct uart_rk_port *up, int bits)
\r
1165 unsigned int status, tmout = 10000;
\r
1167 /* Wait up to 10ms for the character(s) to be sent. */
\r
1169 status = serial_in(up, UART_LSR);
\r
1171 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
\r
1173 if ((status & bits) == bits)
\r
1182 #ifdef CONFIG_CONSOLE_POLL
\r
1184 * Console polling routines for writing and reading from the uart while
\r
1185 * in an interrupt or debug context.
\r
1188 static int serial_rk_get_poll_char(struct uart_port *port)
\r
1190 struct uart_rk_port *up =
\r
1191 container_of(port, struct uart_rk_port, port);
\r
1192 unsigned char lsr = serial_in(up, UART_LSR);
\r
1194 while (!(lsr & UART_LSR_DR))
\r
1195 lsr = serial_in(up, UART_LSR);
\r
1197 return serial_in(up, UART_RX);
\r
1200 static void serial_rk_put_poll_char(struct uart_port *port,
\r
1204 struct uart_rk_port *up =
\r
1205 container_of(port, struct uart_rk_port, port);
\r
1208 * First save the IER then disable the interrupts
\r
1210 ier = serial_in(up, UART_IER);
\r
1211 serial_out(up, UART_IER, 0);
\r
1213 wait_for_xmitr(up, UART_LSR_TEMT);
\r
1215 * Send the character out.
\r
1216 * If a LF, also do CR...
\r
1218 serial_out(up, UART_TX, c);
\r
1220 wait_for_xmitr(up, UART_LSR_TEMT);
\r
1221 serial_out(up, UART_TX, 13);
\r
1225 * Finally, wait for transmitter to become empty
\r
1226 * and restore the IER
\r
1228 wait_for_xmitr(up, UART_LSR_TEMT);
\r
1229 serial_out(up, UART_IER, ier);
\r
1232 #endif /* CONFIG_CONSOLE_POLL */
\r
1234 static int serial_rk_startup(struct uart_port *port)
\r
1236 struct uart_rk_port *up =
\r
1237 container_of(port, struct uart_rk_port, port);
\r
1238 unsigned long flags;
\r
1239 int retval, fifosize = 0;
\r
1242 dev_dbg(port->dev, "%s\n", __func__);
\r
1245 * Allocate the IRQ
\r
1247 retval = request_irq(up->port.irq, serial_rk_interrupt, up->port.irqflags,
\r
1253 #ifdef CONFIG_CLOCK_CTRL
\r
1254 clk_prepare_enable(up->clk);
\r
1255 clk_prepare_enable(up->pclk); // enable the config uart clock
\r
1258 * Clear the FIFO buffers and disable them.
\r
1259 * (they will be reenabled in set_termios())
\r
1261 serial_rk_clear_fifos(up);
\r
1263 //read uart fifo size hhb@rock-chips.com
\r
1264 fifosize = __raw_readl(up->port.membase + 0xf4);
\r
1265 up->port.fifosize = ((fifosize >> 16) & 0xff) << 4;
\r
1266 if(up->port.fifosize <= 0)
\r
1267 up->port.fifosize = 32;
\r
1268 //printk("fifo size:%d :%08x\n", up->port.fifosize, fifosize);
\r
1271 * Clear the interrupt registers.
\r
1273 (void) serial_in(up, UART_LSR);
\r
1274 (void) serial_in(up, UART_RX);
\r
1275 (void) serial_in(up, UART_IIR);
\r
1276 (void) serial_in(up, UART_MSR);
\r
1277 (void) serial_in(up, UART_USR);
\r
1280 * Now, initialize the UART
\r
1282 serial_lcr_write(up, UART_LCR_WLEN8 | UART_LCR_EPAR);
\r
1284 spin_lock_irqsave(&up->port.lock, flags);
\r
1287 * Most PC uarts need OUT2 raised to enable interrupts.
\r
1289 // up->port.mctrl |= TIOCM_OUT2;
\r
1291 serial_rk_set_mctrl(&up->port, up->port.mctrl);
\r
1293 spin_unlock_irqrestore(&up->port.lock, flags);
\r
1296 * Clear the interrupt registers again for luck, and clear the
\r
1297 * saved flags to avoid getting false values from polling
\r
1298 * routines or the previous session.
\r
1300 (void) serial_in(up, UART_LSR);
\r
1301 (void) serial_in(up, UART_RX);
\r
1302 (void) serial_in(up, UART_IIR);
\r
1303 (void) serial_in(up, UART_MSR);
\r
1304 (void) serial_in(up, UART_USR);
\r
1305 up->lsr_saved_flags = 0;
\r
1307 up->msr_saved_flags = 0;
\r
1310 if (up->dma->use_dma & TX_DMA) {
\r
1311 if(up->port.state->xmit.buf != up->dma->tx_buffer){
\r
1312 free_page((unsigned long)up->port.state->xmit.buf);
\r
1313 up->port.state->xmit.buf = up->dma->tx_buffer;
\r
1319 serial_out(up, UART_IER, up->ier);
\r
1323 * Finally, enable interrupts. Note: Modem status interrupts
\r
1324 * are set via set_termios(), which will be occurring imminently
\r
1325 * anyway, so we don't enable them here.
\r
1332 static void serial_rk_shutdown(struct uart_port *port)
\r
1334 struct uart_rk_port *up =
\r
1335 container_of(port, struct uart_rk_port, port);
\r
1336 unsigned long flags;
\r
1338 dev_dbg(port->dev, "%s\n", __func__);
\r
1340 * Disable interrupts from this port
\r
1343 serial_out(up, UART_IER, 0);
\r
1345 spin_lock_irqsave(&up->port.lock, flags);
\r
1346 // up->port.mctrl &= ~TIOCM_OUT2;
\r
1347 serial_rk_set_mctrl(&up->port, up->port.mctrl);
\r
1348 spin_unlock_irqrestore(&up->port.lock, flags);
\r
1351 * Disable break condition and FIFOs
\r
1353 serial_lcr_write(up, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
\r
1354 serial_rk_clear_fifos(up);
\r
1357 * Read data port to reset things, and then free the irq
\r
1359 (void) serial_in(up, UART_RX);
\r
1361 if (up->dma->use_dma & TX_DMA)
\r
1362 up->port.state->xmit.buf = NULL;
\r
1364 free_irq(up->port.irq, up);
\r
1365 #ifdef CONFIG_CLOCK_CTRL
\r
1366 clk_disable_unprepare(up->clk);
\r
1367 clk_disable_unprepare(up->pclk);
\r
1372 serial_rk_set_termios(struct uart_port *port, struct ktermios *termios,
\r
1373 struct ktermios *old)
\r
1375 struct uart_rk_port *up =
\r
1376 container_of(port, struct uart_rk_port, port);
\r
1377 unsigned char cval = 0, fcr = 0, mcr = 0;
\r
1378 unsigned long flags;
\r
1379 unsigned int baud, quot;
\r
1381 dev_dbg(port->dev, "+%s\n", __func__);
\r
1384 //stop dma tx, which might make the uart be busy while some registers are set
\r
1385 if(up->dma->tx_dma_used) {
\r
1386 serial_rk_stop_dma_tx(up);
\r
1390 switch (termios->c_cflag & CSIZE) {
\r
1392 cval = UART_LCR_WLEN5;
\r
1395 cval = UART_LCR_WLEN6;
\r
1398 cval = UART_LCR_WLEN7;
\r
1402 cval = UART_LCR_WLEN8;
\r
1406 if (termios->c_cflag & CSTOPB){
\r
1407 cval |= UART_LCR_STOP;
\r
1409 if (termios->c_cflag & PARENB){
\r
1410 cval |= UART_LCR_PARITY;
\r
1412 if (!(termios->c_cflag & PARODD)){
\r
1413 cval |= UART_LCR_EPAR;
\r
1416 if (termios->c_cflag & CMSPAR)
\r
1417 cval |= UART_LCR_SPAR;
\r
1422 * Ask the core to calculate the divisor for us.
\r
1424 baud = uart_get_baud_rate(port, termios, old,
\r
1425 port->uartclk / 16 / 0xffff,
\r
1426 port->uartclk / 16);
\r
1428 quot = uart_get_divisor(port, baud);
\r
1429 //dev_info(up->port.dev, "uartclk:%d\n", port->uartclk/16);
\r
1430 //dev_info(up->port.dev, "baud:%d\n", baud);
\r
1431 //dev_info(up->port.dev, "quot:%d\n", quot);
\r
1434 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
\r
1437 fcr = UART_FCR_ENABLE_FIFO;
\r
1439 //added by hhb@rock-chips.com
\r
1440 if(up->dma->use_dma & TX_DMA){
\r
1441 fcr |= UART_FCR_T_TRIG_01;
\r
1445 fcr |= UART_FCR_T_TRIG_01;
\r
1449 //added by hhb@rock-chips.com
\r
1450 if(up->dma->use_dma & RX_DMA){
\r
1451 fcr |= UART_FCR_R_TRIG_00;
\r
1455 if (termios->c_cflag & CRTSCTS)
\r
1456 fcr |= UART_FCR_R_TRIG_11;
\r
1458 fcr |= UART_FCR_R_TRIG_00;
\r
1463 * MCR-based auto flow control. When AFE is enabled, RTS will be
\r
1464 * deasserted when the receive FIFO contains more characters than
\r
1465 * the trigger, or the MCR RTS bit is cleared. In the case where
\r
1466 * the remote UART is not using CTS auto flow control, we must
\r
1467 * have sufficient FIFO entries for the latency of the remote
\r
1468 * UART to respond. IOW, at least 32 bytes of FIFO.
\r
1470 up->mcr &= ~UART_MCR_AFE;
\r
1471 if (termios->c_cflag & CRTSCTS){
\r
1472 up->mcr |= UART_MCR_AFE;
\r
1476 * Ok, we're now changing the port state. Do it with
\r
1477 * interrupts disabled.
\r
1479 spin_lock_irqsave(&up->port.lock, flags);
\r
1482 * Update the per-port timeout.
\r
1484 uart_update_timeout(port, termios->c_cflag, baud);
\r
1486 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
\r
1487 if (termios->c_iflag & INPCK)
\r
1488 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
\r
1489 if (termios->c_iflag & (BRKINT | PARMRK))
\r
1490 up->port.read_status_mask |= UART_LSR_BI;
\r
1493 * Characteres to ignore
\r
1495 up->port.ignore_status_mask = 0;
\r
1496 if (termios->c_iflag & IGNPAR)
\r
1497 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
\r
1498 if (termios->c_iflag & IGNBRK) {
\r
1499 up->port.ignore_status_mask |= UART_LSR_BI;
\r
1501 * If we're ignoring parity and break indicators,
\r
1502 * ignore overruns too (for real raw support).
\r
1504 if (termios->c_iflag & IGNPAR)
\r
1505 up->port.ignore_status_mask |= UART_LSR_OE;
\r
1509 * ignore all characters if CREAD is not set
\r
1511 if ((termios->c_cflag & CREAD) == 0)
\r
1512 up->port.ignore_status_mask |= UART_LSR_DR;
\r
1515 * CTS flow control flag and modem status interrupts
\r
1517 up->ier &= ~UART_IER_MSI;
\r
1519 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
\r
1520 up->ier |= UART_IER_MSI;
\r
1523 //to avoid uart busy when set baud rate hhb@rock-chips.com
\r
1524 serial_out(up, UART_SRR, UART_RESET);
\r
1525 mcr = serial_in(up, UART_MCR);
\r
1526 serial_out(up, UART_MCR, mcr | 0x10); //loopback mode
\r
1528 up->lcr = cval; /* Save LCR */
\r
1530 if(serial_lcr_write(up, cval | UART_LCR_DLAB)) {
\r
1531 if(up->port.line != DBG_PORT)
\r
1532 dbg("serial.%d set DLAB fail\n", up->port.line);
\r
1533 serial_out(up, UART_SRR, UART_RESET);
\r
1537 /* set uart baud rate */
\r
1538 if(serial_dl_write(up, quot)) {
\r
1539 if(up->port.line != DBG_PORT)
\r
1540 dbg("serial.%d set dll fail\n", up->port.line);
\r
1541 serial_out(up, UART_SRR, UART_RESET);
\r
1546 if(serial_lcr_write(up, cval)) {
\r
1547 if(up->port.line != DBG_PORT)
\r
1548 dbg("serial.%d reset DLAB fail\n", up->port.line);
\r
1549 serial_out(up, UART_SRR, UART_RESET);
\r
1553 serial_rk_set_mctrl(&up->port, up->port.mctrl);
\r
1555 serial_out(up, UART_FCR, up->fcr); /* set fcr */
\r
1557 //start serial receive data
\r
1559 if (up->dma->use_dma) {
\r
1560 up->ier |= UART_IER_RLSI;
\r
1561 up->ier |= UART_IER_PTIME; //Programmable THRE Interrupt Mode Enable
\r
1562 if (up->dma->use_dma & RX_DMA)
\r
1563 serial_rk_start_dma_rx(up);
\r
1565 up->ier |= UART_IER_RDI;
\r
1569 // not use dma receive
\r
1570 up->ier |= UART_IER_RDI;
\r
1571 up->ier |= UART_IER_RLSI;
\r
1572 if(up->port.line != DBG_PORT)
\r
1573 up->ier |= UART_IER_PTIME; //Programmable THRE Interrupt Mode Enable
\r
1576 serial_out(up, UART_IER, up->ier);
\r
1579 spin_unlock_irqrestore(&up->port.lock, flags);
\r
1581 /* Don't rewrite B0 */
\r
1582 if (tty_termios_baud_rate(termios))
\r
1583 tty_termios_encode_baud_rate(termios, baud, baud);
\r
1584 dev_dbg(port->dev, "-%s baud %d\n", __func__, baud);
\r
1588 spin_unlock_irqrestore(&up->port.lock, flags);
\r
1594 serial_rk_set_ldisc(struct uart_port *port, int new)
\r
1596 if (new == N_PPS) {
\r
1597 port->flags |= UPF_HARDPPS_CD;
\r
1598 serial_rk_enable_ms(port);
\r
1600 port->flags &= ~UPF_HARDPPS_CD;
\r
1605 serial_rk_pm(struct uart_port *port, unsigned int state,
\r
1606 unsigned int oldstate)
\r
1608 #ifdef CONFIG_CLOCK_CTRL
\r
1609 struct uart_rk_port *up =
\r
1610 container_of(port, struct uart_rk_port, port);
\r
1612 dev_dbg(port->dev, "%s: %s\n", __func__, state ? "disable" : "enable");
\r
1614 clk_disable_unprepare(up->clk);
\r
1615 clk_disable_unprepare(up->pclk);
\r
1617 clk_prepare_enable(up->clk);
\r
1618 clk_prepare_enable(up->pclk);
\r
1623 static void serial_rk_release_port(struct uart_port *port)
\r
1625 dev_dbg(port->dev, "%s\n", __func__);
\r
1628 static int serial_rk_request_port(struct uart_port *port)
\r
1630 dev_dbg(port->dev, "%s\n", __func__);
\r
1634 static void serial_rk_config_port(struct uart_port *port, int flags)
\r
1636 dev_dbg(port->dev, "%s\n", __func__);
\r
1637 port->type = PORT_RK;
\r
1641 serial_rk_verify_port(struct uart_port *port, struct serial_struct *ser)
\r
1643 /* we don't want the core code to modify any port params */
\r
1644 dev_dbg(port->dev, "%s\n", __func__);
\r
1648 static const char *
\r
1649 serial_rk_type(struct uart_port *port)
\r
1651 struct uart_rk_port *up =
\r
1652 container_of(port, struct uart_rk_port, port);
\r
1654 dev_dbg(port->dev, "%s: %s\n", __func__, up->name);
\r
1658 static struct uart_ops serial_rk_pops = {
\r
1659 .tx_empty = serial_rk_tx_empty,
\r
1660 .set_mctrl = serial_rk_set_mctrl,
\r
1661 .get_mctrl = serial_rk_get_mctrl,
\r
1662 .stop_tx = serial_rk_stop_tx,
\r
1663 .start_tx = serial_rk_start_tx,
\r
1664 .stop_rx = serial_rk_stop_rx,
\r
1665 .enable_ms = serial_rk_enable_ms,
\r
1666 .break_ctl = serial_rk_break_ctl,
\r
1667 .startup = serial_rk_startup,
\r
1668 .shutdown = serial_rk_shutdown,
\r
1669 .set_termios = serial_rk_set_termios,
\r
1671 .set_ldisc = serial_rk_set_ldisc,
\r
1673 .pm = serial_rk_pm,
\r
1674 .type = serial_rk_type,
\r
1675 .release_port = serial_rk_release_port,
\r
1676 .request_port = serial_rk_request_port,
\r
1677 .config_port = serial_rk_config_port,
\r
1678 .verify_port = serial_rk_verify_port,
\r
1679 #ifdef CONFIG_CONSOLE_POLL
\r
1680 .poll_get_char = serial_rk_get_poll_char,
\r
1681 .poll_put_char = serial_rk_put_poll_char,
\r
1685 #ifdef CONFIG_SERIAL_ROCKCHIP_CONSOLE
\r
1687 static struct uart_rk_port *serial_rk_console_ports[UART_NR];
\r
1689 static void serial_rk_console_putchar(struct uart_port *port, int ch)
\r
1691 struct uart_rk_port *up =
\r
1692 container_of(port, struct uart_rk_port, port);
\r
1694 wait_for_xmitr(up, UART_LSR_THRE);
\r
1695 serial_out(up, UART_TX, ch);
\r
1699 * Print a string to the serial port trying not to disturb
\r
1700 * any possible real use of the port...
\r
1702 * The console_lock must be held when we get here.
\r
1705 serial_rk_console_write(struct console *co, const char *s, unsigned int count)
\r
1707 struct uart_rk_port *up = serial_rk_console_ports[co->index];
\r
1708 unsigned long flags;
\r
1712 touch_nmi_watchdog();
\r
1714 local_irq_save(flags);
\r
1715 if (up->port.sysrq) {
\r
1716 /* serial_rk_handle_port() already took the lock */
\r
1718 } else if (oops_in_progress) {
\r
1719 locked = spin_trylock(&up->port.lock);
\r
1721 spin_lock(&up->port.lock);
\r
1724 * First save the IER then disable the interrupts
\r
1726 ier = serial_in(up, UART_IER);
\r
1728 serial_out(up, UART_IER, 0);
\r
1730 uart_console_write(&up->port, s, count, serial_rk_console_putchar);
\r
1733 * Finally, wait for transmitter to become empty
\r
1734 * and restore the IER
\r
1736 wait_for_xmitr(up, UART_LSR_TEMT);
\r
1737 serial_out(up, UART_IER, ier);
\r
1741 * The receive handling will happen properly because the
\r
1742 * receive ready bit will still be set; it is not cleared
\r
1743 * on read. However, modem control will not, we must
\r
1744 * call it if we have saved something in the saved flags
\r
1745 * while processing with interrupts off.
\r
1747 if (up->msr_saved_flags)
\r
1748 check_modem_status(up);
\r
1752 spin_unlock(&up->port.lock);
\r
1753 local_irq_restore(flags);
\r
1756 #ifdef CONFIG_RK_CONSOLE_THREAD
\r
1757 #include <linux/kfifo.h>
\r
1758 #include <linux/kthread.h>
\r
1759 static struct task_struct *console_task;
\r
1760 #define FIFO_SIZE SZ_512K
\r
1761 static DEFINE_KFIFO(fifo, unsigned char, FIFO_SIZE);
\r
1762 static bool console_thread_stop;
\r
1764 static void console_putc(struct uart_rk_port *up, unsigned int c)
\r
1766 while (!(serial_in(up, UART_USR) & UART_USR_TX_FIFO_NOT_FULL))
\r
1768 serial_out(up, UART_TX, c);
\r
1771 static void console_flush(struct uart_rk_port *up)
\r
1773 while (!(serial_in(up, UART_USR) & UART_USR_TX_FIFO_EMPTY))
\r
1777 static int console_thread(void *data)
\r
1779 struct uart_rk_port *up = data;
\r
1783 set_current_state(TASK_INTERRUPTIBLE);
\r
1785 if (kthread_should_stop())
\r
1787 set_current_state(TASK_RUNNING);
\r
1788 while (!console_thread_stop && serial_in(up, UART_SFE) && kfifo_get(&fifo, &c)) {
\r
1789 console_putc(up, c);
\r
1791 if (!console_thread_stop)
\r
1792 console_flush(up);
\r
1798 static void console_write(struct console *co, const char *s, unsigned int count)
\r
1800 struct uart_rk_port *up = serial_rk_console_ports[co->index];
\r
1801 unsigned int fifo_count = FIFO_SIZE;
\r
1802 unsigned char c, r = '\r';
\r
1804 if (console_thread_stop ||
\r
1805 oops_in_progress ||
\r
1806 system_state == SYSTEM_HALT ||
\r
1807 system_state == SYSTEM_POWER_OFF ||
\r
1808 system_state == SYSTEM_RESTART) {
\r
1809 if (!console_thread_stop) {
\r
1810 console_thread_stop = true;
\r
1812 console_flush(up);
\r
1813 while (fifo_count-- && kfifo_get(&fifo, &c))
\r
1814 console_putc(up, c);
\r
1818 console_putc(up, r);
\r
1820 console_putc(up, *s++);
\r
1822 console_flush(up);
\r
1826 kfifo_put(&fifo, &r);
\r
1828 kfifo_put(&fifo, s++);
\r
1830 wake_up_process(console_task);
\r
1835 static int __init serial_rk_console_setup(struct console *co, char *options)
\r
1837 struct uart_rk_port *up;
\r
1838 int baud = 115200;
\r
1843 if (unlikely(co->index >= UART_NR || co->index < 0))
\r
1846 if (serial_rk_console_ports[co->index] == NULL)
\r
1848 up = serial_rk_console_ports[co->index];
\r
1851 uart_parse_options(options, &baud, &parity, &bits, &flow);
\r
1853 #ifdef CONFIG_RK_CONSOLE_THREAD
\r
1854 if (!console_task) {
\r
1855 console_task = kthread_create(console_thread, up, "kconsole");
\r
1856 if (!IS_ERR(console_task))
\r
1857 co->write = console_write;
\r
1860 return uart_set_options(&up->port, co, baud, parity, bits, flow);
\r
1863 static struct console serial_rk_console = {
\r
1865 .write = serial_rk_console_write,
\r
1866 .device = uart_console_device,
\r
1867 .setup = serial_rk_console_setup,
\r
1868 .flags = CON_PRINTBUFFER | CON_ANYTIME,
\r
1870 .data = &serial_rk_reg,
\r
1873 static void serial_rk_add_console_port(struct uart_rk_port *up)
\r
1875 serial_rk_console_ports[up->pdev->id] = up;
\r
1878 #define SERIAL_CONSOLE &serial_rk_console
\r
1880 #define SERIAL_CONSOLE NULL
\r
1882 static inline void serial_rk_add_console_port(struct uart_rk_port *up)
\r
1887 static struct uart_driver serial_rk_reg = {
\r
1888 .owner = THIS_MODULE,
\r
1889 .driver_name = "rk_serial",
\r
1890 .dev_name = "ttyS",
\r
1891 .major = TTY_MAJOR,
\r
1893 .cons = SERIAL_CONSOLE,
\r
1897 static irqreturn_t serial_rk_wakeup_handler(int irq, void *dev) {
\r
1898 struct uart_rk_port *up = dev;
\r
1899 struct uart_wake_up *wakeup = up->wakeup;
\r
1900 if(wakeup->enable == 1) {
\r
1901 iomux_set(wakeup->rx_mode);
\r
1902 wake_lock_timeout(&wakeup->wakelock, 3 * HZ);
\r
1907 static int serial_rk_setup_wakeup_irq(struct uart_rk_port *up)
\r
1910 struct uart_wake_up *wakeup = up->wakeup;
\r
1912 if(wakeup->enable == 1) {
\r
1913 memset(wakeup->wakelock_name, 0, 32);
\r
1914 sprintf(wakeup->wakelock_name, "serial.%d_wakelock", up->port.line);
\r
1915 wake_lock_init(&wakeup->wakelock, WAKE_LOCK_SUSPEND, wakeup->wakelock_name);
\r
1916 memset(wakeup->rx_pin_name, 0, 32);
\r
1917 sprintf(wakeup->rx_pin_name, "UART%d_SIN", up->port.line);
\r
1918 wakeup->rx_pin = iomux_mode_to_gpio(wakeup->rx_mode);
\r
1919 ret = gpio_request(wakeup->rx_pin, wakeup->rx_pin_name);
\r
1921 printk("request %s fail ! \n", wakeup->rx_pin_name);
\r
1924 gpio_direction_input(wakeup->rx_pin);
\r
1925 wakeup->rx_irq = gpio_to_irq(wakeup->rx_pin);
\r
1926 memset(wakeup->rx_irq_name, 0, 32);
\r
1927 sprintf(wakeup->rx_irq_name, "serial.%d_wake_up_irq", up->port.line);
\r
1928 ret = request_irq(wakeup->rx_irq, serial_rk_wakeup_handler, IRQF_TRIGGER_FALLING, wakeup->rx_irq_name, up);
\r
1930 printk("%s request fail\n", wakeup->rx_irq_name);
\r
1933 disable_irq_nosync(wakeup->rx_irq);
\r
1934 enable_irq_wake(wakeup->rx_irq);
\r
1935 iomux_set(wakeup->rx_mode);
\r
1940 static int serial_rk_enable_wakeup_irq(struct uart_rk_port *up) {
\r
1941 struct uart_wake_up *wakeup = up->wakeup;
\r
1942 if(wakeup->enable == 1) {
\r
1943 iomux_set(wakeup->rx_mode & 0xfff0);
\r
1944 enable_irq(wakeup->rx_irq);
\r
1949 static int serial_rk_disable_wakeup_irq(struct uart_rk_port *up) {
\r
1950 struct uart_wake_up *wakeup = up->wakeup;
\r
1951 if(wakeup->enable == 1) {
\r
1952 disable_irq_nosync(wakeup->rx_irq);
\r
1953 iomux_set(wakeup->rx_mode);
\r
1958 static int serial_rk_remove_wakeup_irq(struct uart_rk_port *up) {
\r
1959 struct uart_wake_up *wakeup = up->wakeup;
\r
1960 if(wakeup->enable == 1) {
\r
1961 //disable_irq_nosync(wakeup->rx_irq);
\r
1962 free_irq(wakeup->rx_irq, NULL);
\r
1963 gpio_free(wakeup->rx_pin);
\r
1964 wake_lock_destroy(&wakeup->wakelock);
\r
1971 static int of_rk_serial_parse_dt(struct device_node *np, struct of_rk_serial *rks)
\r
1973 unsigned int val = 0;
\r
1974 const char *s = NULL;
\r
1976 rks->id = of_alias_get_id(np, "serial");
\r
1977 if(!of_property_read_u32(np, "clock-frequency", &val))
\r
1978 rks->uartclk = val;
\r
1982 for(i = 0; i < 2; i++) {
\r
1983 ret = of_property_read_string_index(np, "dma-names", i, &s);
\r
1985 if(!strcmp(s, "tx"))
\r
1986 rks->use_dma |= TX_DMA;
\r
1987 else if (!strcmp(s, "rx"))
\r
1988 rks->use_dma |= RX_DMA;
\r
1996 static int serial_rk_probe(struct platform_device *pdev)
\r
1998 struct uart_rk_port *up;
\r
1999 struct resource *mem;
\r
2001 int ret = -ENOSPC;
\r
2002 struct of_rk_serial rks;
\r
2004 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
\r
2008 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
\r
2009 up->port.membase = devm_request_and_ioremap(&pdev->dev, mem);
\r
2010 if (!up->port.membase)
\r
2013 irq = platform_get_irq(pdev, 0);
\r
2015 dev_err(&pdev->dev, "no irq resource?\n");
\r
2020 of_rk_serial_parse_dt(pdev->dev.of_node, &rks);
\r
2021 pdev->id = rks.id;
\r
2024 sprintf(up->name, "rk29_serial.%d", pdev->id);
\r
2026 #ifdef CONFIG_CLOCK_CTRL
\r
2027 up->pclk = devm_clk_get(&pdev->dev, "pclk_uart");
\r
2028 up->clk = devm_clk_get(&pdev->dev, "sclk_uart");
\r
2029 if (unlikely(IS_ERR(up->clk)) || unlikely(IS_ERR(up->pclk))) {
\r
2030 dev_err(&pdev->dev, "get clock fail\n");
\r
2034 up->tx_loadsz = 30;
\r
2036 up->dma = devm_kzalloc(&pdev->dev, sizeof(struct rk_uart_dma), GFP_KERNEL);
\r
2038 dev_err(&pdev->dev, "unable to allocate mem\n");
\r
2041 up->dma->use_dma = rks.use_dma;
\r
2044 up->wakeup = &rk29_uart_ports_wakeup[pdev->id];
\r
2046 up->port.dev = &pdev->dev;
\r
2047 up->port.type = PORT_RK;
\r
2048 up->port.irq = irq;
\r
2049 up->port.iotype = UPIO_MEM;
\r
2051 up->port.regshift = 2;
\r
2052 //fifo size default is 32, but it will be updated later when start_up
\r
2053 up->port.fifosize = 32;
\r
2054 up->port.ops = &serial_rk_pops;
\r
2055 up->port.line = pdev->id;
\r
2056 up->port.iobase = mem->start;
\r
2057 up->port.mapbase = mem->start;
\r
2058 up->port.irqflags = IRQF_DISABLED;
\r
2059 #if defined(CONFIG_CLOCK_CTRL)
\r
2060 up->port.uartclk = clk_get_rate(up->clk);
\r
2061 #elif defined(CONFIG_OF)
\r
2062 up->port.uartclk = rks.uartclk;
\r
2064 up->port.uartclk = 24000000;
\r
2068 /* set dma config */
\r
2069 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
\r
2070 if(up->dma->use_dma & RX_DMA) {
\r
2072 up->dma->use_timer = USE_TIMER;
\r
2073 up->dma->rx_timer.function = serial_rk_report_dma_rx;
\r
2074 up->dma->rx_timer.data = (unsigned long)up;
\r
2075 up->dma->rx_timeout = 10;
\r
2076 up->dma->rx_timer.expires = jiffies + msecs_to_jiffies(up->dma->rx_timeout);
\r
2077 init_timer(&up->dma->rx_timer);
\r
2080 up->dma->rb_size = DMA_SERIAL_BUFFER_SIZE;
\r
2081 up->dma->rx_buffer = dmam_alloc_coherent(up->port.dev, up->dma->rb_size,
\r
2082 &up->dma->rx_phy_addr, DMA_MEMORY_MAP);
\r
2083 up->dma->rb_tail = 0;
\r
2084 up->dma->rx_dma_inited = 0;
\r
2085 up->dma->rx_dma_used = 0;
\r
2087 if(!up->dma->rx_buffer){
\r
2088 dev_info(up->port.dev, "dmam_alloc_coherent dma_rx_buffer fail\n");
\r
2091 dev_info(up->port.dev, "dma_rx_buffer %p\n", up->dma->rx_buffer);
\r
2092 dev_info(up->port.dev, "dma_rx_phy 0x%08x\n", (unsigned)up->dma->rx_phy_addr);
\r
2096 //INIT_WORK(&up->uart_work, serial_rk_report_revdata_workfunc);
\r
2097 //INIT_WORK(&up->uart_work_rx, serial_rk_start_dma_rx);
\r
2098 //up->uart_wq = create_singlethread_workqueue("uart_workqueue");
\r
2099 spin_lock_init(&(up->dma->rx_lock));
\r
2100 serial_rk_init_dma_rx(up);
\r
2103 if(up->dma->use_dma & TX_DMA){
\r
2105 up->dma->tb_size = UART_XMIT_SIZE;
\r
2106 up->dma->tx_buffer = dmam_alloc_coherent(up->port.dev, up->dma->tb_size,
\r
2107 &up->dma->tx_phy_addr, DMA_MEMORY_MAP);
\r
2108 if(!up->dma->tx_buffer){
\r
2109 dev_info(up->port.dev, "dmam_alloc_coherent dma_tx_buffer fail\n");
\r
2112 dev_info(up->port.dev, "dma_tx_buffer %p\n", up->dma->tx_buffer);
\r
2113 dev_info(up->port.dev, "dma_tx_phy 0x%08x\n", (unsigned) up->dma->tx_phy_addr);
\r
2115 spin_lock_init(&(up->dma->tx_lock));
\r
2116 serial_rk_init_dma_tx(up);
\r
2121 serial_rk_add_console_port(up);
\r
2122 ret = uart_add_one_port(&serial_rk_reg, &up->port);
\r
2125 platform_set_drvdata(pdev, up);
\r
2126 dev_info(&pdev->dev, "membase %p\n", up->port.membase);
\r
2128 serial_rk_setup_wakeup_irq(up);
\r
2133 static int serial_rk_remove(struct platform_device *pdev)
\r
2135 struct uart_rk_port *up = platform_get_drvdata(pdev);
\r
2137 platform_set_drvdata(pdev, NULL);
\r
2140 serial_rk_release_dma_tx(up);
\r
2141 serial_rk_release_dma_rx(up);
\r
2144 serial_rk_remove_wakeup_irq(up);
\r
2146 //destroy_workqueue(up->uart_wq);
\r
2147 uart_remove_one_port(&serial_rk_reg, &up->port);
\r
2148 up->port.membase = NULL;
\r
2154 static int serial_rk_suspend(struct platform_device *dev, pm_message_t state)
\r
2156 struct uart_rk_port *up = platform_get_drvdata(dev);
\r
2158 if (up && up->port.line != DBG_PORT && POWER_MANEGEMENT){
\r
2159 uart_suspend_port(&serial_rk_reg, &up->port);
\r
2161 if(up->port.line == DBG_PORT && POWER_MANEGEMENT){
\r
2162 serial_rk_pm(&up->port, 1, 0);
\r
2165 serial_rk_enable_wakeup_irq(up);
\r
2170 static int serial_rk_resume(struct platform_device *dev)
\r
2172 struct uart_rk_port *up = platform_get_drvdata(dev);
\r
2174 serial_rk_disable_wakeup_irq(up);
\r
2176 if (up && up->port.line != DBG_PORT && POWER_MANEGEMENT){
\r
2177 uart_resume_port(&serial_rk_reg, &up->port);
\r
2179 if(up->port.line == DBG_PORT && POWER_MANEGEMENT){
\r
2180 serial_rk_pm(&up->port, 0, 1);
\r
2185 static const struct of_device_id of_rk_serial_match[] = {
\r
2186 { .compatible = "rockchip,serial" },
\r
2187 { /* Sentinel */ }
\r
2190 static struct platform_driver serial_rk_driver = {
\r
2191 .probe = serial_rk_probe,
\r
2192 .remove = serial_rk_remove,
\r
2193 .suspend = serial_rk_suspend,
\r
2194 .resume = serial_rk_resume,
\r
2198 .of_match_table = of_rk_serial_match,
\r
2200 .owner = THIS_MODULE,
\r
2204 static int __init serial_rk_init(void)
\r
2207 //hhb@rock-chips.com
\r
2208 printk("%s\n", VERSION_AND_TIME);
\r
2209 ret = uart_register_driver(&serial_rk_reg);
\r
2212 ret = platform_driver_register(&serial_rk_driver);
\r
2214 uart_unregister_driver(&serial_rk_reg);
\r
2218 static void __exit serial_rk_exit(void)
\r
2220 platform_driver_unregister(&serial_rk_driver);
\r
2221 uart_unregister_driver(&serial_rk_reg);
\r
2224 module_init(serial_rk_init);
\r
2225 module_exit(serial_rk_exit);
\r
2227 MODULE_LICENSE("GPL");
\r
2228 MODULE_DESCRIPTION("RK UART driver");
\r