drivers/tty/serial/rk_serial.c

   1 /*\r
   2  * Driver for RK-UART controller.\r
   3  * Based on drivers/tty/serial/8250.c\r
   4  *\r
   5  * Copyright (C) 2011 Rochchip.\r
   6  *\r
   7  * This program is free software; you can redistribute it and/or modify\r
   8  * it under the terms of the GNU General Public License as published by\r
   9  * the Free Software Foundation; either version 2 of the License, or\r
  10 \r
  11  * (at your option) any later version.\r
  12  *\r
  13  * Author: hhb@rock-chips.com\r
  14  * Date: 2011.06.18\r
  15  */\r
  16 \r
  17 #if defined(CONFIG_SERIAL_ROCKCHIP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)\r
  18 #define SUPPORT_SYSRQ\r
  19 #endif\r
  20 \r
  21 #include <linux/module.h>\r
  22 #include <linux/ioport.h>\r
  23 #include <linux/init.h>\r
  24 #include <linux/console.h>\r
  25 #include <linux/sysrq.h>\r
  26 #include <linux/delay.h>\r
  27 #include <linux/platform_device.h>\r
  28 #include <linux/tty.h>\r
  29 #include <linux/ratelimit.h>\r
  30 #include <linux/tty_flip.h>\r
  31 #include <linux/serial_reg.h>\r
  32 #include <linux/serial_core.h>\r
  33 #include <linux/serial.h>\r
  34 #include <linux/nmi.h>\r
  35 #include <linux/mutex.h>\r
  36 #include <linux/slab.h>\r
  37 #include <linux/clk.h>\r
  38 #include <linux/timer.h>\r
  39 #include <linux/workqueue.h>\r
  40 #include <linux/dma-mapping.h>\r
  41 #include <asm/io.h>\r
  42 #include <asm/irq.h>\r
  43 \r
  44 #include <linux/dmaengine.h>\r
  45 \r
  46 #ifdef CONFIG_OF\r
  47 #include <linux/of.h>\r
  48 #endif\r
  49 \r
  50 \r
  51 /*\r
  52 *                        Driver Version Note\r
  53 *\r
  54 *v0.0 : this driver is 2.6.32 kernel driver;\r
  55 *v0.1 : this driver is 3.0.8 kernel driver;\r
  56 *v1.0 : 2012-08-09\r
  57 *               1.modify dma dirver;\r
  58 *               2.enable Programmable THRE Interrupt Mode, so we can just judge ((up->iir & 0x0f) == 0x02) when transmit\r
  59 *               3.reset uart and set it to loopback state to ensure setting baud rate sucessfully \r
  60 *v1.1 : 2012-08-23\r
  61 *               1. dma driver:make "when tx dma is only enable" work functionally  \r
  62 *v1.2 : 2012-08-28\r
  63 *               1. dma driver:serial rx use new dma interface  rk29_dma_enqueue_ring \r
  64 *v1.3 : 2012-12-14\r
  65 *               1. When enable Programmable THRE Interrupt Mode, in lsr register, only UART_LSR_TEMT means transmit empty, but\r
  66                  UART_LSR_THRE doesn't. So, the macro BOTH_EMPTY should be replaced with UART_LSR_TEMT.\r
  67 *v1.4 : 2013-04-16\r
  68 *               1.fix bug dma buffer free error\r
  69 *v1.5 : 2013-10-17\r
  70 *               1.in some case, set uart rx as gpio interrupt to wake up arm, when arm suspends \r
  71 *v1.6 : 2013-11-29\r
  72                 migrate to kernel3.10,and fit device tree\r
  73 *v1.7 : 2014-03-03\r
  74                 DMA use new interfaces, and use some interfaces with devm_ prefix \r
  75 *v1.8 : 2014-03-04\r
  76 *               1.clear receive time out interrupt request in irq handler       \r
  77 */\r
  78 #define VERSION_AND_TIME  "rk_serial.c v1.8 2014-03-04"\r
  79 \r
  80 #define PORT_RK         90\r
  81 #define UART_USR        0x1F    /* UART Status Register */\r
  82 #define UART_USR_TX_FIFO_EMPTY          0x04 /* Transmit FIFO empty */\r
  83 #define UART_USR_TX_FIFO_NOT_FULL       0x02 /* Transmit FIFO not full */\r
  84 #define UART_USR_BUSY (1)\r
  85 #define UART_IER_PTIME  0x80    /* Programmable THRE Interrupt Mode Enable */\r
  86 #define UART_LSR_RFE    0x80    /* receive fifo error */\r
  87 #define UART_SRR                0x22    /* software reset register */\r
  88 #define UART_SFE        0x26    /* Shadow FIFO Enable */\r
  89 #define UART_RESET              0x01\r
  90 \r
  91 \r
  92 //#define BOTH_EMPTY    (UART_LSR_TEMT | UART_LSR_THRE)\r
  93 #define UART_NR 5   //uart port number\r
  94 \r
  95 \r
  96 /* configurate whether the port transmit-receive by DMA in menuconfig*/\r
  97 #define OPEN_DMA      1\r
  98 #define CLOSE_DMA     0\r
  99 \r
 100 #define TX_DMA (1)\r
 101 #define RX_DMA (2)\r
 102 #define DMA_SERIAL_BUFFER_SIZE     (UART_XMIT_SIZE*2)\r
 103 #define CONFIG_CLOCK_CTRL  1\r
 104 //serial wake up \r
 105 #ifdef CONFIG_UART0_WAKEUP_RK29 \r
 106 #define UART0_USE_WAKEUP CONFIG_UART0_WAKEUP_RK29\r
 107 #else\r
 108 #define UART0_USE_WAKEUP 0\r
 109 #endif\r
 110 #ifdef CONFIG_UART1_WAKEUP_RK29\r
 111 #define UART1_USE_WAKEUP CONFIG_UART1_WAKEUP_RK29\r
 112 #else\r
 113 #define UART1_USE_WAKEUP 0\r
 114 #endif\r
 115 #ifdef CONFIG_UART2_WAKEUP_RK29\r
 116 #define UART2_USE_WAKEUP CONFIG_UART2_WAKEUP_RK29\r
 117 #else\r
 118 #define UART2_USE_WAKEUP 0\r
 119 #endif\r
 120 #ifdef CONFIG_UART3_WAKEUP_RK29\r
 121 #define UART3_USE_WAKEUP CONFIG_UART3_WAKEUP_RK29\r
 122 #else\r
 123 #define UART3_USE_WAKEUP 0\r
 124 #endif\r
 125 \r
 126 #define USE_TIMER    1           // use timer for dma transport\r
 127 #define POWER_MANEGEMENT 1\r
 128 #define RX_TIMEOUT              (3000*3)  //uint ms\r
 129 #define DMA_TX_TRRIGE_LEVEL 128\r
 130 #define SERIAL_CIRC_CNT_TO_END(xmit)   CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)\r
 131 \r
 132 #define USE_DMA  OPEN_DMA\r
 133 \r
 134 #define USE_WAKEUP (UART0_USE_WAKEUP | UART1_USE_WAKEUP | UART2_USE_WAKEUP | UART3_USE_WAKEUP)\r
 135 \r
 136 #if USE_WAKEUP\r
 137 #include <mach/iomux.h>\r
 138 #include <linux/wakelock.h>\r
 139 #endif\r
 140 \r
 141 \r
 142 \r
 143 static struct uart_driver serial_rk_reg;\r
 144 \r
 145 /*\r
 146  * Debugging.\r
 147  */\r
 148 #ifdef CONFIG_ARCH_RK29\r
 149 #define DBG_PORT 1   //DBG_PORT which uart is used to print log message\r
 150 #else\r
 151 #ifndef CONFIG_RK_DEBUG_UART   //DBG_PORT which uart is used to print log message\r
 152 #define DBG_PORT 2\r
 153 #else\r
 154 #define DBG_PORT CONFIG_RK_DEBUG_UART\r
 155 #endif\r
 156 #endif\r
 157 \r
 158 #ifdef CONFIG_SERIAL_CORE_CONSOLE\r
 159 #define uart_console(port)      ((port)->cons && (port)->cons->index == (port)->line)\r
 160 #else\r
 161 #define uart_console(port)      (0)\r
 162 #endif\r
 163 \r
 164 \r
 165 extern void printascii(const char *);\r
 166 static void dbg(const char *fmt, ...)\r
 167 {\r
 168         va_list va;\r
 169         char buff[256];\r
 170 \r
 171         va_start(va, fmt);\r
 172         vsprintf(buff, fmt, va);\r
 173         va_end(va);\r
 174 \r
 175 #if defined(CONFIG_DEBUG_LL) || defined(CONFIG_RK_EARLY_PRINTK)\r
 176         printascii(buff);\r
 177 #endif\r
 178 }\r
 179 \r
 180 //enable log output\r
 181 #define DEBUG 0\r
 182 static int log_port = -1;\r
 183 module_param(log_port, int, S_IRUGO|S_IWUSR);\r
 184 \r
 185 #if DEBUG\r
 186 #define DEBUG_INTR(fmt...)      if (up->port.line == log_port && !uart_console(&up->port)) dbg(fmt)\r
 187 #else\r
 188 #define DEBUG_INTR(fmt...)      do { } while (0)\r
 189 #endif\r
 190 \r
 191 \r
 192 #if USE_DMA\r
 193 /* added by hhb@rock-chips.com for uart dma transfer */\r
 194 \r
 195 struct rk_uart_dma {\r
 196         u32 use_dma;            //1:used\r
 197         //enum dma_ch rx_dmach;\r
 198         //enum dma_ch tx_dmach;\r
 199 \r
 200         //receive and transfer buffer\r
 201         char * rx_buffer;    //visual memory\r
 202         char * tx_buffer;\r
 203         dma_addr_t rx_phy_addr;  //physical memory\r
 204         dma_addr_t tx_phy_addr;\r
 205         u32 rb_size;             //buffer size\r
 206         u32 tb_size;\r
 207 \r
 208         //regard the rx buffer as a circular buffer\r
 209         u32 rb_head;\r
 210         u32 rb_tail;\r
 211         u32 rx_size;\r
 212 \r
 213         spinlock_t              tx_lock;\r
 214         spinlock_t              rx_lock;\r
 215 \r
 216         char tx_dma_inited;   //1:dma tx channel has been init\r
 217         char rx_dma_inited;      //1:dma rx channel has been init\r
 218         char tx_dma_used;        //1:dma tx is working\r
 219         char rx_dma_used;    //1:dma rx is working\r
 220 \r
 221         /* timer to poll activity on rx dma */\r
 222         char use_timer;\r
 223         int      rx_timeout;\r
 224         struct timer_list rx_timer;\r
 225 \r
 226         struct dma_chan         *dma_chan_rx, *dma_chan_tx;\r
 227         struct scatterlist      rx_sgl, tx_sgl;\r
 228         unsigned int            rx_bytes, tx_bytes;\r
 229 };\r
 230 #endif\r
 231 \r
 232 #if USE_WAKEUP  \r
 233 struct uart_wake_up {\r
 234         unsigned int enable;\r
 235         unsigned int rx_mode;\r
 236         unsigned int tx_mode;\r
 237         unsigned int rx_pin;\r
 238         char rx_pin_name[32];\r
 239         unsigned int tx_pin;\r
 240         unsigned int rx_irq;\r
 241         char rx_irq_name[32];\r
 242         struct wake_lock wakelock;\r
 243         char wakelock_name[32];\r
 244 };\r
 245 #endif\r
 246 \r
 247 #ifdef CONFIG_OF\r
 248 struct of_rk_serial {\r
 249         unsigned int id;\r
 250         unsigned int use_dma;   \r
 251         unsigned int uartclk;\r
 252 };\r
 253 #endif\r
 254 \r
 255 \r
 256 struct uart_rk_port {\r
 257         struct uart_port        port;\r
 258         struct platform_device  *pdev;\r
 259         struct clk              *clk;\r
 260         struct clk              *pclk;\r
 261         unsigned int            tx_loadsz;      /* transmit fifo load size */\r
 262         unsigned char           ier;\r
 263         unsigned char           lcr;\r
 264         unsigned char           mcr;\r
 265         unsigned char           iir;\r
 266         unsigned char           fcr;\r
 267         /*\r
 268          * Some bits in registers are cleared on a read, so they must\r
 269          * be saved whenever the register is read but the bits will not\r
 270          * be immediately processed.\r
 271          */\r
 272 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS\r
 273         unsigned char           lsr_saved_flags;\r
 274 #if 0\r
 275 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA\r
 276         unsigned char           msr_saved_flags;\r
 277 #endif\r
 278 \r
 279         char                    name[16];\r
 280         char                    fifo[64];\r
 281         char                    fifo_size;\r
 282         unsigned long           port_activity;\r
 283         struct work_struct uart_work;\r
 284         struct work_struct uart_work_rx;\r
 285         struct workqueue_struct *uart_wq;\r
 286         struct rk_uart_dma *dma;\r
 287 #if USE_WAKEUP\r
 288         struct uart_wake_up *wakeup;\r
 289 #endif\r
 290 };\r
 291 \r
 292 #if USE_DMA\r
 293 static void serial_rk_release_dma_tx(struct uart_rk_port *up);\r
 294 static int serial_rk_start_dma_tx(struct uart_rk_port *up);\r
 295 //static void serial_rk_rx_timeout(unsigned long uart);\r
 296 static void serial_rk_release_dma_rx(struct uart_rk_port *up);\r
 297 static int serial_rk_start_dma_rx(struct uart_rk_port *up);\r
 298 static void serial_rk_stop_dma_tx(struct uart_rk_port *up);\r
 299 static void serial_rk_stop_dma_rx(struct uart_rk_port *up);\r
 300 \r
 301 #else\r
 302 static inline int serial_rk_start_tx_dma(struct uart_port *port) { return 0; }\r
 303 #endif\r
 304 static int serial_rk_startup(struct uart_port *port);\r
 305 \r
 306 static inline unsigned int serial_in(struct uart_rk_port *up, int offset)\r
 307 {\r
 308         offset = offset << 2;\r
 309 \r
 310         return __raw_readl(up->port.membase + offset);\r
 311 }\r
 312 \r
 313 /* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */\r
 314 static inline void dwapb_save_out_value(struct uart_rk_port *up, int offset,\r
 315                                         unsigned char value)\r
 316 {\r
 317         if (offset == UART_LCR)\r
 318                 up->lcr = value;\r
 319 }\r
 320 \r
 321 /* Read the IER to ensure any interrupt is cleared before returning from ISR. */\r
 322 static inline void dwapb_check_clear_ier(struct uart_rk_port *up, int offset)\r
 323 {\r
 324         if (offset == UART_TX || offset == UART_IER)\r
 325                 serial_in(up, UART_IER);\r
 326 }\r
 327 \r
 328 static inline void serial_out(struct uart_rk_port *up, int offset, unsigned char value)\r
 329 {\r
 330         dwapb_save_out_value(up, offset, value);\r
 331         __raw_writel(value, up->port.membase + (offset << 2));\r
 332         if (offset != UART_TX)\r
 333                 dsb(sy);\r
 334         dwapb_check_clear_ier(up, offset);\r
 335 }\r
 336 \r
 337 /* Uart divisor latch read */\r
 338 static inline int serial_dl_read(struct uart_rk_port *up)\r
 339 {\r
 340         return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;\r
 341 }\r
 342 \r
 343 /* Uart divisor latch write */\r
 344 static int serial_dl_write(struct uart_rk_port *up, unsigned int value)\r
 345 {\r
 346         unsigned int tmout = 100;\r
 347 \r
 348         while(!(serial_in(up, UART_LCR) & UART_LCR_DLAB)){\r
 349                 if (--tmout == 0){\r
 350                         if(up->port.line != DBG_PORT)\r
 351                                 dbg("set serial.%d baudrate fail with DLAB not set\n", up->port.line);\r
 352                         return -1;\r
 353                 }\r
 354         }\r
 355 \r
 356         tmout = 15000;\r
 357         while(serial_in(up, UART_USR) & UART_USR_BUSY){\r
 358                 if (--tmout == 0){\r
 359                         if(up->port.line != DBG_PORT)\r
 360                                 dbg("set serial.%d baudrate timeout\n", up->port.line);\r
 361                         return -1;\r
 362                 }\r
 363                 udelay(1);\r
 364         }\r
 365 \r
 366         serial_out(up, UART_DLL, value & 0xff);\r
 367         serial_out(up, UART_DLM, value >> 8 & 0xff);\r
 368 \r
 369         return 0;\r
 370 \r
 371 }\r
 372 \r
 373 static int serial_lcr_write(struct uart_rk_port *up, unsigned char value)\r
 374 {\r
 375         unsigned int tmout = 15000;\r
 376 \r
 377         while(serial_in(up, UART_USR) & UART_USR_BUSY){\r
 378                 if (--tmout == 0){\r
 379                         if(up->port.line != DBG_PORT)\r
 380                                 dbg("set serial.%d lc r = 0x%02x timeout\n", up->port.line, value);\r
 381                         return -1;\r
 382                 }\r
 383                 udelay(1);\r
 384         }\r
 385 \r
 386         serial_out(up, UART_LCR, value);\r
 387 \r
 388         return 0;\r
 389 }\r
 390 \r
 391 static inline void serial_rk_enable_ier_thri(struct uart_rk_port *up)\r
 392 {\r
 393         if (!(up->ier & UART_IER_THRI)) {\r
 394                 up->ier |= UART_IER_THRI;\r
 395                 serial_out(up, UART_IER, up->ier);\r
 396         }\r
 397 }\r
 398 \r
 399 \r
 400 static inline void serial_rk_disable_ier_thri(struct uart_rk_port *up)\r
 401 {\r
 402         if (up->ier & UART_IER_THRI) {\r
 403                 up->ier &= ~UART_IER_THRI;\r
 404                 serial_out(up, UART_IER, up->ier);\r
 405         }\r
 406 }\r
 407 \r
 408 static int rk29_uart_dump_register(struct uart_rk_port *up){\r
 409 \r
 410         unsigned int reg_value = 0;\r
 411 \r
 412         reg_value = serial_in(up, UART_IER);\r
 413         dbg("UART_IER = 0x%0x\n", reg_value);\r
 414         reg_value = serial_in(up, UART_IIR);\r
 415         dbg("UART_IIR = 0x%0x\n", reg_value);\r
 416     reg_value = serial_in(up, UART_LSR);\r
 417     dbg("UART_LSR = 0x%0x\n", reg_value);\r
 418     reg_value = serial_in(up, UART_MSR);\r
 419     dbg("UART_MSR = 0x%0x\n", reg_value);\r
 420     reg_value = serial_in(up, UART_MCR);\r
 421     dbg("UART_MCR = 0x%0x\n", reg_value);\r
 422     reg_value = serial_in(up, 0x21);\r
 423     dbg("UART_RFL = 0x%0x\n", reg_value);\r
 424     reg_value = serial_in(up, UART_LCR);\r
 425     dbg("UART_LCR = 0x%0x\n", reg_value);\r
 426         return 0;\r
 427 \r
 428 }\r
 429 \r
 430 /*\r
 431  * FIFO support.\r
 432  */\r
 433 static void serial_rk_clear_fifos(struct uart_rk_port *up)\r
 434 {\r
 435         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);\r
 436         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |\r
 437                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);\r
 438         serial_out(up, UART_FCR, 0);\r
 439 }\r
 440 \r
 441 static inline void __stop_tx(struct uart_rk_port *p)\r
 442 {\r
 443         if (p->ier & UART_IER_THRI) {\r
 444                 p->ier &= ~UART_IER_THRI;\r
 445                 serial_out(p, UART_IER, p->ier);\r
 446         }\r
 447 }\r
 448 \r
 449 static void serial_rk_stop_tx(struct uart_port *port)\r
 450 {\r
 451         struct uart_rk_port *up =\r
 452                 container_of(port, struct uart_rk_port, port);\r
 453 #if USE_DMA\r
 454         struct rk_uart_dma *uart_dma = up->dma;\r
 455         if(uart_dma->use_dma & TX_DMA){\r
 456                 serial_rk_stop_dma_tx(up);\r
 457         }\r
 458 #endif\r
 459         __stop_tx(up);\r
 460 }\r
 461 \r
 462 \r
 463 static void serial_rk_start_tx(struct uart_port *port)\r
 464 {\r
 465         struct uart_rk_port *up =\r
 466                 container_of(port, struct uart_rk_port, port);\r
 467 \r
 468 #if USE_DMA\r
 469         if(up->dma->use_dma & TX_DMA) {\r
 470                 if(!up->dma->tx_dma_used)\r
 471                         serial_rk_enable_ier_thri(up);\r
 472         }else {\r
 473                 serial_rk_enable_ier_thri(up);\r
 474         }\r
 475 #else\r
 476         serial_rk_enable_ier_thri(up);\r
 477 #endif\r
 478 }\r
 479 \r
 480 \r
 481 static void serial_rk_stop_rx(struct uart_port *port)\r
 482 {\r
 483         struct uart_rk_port *up =\r
 484                 container_of(port, struct uart_rk_port, port);\r
 485 #if USE_DMA\r
 486         struct rk_uart_dma *uart_dma = up->dma;\r
 487         if(uart_dma->use_dma & RX_DMA){\r
 488                 serial_rk_stop_dma_rx(up);\r
 489         }\r
 490 #endif\r
 491         up->ier &= ~UART_IER_RLSI;\r
 492         up->port.read_status_mask &= ~UART_LSR_DR;\r
 493         serial_out(up, UART_IER, up->ier);\r
 494 }\r
 495 \r
 496 \r
 497 static void serial_rk_enable_ms(struct uart_port *port)\r
 498 {\r
 499         /* no MSR capabilities */\r
 500 #if 0\r
 501         struct uart_rk_port *up =\r
 502                 container_of(port, struct uart_rk_port, port);\r
 503 \r
 504         dev_dbg(port->dev, "%s\n", __func__);\r
 505         up->ier |= UART_IER_MSI;\r
 506         serial_out(up, UART_IER, up->ier);\r
 507 #endif\r
 508 }\r
 509 \r
 510 #if USE_WAKEUP\r
 511 static struct uart_wake_up rk29_uart_ports_wakeup[] = {\r
 512                 {UART0_USE_WAKEUP, UART0_SIN, UART0_SOUT},\r
 513                 {UART1_USE_WAKEUP, UART1_SIN, UART1_SOUT},\r
 514                 {UART2_USE_WAKEUP, UART2_SIN, UART2_SOUT},\r
 515                 {UART3_USE_WAKEUP, UART3_SIN, UART3_SOUT},\r
 516 };\r
 517 #endif\r
 518 \r
 519 #if USE_DMA\r
 520 /* DMAC PL330 add by hhb@rock-chips.com */\r
 521 \r
 522 static void serial_rk_stop_dma_tx(struct uart_rk_port *up)\r
 523 {\r
 524         struct rk_uart_dma *uart_dma = up->dma;\r
 525         \r
 526         if(uart_dma && uart_dma->tx_dma_used) {\r
 527                 dmaengine_terminate_all(uart_dma->dma_chan_tx);\r
 528                 uart_dma->tx_dma_used = 0;\r
 529         }\r
 530 }\r
 531 \r
 532 static void serial_rk_release_dma_tx(struct uart_rk_port *up)\r
 533 {\r
 534         struct rk_uart_dma *uart_dma = up->dma;\r
 535 \r
 536         if(uart_dma && uart_dma->tx_dma_inited) {\r
 537                 serial_rk_stop_dma_tx(up);\r
 538                 dma_release_channel(uart_dma->dma_chan_tx);\r
 539                 uart_dma->dma_chan_tx = NULL;\r
 540                 uart_dma->tx_dma_inited = 0;\r
 541         }\r
 542 }\r
 543 \r
 544 static void dma_tx_callback(void *data)\r
 545 {\r
 546         struct uart_port *port = data;\r
 547         struct uart_rk_port *up = container_of(port, struct uart_rk_port, port);\r
 548         struct circ_buf *xmit = &port->state->xmit;\r
 549         struct rk_uart_dma *uart_dma = up->dma;\r
 550         struct scatterlist *sgl = &uart_dma->tx_sgl;\r
 551 \r
 552         dma_unmap_sg(up->port.dev, sgl, 1, DMA_TO_DEVICE);\r
 553 \r
 554         xmit->tail = (xmit->tail + uart_dma->tx_bytes) & (UART_XMIT_SIZE - 1);\r
 555         port->icount.tx += uart_dma->tx_bytes;\r
 556         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)\r
 557                 uart_write_wakeup(port);\r
 558 \r
 559         //spin_lock(&(up->dma->tx_lock));\r
 560         uart_dma->tx_dma_used = 0;\r
 561         //spin_unlock(&(up->dma->tx_lock));\r
 562         serial_rk_enable_ier_thri(up);\r
 563         up->port_activity = jiffies;\r
 564 //      dev_info(up->port.dev, "s:%d\n", size);\r
 565 \r
 566 }\r
 567 static int serial_rk_init_dma_tx(struct uart_rk_port *up) {\r
 568 \r
 569         struct dma_slave_config slave_config;\r
 570         struct uart_port *port = &up->port;\r
 571         struct rk_uart_dma *uart_dma = up->dma;\r
 572         int ret;\r
 573 \r
 574         if(!uart_dma){\r
 575                 dev_info(up->port.dev, "serial_rk_init_dma_tx fail\n");\r
 576                 return -1;\r
 577         }\r
 578 \r
 579         if(uart_dma->tx_dma_inited) {\r
 580                 return 0;\r
 581         }\r
 582 \r
 583         uart_dma->dma_chan_tx = dma_request_slave_channel(port->dev, "tx");\r
 584         if (!uart_dma->dma_chan_tx) {\r
 585                 dev_err(port->dev, "cannot get the TX DMA channel!\n");\r
 586                 ret = -EINVAL;\r
 587         }\r
 588 \r
 589         slave_config.direction = DMA_MEM_TO_DEV;        \r
 590         slave_config.dst_addr = port->mapbase + UART_TX;        \r
 591         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;        \r
 592         slave_config.dst_maxburst = 16;\r
 593         ret = dmaengine_slave_config(uart_dma->dma_chan_tx, &slave_config);     \r
 594         if (ret) {\r
 595                 dev_err(port->dev, "error in TX dma configuration.");   \r
 596                 return ret;\r
 597         }\r
 598 \r
 599         uart_dma->tx_dma_inited = 1;\r
 600         dev_info(port->dev, "serial_rk_init_dma_tx sucess\n");\r
 601         return 0;\r
 602 }\r
 603 \r
 604 static int serial_rk_start_dma_tx(struct uart_rk_port *up)\r
 605 {\r
 606         int count = 0;\r
 607         struct uart_port *port = &up->port;\r
 608         struct circ_buf *xmit = &port->state->xmit;\r
 609         struct rk_uart_dma *uart_dma = up->dma;\r
 610         struct scatterlist *sgl = &uart_dma->tx_sgl;\r
 611         struct dma_async_tx_descriptor *desc;\r
 612         int ret;\r
 613 \r
 614         if(!uart_dma->use_dma)\r
 615                 goto err_out;\r
 616 \r
 617         if(-1 == serial_rk_init_dma_tx(up))\r
 618                 goto err_out;\r
 619 \r
 620         if (1 == uart_dma->tx_dma_used)\r
 621                 return 1;\r
 622 \r
 623 //      spin_lock(&(uart_dma->tx_lock));\r
 624         __stop_tx(up);\r
 625 \r
 626         count = SERIAL_CIRC_CNT_TO_END(xmit);\r
 627         count -= count%16;\r
 628         if(count >= DMA_TX_TRRIGE_LEVEL) {\r
 629                 uart_dma->tx_bytes = count;\r
 630                 sg_init_one(sgl, uart_dma->tx_buffer + xmit->tail, count);\r
 631                 ret = dma_map_sg(port->dev, sgl, 1, DMA_TO_DEVICE);\r
 632                 \r
 633                 if (ret == 0) {\r
 634                         dev_err(port->dev, "DMA mapping error for TX.\n");      \r
 635                         return -1;\r
 636                 }       \r
 637                 desc = dmaengine_prep_slave_sg(uart_dma->dma_chan_tx, sgl, 1,\r
 638                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);    \r
 639 \r
 640                 if (!desc) {\r
 641                         dev_err(port->dev, "We cannot prepare for the TX slave dma!\n");                \r
 642                         return -1;      \r
 643                 }       \r
 644                 desc->callback = dma_tx_callback;       \r
 645                 desc->callback_param = port;    \r
 646                 dmaengine_submit(desc);\r
 647                 dma_async_issue_pending(uart_dma->dma_chan_tx);\r
 648                 uart_dma->tx_dma_used = 1;\r
 649         }\r
 650 //      spin_unlock(&(uart_dma->tx_lock));\r
 651         return 1;\r
 652 err_out:\r
 653         dev_info(up->port.dev, "-serial_rk_start_dma_tx-error-\n");\r
 654         return -1;\r
 655 }\r
 656 \r
 657 \r
 658 \r
 659 /*RX*/\r
 660 #if 0\r
 661 static void serial_rk_dma_rxcb(void *buf, int size, enum rk29_dma_buffresult result) {\r
 662 \r
 663         //printk(">>%s:%d\n", __func__, result);\r
 664 }\r
 665 #endif\r
 666 \r
 667 static void serial_rk_stop_dma_rx(struct uart_rk_port *up)\r
 668 {\r
 669         struct rk_uart_dma *uart_dma = up->dma;\r
 670         \r
 671         if(uart_dma && uart_dma->rx_dma_used) {\r
 672                 del_timer(&uart_dma->rx_timer);\r
 673                 dmaengine_terminate_all(uart_dma->dma_chan_rx); \r
 674                 uart_dma->rb_tail = 0;\r
 675                 uart_dma->rx_dma_used = 0;\r
 676         }\r
 677 }\r
 678 \r
 679 \r
 680 static void serial_rk_release_dma_rx(struct uart_rk_port *up)\r
 681 {\r
 682         struct rk_uart_dma *uart_dma = up->dma;\r
 683         \r
 684         if(uart_dma && uart_dma->rx_dma_inited) {\r
 685                 serial_rk_stop_dma_rx(up);\r
 686                 dma_release_channel(uart_dma->dma_chan_rx);\r
 687                 uart_dma->dma_chan_rx = NULL;   \r
 688                 uart_dma->rx_dma_inited = 0;\r
 689         }\r
 690 }\r
 691 \r
 692 \r
 693 static int serial_rk_init_dma_rx(struct uart_rk_port *up) \r
 694 {\r
 695         int ret;\r
 696         struct uart_port *port = &up->port;\r
 697         struct dma_slave_config slave_config;\r
 698         struct rk_uart_dma *uart_dma = up->dma;\r
 699 \r
 700         if(!uart_dma) {\r
 701                 dev_info(port->dev, "serial_rk_init_dma_rx: port fail\n");\r
 702                 return -1;\r
 703         }\r
 704 \r
 705         if(uart_dma->rx_dma_inited) {\r
 706                 return 0;\r
 707         }\r
 708 \r
 709         uart_dma->dma_chan_rx = dma_request_slave_channel(port->dev, "rx");\r
 710         if (!uart_dma->dma_chan_rx) {\r
 711                 dev_err(port->dev, "cannot get the DMA channel.\n");\r
 712                 return -1;\r
 713         }\r
 714 \r
 715         slave_config.direction = DMA_DEV_TO_MEM;        \r
 716         slave_config.src_addr = port->mapbase + UART_RX;        \r
 717         slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;        \r
 718         slave_config.src_maxburst = 1;\r
 719         ret = dmaengine_slave_config(uart_dma->dma_chan_rx, &slave_config);     \r
 720         if (ret) {\r
 721                 dev_err(port->dev, "error in RX dma configuration.\n");         \r
 722                 return ret;     \r
 723         }\r
 724 \r
 725         uart_dma->rx_dma_inited = 1;\r
 726         dev_info(port->dev, "serial_rk_init_dma_rx sucess\n");\r
 727         return 0;\r
 728 }\r
 729 \r
 730 static int serial_rk_start_dma_rx(struct uart_rk_port *up)\r
 731 {\r
 732         struct uart_port *port = &up->port;\r
 733         struct rk_uart_dma *uart_dma = up->dma; \r
 734         struct dma_async_tx_descriptor *desc;   \r
 735         \r
 736         if(!uart_dma->use_dma)\r
 737                 return 0;\r
 738 \r
 739         if(uart_dma->rx_dma_used == 1)\r
 740                 return 0;\r
 741 \r
 742         if(-1 == serial_rk_init_dma_rx(up)){\r
 743                 dev_info(up->port.dev, "*******serial_rk_init_dma_rx*******error*******\n");\r
 744                 return -1;\r
 745         }\r
 746         desc = dmaengine_prep_dma_cyclic(uart_dma->dma_chan_rx, uart_dma->rx_phy_addr, uart_dma->rb_size, uart_dma->rb_size/2,DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);      \r
 747 \r
 748         if (!desc) {\r
 749                 dev_err(port->dev, "We cannot prepare for the RX slave dma!\n");                \r
 750                 return -EINVAL; \r
 751         }\r
 752 \r
 753         //desc->callback = dma_rx_callback;     \r
 754         //desc->callback_param = port;  \r
 755         dev_dbg(port->dev, "RX: prepare for the DMA.\n");\r
 756         dmaengine_submit(desc); \r
 757         dma_async_issue_pending(uart_dma->dma_chan_rx);\r
 758 \r
 759         uart_dma->rx_dma_used = 1;\r
 760         if(uart_dma->use_timer == 1){\r
 761                 mod_timer(&uart_dma->rx_timer, jiffies + msecs_to_jiffies(uart_dma->rx_timeout));\r
 762         }\r
 763         up->port_activity = jiffies;\r
 764         return 1;\r
 765 }\r
 766 \r
 767 static void serial_rk_update_rb_addr(struct uart_rk_port *up)\r
 768 {\r
 769         struct rk_uart_dma *uart_dma = up->dma;\r
 770         struct dma_tx_state state;      \r
 771         //spin_lock(&(up->dma->rx_lock));\r
 772         uart_dma->rx_size = 0;\r
 773         if(uart_dma->rx_dma_used == 1) {\r
 774                 dmaengine_tx_status(uart_dma->dma_chan_rx, (dma_cookie_t)0, &state);\r
 775                 uart_dma->rb_head = (state.residue - uart_dma->rx_phy_addr);\r
 776                 uart_dma->rx_size = CIRC_CNT(uart_dma->rb_head, uart_dma->rb_tail, uart_dma->rb_size);\r
 777         }\r
 778         //spin_unlock(&(up->dma->rx_lock));\r
 779 }\r
 780 \r
 781 static void serial_rk_report_dma_rx(unsigned long uart)\r
 782 {\r
 783         int count, flip = 0;\r
 784         struct uart_rk_port *up = (struct uart_rk_port *)uart;\r
 785         struct uart_port *port = &up->port;\r
 786         struct rk_uart_dma *uart_dma = up->dma;\r
 787 \r
 788         if(!uart_dma->rx_dma_used || !port->state->port.tty)\r
 789                 return;\r
 790 \r
 791         serial_rk_update_rb_addr(up);\r
 792         //if (uart_dma->rx_size > 0)\r
 793         //      printk("rx_size:%d ADDR:%x\n", uart_dma->rx_size, uart_dma->rb_head);\r
 794         while(1) {\r
 795                 count = CIRC_CNT_TO_END(uart_dma->rb_head, uart_dma->rb_tail, uart_dma->rb_size);\r
 796                 if(count <= 0)\r
 797                         break;\r
 798                 port->icount.rx += count;\r
 799                 flip = tty_insert_flip_string(&port->state->port, uart_dma->rx_buffer\r
 800                         + uart_dma->rb_tail, count);\r
 801                 tty_flip_buffer_push(&port->state->port);\r
 802                 uart_dma->rb_tail = (uart_dma->rb_tail + count) & (uart_dma->rb_size - 1);\r
 803                 up->port_activity = jiffies;\r
 804         }\r
 805 \r
 806         if(uart_dma->use_timer == 1)\r
 807                 mod_timer(&uart_dma->rx_timer, jiffies + msecs_to_jiffies(uart_dma->rx_timeout));\r
 808 }\r
 809 #endif /* USE_DMA */\r
 810 \r
 811 \r
 812 static void\r
 813 receive_chars(struct uart_rk_port *up, unsigned int *status)\r
 814 {\r
 815         struct tty_struct *tty = up->port.state->port.tty;\r
 816         unsigned char ch, lsr = *status;\r
 817         int max_count = 256;\r
 818         char flag;\r
 819 \r
 820         do {\r
 821                 if (likely(lsr & UART_LSR_DR)){\r
 822                         ch = serial_in(up, UART_RX);\r
 823                 }\r
 824                 else\r
 825                         /*\r
 826                          * Intel 82571 has a Serial Over Lan device that will\r
 827                          * set UART_LSR_BI without setting UART_LSR_DR when\r
 828                          * it receives a break. To avoid reading from the\r
 829                          * receive buffer without UART_LSR_DR bit set, we\r
 830                          * just force the read character to be 0\r
 831                          */\r
 832                         ch = 0;\r
 833 \r
 834                 flag = TTY_NORMAL;\r
 835                 up->port.icount.rx++;\r
 836 \r
 837                 lsr |= up->lsr_saved_flags;\r
 838                 up->lsr_saved_flags = 0;\r
 839 \r
 840                 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {\r
 841                         /*\r
 842                          * For statistics only\r
 843                          */\r
 844                         if (lsr & UART_LSR_BI) {\r
 845                                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);\r
 846                                 up->port.icount.brk++;\r
 847                                 /*\r
 848                                  * We do the SysRQ and SAK checking\r
 849                                  * here because otherwise the break\r
 850                                  * may get masked by ignore_status_mask\r
 851                                  * or read_status_mask.\r
 852                                  */\r
 853                                 if (uart_handle_break(&up->port))\r
 854                                         goto ignore_char;\r
 855                         } else if (lsr & UART_LSR_PE)\r
 856                                 up->port.icount.parity++;\r
 857                         else if (lsr & UART_LSR_FE)\r
 858                                 up->port.icount.frame++;\r
 859                         if (lsr & UART_LSR_OE)\r
 860                                 up->port.icount.overrun++;\r
 861 \r
 862 \r
 863                         /*\r
 864                          * Mask off conditions which should be ignored.\r
 865                          */\r
 866                         lsr &= up->port.read_status_mask;\r
 867 \r
 868                         if (lsr & UART_LSR_BI) {\r
 869                                 DEBUG_INTR("handling break....");\r
 870                                 flag = TTY_BREAK;\r
 871                         } else if (lsr & UART_LSR_PE)\r
 872                                 flag = TTY_PARITY;\r
 873                         else if (lsr & UART_LSR_FE)\r
 874                                 flag = TTY_FRAME;\r
 875                 }\r
 876                 if (uart_handle_sysrq_char(&up->port, ch))\r
 877                         goto ignore_char;\r
 878 \r
 879                 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);\r
 880 \r
 881 ignore_char:\r
 882                 lsr = serial_in(up, UART_LSR);\r
 883         } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));\r
 884         spin_unlock(&up->port.lock);\r
 885         tty_flip_buffer_push(tty->port);\r
 886         spin_lock(&up->port.lock);\r
 887         *status = lsr;\r
 888 }\r
 889 \r
 890 static void transmit_chars(struct uart_rk_port *up)\r
 891 {\r
 892         struct circ_buf *xmit = &up->port.state->xmit;\r
 893         int count;\r
 894 \r
 895         if (up->port.x_char) {\r
 896                 serial_out(up, UART_TX, up->port.x_char);\r
 897                 up->port.icount.tx++;\r
 898                 up->port.x_char = 0;\r
 899                 return;\r
 900         }\r
 901         if (uart_tx_stopped(&up->port)) {\r
 902                 __stop_tx(up);\r
 903                 return;\r
 904         }\r
 905         if (uart_circ_empty(xmit)) {\r
 906                 __stop_tx(up);\r
 907                 return;\r
 908         }\r
 909 #if USE_DMA\r
 910         //hhb\r
 911         if(up->dma->use_dma & TX_DMA){\r
 912                 if(SERIAL_CIRC_CNT_TO_END(xmit) >= DMA_TX_TRRIGE_LEVEL){\r
 913                         serial_rk_start_dma_tx(up);\r
 914                         return;\r
 915                 }\r
 916         }\r
 917 #endif\r
 918         count = up->port.fifosize - serial_in(up , 0x20);\r
 919         do {\r
 920                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);\r
 921                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);\r
 922                 up->port.icount.tx++;\r
 923                 if (uart_circ_empty(xmit))\r
 924                         break;\r
 925         } while (--count > 0);\r
 926 \r
 927         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)\r
 928                 uart_write_wakeup(&up->port);\r
 929 \r
 930         DEBUG_INTR("THRE...");\r
 931 #if USE_DMA\r
 932         up->port_activity = jiffies;\r
 933 #endif\r
 934         if (uart_circ_empty(xmit))\r
 935                 __stop_tx(up);\r
 936 }\r
 937 \r
 938 static unsigned int check_modem_status(struct uart_rk_port *up)\r
 939 {\r
 940         unsigned int status = serial_in(up, UART_MSR);\r
 941 \r
 942 #if 0\r
 943         status |= up->msr_saved_flags;\r
 944         up->msr_saved_flags = 0;\r
 945         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&\r
 946             up->port.state != NULL) {\r
 947                 if (status & UART_MSR_TERI)\r
 948                         up->port.icount.rng++;\r
 949                 if (status & UART_MSR_DDSR)\r
 950                         up->port.icount.dsr++;\r
 951                 if (status & UART_MSR_DDCD)\r
 952                         uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);\r
 953                 if (status & UART_MSR_DCTS)\r
 954                         uart_handle_cts_change(&up->port, status & UART_MSR_CTS);\r
 955 \r
 956                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);\r
 957         }\r
 958 #endif\r
 959 \r
 960         return status;\r
 961 }\r
 962 \r
 963 \r
 964 /*\r
 965  * This handles the interrupt from one port.\r
 966  */\r
 967 static void serial_rk_handle_port(struct uart_rk_port *up)\r
 968 {\r
 969         unsigned int status;\r
 970         unsigned long flags;\r
 971         spin_lock_irqsave(&up->port.lock, flags);\r
 972 \r
 973         /* reading UART_LSR can automatically clears PE FE OE bits, except receive fifo error bit*/\r
 974         status = serial_in(up, UART_LSR);\r
 975 \r
 976         DEBUG_INTR("status = %x...\n", status);\r
 977 #if USE_DMA\r
 978         /* DMA mode enable */\r
 979         if(up->dma->use_dma) {\r
 980 \r
 981                 if (status & UART_LSR_RFE) {\r
 982                         if(up->port.line != DBG_PORT){\r
 983                                 dev_info(up->port.dev, "error:lsr=0x%x\n", status);\r
 984                                 status = serial_in(up, UART_LSR);\r
 985                                 DEBUG_INTR("error:lsr=0x%x\n", status);\r
 986                         }\r
 987                 }\r
 988 \r
 989                 if (status & 0x02) {\r
 990                         if(up->port.line != DBG_PORT){\r
 991                                 dev_info(up->port.dev, "error:lsr=0x%x\n", status);\r
 992                                 status = serial_in(up, UART_LSR);\r
 993                                 DEBUG_INTR("error:lsr=0x%x\n", status);\r
 994                         }\r
 995                 }\r
 996 \r
 997                 if(!(up->dma->use_dma & RX_DMA)) {\r
 998                         if (status & (UART_LSR_DR | UART_LSR_BI)) {\r
 999                                 receive_chars(up, &status);\r
1000                         } else if ((up->iir & 0x0f) == 0x0c) {\r
1001                 serial_in(up, UART_RX);\r
1002                 }\r
1003                 }\r
1004 \r
1005                 if ((up->iir & 0x0f) == 0x02) {\r
1006                         transmit_chars(up);\r
1007                 }\r
1008         } else \r
1009 #endif\r
1010         {   //dma mode disable\r
1011 \r
1012                 /*\r
1013                  * when uart receive a serial of data which doesn't have stop bit and so on, that causes frame error,and\r
1014                  * set UART_LSR_RFE to one,what is worse,we couldn't read the data in the receive fifo. So if\r
1015                  * wo don't clear this bit and reset the receive fifo, the received data available interrupt would\r
1016                  * occur continuously.  added by hhb@rock-chips.com 2011-08-05\r
1017                  */\r
1018 \r
1019                 if (status & UART_LSR_RFE) {\r
1020                         if(up->port.line != DBG_PORT){\r
1021                                 dev_info(up->port.dev, "error:lsr=0x%x\n", status);\r
1022                                 status = serial_in(up, UART_LSR);\r
1023                                 DEBUG_INTR("error:lsr=0x%x\n", status);\r
1024                                 rk29_uart_dump_register(up);\r
1025                         }\r
1026                 }\r
1027 \r
1028                 if (status & (UART_LSR_DR | UART_LSR_BI)) {\r
1029                         receive_chars(up, &status);\r
1030                 } else if ((up->iir & 0x0f) == 0x0c) {\r
1031             serial_in(up, UART_RX);\r
1032         }\r
1033                 check_modem_status(up);\r
1034                 //hhb@rock-chips.com when FIFO and THRE mode both are enabled,and FIFO TX empty trigger is set to larger than 1,\r
1035                 //,we need to add ((up->iir & 0x0f) == 0x02) to transmit_chars,because when entering interrupt,the FIFO and THR\r
1036                 //might not be 1.\r
1037                 if ((up->iir & 0x0f) == 0x02) {\r
1038                         transmit_chars(up);\r
1039                 }\r
1040         }\r
1041         spin_unlock_irqrestore(&up->port.lock, flags);\r
1042 }\r
1043 \r
1044 /*\r
1045  * This is the serial driver's interrupt routine.\r
1046  */\r
1047 \r
1048 static irqreturn_t serial_rk_interrupt(int irq, void *dev_id)\r
1049 {\r
1050         struct uart_rk_port *up = dev_id;\r
1051         int handled = 0;\r
1052         unsigned int iir;\r
1053 \r
1054         iir = serial_in(up, UART_IIR);\r
1055 \r
1056         DEBUG_INTR("%s(%d) iir = 0x%02x\n", __func__, irq, iir);\r
1057         up->iir = iir;\r
1058 \r
1059         if (!(iir & UART_IIR_NO_INT)) {\r
1060                 serial_rk_handle_port(up);\r
1061                 handled = 1;\r
1062         } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {\r
1063 \r
1064                 /* The DesignWare APB UART has an Busy Detect (0x07)\r
1065                  * interrupt meaning an LCR write attempt occured while the\r
1066                  * UART was busy. The interrupt must be cleared by reading\r
1067                  * the UART status register (USR) and the LCR re-written. */\r
1068 \r
1069                 if(!(serial_in(up, UART_USR) & UART_USR_BUSY)){\r
1070                         serial_out(up, UART_LCR, up->lcr);\r
1071                 }\r
1072                 handled = 1;\r
1073                 dbg("the serial.%d is busy\n", up->port.line);\r
1074         }\r
1075         DEBUG_INTR("end(%d).\n", handled);\r
1076 \r
1077         return IRQ_RETVAL(handled);\r
1078 }\r
1079 \r
1080 static unsigned int serial_rk_tx_empty(struct uart_port *port)\r
1081 {\r
1082         struct uart_rk_port *up =\r
1083                 container_of(port, struct uart_rk_port, port);\r
1084         unsigned long flags;\r
1085         unsigned int lsr;\r
1086 \r
1087         dev_dbg(port->dev, "%s\n", __func__);\r
1088         spin_lock_irqsave(&up->port.lock, flags);\r
1089         lsr = serial_in(up, UART_LSR);\r
1090         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;\r
1091         spin_unlock_irqrestore(&up->port.lock, flags);\r
1092 \r
1093         return (lsr & UART_LSR_TEMT) == UART_LSR_TEMT ? TIOCSER_TEMT : 0;\r
1094 }\r
1095 \r
1096 static unsigned int serial_rk_get_mctrl(struct uart_port *port)\r
1097 {\r
1098         struct uart_rk_port *up =\r
1099                 container_of(port, struct uart_rk_port, port);\r
1100         unsigned int status;\r
1101         unsigned int ret;\r
1102 \r
1103         status = check_modem_status(up);\r
1104 \r
1105         ret = 0;\r
1106         if (status & UART_MSR_DCD)\r
1107                 ret |= TIOCM_CAR;\r
1108         if (status & UART_MSR_RI)\r
1109                 ret |= TIOCM_RNG;\r
1110         if (status & UART_MSR_DSR)\r
1111                 ret |= TIOCM_DSR;\r
1112         if (status & UART_MSR_CTS)\r
1113                 ret |= TIOCM_CTS;\r
1114         dev_dbg(port->dev, "%s 0x%08x\n", __func__, ret);\r
1115         return ret;\r
1116 }\r
1117 \r
1118 static void serial_rk_set_mctrl(struct uart_port *port, unsigned int mctrl)\r
1119 {\r
1120         struct uart_rk_port *up =\r
1121                 container_of(port, struct uart_rk_port, port);\r
1122         unsigned char mcr = 0;\r
1123 \r
1124         dev_dbg(port->dev, "+%s\n", __func__);\r
1125         if (mctrl & TIOCM_RTS)\r
1126                 mcr |= UART_MCR_RTS;\r
1127         if (mctrl & TIOCM_DTR)\r
1128                 mcr |= UART_MCR_DTR;\r
1129         if (mctrl & TIOCM_OUT1)\r
1130                 mcr |= UART_MCR_OUT1;\r
1131         if (mctrl & TIOCM_OUT2)\r
1132                 mcr |= UART_MCR_OUT2;\r
1133         if (mctrl & TIOCM_LOOP)\r
1134                 mcr |= UART_MCR_LOOP;\r
1135 \r
1136         mcr |= up->mcr;\r
1137 \r
1138         serial_out(up, UART_MCR, mcr);\r
1139         dev_dbg(port->dev, "-serial.%d %s mcr: 0x%02x\n", port->line, __func__, mcr);\r
1140 }\r
1141 \r
1142 static void serial_rk_break_ctl(struct uart_port *port, int break_state)\r
1143 {\r
1144         struct uart_rk_port *up =\r
1145                 container_of(port, struct uart_rk_port, port);\r
1146         unsigned long flags;\r
1147 \r
1148         dev_dbg(port->dev, "+%s\n", __func__);\r
1149         spin_lock_irqsave(&up->port.lock, flags);\r
1150         if (break_state == -1)\r
1151                 up->lcr |= UART_LCR_SBC;\r
1152         else\r
1153                 up->lcr &= ~UART_LCR_SBC;\r
1154         serial_lcr_write(up, up->lcr);\r
1155         spin_unlock_irqrestore(&up->port.lock, flags);\r
1156         dev_dbg(port->dev, "-%s lcr: 0x%02x\n", __func__, up->lcr);\r
1157 }\r
1158 \r
1159 #if defined(CONFIG_SERIAL_ROCKCHIP_CONSOLE) || defined(CONFIG_CONSOLE_POLL)\r
1160 /*\r
1161  *      Wait for transmitter & holding register to empty\r
1162  */\r
1163 static void wait_for_xmitr(struct uart_rk_port *up, int bits)\r
1164 {\r
1165         unsigned int status, tmout = 10000;\r
1166 \r
1167         /* Wait up to 10ms for the character(s) to be sent. */\r
1168         for (;;) {\r
1169                 status = serial_in(up, UART_LSR);\r
1170 \r
1171                 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;\r
1172 \r
1173                 if ((status & bits) == bits)\r
1174                         break;\r
1175                 if (--tmout == 0)\r
1176                         break;\r
1177                 udelay(1);\r
1178         }\r
1179 }\r
1180 #endif\r
1181 \r
1182 #ifdef CONFIG_CONSOLE_POLL\r
1183 /*\r
1184  * Console polling routines for writing and reading from the uart while\r
1185  * in an interrupt or debug context.\r
1186  */\r
1187 \r
1188 static int serial_rk_get_poll_char(struct uart_port *port)\r
1189 {\r
1190         struct uart_rk_port *up =\r
1191                 container_of(port, struct uart_rk_port, port);\r
1192         unsigned char lsr = serial_in(up, UART_LSR);\r
1193 \r
1194         while (!(lsr & UART_LSR_DR))\r
1195                 lsr = serial_in(up, UART_LSR);\r
1196 \r
1197         return serial_in(up, UART_RX);\r
1198 }\r
1199 \r
1200 static void serial_rk_put_poll_char(struct uart_port *port,\r
1201                          unsigned char c)\r
1202 {\r
1203         unsigned int ier;\r
1204         struct uart_rk_port *up =\r
1205                 container_of(port, struct uart_rk_port, port);\r
1206 \r
1207         /*\r
1208          *      First save the IER then disable the interrupts\r
1209          */\r
1210         ier = serial_in(up, UART_IER);\r
1211         serial_out(up, UART_IER, 0);\r
1212 \r
1213         wait_for_xmitr(up, UART_LSR_TEMT);\r
1214         /*\r
1215          *      Send the character out.\r
1216          *      If a LF, also do CR...\r
1217          */\r
1218         serial_out(up, UART_TX, c);\r
1219         if (c == 10) {\r
1220                 wait_for_xmitr(up, UART_LSR_TEMT);\r
1221                 serial_out(up, UART_TX, 13);\r
1222         }\r
1223 \r
1224         /*\r
1225          *      Finally, wait for transmitter to become empty\r
1226          *      and restore the IER\r
1227          */\r
1228         wait_for_xmitr(up, UART_LSR_TEMT);\r
1229         serial_out(up, UART_IER, ier);\r
1230 }\r
1231 \r
1232 #endif /* CONFIG_CONSOLE_POLL */\r
1233 \r
1234 static int serial_rk_startup(struct uart_port *port)\r
1235 {\r
1236         struct uart_rk_port *up =\r
1237                 container_of(port, struct uart_rk_port, port);\r
1238         unsigned long flags;\r
1239         int retval, fifosize = 0;\r
1240         \r
1241 \r
1242         dev_dbg(port->dev, "%s\n", __func__);\r
1243 \r
1244         /*\r
1245          * Allocate the IRQ\r
1246          */\r
1247         retval = request_irq(up->port.irq, serial_rk_interrupt, up->port.irqflags,\r
1248                                 up->name, up);\r
1249         if (retval)\r
1250                 return retval;\r
1251 \r
1252         up->mcr = 0;\r
1253 #ifdef CONFIG_CLOCK_CTRL\r
1254         clk_prepare_enable(up->clk);\r
1255         clk_prepare_enable(up->pclk); // enable the config uart clock\r
1256 #endif\r
1257         /*\r
1258          * Clear the FIFO buffers and disable them.\r
1259          * (they will be reenabled in set_termios())\r
1260          */\r
1261         serial_rk_clear_fifos(up);\r
1262 \r
1263         //read uart fifo size  hhb@rock-chips.com\r
1264         fifosize = __raw_readl(up->port.membase + 0xf4);\r
1265         up->port.fifosize = ((fifosize >> 16) & 0xff) << 4;\r
1266         if(up->port.fifosize <= 0)\r
1267                 up->port.fifosize = 32;\r
1268         //printk("fifo size:%d :%08x\n", up->port.fifosize, fifosize);\r
1269 \r
1270         /*\r
1271          * Clear the interrupt registers.\r
1272          */\r
1273         (void) serial_in(up, UART_LSR);\r
1274         (void) serial_in(up, UART_RX);\r
1275         (void) serial_in(up, UART_IIR);\r
1276         (void) serial_in(up, UART_MSR);\r
1277         (void) serial_in(up, UART_USR);\r
1278 \r
1279         /*\r
1280          * Now, initialize the UART\r
1281          */\r
1282         serial_lcr_write(up, UART_LCR_WLEN8 | UART_LCR_EPAR);\r
1283 \r
1284         spin_lock_irqsave(&up->port.lock, flags);\r
1285 \r
1286         /*\r
1287          * Most PC uarts need OUT2 raised to enable interrupts.\r
1288          */\r
1289 //      up->port.mctrl |= TIOCM_OUT2;\r
1290 \r
1291         serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1292 \r
1293         spin_unlock_irqrestore(&up->port.lock, flags);\r
1294 \r
1295         /*\r
1296          * Clear the interrupt registers again for luck, and clear the\r
1297          * saved flags to avoid getting false values from polling\r
1298          * routines or the previous session.\r
1299          */\r
1300         (void) serial_in(up, UART_LSR);\r
1301         (void) serial_in(up, UART_RX);\r
1302         (void) serial_in(up, UART_IIR);\r
1303         (void) serial_in(up, UART_MSR);\r
1304         (void) serial_in(up, UART_USR);\r
1305         up->lsr_saved_flags = 0;\r
1306 #if 0\r
1307         up->msr_saved_flags = 0;\r
1308 #endif\r
1309 #if USE_DMA\r
1310         if (up->dma->use_dma & TX_DMA) {\r
1311                 if(up->port.state->xmit.buf != up->dma->tx_buffer){\r
1312                         free_page((unsigned long)up->port.state->xmit.buf);\r
1313                         up->port.state->xmit.buf = up->dma->tx_buffer;\r
1314                 }\r
1315         } else \r
1316 #endif\r
1317         {\r
1318                 up->ier = 0;\r
1319                 serial_out(up, UART_IER, up->ier);\r
1320         }\r
1321 \r
1322         /*\r
1323          * Finally, enable interrupts.  Note: Modem status interrupts\r
1324          * are set via set_termios(), which will be occurring imminently\r
1325          * anyway, so we don't enable them here.\r
1326          */\r
1327 \r
1328         return 0;\r
1329 }\r
1330 \r
1331 \r
1332 static void serial_rk_shutdown(struct uart_port *port)\r
1333 {\r
1334         struct uart_rk_port *up =\r
1335                 container_of(port, struct uart_rk_port, port);\r
1336         unsigned long flags;\r
1337 \r
1338         dev_dbg(port->dev, "%s\n", __func__);\r
1339         /*\r
1340          * Disable interrupts from this port\r
1341          */\r
1342         up->ier = 0;\r
1343         serial_out(up, UART_IER, 0);\r
1344 \r
1345         spin_lock_irqsave(&up->port.lock, flags);\r
1346 //      up->port.mctrl &= ~TIOCM_OUT2;\r
1347         serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1348         spin_unlock_irqrestore(&up->port.lock, flags);\r
1349 \r
1350         /*\r
1351          * Disable break condition and FIFOs\r
1352          */\r
1353         serial_lcr_write(up, serial_in(up, UART_LCR) & ~UART_LCR_SBC);\r
1354         serial_rk_clear_fifos(up);\r
1355 \r
1356         /*\r
1357          * Read data port to reset things, and then free the irq\r
1358          */\r
1359         (void) serial_in(up, UART_RX);\r
1360 #if USE_DMA\r
1361         if (up->dma->use_dma & TX_DMA)\r
1362                 up->port.state->xmit.buf = NULL;\r
1363 #endif\r
1364         free_irq(up->port.irq, up);\r
1365 #ifdef CONFIG_CLOCK_CTRL\r
1366         clk_disable_unprepare(up->clk);\r
1367         clk_disable_unprepare(up->pclk); \r
1368 #endif\r
1369 }\r
1370 \r
1371 static void\r
1372 serial_rk_set_termios(struct uart_port *port, struct ktermios *termios,\r
1373                       struct ktermios *old)\r
1374 {\r
1375         struct uart_rk_port *up =\r
1376                 container_of(port, struct uart_rk_port, port);\r
1377         unsigned char cval = 0, fcr = 0, mcr = 0;\r
1378         unsigned long flags;\r
1379         unsigned int baud, quot;\r
1380 \r
1381         dev_dbg(port->dev, "+%s\n", __func__);\r
1382 \r
1383 #if USE_DMA\r
1384         //stop dma tx, which might make the uart be busy while some registers are set\r
1385         if(up->dma->tx_dma_used) {\r
1386                 serial_rk_stop_dma_tx(up);\r
1387         }\r
1388 #endif\r
1389 \r
1390         switch (termios->c_cflag & CSIZE) {\r
1391         case CS5:\r
1392                 cval = UART_LCR_WLEN5;\r
1393                 break;\r
1394         case CS6:\r
1395                 cval = UART_LCR_WLEN6;\r
1396                 break;\r
1397         case CS7:\r
1398                 cval = UART_LCR_WLEN7;\r
1399                 break;\r
1400         case CS8:\r
1401         default:\r
1402                 cval = UART_LCR_WLEN8;\r
1403                 break;\r
1404         }\r
1405 \r
1406         if (termios->c_cflag & CSTOPB){\r
1407                 cval |= UART_LCR_STOP;\r
1408         }\r
1409         if (termios->c_cflag & PARENB){\r
1410                 cval |= UART_LCR_PARITY;\r
1411         }\r
1412         if (!(termios->c_cflag & PARODD)){\r
1413                 cval |= UART_LCR_EPAR;\r
1414         }\r
1415 #ifdef CMSPAR\r
1416         if (termios->c_cflag & CMSPAR)\r
1417                 cval |= UART_LCR_SPAR;\r
1418 #endif\r
1419 \r
1420 \r
1421         /*\r
1422          * Ask the core to calculate the divisor for us.\r
1423          */\r
1424         baud = uart_get_baud_rate(port, termios, old,\r
1425                                   port->uartclk / 16 / 0xffff,\r
1426                                   port->uartclk / 16);\r
1427 \r
1428         quot = uart_get_divisor(port, baud);\r
1429         //dev_info(up->port.dev, "uartclk:%d\n", port->uartclk/16);\r
1430         //dev_info(up->port.dev, "baud:%d\n", baud);\r
1431         //dev_info(up->port.dev, "quot:%d\n", quot);\r
1432 \r
1433         if (baud < 2400){\r
1434                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;\r
1435         }\r
1436         else{\r
1437                 fcr = UART_FCR_ENABLE_FIFO;\r
1438 #if USE_DMA\r
1439                 //added by hhb@rock-chips.com\r
1440                 if(up->dma->use_dma & TX_DMA){\r
1441                         fcr |= UART_FCR_T_TRIG_01;\r
1442                 } else\r
1443 #endif\r
1444                 {\r
1445                         fcr |= UART_FCR_T_TRIG_01;\r
1446                 }\r
1447 \r
1448 #if USE_DMA\r
1449                 //added by hhb@rock-chips.com\r
1450                 if(up->dma->use_dma & RX_DMA){  \r
1451                         fcr |= UART_FCR_R_TRIG_00;\r
1452                 } else\r
1453 #endif\r
1454                 {\r
1455                         if (termios->c_cflag & CRTSCTS)\r
1456                                 fcr |= UART_FCR_R_TRIG_11;\r
1457                         else\r
1458                                 fcr |= UART_FCR_R_TRIG_00;\r
1459                 }\r
1460         }\r
1461 \r
1462         /*\r
1463          * MCR-based auto flow control.  When AFE is enabled, RTS will be\r
1464          * deasserted when the receive FIFO contains more characters than\r
1465          * the trigger, or the MCR RTS bit is cleared.  In the case where\r
1466          * the remote UART is not using CTS auto flow control, we must\r
1467          * have sufficient FIFO entries for the latency of the remote\r
1468          * UART to respond.  IOW, at least 32 bytes of FIFO.\r
1469          */\r
1470         up->mcr &= ~UART_MCR_AFE;\r
1471         if (termios->c_cflag & CRTSCTS){\r
1472                 up->mcr |= UART_MCR_AFE;\r
1473         }\r
1474 \r
1475         /*\r
1476          * Ok, we're now changing the port state.  Do it with\r
1477          * interrupts disabled.\r
1478          */\r
1479         spin_lock_irqsave(&up->port.lock, flags);\r
1480 \r
1481         /*\r
1482          * Update the per-port timeout.\r
1483          */\r
1484         uart_update_timeout(port, termios->c_cflag, baud);\r
1485 \r
1486         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;\r
1487         if (termios->c_iflag & INPCK)\r
1488                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;\r
1489         if (termios->c_iflag & (BRKINT | PARMRK))\r
1490                 up->port.read_status_mask |= UART_LSR_BI;\r
1491 \r
1492         /*\r
1493          * Characteres to ignore\r
1494          */\r
1495         up->port.ignore_status_mask = 0;\r
1496         if (termios->c_iflag & IGNPAR)\r
1497                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;\r
1498         if (termios->c_iflag & IGNBRK) {\r
1499                 up->port.ignore_status_mask |= UART_LSR_BI;\r
1500                 /*\r
1501                  * If we're ignoring parity and break indicators,\r
1502                  * ignore overruns too (for real raw support).\r
1503                  */\r
1504                 if (termios->c_iflag & IGNPAR)\r
1505                         up->port.ignore_status_mask |= UART_LSR_OE;\r
1506         }\r
1507 \r
1508         /*\r
1509          * ignore all characters if CREAD is not set\r
1510          */\r
1511         if ((termios->c_cflag & CREAD) == 0)\r
1512                 up->port.ignore_status_mask |= UART_LSR_DR;\r
1513 \r
1514         /*\r
1515          * CTS flow control flag and modem status interrupts\r
1516          */\r
1517         up->ier &= ~UART_IER_MSI;\r
1518 #if 0\r
1519         if (UART_ENABLE_MS(&up->port, termios->c_cflag))\r
1520                 up->ier |= UART_IER_MSI;\r
1521 #endif\r
1522 \r
1523         //to avoid uart busy when set baud rate  hhb@rock-chips.com\r
1524         serial_out(up, UART_SRR, UART_RESET);\r
1525         mcr = serial_in(up, UART_MCR);\r
1526         serial_out(up, UART_MCR, mcr | 0x10);  //loopback mode\r
1527         \r
1528         up->lcr = cval;                         /* Save LCR */\r
1529         /* set DLAB */\r
1530         if(serial_lcr_write(up, cval | UART_LCR_DLAB)) {\r
1531                 if(up->port.line != DBG_PORT)\r
1532                         dbg("serial.%d set DLAB fail\n", up->port.line);\r
1533                 serial_out(up, UART_SRR, UART_RESET);\r
1534                 goto fail;\r
1535         }\r
1536 \r
1537         /* set uart baud rate */\r
1538         if(serial_dl_write(up, quot)) {\r
1539                 if(up->port.line != DBG_PORT)\r
1540                         dbg("serial.%d set dll fail\n", up->port.line);\r
1541                 serial_out(up, UART_SRR, UART_RESET);\r
1542                 goto fail;\r
1543         }\r
1544 \r
1545         /* reset DLAB */\r
1546         if(serial_lcr_write(up, cval)) {\r
1547                 if(up->port.line != DBG_PORT)\r
1548                         dbg("serial.%d reset DLAB fail\n", up->port.line);\r
1549                 serial_out(up, UART_SRR, UART_RESET);\r
1550                 goto fail;\r
1551         }\r
1552         else {\r
1553                 serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1554                 up->fcr = fcr;\r
1555                 serial_out(up, UART_FCR, up->fcr);              /* set fcr */\r
1556                 up->ier = 0;\r
1557                 //start serial receive data\r
1558 #if USE_DMA\r
1559                 if (up->dma->use_dma) {\r
1560                         up->ier |= UART_IER_RLSI;\r
1561                         up->ier |= UART_IER_PTIME;   //Programmable THRE Interrupt Mode Enable\r
1562                         if (up->dma->use_dma & RX_DMA)\r
1563                                 serial_rk_start_dma_rx(up);\r
1564                         else\r
1565                                 up->ier |= UART_IER_RDI;\r
1566                 } else\r
1567 #endif\r
1568                 {\r
1569                         //  not use dma receive\r
1570                         up->ier |= UART_IER_RDI;\r
1571                         up->ier |= UART_IER_RLSI;\r
1572                         if(up->port.line != DBG_PORT)\r
1573                                 up->ier |= UART_IER_PTIME;   //Programmable THRE Interrupt Mode Enable\r
1574 \r
1575                 }\r
1576                 serial_out(up, UART_IER, up->ier);\r
1577         }\r
1578         \r
1579         spin_unlock_irqrestore(&up->port.lock, flags);\r
1580 \r
1581         /* Don't rewrite B0 */\r
1582         if (tty_termios_baud_rate(termios))\r
1583                 tty_termios_encode_baud_rate(termios, baud, baud);\r
1584         dev_dbg(port->dev, "-%s baud %d\n", __func__, baud);\r
1585         return;\r
1586 \r
1587 fail:\r
1588         spin_unlock_irqrestore(&up->port.lock, flags);\r
1589 \r
1590 }\r
1591 \r
1592 #if 0\r
1593 static void\r
1594 serial_rk_set_ldisc(struct uart_port *port, int new)\r
1595 {\r
1596         if (new == N_PPS) {\r
1597                 port->flags |= UPF_HARDPPS_CD;\r
1598                 serial_rk_enable_ms(port);\r
1599         } else\r
1600                 port->flags &= ~UPF_HARDPPS_CD;\r
1601 }\r
1602 #endif\r
1603 \r
1604 static void\r
1605 serial_rk_pm(struct uart_port *port, unsigned int state,\r
1606               unsigned int oldstate)\r
1607 {\r
1608 #ifdef CONFIG_CLOCK_CTRL\r
1609         struct uart_rk_port *up =\r
1610                 container_of(port, struct uart_rk_port, port);\r
1611 \r
1612         dev_dbg(port->dev, "%s: %s\n", __func__, state ? "disable" : "enable");\r
1613         if (state) {\r
1614         clk_disable_unprepare(up->clk);\r
1615         clk_disable_unprepare(up->pclk); \r
1616         } else {\r
1617         clk_prepare_enable(up->clk);\r
1618         clk_prepare_enable(up->pclk); \r
1619         }\r
1620 #endif\r
1621 }\r
1622 \r
1623 static void serial_rk_release_port(struct uart_port *port)\r
1624 {\r
1625         dev_dbg(port->dev, "%s\n", __func__);\r
1626 }\r
1627 \r
1628 static int serial_rk_request_port(struct uart_port *port)\r
1629 {\r
1630         dev_dbg(port->dev, "%s\n", __func__);\r
1631         return 0;\r
1632 }\r
1633 \r
1634 static void serial_rk_config_port(struct uart_port *port, int flags)\r
1635 {\r
1636         dev_dbg(port->dev, "%s\n", __func__);\r
1637         port->type = PORT_RK;\r
1638 }\r
1639 \r
1640 static int\r
1641 serial_rk_verify_port(struct uart_port *port, struct serial_struct *ser)\r
1642 {\r
1643         /* we don't want the core code to modify any port params */\r
1644         dev_dbg(port->dev, "%s\n", __func__);\r
1645         return -EINVAL;\r
1646 }\r
1647 \r
1648 static const char *\r
1649 serial_rk_type(struct uart_port *port)\r
1650 {\r
1651         struct uart_rk_port *up =\r
1652                 container_of(port, struct uart_rk_port, port);\r
1653 \r
1654         dev_dbg(port->dev, "%s: %s\n", __func__, up->name);\r
1655         return up->name;\r
1656 }\r
1657 \r
1658 static struct uart_ops serial_rk_pops = {\r
1659         .tx_empty       = serial_rk_tx_empty,\r
1660         .set_mctrl      = serial_rk_set_mctrl,\r
1661         .get_mctrl      = serial_rk_get_mctrl,\r
1662         .stop_tx        = serial_rk_stop_tx,\r
1663         .start_tx       = serial_rk_start_tx,\r
1664         .stop_rx        = serial_rk_stop_rx,\r
1665         .enable_ms      = serial_rk_enable_ms,\r
1666         .break_ctl      = serial_rk_break_ctl,\r
1667         .startup        = serial_rk_startup,\r
1668         .shutdown       = serial_rk_shutdown,\r
1669         .set_termios    = serial_rk_set_termios,\r
1670 #if 0\r
1671         .set_ldisc      = serial_rk_set_ldisc,\r
1672 #endif\r
1673         .pm             = serial_rk_pm,\r
1674         .type           = serial_rk_type,\r
1675         .release_port   = serial_rk_release_port,\r
1676         .request_port   = serial_rk_request_port,\r
1677         .config_port    = serial_rk_config_port,\r
1678         .verify_port    = serial_rk_verify_port,\r
1679 #ifdef CONFIG_CONSOLE_POLL\r
1680         .poll_get_char = serial_rk_get_poll_char,\r
1681         .poll_put_char = serial_rk_put_poll_char,\r
1682 #endif\r
1683 };\r
1684 \r
1685 #ifdef CONFIG_SERIAL_ROCKCHIP_CONSOLE\r
1686 \r
1687 static struct uart_rk_port *serial_rk_console_ports[UART_NR];\r
1688 \r
1689 static void serial_rk_console_putchar(struct uart_port *port, int ch)\r
1690 {\r
1691         struct uart_rk_port *up =\r
1692                 container_of(port, struct uart_rk_port, port);\r
1693 \r
1694         wait_for_xmitr(up, UART_LSR_THRE);\r
1695         serial_out(up, UART_TX, ch);\r
1696 }\r
1697 \r
1698 /*\r
1699  *      Print a string to the serial port trying not to disturb\r
1700  *      any possible real use of the port...\r
1701  *\r
1702  *      The console_lock must be held when we get here.\r
1703  */\r
1704 static void\r
1705 serial_rk_console_write(struct console *co, const char *s, unsigned int count)\r
1706 {\r
1707         struct uart_rk_port *up = serial_rk_console_ports[co->index];\r
1708         unsigned long flags;\r
1709         unsigned int ier;\r
1710         int locked = 1;\r
1711 \r
1712         touch_nmi_watchdog();\r
1713 \r
1714         local_irq_save(flags);\r
1715         if (up->port.sysrq) {\r
1716                 /* serial_rk_handle_port() already took the lock */\r
1717                 locked = 0;\r
1718         } else if (oops_in_progress) {\r
1719                 locked = spin_trylock(&up->port.lock);\r
1720         } else\r
1721                 spin_lock(&up->port.lock);\r
1722 \r
1723         /*\r
1724          *      First save the IER then disable the interrupts\r
1725          */\r
1726         ier = serial_in(up, UART_IER);\r
1727 \r
1728         serial_out(up, UART_IER, 0);\r
1729 \r
1730         uart_console_write(&up->port, s, count, serial_rk_console_putchar);\r
1731 \r
1732         /*\r
1733          *      Finally, wait for transmitter to become empty\r
1734          *      and restore the IER\r
1735          */\r
1736         wait_for_xmitr(up, UART_LSR_TEMT);\r
1737         serial_out(up, UART_IER, ier);\r
1738 \r
1739 #if 0\r
1740         /*\r
1741          *      The receive handling will happen properly because the\r
1742          *      receive ready bit will still be set; it is not cleared\r
1743          *      on read.  However, modem control will not, we must\r
1744          *      call it if we have saved something in the saved flags\r
1745          *      while processing with interrupts off.\r
1746          */\r
1747         if (up->msr_saved_flags)\r
1748                 check_modem_status(up);\r
1749 #endif\r
1750 \r
1751         if (locked)\r
1752                 spin_unlock(&up->port.lock);\r
1753         local_irq_restore(flags);\r
1754 }\r
1755 \r
1756 #ifdef CONFIG_RK_CONSOLE_THREAD\r
1757 #include <linux/kfifo.h>\r
1758 #include <linux/kthread.h>\r
1759 static struct task_struct *console_task;\r
1760 #define FIFO_SIZE SZ_512K\r
1761 static DEFINE_KFIFO(fifo, unsigned char, FIFO_SIZE);\r
1762 static bool console_thread_stop;\r
1763 \r
1764 static void console_putc(struct uart_rk_port *up, unsigned int c)\r
1765 {\r
1766         while (!(serial_in(up, UART_USR) & UART_USR_TX_FIFO_NOT_FULL))\r
1767                 cpu_relax();\r
1768         serial_out(up, UART_TX, c);\r
1769 }\r
1770 \r
1771 static void console_flush(struct uart_rk_port *up)\r
1772 {\r
1773         while (!(serial_in(up, UART_USR) & UART_USR_TX_FIFO_EMPTY))\r
1774                 cpu_relax();\r
1775 }\r
1776 \r
1777 static int console_thread(void *data)\r
1778 {\r
1779         struct uart_rk_port *up = data;\r
1780         unsigned char c;\r
1781 \r
1782         while (1) {\r
1783                 set_current_state(TASK_INTERRUPTIBLE);\r
1784                 schedule();\r
1785                 if (kthread_should_stop())\r
1786                         break;\r
1787                 set_current_state(TASK_RUNNING);\r
1788                 while (!console_thread_stop && serial_in(up, UART_SFE) && kfifo_get(&fifo, &c)) {\r
1789                         console_putc(up, c);\r
1790                 }\r
1791                 if (!console_thread_stop)\r
1792                         console_flush(up);\r
1793         }\r
1794 \r
1795         return 0;\r
1796 }\r
1797 \r
1798 static void console_write(struct console *co, const char *s, unsigned int count)\r
1799 {\r
1800         struct uart_rk_port *up = serial_rk_console_ports[co->index];\r
1801         unsigned int fifo_count = FIFO_SIZE;\r
1802         unsigned char c, r = '\r';\r
1803 \r
1804         if (console_thread_stop ||\r
1805             oops_in_progress ||\r
1806             system_state == SYSTEM_HALT ||\r
1807             system_state == SYSTEM_POWER_OFF ||\r
1808             system_state == SYSTEM_RESTART) {\r
1809                 if (!console_thread_stop) {\r
1810                         console_thread_stop = true;\r
1811                         smp_wmb();\r
1812                         console_flush(up);\r
1813                         while (fifo_count-- && kfifo_get(&fifo, &c))\r
1814                                 console_putc(up, c);\r
1815                 }\r
1816                 while (count--) {\r
1817                         if (*s == '\n') {\r
1818                                 console_putc(up, r);\r
1819                         }\r
1820                         console_putc(up, *s++);\r
1821                 }\r
1822                 console_flush(up);\r
1823         } else {\r
1824                 while (count--) {\r
1825                         if (*s == '\n') {\r
1826                                 kfifo_put(&fifo, &r);\r
1827                         }\r
1828                         kfifo_put(&fifo, s++);\r
1829                 }\r
1830                 wake_up_process(console_task);\r
1831         }\r
1832 }\r
1833 #endif\r
1834 \r
1835 static int __init serial_rk_console_setup(struct console *co, char *options)\r
1836 {\r
1837         struct uart_rk_port *up;\r
1838         int baud = 115200;\r
1839         int bits = 8;\r
1840         int parity = 'n';\r
1841         int flow = 'n';\r
1842 \r
1843         if (unlikely(co->index >= UART_NR || co->index < 0))\r
1844                 return -ENODEV;\r
1845 \r
1846         if (serial_rk_console_ports[co->index] == NULL)\r
1847                 return -ENODEV;\r
1848         up = serial_rk_console_ports[co->index];\r
1849 \r
1850         if (options)\r
1851                 uart_parse_options(options, &baud, &parity, &bits, &flow);\r
1852 \r
1853 #ifdef CONFIG_RK_CONSOLE_THREAD\r
1854         if (!console_task) {\r
1855                 console_task = kthread_create(console_thread, up, "kconsole");\r
1856                 if (!IS_ERR(console_task))\r
1857                         co->write = console_write;\r
1858         }\r
1859 #endif\r
1860         return uart_set_options(&up->port, co, baud, parity, bits, flow);\r
1861 }\r
1862 \r
1863 static struct console serial_rk_console = {\r
1864         .name           = "ttyS",\r
1865         .write          = serial_rk_console_write,\r
1866         .device         = uart_console_device,\r
1867         .setup          = serial_rk_console_setup,\r
1868         .flags          = CON_PRINTBUFFER | CON_ANYTIME,\r
1869         .index          = -1,\r
1870         .data           = &serial_rk_reg,\r
1871 };\r
1872 \r
1873 static void serial_rk_add_console_port(struct uart_rk_port *up)\r
1874 {\r
1875         serial_rk_console_ports[up->pdev->id] = up;\r
1876 }\r
1877 \r
1878 #define SERIAL_CONSOLE  &serial_rk_console\r
1879 #else\r
1880 #define SERIAL_CONSOLE  NULL\r
1881 \r
1882 static inline void serial_rk_add_console_port(struct uart_rk_port *up)\r
1883 {}\r
1884 \r
1885 #endif\r
1886 \r
1887 static struct uart_driver serial_rk_reg = {\r
1888         .owner                  = THIS_MODULE,\r
1889         .driver_name            = "rk_serial",\r
1890         .dev_name               = "ttyS",\r
1891         .major                  = TTY_MAJOR,\r
1892         .minor                  = 64,\r
1893         .cons                   = SERIAL_CONSOLE,\r
1894         .nr                     = UART_NR,\r
1895 };\r
1896 #if USE_WAKEUP\r
1897 static irqreturn_t serial_rk_wakeup_handler(int irq, void *dev) {\r
1898         struct uart_rk_port *up = dev;\r
1899         struct uart_wake_up *wakeup = up->wakeup;\r
1900         if(wakeup->enable == 1) {\r
1901                 iomux_set(wakeup->rx_mode);\r
1902                 wake_lock_timeout(&wakeup->wakelock, 3 * HZ);\r
1903         }    \r
1904         return 0;\r
1905 }\r
1906 \r
1907 static int serial_rk_setup_wakeup_irq(struct uart_rk_port *up)\r
1908 {\r
1909         int ret = 0;\r
1910         struct uart_wake_up *wakeup = up->wakeup;\r
1911 \r
1912         if(wakeup->enable == 1) {\r
1913                 memset(wakeup->wakelock_name, 0, 32);\r
1914                 sprintf(wakeup->wakelock_name, "serial.%d_wakelock", up->port.line);\r
1915                 wake_lock_init(&wakeup->wakelock, WAKE_LOCK_SUSPEND, wakeup->wakelock_name);\r
1916                 memset(wakeup->rx_pin_name, 0, 32);             \r
1917                 sprintf(wakeup->rx_pin_name, "UART%d_SIN", up->port.line);\r
1918                 wakeup->rx_pin = iomux_mode_to_gpio(wakeup->rx_mode);\r
1919                 ret = gpio_request(wakeup->rx_pin, wakeup->rx_pin_name);\r
1920                 if (ret) {\r
1921                         printk("request %s fail ! \n", wakeup->rx_pin_name);\r
1922                     return ret;\r
1923                 }\r
1924                 gpio_direction_input(wakeup->rx_pin);\r
1925                 wakeup->rx_irq = gpio_to_irq(wakeup->rx_pin);\r
1926                 memset(wakeup->rx_irq_name, 0, 32);\r
1927                 sprintf(wakeup->rx_irq_name, "serial.%d_wake_up_irq", up->port.line);\r
1928                 ret = request_irq(wakeup->rx_irq, serial_rk_wakeup_handler, IRQF_TRIGGER_FALLING, wakeup->rx_irq_name, up);\r
1929                 if(ret < 0) {\r
1930                         printk("%s request fail\n", wakeup->rx_irq_name);\r
1931                     return ret;\r
1932                 }\r
1933                 disable_irq_nosync(wakeup->rx_irq);\r
1934                 enable_irq_wake(wakeup->rx_irq);\r
1935                 iomux_set(wakeup->rx_mode);\r
1936         }\r
1937         return ret;\r
1938 }\r
1939 \r
1940 static int serial_rk_enable_wakeup_irq(struct uart_rk_port *up) {\r
1941         struct uart_wake_up *wakeup = up->wakeup;\r
1942         if(wakeup->enable == 1) {\r
1943                 iomux_set(wakeup->rx_mode & 0xfff0);\r
1944                 enable_irq(wakeup->rx_irq);\r
1945         }\r
1946     return 0;\r
1947 }\r
1948 \r
1949 static int serial_rk_disable_wakeup_irq(struct uart_rk_port *up) {\r
1950         struct uart_wake_up *wakeup = up->wakeup;\r
1951         if(wakeup->enable == 1) {\r
1952                 disable_irq_nosync(wakeup->rx_irq);\r
1953                 iomux_set(wakeup->rx_mode);\r
1954         }\r
1955     return 0;\r
1956 }\r
1957 \r
1958 static int serial_rk_remove_wakeup_irq(struct uart_rk_port *up) {\r
1959         struct uart_wake_up *wakeup = up->wakeup;\r
1960         if(wakeup->enable == 1) {\r
1961                 //disable_irq_nosync(wakeup->rx_irq);\r
1962                 free_irq(wakeup->rx_irq, NULL);\r
1963                 gpio_free(wakeup->rx_pin);\r
1964                 wake_lock_destroy(&wakeup->wakelock);\r
1965         }\r
1966     return 0;\r
1967 }\r
1968 #endif\r
1969 \r
1970 #ifdef CONFIG_OF\r
1971 static int of_rk_serial_parse_dt(struct device_node *np, struct of_rk_serial *rks) \r
1972 {\r
1973         unsigned int val = 0;\r
1974         const char *s = NULL;\r
1975         int ret, i = 0;\r
1976         rks->id = of_alias_get_id(np, "serial");\r
1977         if(!of_property_read_u32(np, "clock-frequency", &val))\r
1978                 rks->uartclk = val;\r
1979 \r
1980 #if USE_DMA\r
1981         rks->use_dma = 0;\r
1982         for(i = 0; i < 2; i++) {\r
1983                 ret = of_property_read_string_index(np, "dma-names", i, &s);\r
1984                 if(!ret) {\r
1985                         if(!strcmp(s, "tx"))\r
1986                                 rks->use_dma |= TX_DMA;\r
1987                          else if (!strcmp(s, "rx"))\r
1988                                 rks->use_dma |= RX_DMA;\r
1989                 }\r
1990         }\r
1991 #endif\r
1992         return 0;\r
1993 }\r
1994 #endif\r
1995 \r
1996 static int serial_rk_probe(struct platform_device *pdev)\r
1997 {\r
1998         struct uart_rk_port     *up;\r
1999         struct resource         *mem;\r
2000         int irq;\r
2001         int ret = -ENOSPC;\r
2002         struct of_rk_serial rks;\r
2003 \r
2004         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);\r
2005         if (!up)\r
2006                 return -ENOMEM;\r
2007 \r
2008         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
2009         up->port.membase = devm_request_and_ioremap(&pdev->dev, mem);\r
2010         if (!up->port.membase)\r
2011                 return -ENOMEM;\r
2012 \r
2013         irq = platform_get_irq(pdev, 0);\r
2014         if (irq < 0) {\r
2015                 dev_err(&pdev->dev, "no irq resource?\n");\r
2016                 return irq;\r
2017         }\r
2018 \r
2019 #ifdef CONFIG_OF\r
2020         of_rk_serial_parse_dt(pdev->dev.of_node, &rks);\r
2021         pdev->id = rks.id;\r
2022 #endif\r
2023 \r
2024         sprintf(up->name, "rk29_serial.%d", pdev->id);\r
2025         up->pdev = pdev;\r
2026 #ifdef CONFIG_CLOCK_CTRL\r
2027         up->pclk = devm_clk_get(&pdev->dev, "pclk_uart");\r
2028         up->clk = devm_clk_get(&pdev->dev, "sclk_uart");\r
2029         if (unlikely(IS_ERR(up->clk)) || unlikely(IS_ERR(up->pclk))) {\r
2030                 dev_err(&pdev->dev, "get clock fail\n");\r
2031                 return -EINVAL;\r
2032         }\r
2033 #endif\r
2034         up->tx_loadsz = 30;\r
2035 #if USE_DMA\r
2036         up->dma = devm_kzalloc(&pdev->dev, sizeof(struct rk_uart_dma), GFP_KERNEL);\r
2037         if (!up->dma) {\r
2038                 dev_err(&pdev->dev, "unable to allocate mem\n");\r
2039                 return -ENOMEM;\r
2040         }\r
2041         up->dma->use_dma = rks.use_dma;\r
2042 #endif\r
2043 #if USE_WAKEUP\r
2044         up->wakeup = &rk29_uart_ports_wakeup[pdev->id];\r
2045 #endif\r
2046         up->port.dev = &pdev->dev;\r
2047         up->port.type = PORT_RK;\r
2048         up->port.irq = irq;\r
2049         up->port.iotype = UPIO_MEM;\r
2050         \r
2051         up->port.regshift = 2;\r
2052         //fifo size default is 32, but it will be updated later when start_up\r
2053         up->port.fifosize = 32;\r
2054         up->port.ops = &serial_rk_pops;\r
2055         up->port.line = pdev->id;\r
2056         up->port.iobase = mem->start;\r
2057         up->port.mapbase = mem->start;\r
2058         up->port.irqflags = IRQF_DISABLED;\r
2059 #if defined(CONFIG_CLOCK_CTRL)\r
2060         up->port.uartclk = clk_get_rate(up->clk);\r
2061 #elif defined(CONFIG_OF)\r
2062         up->port.uartclk = rks.uartclk;\r
2063 #else\r
2064         up->port.uartclk = 24000000;\r
2065 #endif\r
2066 \r
2067 #if USE_DMA\r
2068         /* set dma config */\r
2069         pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);\r
2070         if(up->dma->use_dma & RX_DMA) {\r
2071                 //timer\r
2072                 up->dma->use_timer = USE_TIMER;\r
2073                 up->dma->rx_timer.function = serial_rk_report_dma_rx;\r
2074                 up->dma->rx_timer.data = (unsigned long)up;\r
2075                 up->dma->rx_timeout = 10;\r
2076                 up->dma->rx_timer.expires = jiffies + msecs_to_jiffies(up->dma->rx_timeout);\r
2077                 init_timer(&up->dma->rx_timer);\r
2078 \r
2079                 //rx buffer\r
2080                 up->dma->rb_size = DMA_SERIAL_BUFFER_SIZE;\r
2081                 up->dma->rx_buffer = dmam_alloc_coherent(up->port.dev, up->dma->rb_size,\r
2082                                 &up->dma->rx_phy_addr, DMA_MEMORY_MAP);\r
2083                 up->dma->rb_tail = 0;\r
2084                 up->dma->rx_dma_inited = 0;\r
2085                 up->dma->rx_dma_used = 0;\r
2086 \r
2087                 if(!up->dma->rx_buffer){\r
2088                         dev_info(up->port.dev, "dmam_alloc_coherent dma_rx_buffer fail\n");\r
2089                 }\r
2090                 else {\r
2091                         dev_info(up->port.dev, "dma_rx_buffer %p\n", up->dma->rx_buffer);\r
2092                         dev_info(up->port.dev, "dma_rx_phy 0x%08x\n", (unsigned)up->dma->rx_phy_addr);\r
2093                 }\r
2094 \r
2095                 // work queue\r
2096                 //INIT_WORK(&up->uart_work, serial_rk_report_revdata_workfunc);\r
2097                 //INIT_WORK(&up->uart_work_rx, serial_rk_start_dma_rx);\r
2098                 //up->uart_wq = create_singlethread_workqueue("uart_workqueue");\r
2099                 spin_lock_init(&(up->dma->rx_lock));\r
2100                 serial_rk_init_dma_rx(up);\r
2101         }\r
2102 \r
2103         if(up->dma->use_dma & TX_DMA){\r
2104                 //tx buffer\r
2105                 up->dma->tb_size = UART_XMIT_SIZE;\r
2106                 up->dma->tx_buffer = dmam_alloc_coherent(up->port.dev, up->dma->tb_size,\r
2107                                 &up->dma->tx_phy_addr, DMA_MEMORY_MAP);\r
2108                 if(!up->dma->tx_buffer){\r
2109                         dev_info(up->port.dev, "dmam_alloc_coherent dma_tx_buffer fail\n");\r
2110                 }\r
2111                 else{\r
2112                         dev_info(up->port.dev, "dma_tx_buffer %p\n", up->dma->tx_buffer);\r
2113                         dev_info(up->port.dev, "dma_tx_phy 0x%08x\n", (unsigned) up->dma->tx_phy_addr);\r
2114                 }\r
2115                 spin_lock_init(&(up->dma->tx_lock));\r
2116                 serial_rk_init_dma_tx(up);\r
2117         }\r
2118 \r
2119         \r
2120 #endif\r
2121         serial_rk_add_console_port(up);\r
2122         ret = uart_add_one_port(&serial_rk_reg, &up->port);\r
2123         if (ret != 0)\r
2124                 return ret;\r
2125         platform_set_drvdata(pdev, up);\r
2126         dev_info(&pdev->dev, "membase %p\n", up->port.membase);\r
2127 #if USE_WAKEUP\r
2128         serial_rk_setup_wakeup_irq(up); \r
2129 #endif\r
2130         return 0;\r
2131 }\r
2132 \r
2133 static int serial_rk_remove(struct platform_device *pdev)\r
2134 {\r
2135         struct uart_rk_port *up = platform_get_drvdata(pdev);\r
2136 \r
2137         platform_set_drvdata(pdev, NULL);\r
2138         if (up) {\r
2139 #if USE_DMA\r
2140                 serial_rk_release_dma_tx(up);\r
2141                 serial_rk_release_dma_rx(up);\r
2142 #endif\r
2143 #if USE_WAKEUP\r
2144         serial_rk_remove_wakeup_irq(up);\r
2145 #endif\r
2146                 //destroy_workqueue(up->uart_wq);\r
2147                 uart_remove_one_port(&serial_rk_reg, &up->port);\r
2148                 up->port.membase = NULL;\r
2149         }\r
2150 \r
2151         return 0;\r
2152 }\r
2153 \r
2154 static int serial_rk_suspend(struct platform_device *dev, pm_message_t state)\r
2155 {\r
2156         struct uart_rk_port *up = platform_get_drvdata(dev);\r
2157 \r
2158         if (up && up->port.line != DBG_PORT && POWER_MANEGEMENT){\r
2159                 uart_suspend_port(&serial_rk_reg, &up->port);\r
2160         }\r
2161         if(up->port.line == DBG_PORT && POWER_MANEGEMENT){\r
2162                 serial_rk_pm(&up->port, 1, 0);\r
2163         }\r
2164 #if USE_WAKEUP\r
2165     serial_rk_enable_wakeup_irq(up);\r
2166 #endif\r
2167         return 0;\r
2168 }\r
2169 \r
2170 static int serial_rk_resume(struct platform_device *dev)\r
2171 {\r
2172         struct uart_rk_port *up = platform_get_drvdata(dev);\r
2173 #if USE_WAKEUP\r
2174     serial_rk_disable_wakeup_irq(up);\r
2175 #endif\r
2176         if (up && up->port.line != DBG_PORT && POWER_MANEGEMENT){\r
2177                 uart_resume_port(&serial_rk_reg, &up->port);\r
2178         }\r
2179         if(up->port.line == DBG_PORT && POWER_MANEGEMENT){\r
2180                 serial_rk_pm(&up->port, 0, 1);\r
2181         }\r
2182         return 0;\r
2183 }\r
2184 #ifdef CONFIG_OF\r
2185 static const struct of_device_id of_rk_serial_match[] = {\r
2186         { .compatible = "rockchip,serial" },\r
2187         { /* Sentinel */ }\r
2188 };\r
2189 #endif\r
2190 static struct platform_driver serial_rk_driver = {\r
2191         .probe          = serial_rk_probe,\r
2192         .remove         = serial_rk_remove,\r
2193         .suspend        = serial_rk_suspend,\r
2194         .resume         = serial_rk_resume,\r
2195         .driver         = {\r
2196                 .name   = "serial",\r
2197 #ifdef CONFIG_OF\r
2198                 .of_match_table = of_rk_serial_match,\r
2199 #endif\r
2200                 .owner  = THIS_MODULE,\r
2201         },\r
2202 };\r
2203 \r
2204 static int __init serial_rk_init(void)\r
2205 {\r
2206         int ret;\r
2207         //hhb@rock-chips.com\r
2208         printk("%s\n", VERSION_AND_TIME);\r
2209         ret = uart_register_driver(&serial_rk_reg);\r
2210         if (ret)\r
2211                 return ret;\r
2212         ret = platform_driver_register(&serial_rk_driver);\r
2213         if (ret != 0)\r
2214                 uart_unregister_driver(&serial_rk_reg);\r
2215         return ret;\r
2216 }\r
2217 \r
2218 static void __exit serial_rk_exit(void)\r
2219 {\r
2220         platform_driver_unregister(&serial_rk_driver);\r
2221         uart_unregister_driver(&serial_rk_reg);\r
2222 }\r
2223 \r
2224 module_init(serial_rk_init);\r
2225 module_exit(serial_rk_exit);\r
2226 \r
2227 MODULE_LICENSE("GPL");\r
2228 MODULE_DESCRIPTION("RK UART driver");\r