drivers/tty/serial/rk_serial.c

   1 /*\r
   2  * Driver for RK-UART controller.\r
   3  * Based on drivers/tty/serial/8250.c\r
   4  *\r
   5  * Copyright (C) 2011 Rochchip.\r
   6  *\r
   7  * This program is free software; you can redistribute it and/or modify\r
   8  * it under the terms of the GNU General Public License as published by\r
   9  * the Free Software Foundation; either version 2 of the License, or\r
  10 \r
  11  * (at your option) any later version.\r
  12  *\r
  13  * Author: hhb@rock-chips.com\r
  14  * Date: 2011.06.18\r
  15  */\r
  16 \r
  17 #if defined(CONFIG_SERIAL_ROCKCHIP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)\r
  18 #define SUPPORT_SYSRQ\r
  19 #endif\r
  20 \r
  21 #include <linux/module.h>\r
  22 #include <linux/ioport.h>\r
  23 #include <linux/init.h>\r
  24 #include <linux/console.h>\r
  25 #include <linux/sysrq.h>\r
  26 #include <linux/delay.h>\r
  27 #include <linux/platform_device.h>\r
  28 #include <linux/tty.h>\r
  29 #include <linux/ratelimit.h>\r
  30 #include <linux/tty_flip.h>\r
  31 #include <linux/serial_reg.h>\r
  32 #include <linux/serial_core.h>\r
  33 #include <linux/serial.h>\r
  34 #include <linux/nmi.h>\r
  35 #include <linux/mutex.h>\r
  36 #include <linux/slab.h>\r
  37 #include <linux/clk.h>\r
  38 #include <linux/timer.h>\r
  39 #include <linux/workqueue.h>\r
  40 #include <linux/dma-mapping.h>\r
  41 #include <asm/io.h>\r
  42 #include <asm/irq.h>\r
  43 \r
  44 #include <linux/dmaengine.h>\r
  45 \r
  46 #ifdef CONFIG_OF\r
  47 #include <linux/of.h>\r
  48 #endif\r
  49 \r
  50 \r
  51 /*\r
  52 *                        Driver Version Note\r
  53 *\r
  54 *v0.0 : this driver is 2.6.32 kernel driver;\r
  55 *v0.1 : this driver is 3.0.8 kernel driver;\r
  56 *v1.0 : 2012-08-09\r
  57 *               1.modify dma dirver;\r
  58 *               2.enable Programmable THRE Interrupt Mode, so we can just judge ((up->iir & 0x0f) == 0x02) when transmit\r
  59 *               3.reset uart and set it to loopback state to ensure setting baud rate sucessfully \r
  60 *v1.1 : 2012-08-23\r
  61 *               1. dma driver:make "when tx dma is only enable" work functionally  \r
  62 *v1.2 : 2012-08-28\r
  63 *               1. dma driver:serial rx use new dma interface  rk29_dma_enqueue_ring \r
  64 *v1.3 : 2012-12-14\r
  65 *               1. When enable Programmable THRE Interrupt Mode, in lsr register, only UART_LSR_TEMT means transmit empty, but\r
  66                  UART_LSR_THRE doesn't. So, the macro BOTH_EMPTY should be replaced with UART_LSR_TEMT.\r
  67 *v1.4 : 2013-04-16\r
  68 *               1.fix bug dma buffer free error\r
  69 *v1.5 : 2013-10-17\r
  70 *               1.in some case, set uart rx as gpio interrupt to wake up arm, when arm suspends \r
  71 *v1.6 : 2013-11-29\r
  72                 migrate to kernel3.10,and fit device tree\r
  73 *v1.7 : 2014-03-03\r
  74                 DMA use new interfaces, and use some interfaces with devm_ prefix \r
  75 *v1.8 : 2014-03-04\r
  76 *               1.clear receive time out interrupt request in irq handler       \r
  77 */\r
  78 #define VERSION_AND_TIME  "rk_serial.c v1.8 2014-03-04"\r
  79 \r
  80 #define PORT_RK         90\r
  81 #define UART_USR        0x1F    /* UART Status Register */\r
  82 #define UART_USR_BUSY (1)\r
  83 #define UART_IER_PTIME  0x80    /* Programmable THRE Interrupt Mode Enable */\r
  84 #define UART_LSR_RFE    0x80    /* receive fifo error */\r
  85 #define UART_SRR                0x22    /* software reset register */\r
  86 #define UART_RESET              0x01\r
  87 \r
  88 \r
  89 //#define BOTH_EMPTY    (UART_LSR_TEMT | UART_LSR_THRE)\r
  90 #define UART_NR 5   //uart port number\r
  91 \r
  92 \r
  93 /* configurate whether the port transmit-receive by DMA in menuconfig*/\r
  94 #define OPEN_DMA      1\r
  95 #define CLOSE_DMA     0\r
  96 \r
  97 #define TX_DMA (1)\r
  98 #define RX_DMA (2)\r
  99 #define DMA_SERIAL_BUFFER_SIZE     (UART_XMIT_SIZE*2)\r
 100 #define CONFIG_CLOCK_CTRL  1\r
 101 //serial wake up \r
 102 #ifdef CONFIG_UART0_WAKEUP_RK29 \r
 103 #define UART0_USE_WAKEUP CONFIG_UART0_WAKEUP_RK29\r
 104 #else\r
 105 #define UART0_USE_WAKEUP 0\r
 106 #endif\r
 107 #ifdef CONFIG_UART1_WAKEUP_RK29\r
 108 #define UART1_USE_WAKEUP CONFIG_UART1_WAKEUP_RK29\r
 109 #else\r
 110 #define UART1_USE_WAKEUP 0\r
 111 #endif\r
 112 #ifdef CONFIG_UART2_WAKEUP_RK29\r
 113 #define UART2_USE_WAKEUP CONFIG_UART2_WAKEUP_RK29\r
 114 #else\r
 115 #define UART2_USE_WAKEUP 0\r
 116 #endif\r
 117 #ifdef CONFIG_UART3_WAKEUP_RK29\r
 118 #define UART3_USE_WAKEUP CONFIG_UART3_WAKEUP_RK29\r
 119 #else\r
 120 #define UART3_USE_WAKEUP 0\r
 121 #endif\r
 122 \r
 123 #define USE_TIMER    1           // use timer for dma transport\r
 124 #define POWER_MANEGEMENT 1\r
 125 #define RX_TIMEOUT              (3000*3)  //uint ms\r
 126 #define DMA_TX_TRRIGE_LEVEL 128\r
 127 #define SERIAL_CIRC_CNT_TO_END(xmit)   CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)\r
 128 \r
 129 #define USE_DMA  OPEN_DMA\r
 130 \r
 131 #define USE_WAKEUP (UART0_USE_WAKEUP | UART1_USE_WAKEUP | UART2_USE_WAKEUP | UART3_USE_WAKEUP)\r
 132 \r
 133 #if USE_WAKEUP\r
 134 #include <mach/iomux.h>\r
 135 #include <linux/wakelock.h>\r
 136 #endif\r
 137 \r
 138 \r
 139 \r
 140 static struct uart_driver serial_rk_reg;\r
 141 \r
 142 /*\r
 143  * Debugging.\r
 144  */\r
 145 #ifdef CONFIG_ARCH_RK29\r
 146 #define DBG_PORT 1   //DBG_PORT which uart is used to print log message\r
 147 #else\r
 148 #ifndef CONFIG_RK_DEBUG_UART   //DBG_PORT which uart is used to print log message\r
 149 #define DBG_PORT 2\r
 150 #else\r
 151 #define DBG_PORT CONFIG_RK_DEBUG_UART\r
 152 #endif\r
 153 #endif\r
 154 \r
 155 #ifdef CONFIG_SERIAL_CORE_CONSOLE\r
 156 #define uart_console(port)      ((port)->cons && (port)->cons->index == (port)->line)\r
 157 #else\r
 158 #define uart_console(port)      (0)\r
 159 #endif\r
 160 \r
 161 \r
 162 extern void printascii(const char *);\r
 163 static void dbg(const char *fmt, ...)\r
 164 {\r
 165         va_list va;\r
 166         char buff[256];\r
 167 \r
 168         va_start(va, fmt);\r
 169         vsprintf(buff, fmt, va);\r
 170         va_end(va);\r
 171 \r
 172 #if defined(CONFIG_DEBUG_LL) || defined(CONFIG_RK_EARLY_PRINTK)\r
 173         printascii(buff);\r
 174 #endif\r
 175 }\r
 176 \r
 177 //enable log output\r
 178 #define DEBUG 0\r
 179 static int log_port = -1;\r
 180 module_param(log_port, int, S_IRUGO|S_IWUSR);\r
 181 \r
 182 #if DEBUG\r
 183 #define DEBUG_INTR(fmt...)      if (up->port.line == log_port && !uart_console(&up->port)) dbg(fmt)\r
 184 #else\r
 185 #define DEBUG_INTR(fmt...)      do { } while (0)\r
 186 #endif\r
 187 \r
 188 \r
 189 #if USE_DMA\r
 190 /* added by hhb@rock-chips.com for uart dma transfer */\r
 191 \r
 192 struct rk_uart_dma {\r
 193         u32 use_dma;            //1:used\r
 194         //enum dma_ch rx_dmach;\r
 195         //enum dma_ch tx_dmach;\r
 196 \r
 197         //receive and transfer buffer\r
 198         char * rx_buffer;    //visual memory\r
 199         char * tx_buffer;\r
 200         dma_addr_t rx_phy_addr;  //physical memory\r
 201         dma_addr_t tx_phy_addr;\r
 202         u32 rb_size;             //buffer size\r
 203         u32 tb_size;\r
 204 \r
 205         //regard the rx buffer as a circular buffer\r
 206         u32 rb_head;\r
 207         u32 rb_tail;\r
 208         u32 rx_size;\r
 209 \r
 210         spinlock_t              tx_lock;\r
 211         spinlock_t              rx_lock;\r
 212 \r
 213         char tx_dma_inited;   //1:dma tx channel has been init\r
 214         char rx_dma_inited;      //1:dma rx channel has been init\r
 215         char tx_dma_used;        //1:dma tx is working\r
 216         char rx_dma_used;    //1:dma rx is working\r
 217 \r
 218         /* timer to poll activity on rx dma */\r
 219         char use_timer;\r
 220         int      rx_timeout;\r
 221         struct timer_list rx_timer;\r
 222 \r
 223         struct dma_chan         *dma_chan_rx, *dma_chan_tx;\r
 224         struct scatterlist      rx_sgl, tx_sgl;\r
 225         unsigned int            rx_bytes, tx_bytes;\r
 226 };\r
 227 #endif\r
 228 \r
 229 #if USE_WAKEUP  \r
 230 struct uart_wake_up {\r
 231         unsigned int enable;\r
 232         unsigned int rx_mode;\r
 233         unsigned int tx_mode;\r
 234         unsigned int rx_pin;\r
 235         char rx_pin_name[32];\r
 236         unsigned int tx_pin;\r
 237         unsigned int rx_irq;\r
 238         char rx_irq_name[32];\r
 239         struct wake_lock wakelock;\r
 240         char wakelock_name[32];\r
 241 };\r
 242 #endif\r
 243 \r
 244 #ifdef CONFIG_OF\r
 245 struct of_rk_serial {\r
 246         unsigned int id;\r
 247         unsigned int use_dma;   \r
 248         unsigned int uartclk;\r
 249 };\r
 250 #endif\r
 251 \r
 252 \r
 253 struct uart_rk_port {\r
 254         struct uart_port        port;\r
 255         struct platform_device  *pdev;\r
 256         struct clk              *clk;\r
 257         struct clk              *pclk;\r
 258         unsigned int            tx_loadsz;      /* transmit fifo load size */\r
 259         unsigned char           ier;\r
 260         unsigned char           lcr;\r
 261         unsigned char           mcr;\r
 262         unsigned char           iir;\r
 263         unsigned char           fcr;\r
 264         /*\r
 265          * Some bits in registers are cleared on a read, so they must\r
 266          * be saved whenever the register is read but the bits will not\r
 267          * be immediately processed.\r
 268          */\r
 269 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS\r
 270         unsigned char           lsr_saved_flags;\r
 271 #if 0\r
 272 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA\r
 273         unsigned char           msr_saved_flags;\r
 274 #endif\r
 275 \r
 276         char                    name[16];\r
 277         char                    fifo[64];\r
 278         char                    fifo_size;\r
 279         unsigned long           port_activity;\r
 280         struct work_struct uart_work;\r
 281         struct work_struct uart_work_rx;\r
 282         struct workqueue_struct *uart_wq;\r
 283         struct rk_uart_dma *dma;\r
 284 #if USE_WAKEUP\r
 285         struct uart_wake_up *wakeup;\r
 286 #endif\r
 287 };\r
 288 \r
 289 #if USE_DMA\r
 290 static void serial_rk_release_dma_tx(struct uart_rk_port *up);\r
 291 static int serial_rk_start_dma_tx(struct uart_rk_port *up);\r
 292 //static void serial_rk_rx_timeout(unsigned long uart);\r
 293 static void serial_rk_release_dma_rx(struct uart_rk_port *up);\r
 294 static int serial_rk_start_dma_rx(struct uart_rk_port *up);\r
 295 static void serial_rk_stop_dma_tx(struct uart_rk_port *up);\r
 296 static void serial_rk_stop_dma_rx(struct uart_rk_port *up);\r
 297 \r
 298 #else\r
 299 static inline int serial_rk_start_tx_dma(struct uart_port *port) { return 0; }\r
 300 #endif\r
 301 static int serial_rk_startup(struct uart_port *port);\r
 302 \r
 303 static inline unsigned int serial_in(struct uart_rk_port *up, int offset)\r
 304 {\r
 305         offset = offset << 2;\r
 306 \r
 307         return __raw_readb(up->port.membase + offset);\r
 308 }\r
 309 \r
 310 /* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */\r
 311 static inline void dwapb_save_out_value(struct uart_rk_port *up, int offset,\r
 312                                         unsigned char value)\r
 313 {\r
 314         if (offset == UART_LCR)\r
 315                 up->lcr = value;\r
 316 }\r
 317 \r
 318 /* Read the IER to ensure any interrupt is cleared before returning from ISR. */\r
 319 static inline void dwapb_check_clear_ier(struct uart_rk_port *up, int offset)\r
 320 {\r
 321         if (offset == UART_TX || offset == UART_IER)\r
 322                 serial_in(up, UART_IER);\r
 323 }\r
 324 \r
 325 static inline void serial_out(struct uart_rk_port *up, int offset, unsigned char value)\r
 326 {\r
 327         dwapb_save_out_value(up, offset, value);\r
 328         __raw_writeb(value, up->port.membase + (offset << 2));\r
 329         if (offset != UART_TX)\r
 330                 dsb();\r
 331         dwapb_check_clear_ier(up, offset);\r
 332 }\r
 333 \r
 334 /* Uart divisor latch read */\r
 335 static inline int serial_dl_read(struct uart_rk_port *up)\r
 336 {\r
 337         return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;\r
 338 }\r
 339 \r
 340 /* Uart divisor latch write */\r
 341 static int serial_dl_write(struct uart_rk_port *up, unsigned int value)\r
 342 {\r
 343         unsigned int tmout = 100;\r
 344 \r
 345         while(!(serial_in(up, UART_LCR) & UART_LCR_DLAB)){\r
 346                 if (--tmout == 0){\r
 347                         if(up->port.line != DBG_PORT)\r
 348                                 dbg("set serial.%d baudrate fail with DLAB not set\n", up->port.line);\r
 349                         return -1;\r
 350                 }\r
 351         }\r
 352 \r
 353         tmout = 15000;\r
 354         while(serial_in(up, UART_USR) & UART_USR_BUSY){\r
 355                 if (--tmout == 0){\r
 356                         if(up->port.line != DBG_PORT)\r
 357                                 dbg("set serial.%d baudrate timeout\n", up->port.line);\r
 358                         return -1;\r
 359                 }\r
 360                 udelay(1);\r
 361         }\r
 362 \r
 363         serial_out(up, UART_DLL, value & 0xff);\r
 364         serial_out(up, UART_DLM, value >> 8 & 0xff);\r
 365 \r
 366         return 0;\r
 367 \r
 368 }\r
 369 \r
 370 static int serial_lcr_write(struct uart_rk_port *up, unsigned char value)\r
 371 {\r
 372         unsigned int tmout = 15000;\r
 373 \r
 374         while(serial_in(up, UART_USR) & UART_USR_BUSY){\r
 375                 if (--tmout == 0){\r
 376                         if(up->port.line != DBG_PORT)\r
 377                                 dbg("set serial.%d lc r = 0x%02x timeout\n", up->port.line, value);\r
 378                         return -1;\r
 379                 }\r
 380                 udelay(1);\r
 381         }\r
 382 \r
 383         serial_out(up, UART_LCR, value);\r
 384 \r
 385         return 0;\r
 386 }\r
 387 \r
 388 static inline void serial_rk_enable_ier_thri(struct uart_rk_port *up)\r
 389 {\r
 390         if (!(up->ier & UART_IER_THRI)) {\r
 391                 up->ier |= UART_IER_THRI;\r
 392                 serial_out(up, UART_IER, up->ier);\r
 393         }\r
 394 }\r
 395 \r
 396 \r
 397 static inline void serial_rk_disable_ier_thri(struct uart_rk_port *up)\r
 398 {\r
 399         if (up->ier & UART_IER_THRI) {\r
 400                 up->ier &= ~UART_IER_THRI;\r
 401                 serial_out(up, UART_IER, up->ier);\r
 402         }\r
 403 }\r
 404 \r
 405 static int rk29_uart_dump_register(struct uart_rk_port *up){\r
 406 \r
 407         unsigned int reg_value = 0;\r
 408 \r
 409         reg_value = serial_in(up, UART_IER);\r
 410         dbg("UART_IER = 0x%0x\n", reg_value);\r
 411         reg_value = serial_in(up, UART_IIR);\r
 412         dbg("UART_IIR = 0x%0x\n", reg_value);\r
 413     reg_value = serial_in(up, UART_LSR);\r
 414     dbg("UART_LSR = 0x%0x\n", reg_value);\r
 415     reg_value = serial_in(up, UART_MSR);\r
 416     dbg("UART_MSR = 0x%0x\n", reg_value);\r
 417     reg_value = serial_in(up, UART_MCR);\r
 418     dbg("UART_MCR = 0x%0x\n", reg_value);\r
 419     reg_value = serial_in(up, 0x21);\r
 420     dbg("UART_RFL = 0x%0x\n", reg_value);\r
 421     reg_value = serial_in(up, UART_LCR);\r
 422     dbg("UART_LCR = 0x%0x\n", reg_value);\r
 423         return 0;\r
 424 \r
 425 }\r
 426 \r
 427 /*\r
 428  * FIFO support.\r
 429  */\r
 430 static void serial_rk_clear_fifos(struct uart_rk_port *up)\r
 431 {\r
 432         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);\r
 433         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |\r
 434                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);\r
 435         serial_out(up, UART_FCR, 0);\r
 436 }\r
 437 \r
 438 static inline void __stop_tx(struct uart_rk_port *p)\r
 439 {\r
 440         if (p->ier & UART_IER_THRI) {\r
 441                 p->ier &= ~UART_IER_THRI;\r
 442                 serial_out(p, UART_IER, p->ier);\r
 443         }\r
 444 }\r
 445 \r
 446 static void serial_rk_stop_tx(struct uart_port *port)\r
 447 {\r
 448         struct uart_rk_port *up =\r
 449                 container_of(port, struct uart_rk_port, port);\r
 450 #if USE_DMA\r
 451         struct rk_uart_dma *uart_dma = up->dma;\r
 452         if(uart_dma->use_dma & TX_DMA){\r
 453                 serial_rk_stop_dma_tx(up);\r
 454         }\r
 455 #endif\r
 456         __stop_tx(up);\r
 457 }\r
 458 \r
 459 \r
 460 static void serial_rk_start_tx(struct uart_port *port)\r
 461 {\r
 462         struct uart_rk_port *up =\r
 463                 container_of(port, struct uart_rk_port, port);\r
 464 \r
 465 #if USE_DMA\r
 466         if(up->dma->use_dma & TX_DMA) {\r
 467                 if(!up->dma->tx_dma_used)\r
 468                         serial_rk_enable_ier_thri(up);\r
 469         }else {\r
 470                 serial_rk_enable_ier_thri(up);\r
 471         }\r
 472 #else\r
 473         serial_rk_enable_ier_thri(up);\r
 474 #endif\r
 475 }\r
 476 \r
 477 \r
 478 static void serial_rk_stop_rx(struct uart_port *port)\r
 479 {\r
 480         struct uart_rk_port *up =\r
 481                 container_of(port, struct uart_rk_port, port);\r
 482 #if USE_DMA\r
 483         struct rk_uart_dma *uart_dma = up->dma;\r
 484         if(uart_dma->use_dma & RX_DMA){\r
 485                 serial_rk_stop_dma_rx(up);\r
 486         }\r
 487 #endif\r
 488         up->ier &= ~UART_IER_RLSI;\r
 489         up->port.read_status_mask &= ~UART_LSR_DR;\r
 490         serial_out(up, UART_IER, up->ier);\r
 491 }\r
 492 \r
 493 \r
 494 static void serial_rk_enable_ms(struct uart_port *port)\r
 495 {\r
 496         /* no MSR capabilities */\r
 497 #if 0\r
 498         struct uart_rk_port *up =\r
 499                 container_of(port, struct uart_rk_port, port);\r
 500 \r
 501         dev_dbg(port->dev, "%s\n", __func__);\r
 502         up->ier |= UART_IER_MSI;\r
 503         serial_out(up, UART_IER, up->ier);\r
 504 #endif\r
 505 }\r
 506 \r
 507 #if USE_WAKEUP\r
 508 static struct uart_wake_up rk29_uart_ports_wakeup[] = {\r
 509                 {UART0_USE_WAKEUP, UART0_SIN, UART0_SOUT},\r
 510                 {UART1_USE_WAKEUP, UART1_SIN, UART1_SOUT},\r
 511                 {UART2_USE_WAKEUP, UART2_SIN, UART2_SOUT},\r
 512                 {UART3_USE_WAKEUP, UART3_SIN, UART3_SOUT},\r
 513 };\r
 514 #endif\r
 515 \r
 516 #if USE_DMA\r
 517 /* DMAC PL330 add by hhb@rock-chips.com */\r
 518 \r
 519 static void serial_rk_stop_dma_tx(struct uart_rk_port *up)\r
 520 {\r
 521         struct rk_uart_dma *uart_dma = up->dma;\r
 522         \r
 523         if(uart_dma && uart_dma->tx_dma_used) {\r
 524                 dmaengine_terminate_all(uart_dma->dma_chan_tx);\r
 525                 uart_dma->tx_dma_used = 0;\r
 526         }\r
 527 }\r
 528 \r
 529 static void serial_rk_release_dma_tx(struct uart_rk_port *up)\r
 530 {\r
 531         struct rk_uart_dma *uart_dma = up->dma;\r
 532 \r
 533         if(uart_dma && uart_dma->tx_dma_inited) {\r
 534                 serial_rk_stop_dma_tx(up);\r
 535                 dma_release_channel(uart_dma->dma_chan_tx);\r
 536                 uart_dma->dma_chan_tx = NULL;\r
 537                 uart_dma->tx_dma_inited = 0;\r
 538         }\r
 539 }\r
 540 \r
 541 static void dma_tx_callback(void *data)\r
 542 {\r
 543         struct uart_port *port = data;\r
 544         struct uart_rk_port *up = container_of(port, struct uart_rk_port, port);\r
 545         struct circ_buf *xmit = &port->state->xmit;\r
 546         struct rk_uart_dma *uart_dma = up->dma;\r
 547         struct scatterlist *sgl = &uart_dma->tx_sgl;\r
 548 \r
 549         dma_unmap_sg(up->port.dev, sgl, 1, DMA_TO_DEVICE);\r
 550 \r
 551         xmit->tail = (xmit->tail + uart_dma->tx_bytes) & (UART_XMIT_SIZE - 1);\r
 552         port->icount.tx += uart_dma->tx_bytes;\r
 553         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)\r
 554                 uart_write_wakeup(port);\r
 555 \r
 556         //spin_lock(&(up->dma->tx_lock));\r
 557         uart_dma->tx_dma_used = 0;\r
 558         //spin_unlock(&(up->dma->tx_lock));\r
 559         serial_rk_enable_ier_thri(up);\r
 560         up->port_activity = jiffies;\r
 561 //      dev_info(up->port.dev, "s:%d\n", size);\r
 562 \r
 563 }\r
 564 static int serial_rk_init_dma_tx(struct uart_rk_port *up) {\r
 565 \r
 566         struct dma_slave_config slave_config;\r
 567         struct uart_port *port = &up->port;\r
 568         struct rk_uart_dma *uart_dma = up->dma;\r
 569         int ret;\r
 570 \r
 571         if(!uart_dma){\r
 572                 dev_info(up->port.dev, "serial_rk_init_dma_tx fail\n");\r
 573                 return -1;\r
 574         }\r
 575 \r
 576         if(uart_dma->tx_dma_inited) {\r
 577                 return 0;\r
 578         }\r
 579 \r
 580         uart_dma->dma_chan_tx = dma_request_slave_channel(port->dev, "tx");\r
 581         if (!uart_dma->dma_chan_tx) {\r
 582                 dev_err(port->dev, "cannot get the TX DMA channel!\n");\r
 583                 ret = -EINVAL;\r
 584         }\r
 585 \r
 586         slave_config.direction = DMA_MEM_TO_DEV;        \r
 587         slave_config.dst_addr = port->mapbase + UART_TX;        \r
 588         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;        \r
 589         slave_config.dst_maxburst = 16;\r
 590         ret = dmaengine_slave_config(uart_dma->dma_chan_tx, &slave_config);     \r
 591         if (ret) {\r
 592                 dev_err(port->dev, "error in TX dma configuration.");   \r
 593                 return ret;\r
 594         }\r
 595 \r
 596         uart_dma->tx_dma_inited = 1;\r
 597         dev_info(port->dev, "serial_rk_init_dma_tx sucess\n");\r
 598         return 0;\r
 599 }\r
 600 \r
 601 static int serial_rk_start_dma_tx(struct uart_rk_port *up)\r
 602 {\r
 603         int count = 0;\r
 604         struct uart_port *port = &up->port;\r
 605         struct circ_buf *xmit = &port->state->xmit;\r
 606         struct rk_uart_dma *uart_dma = up->dma;\r
 607         struct scatterlist *sgl = &uart_dma->tx_sgl;\r
 608         struct dma_async_tx_descriptor *desc;\r
 609         int ret;\r
 610 \r
 611         if(!uart_dma->use_dma)\r
 612                 goto err_out;\r
 613 \r
 614         if(-1 == serial_rk_init_dma_tx(up))\r
 615                 goto err_out;\r
 616 \r
 617         if (1 == uart_dma->tx_dma_used)\r
 618                 return 1;\r
 619 \r
 620 //      spin_lock(&(uart_dma->tx_lock));\r
 621         __stop_tx(up);\r
 622 \r
 623         count = SERIAL_CIRC_CNT_TO_END(xmit);\r
 624         count -= count%16;\r
 625         if(count >= DMA_TX_TRRIGE_LEVEL) {\r
 626                 uart_dma->tx_bytes = count;\r
 627                 sg_init_one(sgl, uart_dma->tx_buffer + xmit->tail, count);\r
 628                 ret = dma_map_sg(port->dev, sgl, 1, DMA_TO_DEVICE);\r
 629                 \r
 630                 if (ret == 0) {\r
 631                         dev_err(port->dev, "DMA mapping error for TX.\n");      \r
 632                         return -1;\r
 633                 }       \r
 634                 desc = dmaengine_prep_slave_sg(uart_dma->dma_chan_tx, sgl, 1,\r
 635                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);    \r
 636 \r
 637                 if (!desc) {\r
 638                         dev_err(port->dev, "We cannot prepare for the TX slave dma!\n");                \r
 639                         return -1;      \r
 640                 }       \r
 641                 desc->callback = dma_tx_callback;       \r
 642                 desc->callback_param = port;    \r
 643                 dmaengine_submit(desc);\r
 644                 dma_async_issue_pending(uart_dma->dma_chan_tx);\r
 645                 uart_dma->tx_dma_used = 1;\r
 646         }\r
 647 //      spin_unlock(&(uart_dma->tx_lock));\r
 648         return 1;\r
 649 err_out:\r
 650         dev_info(up->port.dev, "-serial_rk_start_dma_tx-error-\n");\r
 651         return -1;\r
 652 }\r
 653 \r
 654 \r
 655 \r
 656 /*RX*/\r
 657 #if 0\r
 658 static void serial_rk_dma_rxcb(void *buf, int size, enum rk29_dma_buffresult result) {\r
 659 \r
 660         //printk(">>%s:%d\n", __func__, result);\r
 661 }\r
 662 #endif\r
 663 \r
 664 static void serial_rk_stop_dma_rx(struct uart_rk_port *up)\r
 665 {\r
 666         struct rk_uart_dma *uart_dma = up->dma;\r
 667         \r
 668         if(uart_dma && uart_dma->rx_dma_used) {\r
 669                 del_timer(&uart_dma->rx_timer);\r
 670                 dmaengine_terminate_all(uart_dma->dma_chan_rx); \r
 671                 uart_dma->rb_tail = 0;\r
 672                 uart_dma->rx_dma_used = 0;\r
 673         }\r
 674 }\r
 675 \r
 676 \r
 677 static void serial_rk_release_dma_rx(struct uart_rk_port *up)\r
 678 {\r
 679         struct rk_uart_dma *uart_dma = up->dma;\r
 680         \r
 681         if(uart_dma && uart_dma->rx_dma_inited) {\r
 682                 serial_rk_stop_dma_rx(up);\r
 683                 dma_release_channel(uart_dma->dma_chan_rx);\r
 684                 uart_dma->dma_chan_rx = NULL;   \r
 685                 uart_dma->rx_dma_inited = 0;\r
 686         }\r
 687 }\r
 688 \r
 689 \r
 690 static int serial_rk_init_dma_rx(struct uart_rk_port *up) \r
 691 {\r
 692         int ret;\r
 693         struct uart_port *port = &up->port;\r
 694         struct dma_slave_config slave_config;\r
 695         struct rk_uart_dma *uart_dma = up->dma;\r
 696 \r
 697         if(!uart_dma) {\r
 698                 dev_info(port->dev, "serial_rk_init_dma_rx: port fail\n");\r
 699                 return -1;\r
 700         }\r
 701 \r
 702         if(uart_dma->rx_dma_inited) {\r
 703                 return 0;\r
 704         }\r
 705 \r
 706         uart_dma->dma_chan_rx = dma_request_slave_channel(port->dev, "rx");\r
 707         if (!uart_dma->dma_chan_rx) {\r
 708                 dev_err(port->dev, "cannot get the DMA channel.\n");\r
 709                 return -1;\r
 710         }\r
 711 \r
 712         slave_config.direction = DMA_DEV_TO_MEM;        \r
 713         slave_config.src_addr = port->mapbase + UART_RX;        \r
 714         slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;        \r
 715         slave_config.src_maxburst = 1;\r
 716         ret = dmaengine_slave_config(uart_dma->dma_chan_rx, &slave_config);     \r
 717         if (ret) {\r
 718                 dev_err(port->dev, "error in RX dma configuration.\n");         \r
 719                 return ret;     \r
 720         }\r
 721 \r
 722         uart_dma->rx_dma_inited = 1;\r
 723         dev_info(port->dev, "serial_rk_init_dma_rx sucess\n");\r
 724         return 0;\r
 725 }\r
 726 \r
 727 static int serial_rk_start_dma_rx(struct uart_rk_port *up)\r
 728 {\r
 729         struct uart_port *port = &up->port;\r
 730         struct rk_uart_dma *uart_dma = up->dma; \r
 731         struct dma_async_tx_descriptor *desc;   \r
 732         \r
 733         if(!uart_dma->use_dma)\r
 734                 return 0;\r
 735 \r
 736         if(uart_dma->rx_dma_used == 1)\r
 737                 return 0;\r
 738 \r
 739         if(-1 == serial_rk_init_dma_rx(up)){\r
 740                 dev_info(up->port.dev, "*******serial_rk_init_dma_rx*******error*******\n");\r
 741                 return -1;\r
 742         }\r
 743         desc = dmaengine_prep_dma_cyclic(uart_dma->dma_chan_rx, uart_dma->rx_phy_addr, uart_dma->rb_size, uart_dma->rb_size/2,DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);      \r
 744 \r
 745         if (!desc) {\r
 746                 dev_err(port->dev, "We cannot prepare for the RX slave dma!\n");                \r
 747                 return -EINVAL; \r
 748         }\r
 749 \r
 750         //desc->callback = dma_rx_callback;     \r
 751         //desc->callback_param = port;  \r
 752         dev_dbg(port->dev, "RX: prepare for the DMA.\n");\r
 753         dmaengine_submit(desc); \r
 754         dma_async_issue_pending(uart_dma->dma_chan_rx);\r
 755 \r
 756         uart_dma->rx_dma_used = 1;\r
 757         if(uart_dma->use_timer == 1){\r
 758                 mod_timer(&uart_dma->rx_timer, jiffies + msecs_to_jiffies(uart_dma->rx_timeout));\r
 759         }\r
 760         up->port_activity = jiffies;\r
 761         return 1;\r
 762 }\r
 763 \r
 764 static void serial_rk_update_rb_addr(struct uart_rk_port *up)\r
 765 {\r
 766         struct rk_uart_dma *uart_dma = up->dma;\r
 767         struct dma_tx_state state;      \r
 768         //spin_lock(&(up->dma->rx_lock));\r
 769         uart_dma->rx_size = 0;\r
 770         if(uart_dma->rx_dma_used == 1) {\r
 771                 dmaengine_tx_status(uart_dma->dma_chan_rx, (dma_cookie_t)0, &state);\r
 772                 uart_dma->rb_head = (state.residue - uart_dma->rx_phy_addr);\r
 773                 uart_dma->rx_size = CIRC_CNT(uart_dma->rb_head, uart_dma->rb_tail, uart_dma->rb_size);\r
 774         }\r
 775         //spin_unlock(&(up->dma->rx_lock));\r
 776 }\r
 777 \r
 778 static void serial_rk_report_dma_rx(unsigned long uart)\r
 779 {\r
 780         int count, flip = 0;\r
 781         struct uart_rk_port *up = (struct uart_rk_port *)uart;\r
 782         struct uart_port *port = &up->port;\r
 783         struct rk_uart_dma *uart_dma = up->dma;\r
 784 \r
 785         if(!uart_dma->rx_dma_used || !port->state->port.tty)\r
 786                 return;\r
 787 \r
 788         serial_rk_update_rb_addr(up);\r
 789         //if (uart_dma->rx_size > 0)\r
 790         //      printk("rx_size:%d ADDR:%x\n", uart_dma->rx_size, uart_dma->rb_head);\r
 791         while(1) {\r
 792                 count = CIRC_CNT_TO_END(uart_dma->rb_head, uart_dma->rb_tail, uart_dma->rb_size);\r
 793                 if(count <= 0)\r
 794                         break;\r
 795                 port->icount.rx += count;\r
 796                 flip = tty_insert_flip_string(&port->state->port, uart_dma->rx_buffer\r
 797                         + uart_dma->rb_tail, count);\r
 798                 tty_flip_buffer_push(&port->state->port);\r
 799                 uart_dma->rb_tail = (uart_dma->rb_tail + count) & (uart_dma->rb_size - 1);\r
 800                 up->port_activity = jiffies;\r
 801         }\r
 802 \r
 803         if(uart_dma->use_timer == 1)\r
 804                 mod_timer(&uart_dma->rx_timer, jiffies + msecs_to_jiffies(uart_dma->rx_timeout));\r
 805 }\r
 806 #endif /* USE_DMA */\r
 807 \r
 808 \r
 809 static void\r
 810 receive_chars(struct uart_rk_port *up, unsigned int *status)\r
 811 {\r
 812         struct tty_struct *tty = up->port.state->port.tty;\r
 813         unsigned char ch, lsr = *status;\r
 814         int max_count = 256;\r
 815         char flag;\r
 816 \r
 817         do {\r
 818                 if (likely(lsr & UART_LSR_DR)){\r
 819                         ch = serial_in(up, UART_RX);\r
 820                 }\r
 821                 else\r
 822                         /*\r
 823                          * Intel 82571 has a Serial Over Lan device that will\r
 824                          * set UART_LSR_BI without setting UART_LSR_DR when\r
 825                          * it receives a break. To avoid reading from the\r
 826                          * receive buffer without UART_LSR_DR bit set, we\r
 827                          * just force the read character to be 0\r
 828                          */\r
 829                         ch = 0;\r
 830 \r
 831                 flag = TTY_NORMAL;\r
 832                 up->port.icount.rx++;\r
 833 \r
 834                 lsr |= up->lsr_saved_flags;\r
 835                 up->lsr_saved_flags = 0;\r
 836 \r
 837                 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {\r
 838                         /*\r
 839                          * For statistics only\r
 840                          */\r
 841                         if (lsr & UART_LSR_BI) {\r
 842                                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);\r
 843                                 up->port.icount.brk++;\r
 844                                 /*\r
 845                                  * We do the SysRQ and SAK checking\r
 846                                  * here because otherwise the break\r
 847                                  * may get masked by ignore_status_mask\r
 848                                  * or read_status_mask.\r
 849                                  */\r
 850                                 if (uart_handle_break(&up->port))\r
 851                                         goto ignore_char;\r
 852                         } else if (lsr & UART_LSR_PE)\r
 853                                 up->port.icount.parity++;\r
 854                         else if (lsr & UART_LSR_FE)\r
 855                                 up->port.icount.frame++;\r
 856                         if (lsr & UART_LSR_OE)\r
 857                                 up->port.icount.overrun++;\r
 858 \r
 859 \r
 860                         /*\r
 861                          * Mask off conditions which should be ignored.\r
 862                          */\r
 863                         lsr &= up->port.read_status_mask;\r
 864 \r
 865                         if (lsr & UART_LSR_BI) {\r
 866                                 DEBUG_INTR("handling break....");\r
 867                                 flag = TTY_BREAK;\r
 868                         } else if (lsr & UART_LSR_PE)\r
 869                                 flag = TTY_PARITY;\r
 870                         else if (lsr & UART_LSR_FE)\r
 871                                 flag = TTY_FRAME;\r
 872                 }\r
 873                 if (uart_handle_sysrq_char(&up->port, ch))\r
 874                         goto ignore_char;\r
 875 \r
 876                 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);\r
 877 \r
 878 ignore_char:\r
 879                 lsr = serial_in(up, UART_LSR);\r
 880         } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));\r
 881         spin_unlock(&up->port.lock);\r
 882         tty_flip_buffer_push(tty->port);\r
 883         spin_lock(&up->port.lock);\r
 884         *status = lsr;\r
 885 }\r
 886 \r
 887 static void transmit_chars(struct uart_rk_port *up)\r
 888 {\r
 889         struct circ_buf *xmit = &up->port.state->xmit;\r
 890         int count;\r
 891 \r
 892         if (up->port.x_char) {\r
 893                 serial_out(up, UART_TX, up->port.x_char);\r
 894                 up->port.icount.tx++;\r
 895                 up->port.x_char = 0;\r
 896                 return;\r
 897         }\r
 898         if (uart_tx_stopped(&up->port)) {\r
 899                 __stop_tx(up);\r
 900                 return;\r
 901         }\r
 902         if (uart_circ_empty(xmit)) {\r
 903                 __stop_tx(up);\r
 904                 return;\r
 905         }\r
 906 #if USE_DMA\r
 907         //hhb\r
 908         if(up->dma->use_dma & TX_DMA){\r
 909                 if(SERIAL_CIRC_CNT_TO_END(xmit) >= DMA_TX_TRRIGE_LEVEL){\r
 910                         serial_rk_start_dma_tx(up);\r
 911                         return;\r
 912                 }\r
 913         }\r
 914 #endif\r
 915         count = up->port.fifosize - serial_in(up , 0x20);\r
 916         do {\r
 917                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);\r
 918                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);\r
 919                 up->port.icount.tx++;\r
 920                 if (uart_circ_empty(xmit))\r
 921                         break;\r
 922         } while (--count > 0);\r
 923 \r
 924         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)\r
 925                 uart_write_wakeup(&up->port);\r
 926 \r
 927         DEBUG_INTR("THRE...");\r
 928 #if USE_DMA\r
 929         up->port_activity = jiffies;\r
 930 #endif\r
 931         if (uart_circ_empty(xmit))\r
 932                 __stop_tx(up);\r
 933 }\r
 934 \r
 935 static unsigned int check_modem_status(struct uart_rk_port *up)\r
 936 {\r
 937         unsigned int status = serial_in(up, UART_MSR);\r
 938 \r
 939 #if 0\r
 940         status |= up->msr_saved_flags;\r
 941         up->msr_saved_flags = 0;\r
 942         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&\r
 943             up->port.state != NULL) {\r
 944                 if (status & UART_MSR_TERI)\r
 945                         up->port.icount.rng++;\r
 946                 if (status & UART_MSR_DDSR)\r
 947                         up->port.icount.dsr++;\r
 948                 if (status & UART_MSR_DDCD)\r
 949                         uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);\r
 950                 if (status & UART_MSR_DCTS)\r
 951                         uart_handle_cts_change(&up->port, status & UART_MSR_CTS);\r
 952 \r
 953                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);\r
 954         }\r
 955 #endif\r
 956 \r
 957         return status;\r
 958 }\r
 959 \r
 960 \r
 961 /*\r
 962  * This handles the interrupt from one port.\r
 963  */\r
 964 static void serial_rk_handle_port(struct uart_rk_port *up)\r
 965 {\r
 966         unsigned int status;\r
 967         unsigned long flags;\r
 968         spin_lock_irqsave(&up->port.lock, flags);\r
 969 \r
 970         /* reading UART_LSR can automatically clears PE FE OE bits, except receive fifo error bit*/\r
 971         status = serial_in(up, UART_LSR);\r
 972 \r
 973         DEBUG_INTR("status = %x...\n", status);\r
 974 #if USE_DMA\r
 975         /* DMA mode enable */\r
 976         if(up->dma->use_dma) {\r
 977 \r
 978                 if (status & UART_LSR_RFE) {\r
 979                         if(up->port.line != DBG_PORT){\r
 980                                 dev_info(up->port.dev, "error:lsr=0x%x\n", status);\r
 981                                 status = serial_in(up, UART_LSR);\r
 982                                 DEBUG_INTR("error:lsr=0x%x\n", status);\r
 983                         }\r
 984                 }\r
 985 \r
 986                 if (status & 0x02) {\r
 987                         if(up->port.line != DBG_PORT){\r
 988                                 dev_info(up->port.dev, "error:lsr=0x%x\n", status);\r
 989                                 status = serial_in(up, UART_LSR);\r
 990                                 DEBUG_INTR("error:lsr=0x%x\n", status);\r
 991                         }\r
 992                 }\r
 993 \r
 994                 if(!(up->dma->use_dma & RX_DMA)) {\r
 995                         if (status & (UART_LSR_DR | UART_LSR_BI)) {\r
 996                                 receive_chars(up, &status);\r
 997                         } else if ((up->iir & 0x0f) == 0x0c) {\r
 998                 serial_in(up, UART_RX);\r
 999                 }\r
1000                 }\r
1001 \r
1002                 if ((up->iir & 0x0f) == 0x02) {\r
1003                         transmit_chars(up);\r
1004                 }\r
1005         } else \r
1006 #endif\r
1007         {   //dma mode disable\r
1008 \r
1009                 /*\r
1010                  * when uart receive a serial of data which doesn't have stop bit and so on, that causes frame error,and\r
1011                  * set UART_LSR_RFE to one,what is worse,we couldn't read the data in the receive fifo. So if\r
1012                  * wo don't clear this bit and reset the receive fifo, the received data available interrupt would\r
1013                  * occur continuously.  added by hhb@rock-chips.com 2011-08-05\r
1014                  */\r
1015 \r
1016                 if (status & UART_LSR_RFE) {\r
1017                         if(up->port.line != DBG_PORT){\r
1018                                 dev_info(up->port.dev, "error:lsr=0x%x\n", status);\r
1019                                 status = serial_in(up, UART_LSR);\r
1020                                 DEBUG_INTR("error:lsr=0x%x\n", status);\r
1021                                 rk29_uart_dump_register(up);\r
1022                         }\r
1023                 }\r
1024 \r
1025                 if (status & (UART_LSR_DR | UART_LSR_BI)) {\r
1026                         receive_chars(up, &status);\r
1027                 } else if ((up->iir & 0x0f) == 0x0c) {\r
1028             serial_in(up, UART_RX);\r
1029         }\r
1030                 check_modem_status(up);\r
1031                 //hhb@rock-chips.com when FIFO and THRE mode both are enabled,and FIFO TX empty trigger is set to larger than 1,\r
1032                 //,we need to add ((up->iir & 0x0f) == 0x02) to transmit_chars,because when entering interrupt,the FIFO and THR\r
1033                 //might not be 1.\r
1034                 if ((up->iir & 0x0f) == 0x02) {\r
1035                         transmit_chars(up);\r
1036                 }\r
1037         }\r
1038         spin_unlock_irqrestore(&up->port.lock, flags);\r
1039 }\r
1040 \r
1041 /*\r
1042  * This is the serial driver's interrupt routine.\r
1043  */\r
1044 \r
1045 static irqreturn_t serial_rk_interrupt(int irq, void *dev_id)\r
1046 {\r
1047         struct uart_rk_port *up = dev_id;\r
1048         int handled = 0;\r
1049         unsigned int iir;\r
1050 \r
1051         iir = serial_in(up, UART_IIR);\r
1052 \r
1053         DEBUG_INTR("%s(%d) iir = 0x%02x\n", __func__, irq, iir);\r
1054         up->iir = iir;\r
1055 \r
1056         if (!(iir & UART_IIR_NO_INT)) {\r
1057                 serial_rk_handle_port(up);\r
1058                 handled = 1;\r
1059         } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {\r
1060 \r
1061                 /* The DesignWare APB UART has an Busy Detect (0x07)\r
1062                  * interrupt meaning an LCR write attempt occured while the\r
1063                  * UART was busy. The interrupt must be cleared by reading\r
1064                  * the UART status register (USR) and the LCR re-written. */\r
1065 \r
1066                 if(!(serial_in(up, UART_USR) & UART_USR_BUSY)){\r
1067                         serial_out(up, UART_LCR, up->lcr);\r
1068                 }\r
1069                 handled = 1;\r
1070                 dbg("the serial.%d is busy\n", up->port.line);\r
1071         }\r
1072         DEBUG_INTR("end(%d).\n", handled);\r
1073 \r
1074         return IRQ_RETVAL(handled);\r
1075 }\r
1076 \r
1077 static unsigned int serial_rk_tx_empty(struct uart_port *port)\r
1078 {\r
1079         struct uart_rk_port *up =\r
1080                 container_of(port, struct uart_rk_port, port);\r
1081         unsigned long flags;\r
1082         unsigned int lsr;\r
1083 \r
1084         dev_dbg(port->dev, "%s\n", __func__);\r
1085         spin_lock_irqsave(&up->port.lock, flags);\r
1086         lsr = serial_in(up, UART_LSR);\r
1087         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;\r
1088         spin_unlock_irqrestore(&up->port.lock, flags);\r
1089 \r
1090         return (lsr & UART_LSR_TEMT) == UART_LSR_TEMT ? TIOCSER_TEMT : 0;\r
1091 }\r
1092 \r
1093 static unsigned int serial_rk_get_mctrl(struct uart_port *port)\r
1094 {\r
1095         struct uart_rk_port *up =\r
1096                 container_of(port, struct uart_rk_port, port);\r
1097         unsigned int status;\r
1098         unsigned int ret;\r
1099 \r
1100         status = check_modem_status(up);\r
1101 \r
1102         ret = 0;\r
1103         if (status & UART_MSR_DCD)\r
1104                 ret |= TIOCM_CAR;\r
1105         if (status & UART_MSR_RI)\r
1106                 ret |= TIOCM_RNG;\r
1107         if (status & UART_MSR_DSR)\r
1108                 ret |= TIOCM_DSR;\r
1109         if (status & UART_MSR_CTS)\r
1110                 ret |= TIOCM_CTS;\r
1111         dev_dbg(port->dev, "%s 0x%08x\n", __func__, ret);\r
1112         return ret;\r
1113 }\r
1114 \r
1115 static void serial_rk_set_mctrl(struct uart_port *port, unsigned int mctrl)\r
1116 {\r
1117         struct uart_rk_port *up =\r
1118                 container_of(port, struct uart_rk_port, port);\r
1119         unsigned char mcr = 0;\r
1120 \r
1121         dev_dbg(port->dev, "+%s\n", __func__);\r
1122         if (mctrl & TIOCM_RTS)\r
1123                 mcr |= UART_MCR_RTS;\r
1124         if (mctrl & TIOCM_DTR)\r
1125                 mcr |= UART_MCR_DTR;\r
1126         if (mctrl & TIOCM_OUT1)\r
1127                 mcr |= UART_MCR_OUT1;\r
1128         if (mctrl & TIOCM_OUT2)\r
1129                 mcr |= UART_MCR_OUT2;\r
1130         if (mctrl & TIOCM_LOOP)\r
1131                 mcr |= UART_MCR_LOOP;\r
1132 \r
1133         mcr |= up->mcr;\r
1134 \r
1135         serial_out(up, UART_MCR, mcr);\r
1136         dev_dbg(port->dev, "-serial.%d %s mcr: 0x%02x\n", port->line, __func__, mcr);\r
1137 }\r
1138 \r
1139 static void serial_rk_break_ctl(struct uart_port *port, int break_state)\r
1140 {\r
1141         struct uart_rk_port *up =\r
1142                 container_of(port, struct uart_rk_port, port);\r
1143         unsigned long flags;\r
1144 \r
1145         dev_dbg(port->dev, "+%s\n", __func__);\r
1146         spin_lock_irqsave(&up->port.lock, flags);\r
1147         if (break_state == -1)\r
1148                 up->lcr |= UART_LCR_SBC;\r
1149         else\r
1150                 up->lcr &= ~UART_LCR_SBC;\r
1151         serial_lcr_write(up, up->lcr);\r
1152         spin_unlock_irqrestore(&up->port.lock, flags);\r
1153         dev_dbg(port->dev, "-%s lcr: 0x%02x\n", __func__, up->lcr);\r
1154 }\r
1155 \r
1156 #if defined(CONFIG_SERIAL_ROCKCHIP_CONSOLE) || defined(CONFIG_CONSOLE_POLL)\r
1157 /*\r
1158  *      Wait for transmitter & holding register to empty\r
1159  */\r
1160 static void wait_for_xmitr(struct uart_rk_port *up, int bits)\r
1161 {\r
1162         unsigned int status, tmout = 10000;\r
1163 \r
1164         /* Wait up to 10ms for the character(s) to be sent. */\r
1165         for (;;) {\r
1166                 status = serial_in(up, UART_LSR);\r
1167 \r
1168                 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;\r
1169 \r
1170                 if ((status & bits) == bits)\r
1171                         break;\r
1172                 if (--tmout == 0)\r
1173                         break;\r
1174                 udelay(1);\r
1175         }\r
1176 }\r
1177 #endif\r
1178 \r
1179 #ifdef CONFIG_CONSOLE_POLL\r
1180 /*\r
1181  * Console polling routines for writing and reading from the uart while\r
1182  * in an interrupt or debug context.\r
1183  */\r
1184 \r
1185 static int serial_rk_get_poll_char(struct uart_port *port)\r
1186 {\r
1187         struct uart_rk_port *up =\r
1188                 container_of(port, struct uart_rk_port, port);\r
1189         unsigned char lsr = serial_in(up, UART_LSR);\r
1190 \r
1191         while (!(lsr & UART_LSR_DR))\r
1192                 lsr = serial_in(up, UART_LSR);\r
1193 \r
1194         return serial_in(up, UART_RX);\r
1195 }\r
1196 \r
1197 static void serial_rk_put_poll_char(struct uart_port *port,\r
1198                          unsigned char c)\r
1199 {\r
1200         unsigned int ier;\r
1201         struct uart_rk_port *up =\r
1202                 container_of(port, struct uart_rk_port, port);\r
1203 \r
1204         /*\r
1205          *      First save the IER then disable the interrupts\r
1206          */\r
1207         ier = serial_in(up, UART_IER);\r
1208         serial_out(up, UART_IER, 0);\r
1209 \r
1210         wait_for_xmitr(up, UART_LSR_TEMT);\r
1211         /*\r
1212          *      Send the character out.\r
1213          *      If a LF, also do CR...\r
1214          */\r
1215         serial_out(up, UART_TX, c);\r
1216         if (c == 10) {\r
1217                 wait_for_xmitr(up, UART_LSR_TEMT);\r
1218                 serial_out(up, UART_TX, 13);\r
1219         }\r
1220 \r
1221         /*\r
1222          *      Finally, wait for transmitter to become empty\r
1223          *      and restore the IER\r
1224          */\r
1225         wait_for_xmitr(up, UART_LSR_TEMT);\r
1226         serial_out(up, UART_IER, ier);\r
1227 }\r
1228 \r
1229 #endif /* CONFIG_CONSOLE_POLL */\r
1230 \r
1231 static int serial_rk_startup(struct uart_port *port)\r
1232 {\r
1233         struct uart_rk_port *up =\r
1234                 container_of(port, struct uart_rk_port, port);\r
1235         unsigned long flags;\r
1236         int retval, fifosize = 0;\r
1237         \r
1238 \r
1239         dev_dbg(port->dev, "%s\n", __func__);\r
1240 \r
1241         /*\r
1242          * Allocate the IRQ\r
1243          */\r
1244         retval = request_irq(up->port.irq, serial_rk_interrupt, up->port.irqflags,\r
1245                                 up->name, up);\r
1246         if (retval)\r
1247                 return retval;\r
1248 \r
1249         up->mcr = 0;\r
1250 #ifdef CONFIG_CLOCK_CTRL\r
1251         clk_prepare_enable(up->clk);\r
1252         clk_prepare_enable(up->pclk); // enable the config uart clock\r
1253 #endif\r
1254         /*\r
1255          * Clear the FIFO buffers and disable them.\r
1256          * (they will be reenabled in set_termios())\r
1257          */\r
1258         serial_rk_clear_fifos(up);\r
1259 \r
1260         //read uart fifo size  hhb@rock-chips.com\r
1261         fifosize = __raw_readl(up->port.membase + 0xf4);\r
1262         up->port.fifosize = ((fifosize >> 16) & 0xff) << 4;\r
1263         if(up->port.fifosize <= 0)\r
1264                 up->port.fifosize = 32;\r
1265         //printk("fifo size:%d :%08x\n", up->port.fifosize, fifosize);\r
1266 \r
1267         /*\r
1268          * Clear the interrupt registers.\r
1269          */\r
1270         (void) serial_in(up, UART_LSR);\r
1271         (void) serial_in(up, UART_RX);\r
1272         (void) serial_in(up, UART_IIR);\r
1273         (void) serial_in(up, UART_MSR);\r
1274         (void) serial_in(up, UART_USR);\r
1275 \r
1276         /*\r
1277          * Now, initialize the UART\r
1278          */\r
1279         serial_lcr_write(up, UART_LCR_WLEN8 | UART_LCR_EPAR);\r
1280 \r
1281         spin_lock_irqsave(&up->port.lock, flags);\r
1282 \r
1283         /*\r
1284          * Most PC uarts need OUT2 raised to enable interrupts.\r
1285          */\r
1286 //      up->port.mctrl |= TIOCM_OUT2;\r
1287 \r
1288         serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1289 \r
1290         spin_unlock_irqrestore(&up->port.lock, flags);\r
1291 \r
1292         /*\r
1293          * Clear the interrupt registers again for luck, and clear the\r
1294          * saved flags to avoid getting false values from polling\r
1295          * routines or the previous session.\r
1296          */\r
1297         (void) serial_in(up, UART_LSR);\r
1298         (void) serial_in(up, UART_RX);\r
1299         (void) serial_in(up, UART_IIR);\r
1300         (void) serial_in(up, UART_MSR);\r
1301         (void) serial_in(up, UART_USR);\r
1302         up->lsr_saved_flags = 0;\r
1303 #if 0\r
1304         up->msr_saved_flags = 0;\r
1305 #endif\r
1306 #if USE_DMA\r
1307         if (up->dma->use_dma & TX_DMA) {\r
1308                 if(up->port.state->xmit.buf != up->dma->tx_buffer){\r
1309                         free_page((unsigned long)up->port.state->xmit.buf);\r
1310                         up->port.state->xmit.buf = up->dma->tx_buffer;\r
1311                 }\r
1312         } else \r
1313 #endif\r
1314         {\r
1315                 up->ier = 0;\r
1316                 serial_out(up, UART_IER, up->ier);\r
1317         }\r
1318 \r
1319         /*\r
1320          * Finally, enable interrupts.  Note: Modem status interrupts\r
1321          * are set via set_termios(), which will be occurring imminently\r
1322          * anyway, so we don't enable them here.\r
1323          */\r
1324 \r
1325         return 0;\r
1326 }\r
1327 \r
1328 \r
1329 static void serial_rk_shutdown(struct uart_port *port)\r
1330 {\r
1331         struct uart_rk_port *up =\r
1332                 container_of(port, struct uart_rk_port, port);\r
1333         unsigned long flags;\r
1334 \r
1335         dev_dbg(port->dev, "%s\n", __func__);\r
1336         /*\r
1337          * Disable interrupts from this port\r
1338          */\r
1339         up->ier = 0;\r
1340         serial_out(up, UART_IER, 0);\r
1341 \r
1342         spin_lock_irqsave(&up->port.lock, flags);\r
1343 //      up->port.mctrl &= ~TIOCM_OUT2;\r
1344         serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1345         spin_unlock_irqrestore(&up->port.lock, flags);\r
1346 \r
1347         /*\r
1348          * Disable break condition and FIFOs\r
1349          */\r
1350         serial_lcr_write(up, serial_in(up, UART_LCR) & ~UART_LCR_SBC);\r
1351         serial_rk_clear_fifos(up);\r
1352 \r
1353         /*\r
1354          * Read data port to reset things, and then free the irq\r
1355          */\r
1356         (void) serial_in(up, UART_RX);\r
1357 #if USE_DMA\r
1358         if (up->dma->use_dma & TX_DMA)\r
1359                 up->port.state->xmit.buf = NULL;\r
1360 #endif\r
1361         free_irq(up->port.irq, up);\r
1362 #ifdef CONFIG_CLOCK_CTRL\r
1363         clk_disable_unprepare(up->clk);\r
1364         clk_disable_unprepare(up->pclk); \r
1365 #endif\r
1366 }\r
1367 \r
1368 static void\r
1369 serial_rk_set_termios(struct uart_port *port, struct ktermios *termios,\r
1370                       struct ktermios *old)\r
1371 {\r
1372         struct uart_rk_port *up =\r
1373                 container_of(port, struct uart_rk_port, port);\r
1374         unsigned char cval = 0, fcr = 0, mcr = 0;\r
1375         unsigned long flags;\r
1376         unsigned int baud, quot;\r
1377 \r
1378         dev_dbg(port->dev, "+%s\n", __func__);\r
1379 \r
1380 #if USE_DMA\r
1381         //stop dma tx, which might make the uart be busy while some registers are set\r
1382         if(up->dma->tx_dma_used) {\r
1383                 serial_rk_stop_dma_tx(up);\r
1384         }\r
1385 #endif\r
1386 \r
1387         switch (termios->c_cflag & CSIZE) {\r
1388         case CS5:\r
1389                 cval = UART_LCR_WLEN5;\r
1390                 break;\r
1391         case CS6:\r
1392                 cval = UART_LCR_WLEN6;\r
1393                 break;\r
1394         case CS7:\r
1395                 cval = UART_LCR_WLEN7;\r
1396                 break;\r
1397         case CS8:\r
1398         default:\r
1399                 cval = UART_LCR_WLEN8;\r
1400                 break;\r
1401         }\r
1402 \r
1403         if (termios->c_cflag & CSTOPB){\r
1404                 cval |= UART_LCR_STOP;\r
1405         }\r
1406         if (termios->c_cflag & PARENB){\r
1407                 cval |= UART_LCR_PARITY;\r
1408         }\r
1409         if (!(termios->c_cflag & PARODD)){\r
1410                 cval |= UART_LCR_EPAR;\r
1411         }\r
1412 #ifdef CMSPAR\r
1413         if (termios->c_cflag & CMSPAR)\r
1414                 cval |= UART_LCR_SPAR;\r
1415 #endif\r
1416 \r
1417 \r
1418         /*\r
1419          * Ask the core to calculate the divisor for us.\r
1420          */\r
1421         baud = uart_get_baud_rate(port, termios, old,\r
1422                                   port->uartclk / 16 / 0xffff,\r
1423                                   port->uartclk / 16);\r
1424 \r
1425         quot = uart_get_divisor(port, baud);\r
1426         //dev_info(up->port.dev, "uartclk:%d\n", port->uartclk/16);\r
1427         //dev_info(up->port.dev, "baud:%d\n", baud);\r
1428         //dev_info(up->port.dev, "quot:%d\n", quot);\r
1429 \r
1430         if (baud < 2400){\r
1431                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;\r
1432         }\r
1433         else{\r
1434                 fcr = UART_FCR_ENABLE_FIFO;\r
1435 #if USE_DMA\r
1436                 //added by hhb@rock-chips.com\r
1437                 if(up->dma->use_dma & TX_DMA){\r
1438                         fcr |= UART_FCR_T_TRIG_01;\r
1439                 } else\r
1440 #endif\r
1441                 {\r
1442                         fcr |= UART_FCR_T_TRIG_01;\r
1443                 }\r
1444 \r
1445 #if USE_DMA\r
1446                 //added by hhb@rock-chips.com\r
1447                 if(up->dma->use_dma & RX_DMA){  \r
1448                         fcr |= UART_FCR_R_TRIG_00;\r
1449                 } else\r
1450 #endif\r
1451                 {\r
1452                         if (termios->c_cflag & CRTSCTS)\r
1453                                 fcr |= UART_FCR_R_TRIG_11;\r
1454                         else\r
1455                                 fcr |= UART_FCR_R_TRIG_00;\r
1456                 }\r
1457         }\r
1458 \r
1459         /*\r
1460          * MCR-based auto flow control.  When AFE is enabled, RTS will be\r
1461          * deasserted when the receive FIFO contains more characters than\r
1462          * the trigger, or the MCR RTS bit is cleared.  In the case where\r
1463          * the remote UART is not using CTS auto flow control, we must\r
1464          * have sufficient FIFO entries for the latency of the remote\r
1465          * UART to respond.  IOW, at least 32 bytes of FIFO.\r
1466          */\r
1467         up->mcr &= ~UART_MCR_AFE;\r
1468         if (termios->c_cflag & CRTSCTS){\r
1469                 up->mcr |= UART_MCR_AFE;\r
1470         }\r
1471 \r
1472         /*\r
1473          * Ok, we're now changing the port state.  Do it with\r
1474          * interrupts disabled.\r
1475          */\r
1476         spin_lock_irqsave(&up->port.lock, flags);\r
1477 \r
1478         /*\r
1479          * Update the per-port timeout.\r
1480          */\r
1481         uart_update_timeout(port, termios->c_cflag, baud);\r
1482 \r
1483         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;\r
1484         if (termios->c_iflag & INPCK)\r
1485                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;\r
1486         if (termios->c_iflag & (BRKINT | PARMRK))\r
1487                 up->port.read_status_mask |= UART_LSR_BI;\r
1488 \r
1489         /*\r
1490          * Characteres to ignore\r
1491          */\r
1492         up->port.ignore_status_mask = 0;\r
1493         if (termios->c_iflag & IGNPAR)\r
1494                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;\r
1495         if (termios->c_iflag & IGNBRK) {\r
1496                 up->port.ignore_status_mask |= UART_LSR_BI;\r
1497                 /*\r
1498                  * If we're ignoring parity and break indicators,\r
1499                  * ignore overruns too (for real raw support).\r
1500                  */\r
1501                 if (termios->c_iflag & IGNPAR)\r
1502                         up->port.ignore_status_mask |= UART_LSR_OE;\r
1503         }\r
1504 \r
1505         /*\r
1506          * ignore all characters if CREAD is not set\r
1507          */\r
1508         if ((termios->c_cflag & CREAD) == 0)\r
1509                 up->port.ignore_status_mask |= UART_LSR_DR;\r
1510 \r
1511         /*\r
1512          * CTS flow control flag and modem status interrupts\r
1513          */\r
1514         up->ier &= ~UART_IER_MSI;\r
1515 #if 0\r
1516         if (UART_ENABLE_MS(&up->port, termios->c_cflag))\r
1517                 up->ier |= UART_IER_MSI;\r
1518 #endif\r
1519 \r
1520         //to avoid uart busy when set baud rate  hhb@rock-chips.com\r
1521         serial_out(up, UART_SRR, UART_RESET);\r
1522         mcr = serial_in(up, UART_MCR);\r
1523         serial_out(up, UART_MCR, mcr | 0x10);  //loopback mode\r
1524         \r
1525         up->lcr = cval;                         /* Save LCR */\r
1526         /* set DLAB */\r
1527         if(serial_lcr_write(up, cval | UART_LCR_DLAB)) {\r
1528                 if(up->port.line != DBG_PORT)\r
1529                         dbg("serial.%d set DLAB fail\n", up->port.line);\r
1530                 serial_out(up, UART_SRR, UART_RESET);\r
1531                 goto fail;\r
1532         }\r
1533 \r
1534         /* set uart baud rate */\r
1535         if(serial_dl_write(up, quot)) {\r
1536                 if(up->port.line != DBG_PORT)\r
1537                         dbg("serial.%d set dll fail\n", up->port.line);\r
1538                 serial_out(up, UART_SRR, UART_RESET);\r
1539                 goto fail;\r
1540         }\r
1541 \r
1542         /* reset DLAB */\r
1543         if(serial_lcr_write(up, cval)) {\r
1544                 if(up->port.line != DBG_PORT)\r
1545                         dbg("serial.%d reset DLAB fail\n", up->port.line);\r
1546                 serial_out(up, UART_SRR, UART_RESET);\r
1547                 goto fail;\r
1548         }\r
1549         else {\r
1550                 serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1551                 up->fcr = fcr;\r
1552                 serial_out(up, UART_FCR, up->fcr);              /* set fcr */\r
1553                 up->ier = 0;\r
1554                 //start serial receive data\r
1555 #if USE_DMA\r
1556                 if (up->dma->use_dma) {\r
1557                         up->ier |= UART_IER_RLSI;\r
1558                         up->ier |= UART_IER_PTIME;   //Programmable THRE Interrupt Mode Enable\r
1559                         if (up->dma->use_dma & RX_DMA)\r
1560                                 serial_rk_start_dma_rx(up);\r
1561                         else\r
1562                                 up->ier |= UART_IER_RDI;\r
1563                 } else\r
1564 #endif\r
1565                 {\r
1566                         //  not use dma receive\r
1567                         up->ier |= UART_IER_RDI;\r
1568                         up->ier |= UART_IER_RLSI;\r
1569                         if(up->port.line != DBG_PORT)\r
1570                                 up->ier |= UART_IER_PTIME;   //Programmable THRE Interrupt Mode Enable\r
1571 \r
1572                 }\r
1573                 serial_out(up, UART_IER, up->ier);\r
1574         }\r
1575         \r
1576         spin_unlock_irqrestore(&up->port.lock, flags);\r
1577 \r
1578         /* Don't rewrite B0 */\r
1579         if (tty_termios_baud_rate(termios))\r
1580                 tty_termios_encode_baud_rate(termios, baud, baud);\r
1581         dev_dbg(port->dev, "-%s baud %d\n", __func__, baud);\r
1582         return;\r
1583 \r
1584 fail:\r
1585         spin_unlock_irqrestore(&up->port.lock, flags);\r
1586 \r
1587 }\r
1588 \r
1589 #if 0\r
1590 static void\r
1591 serial_rk_set_ldisc(struct uart_port *port, int new)\r
1592 {\r
1593         if (new == N_PPS) {\r
1594                 port->flags |= UPF_HARDPPS_CD;\r
1595                 serial_rk_enable_ms(port);\r
1596         } else\r
1597                 port->flags &= ~UPF_HARDPPS_CD;\r
1598 }\r
1599 #endif\r
1600 \r
1601 static void\r
1602 serial_rk_pm(struct uart_port *port, unsigned int state,\r
1603               unsigned int oldstate)\r
1604 {\r
1605         struct uart_rk_port *up =\r
1606                 container_of(port, struct uart_rk_port, port);\r
1607 \r
1608         dev_dbg(port->dev, "%s: %s\n", __func__, state ? "disable" : "enable");\r
1609         if (state) {\r
1610 #ifdef CONFIG_CLOCK_CTRL\r
1611         clk_disable_unprepare(up->clk);\r
1612         clk_disable_unprepare(up->pclk); \r
1613 #endif\r
1614         } else {\r
1615 #ifdef CONFIG_CLOCK_CTRL\r
1616         clk_prepare_enable(up->clk);\r
1617         clk_prepare_enable(up->pclk); \r
1618 #endif\r
1619         }\r
1620 }\r
1621 \r
1622 static void serial_rk_release_port(struct uart_port *port)\r
1623 {\r
1624         dev_dbg(port->dev, "%s\n", __func__);\r
1625 }\r
1626 \r
1627 static int serial_rk_request_port(struct uart_port *port)\r
1628 {\r
1629         dev_dbg(port->dev, "%s\n", __func__);\r
1630         return 0;\r
1631 }\r
1632 \r
1633 static void serial_rk_config_port(struct uart_port *port, int flags)\r
1634 {\r
1635         dev_dbg(port->dev, "%s\n", __func__);\r
1636         port->type = PORT_RK;\r
1637 }\r
1638 \r
1639 static int\r
1640 serial_rk_verify_port(struct uart_port *port, struct serial_struct *ser)\r
1641 {\r
1642         /* we don't want the core code to modify any port params */\r
1643         dev_dbg(port->dev, "%s\n", __func__);\r
1644         return -EINVAL;\r
1645 }\r
1646 \r
1647 static const char *\r
1648 serial_rk_type(struct uart_port *port)\r
1649 {\r
1650         struct uart_rk_port *up =\r
1651                 container_of(port, struct uart_rk_port, port);\r
1652 \r
1653         dev_dbg(port->dev, "%s: %s\n", __func__, up->name);\r
1654         return up->name;\r
1655 }\r
1656 \r
1657 static struct uart_ops serial_rk_pops = {\r
1658         .tx_empty       = serial_rk_tx_empty,\r
1659         .set_mctrl      = serial_rk_set_mctrl,\r
1660         .get_mctrl      = serial_rk_get_mctrl,\r
1661         .stop_tx        = serial_rk_stop_tx,\r
1662         .start_tx       = serial_rk_start_tx,\r
1663         .stop_rx        = serial_rk_stop_rx,\r
1664         .enable_ms      = serial_rk_enable_ms,\r
1665         .break_ctl      = serial_rk_break_ctl,\r
1666         .startup        = serial_rk_startup,\r
1667         .shutdown       = serial_rk_shutdown,\r
1668         .set_termios    = serial_rk_set_termios,\r
1669 #if 0\r
1670         .set_ldisc      = serial_rk_set_ldisc,\r
1671 #endif\r
1672         .pm             = serial_rk_pm,\r
1673         .type           = serial_rk_type,\r
1674         .release_port   = serial_rk_release_port,\r
1675         .request_port   = serial_rk_request_port,\r
1676         .config_port    = serial_rk_config_port,\r
1677         .verify_port    = serial_rk_verify_port,\r
1678 #ifdef CONFIG_CONSOLE_POLL\r
1679         .poll_get_char = serial_rk_get_poll_char,\r
1680         .poll_put_char = serial_rk_put_poll_char,\r
1681 #endif\r
1682 };\r
1683 \r
1684 #ifdef CONFIG_SERIAL_ROCKCHIP_CONSOLE\r
1685 \r
1686 static struct uart_rk_port *serial_rk_console_ports[UART_NR];\r
1687 \r
1688 static void serial_rk_console_putchar(struct uart_port *port, int ch)\r
1689 {\r
1690         struct uart_rk_port *up =\r
1691                 container_of(port, struct uart_rk_port, port);\r
1692 \r
1693         wait_for_xmitr(up, UART_LSR_THRE);\r
1694         serial_out(up, UART_TX, ch);\r
1695 }\r
1696 \r
1697 /*\r
1698  *      Print a string to the serial port trying not to disturb\r
1699  *      any possible real use of the port...\r
1700  *\r
1701  *      The console_lock must be held when we get here.\r
1702  */\r
1703 static void\r
1704 serial_rk_console_write(struct console *co, const char *s, unsigned int count)\r
1705 {\r
1706         struct uart_rk_port *up = serial_rk_console_ports[co->index];\r
1707         unsigned long flags;\r
1708         unsigned int ier;\r
1709         int locked = 1;\r
1710 \r
1711         touch_nmi_watchdog();\r
1712 \r
1713         local_irq_save(flags);\r
1714         if (up->port.sysrq) {\r
1715                 /* serial_rk_handle_port() already took the lock */\r
1716                 locked = 0;\r
1717         } else if (oops_in_progress) {\r
1718                 locked = spin_trylock(&up->port.lock);\r
1719         } else\r
1720                 spin_lock(&up->port.lock);\r
1721 \r
1722         /*\r
1723          *      First save the IER then disable the interrupts\r
1724          */\r
1725         ier = serial_in(up, UART_IER);\r
1726 \r
1727         serial_out(up, UART_IER, 0);\r
1728 \r
1729         uart_console_write(&up->port, s, count, serial_rk_console_putchar);\r
1730 \r
1731         /*\r
1732          *      Finally, wait for transmitter to become empty\r
1733          *      and restore the IER\r
1734          */\r
1735         wait_for_xmitr(up, UART_LSR_TEMT);\r
1736         serial_out(up, UART_IER, ier);\r
1737 \r
1738 #if 0\r
1739         /*\r
1740          *      The receive handling will happen properly because the\r
1741          *      receive ready bit will still be set; it is not cleared\r
1742          *      on read.  However, modem control will not, we must\r
1743          *      call it if we have saved something in the saved flags\r
1744          *      while processing with interrupts off.\r
1745          */\r
1746         if (up->msr_saved_flags)\r
1747                 check_modem_status(up);\r
1748 #endif\r
1749 \r
1750         if (locked)\r
1751                 spin_unlock(&up->port.lock);\r
1752         local_irq_restore(flags);\r
1753 }\r
1754 \r
1755 static int __init serial_rk_console_setup(struct console *co, char *options)\r
1756 {\r
1757         struct uart_rk_port *up;\r
1758         int baud = 115200;\r
1759         int bits = 8;\r
1760         int parity = 'n';\r
1761         int flow = 'n';\r
1762 \r
1763         if (unlikely(co->index >= UART_NR || co->index < 0))\r
1764                 return -ENODEV;\r
1765 \r
1766         if (serial_rk_console_ports[co->index] == NULL)\r
1767                 return -ENODEV;\r
1768         up = serial_rk_console_ports[co->index];\r
1769 \r
1770         if (options)\r
1771                 uart_parse_options(options, &baud, &parity, &bits, &flow);\r
1772 \r
1773         return uart_set_options(&up->port, co, baud, parity, bits, flow);\r
1774 }\r
1775 \r
1776 static struct console serial_rk_console = {\r
1777         .name           = "ttyS",\r
1778         .write          = serial_rk_console_write,\r
1779         .device         = uart_console_device,\r
1780         .setup          = serial_rk_console_setup,\r
1781         .flags          = CON_PRINTBUFFER | CON_ANYTIME,\r
1782         .index          = -1,\r
1783         .data           = &serial_rk_reg,\r
1784 };\r
1785 \r
1786 static void serial_rk_add_console_port(struct uart_rk_port *up)\r
1787 {\r
1788         serial_rk_console_ports[up->pdev->id] = up;\r
1789 }\r
1790 \r
1791 #define SERIAL_CONSOLE  &serial_rk_console\r
1792 #else\r
1793 #define SERIAL_CONSOLE  NULL\r
1794 \r
1795 static inline void serial_rk_add_console_port(struct uart_rk_port *up)\r
1796 {}\r
1797 \r
1798 #endif\r
1799 \r
1800 static struct uart_driver serial_rk_reg = {\r
1801         .owner                  = THIS_MODULE,\r
1802         .driver_name            = "rk_serial",\r
1803         .dev_name               = "ttyS",\r
1804         .major                  = TTY_MAJOR,\r
1805         .minor                  = 64,\r
1806         .cons                   = SERIAL_CONSOLE,\r
1807         .nr                     = UART_NR,\r
1808 };\r
1809 #if USE_WAKEUP\r
1810 static irqreturn_t serial_rk_wakeup_handler(int irq, void *dev) {\r
1811         struct uart_rk_port *up = dev;\r
1812         struct uart_wake_up *wakeup = up->wakeup;\r
1813         if(wakeup->enable == 1) {\r
1814                 iomux_set(wakeup->rx_mode);\r
1815                 wake_lock_timeout(&wakeup->wakelock, 3 * HZ);\r
1816         }    \r
1817         return 0;\r
1818 }\r
1819 \r
1820 static int serial_rk_setup_wakeup_irq(struct uart_rk_port *up)\r
1821 {\r
1822         int ret = 0;\r
1823         struct uart_wake_up *wakeup = up->wakeup;\r
1824 \r
1825         if(wakeup->enable == 1) {\r
1826                 memset(wakeup->wakelock_name, 0, 32);\r
1827                 sprintf(wakeup->wakelock_name, "serial.%d_wakelock", up->port.line);\r
1828                 wake_lock_init(&wakeup->wakelock, WAKE_LOCK_SUSPEND, wakeup->wakelock_name);\r
1829                 memset(wakeup->rx_pin_name, 0, 32);             \r
1830                 sprintf(wakeup->rx_pin_name, "UART%d_SIN", up->port.line);\r
1831                 wakeup->rx_pin = iomux_mode_to_gpio(wakeup->rx_mode);\r
1832                 ret = gpio_request(wakeup->rx_pin, wakeup->rx_pin_name);\r
1833                 if (ret) {\r
1834                         printk("request %s fail ! \n", wakeup->rx_pin_name);\r
1835                     return ret;\r
1836                 }\r
1837                 gpio_direction_input(wakeup->rx_pin);\r
1838                 wakeup->rx_irq = gpio_to_irq(wakeup->rx_pin);\r
1839                 memset(wakeup->rx_irq_name, 0, 32);\r
1840                 sprintf(wakeup->rx_irq_name, "serial.%d_wake_up_irq", up->port.line);\r
1841                 ret = request_irq(wakeup->rx_irq, serial_rk_wakeup_handler, IRQF_TRIGGER_FALLING, wakeup->rx_irq_name, up);\r
1842                 if(ret < 0) {\r
1843                         printk("%s request fail\n", wakeup->rx_irq_name);\r
1844                     return ret;\r
1845                 }\r
1846                 disable_irq_nosync(wakeup->rx_irq);\r
1847                 enable_irq_wake(wakeup->rx_irq);\r
1848                 iomux_set(wakeup->rx_mode);\r
1849         }\r
1850         return ret;\r
1851 }\r
1852 \r
1853 static int serial_rk_enable_wakeup_irq(struct uart_rk_port *up) {\r
1854         struct uart_wake_up *wakeup = up->wakeup;\r
1855         if(wakeup->enable == 1) {\r
1856                 iomux_set(wakeup->rx_mode & 0xfff0);\r
1857                 enable_irq(wakeup->rx_irq);\r
1858         }\r
1859     return 0;\r
1860 }\r
1861 \r
1862 static int serial_rk_disable_wakeup_irq(struct uart_rk_port *up) {\r
1863         struct uart_wake_up *wakeup = up->wakeup;\r
1864         if(wakeup->enable == 1) {\r
1865                 disable_irq_nosync(wakeup->rx_irq);\r
1866                 iomux_set(wakeup->rx_mode);\r
1867         }\r
1868     return 0;\r
1869 }\r
1870 \r
1871 static int serial_rk_remove_wakeup_irq(struct uart_rk_port *up) {\r
1872         struct uart_wake_up *wakeup = up->wakeup;\r
1873         if(wakeup->enable == 1) {\r
1874                 //disable_irq_nosync(wakeup->rx_irq);\r
1875                 free_irq(wakeup->rx_irq, NULL);\r
1876                 gpio_free(wakeup->rx_pin);\r
1877                 wake_lock_destroy(&wakeup->wakelock);\r
1878         }\r
1879     return 0;\r
1880 }\r
1881 #endif\r
1882 \r
1883 #ifdef CONFIG_OF\r
1884 static int of_rk_serial_parse_dt(struct device_node *np, struct of_rk_serial *rks) \r
1885 {\r
1886         unsigned int val = 0;\r
1887         const char *s = NULL;\r
1888         int ret, i = 0;\r
1889         rks->id = of_alias_get_id(np, "serial");\r
1890         if(!of_property_read_u32(np, "clock-frequency", &val))\r
1891                 rks->uartclk = val;\r
1892 \r
1893 #if USE_DMA\r
1894         rks->use_dma = 0;\r
1895         for(i = 0; i < 2; i++) {\r
1896                 ret = of_property_read_string_index(np, "dma-names", i, &s);\r
1897                 if(!ret) {\r
1898                         if(!strcmp(s, "tx"))\r
1899                                 rks->use_dma |= TX_DMA;\r
1900                          else if (!strcmp(s, "rx"))\r
1901                                 rks->use_dma |= RX_DMA;\r
1902                 }\r
1903         }\r
1904 #endif\r
1905         return 0;\r
1906 }\r
1907 #endif\r
1908 \r
1909 static int serial_rk_probe(struct platform_device *pdev)\r
1910 {\r
1911         struct uart_rk_port     *up;\r
1912         struct resource         *mem;\r
1913         int irq;\r
1914         int ret = -ENOSPC;\r
1915         struct of_rk_serial rks;\r
1916 \r
1917         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);\r
1918         if (!up)\r
1919                 return -ENOMEM;\r
1920 \r
1921         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1922         up->port.membase = devm_request_and_ioremap(&pdev->dev, mem);\r
1923         if (!up->port.membase)\r
1924                 return -ENOMEM;\r
1925 \r
1926         irq = platform_get_irq(pdev, 0);\r
1927         if (irq < 0) {\r
1928                 dev_err(&pdev->dev, "no irq resource?\n");\r
1929                 return irq;\r
1930         }\r
1931 \r
1932 #ifdef CONFIG_OF\r
1933         of_rk_serial_parse_dt(pdev->dev.of_node, &rks);\r
1934         pdev->id = rks.id;\r
1935 #endif\r
1936 \r
1937         sprintf(up->name, "rk29_serial.%d", pdev->id);\r
1938         up->pdev = pdev;\r
1939 #ifdef CONFIG_CLOCK_CTRL\r
1940         up->pclk = devm_clk_get(&pdev->dev, "pclk_uart");\r
1941         up->clk = devm_clk_get(&pdev->dev, "sclk_uart");\r
1942         if (unlikely(IS_ERR(up->clk)) || unlikely(IS_ERR(up->pclk))) {\r
1943                 dev_err(&pdev->dev, "get clock fail\n");\r
1944                 return -EINVAL;\r
1945         }\r
1946 #endif\r
1947         up->tx_loadsz = 30;\r
1948 #if USE_DMA\r
1949         up->dma = devm_kzalloc(&pdev->dev, sizeof(struct rk_uart_dma), GFP_KERNEL);\r
1950         if (!up->dma) {\r
1951                 dev_err(&pdev->dev, "unable to allocate mem\n");\r
1952                 return -ENOMEM;\r
1953         }\r
1954         up->dma->use_dma = rks.use_dma;\r
1955 #endif\r
1956 #if USE_WAKEUP\r
1957         up->wakeup = &rk29_uart_ports_wakeup[pdev->id];\r
1958 #endif\r
1959         up->port.dev = &pdev->dev;\r
1960         up->port.type = PORT_RK;\r
1961         up->port.irq = irq;\r
1962         up->port.iotype = UPIO_MEM;\r
1963         \r
1964         up->port.regshift = 2;\r
1965         //fifo size default is 32, but it will be updated later when start_up\r
1966         up->port.fifosize = 32;\r
1967         up->port.ops = &serial_rk_pops;\r
1968         up->port.line = pdev->id;\r
1969         up->port.iobase = mem->start;\r
1970         up->port.mapbase = mem->start;\r
1971         up->port.irqflags = IRQF_DISABLED;\r
1972 #if defined(CONFIG_CLOCK_CTRL)\r
1973         up->port.uartclk = clk_get_rate(up->clk);\r
1974 #elif defined(CONFIG_OF)\r
1975         up->port.uartclk = rks.uartclk;\r
1976 #else\r
1977         up->port.uartclk = 24000000;\r
1978 #endif\r
1979 \r
1980 #if USE_DMA\r
1981         /* set dma config */\r
1982         pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);\r
1983         if(up->dma->use_dma & RX_DMA) {\r
1984                 //timer\r
1985                 up->dma->use_timer = USE_TIMER;\r
1986                 up->dma->rx_timer.function = serial_rk_report_dma_rx;\r
1987                 up->dma->rx_timer.data = (unsigned long)up;\r
1988                 up->dma->rx_timeout = 10;\r
1989                 up->dma->rx_timer.expires = jiffies + msecs_to_jiffies(up->dma->rx_timeout);\r
1990                 init_timer(&up->dma->rx_timer);\r
1991 \r
1992                 //rx buffer\r
1993                 up->dma->rb_size = DMA_SERIAL_BUFFER_SIZE;\r
1994                 up->dma->rx_buffer = dmam_alloc_coherent(up->port.dev, up->dma->rb_size,\r
1995                                 &up->dma->rx_phy_addr, DMA_MEMORY_MAP);\r
1996                 up->dma->rb_tail = 0;\r
1997                 up->dma->rx_dma_inited = 0;\r
1998                 up->dma->rx_dma_used = 0;\r
1999 \r
2000                 if(!up->dma->rx_buffer){\r
2001                         dev_info(up->port.dev, "dmam_alloc_coherent dma_rx_buffer fail\n");\r
2002                 }\r
2003                 else {\r
2004                         dev_info(up->port.dev, "dma_rx_buffer 0x%08x\n", (unsigned) up->dma->rx_buffer);\r
2005                         dev_info(up->port.dev, "dma_rx_phy 0x%08x\n", (unsigned)up->dma->rx_phy_addr);\r
2006                 }\r
2007 \r
2008                 // work queue\r
2009                 //INIT_WORK(&up->uart_work, serial_rk_report_revdata_workfunc);\r
2010                 //INIT_WORK(&up->uart_work_rx, serial_rk_start_dma_rx);\r
2011                 //up->uart_wq = create_singlethread_workqueue("uart_workqueue");\r
2012                 spin_lock_init(&(up->dma->rx_lock));\r
2013                 serial_rk_init_dma_rx(up);\r
2014         }\r
2015 \r
2016         if(up->dma->use_dma & TX_DMA){\r
2017                 //tx buffer\r
2018                 up->dma->tb_size = UART_XMIT_SIZE;\r
2019                 up->dma->tx_buffer = dmam_alloc_coherent(up->port.dev, up->dma->tb_size,\r
2020                                 &up->dma->tx_phy_addr, DMA_MEMORY_MAP);\r
2021                 if(!up->dma->tx_buffer){\r
2022                         dev_info(up->port.dev, "dmam_alloc_coherent dma_tx_buffer fail\n");\r
2023                 }\r
2024                 else{\r
2025                         dev_info(up->port.dev, "dma_tx_buffer 0x%08x\n", (unsigned) up->dma->tx_buffer);\r
2026                         dev_info(up->port.dev, "dma_tx_phy 0x%08x\n", (unsigned) up->dma->tx_phy_addr);\r
2027                 }\r
2028                 spin_lock_init(&(up->dma->tx_lock));\r
2029                 serial_rk_init_dma_tx(up);\r
2030         }\r
2031 \r
2032         \r
2033 #endif\r
2034         serial_rk_add_console_port(up);\r
2035         ret = uart_add_one_port(&serial_rk_reg, &up->port);\r
2036         if (ret != 0)\r
2037                 return ret;\r
2038         platform_set_drvdata(pdev, up);\r
2039         dev_info(&pdev->dev, "membase 0x%08x\n", (unsigned) up->port.membase);\r
2040 #if USE_WAKEUP\r
2041         serial_rk_setup_wakeup_irq(up); \r
2042 #endif\r
2043         return 0;\r
2044 }\r
2045 \r
2046 static int serial_rk_remove(struct platform_device *pdev)\r
2047 {\r
2048         struct uart_rk_port *up = platform_get_drvdata(pdev);\r
2049 \r
2050         platform_set_drvdata(pdev, NULL);\r
2051         if (up) {\r
2052 #if USE_DMA\r
2053                 serial_rk_release_dma_tx(up);\r
2054                 serial_rk_release_dma_rx(up);\r
2055 #endif\r
2056 #if USE_WAKEUP\r
2057         serial_rk_remove_wakeup_irq(up);\r
2058 #endif\r
2059                 //destroy_workqueue(up->uart_wq);\r
2060                 uart_remove_one_port(&serial_rk_reg, &up->port);\r
2061                 up->port.membase = NULL;\r
2062         }\r
2063 \r
2064         return 0;\r
2065 }\r
2066 \r
2067 static int serial_rk_suspend(struct platform_device *dev, pm_message_t state)\r
2068 {\r
2069         struct uart_rk_port *up = platform_get_drvdata(dev);\r
2070 \r
2071         if (up && up->port.line != DBG_PORT && POWER_MANEGEMENT){\r
2072                 uart_suspend_port(&serial_rk_reg, &up->port);\r
2073         }\r
2074         if(up->port.line == DBG_PORT && POWER_MANEGEMENT){\r
2075                 serial_rk_pm(&up->port, 1, 0);\r
2076         }\r
2077 #if USE_WAKEUP\r
2078     serial_rk_enable_wakeup_irq(up);\r
2079 #endif\r
2080         return 0;\r
2081 }\r
2082 \r
2083 static int serial_rk_resume(struct platform_device *dev)\r
2084 {\r
2085         struct uart_rk_port *up = platform_get_drvdata(dev);\r
2086 #if USE_WAKEUP\r
2087     serial_rk_disable_wakeup_irq(up);\r
2088 #endif\r
2089         if (up && up->port.line != DBG_PORT && POWER_MANEGEMENT){\r
2090                 uart_resume_port(&serial_rk_reg, &up->port);\r
2091         }\r
2092         if(up->port.line == DBG_PORT && POWER_MANEGEMENT){\r
2093                 serial_rk_pm(&up->port, 0, 1);\r
2094         }\r
2095         return 0;\r
2096 }\r
2097 #ifdef CONFIG_OF\r
2098 static const struct of_device_id of_rk_serial_match[] = {\r
2099         { .compatible = "rockchip,serial" },\r
2100         { /* Sentinel */ }\r
2101 };\r
2102 #endif\r
2103 static struct platform_driver serial_rk_driver = {\r
2104         .probe          = serial_rk_probe,\r
2105         .remove         = serial_rk_remove,\r
2106         .suspend        = serial_rk_suspend,\r
2107         .resume         = serial_rk_resume,\r
2108         .driver         = {\r
2109                 .name   = "serial",\r
2110 #ifdef CONFIG_OF\r
2111                 .of_match_table = of_rk_serial_match,\r
2112 #endif\r
2113                 .owner  = THIS_MODULE,\r
2114         },\r
2115 };\r
2116 \r
2117 static int __init serial_rk_init(void)\r
2118 {\r
2119         int ret;\r
2120         //hhb@rock-chips.com\r
2121         printk("%s\n", VERSION_AND_TIME);\r
2122         ret = uart_register_driver(&serial_rk_reg);\r
2123         if (ret)\r
2124                 return ret;\r
2125         ret = platform_driver_register(&serial_rk_driver);\r
2126         if (ret != 0)\r
2127                 uart_unregister_driver(&serial_rk_reg);\r
2128         return ret;\r
2129 }\r
2130 \r
2131 static void __exit serial_rk_exit(void)\r
2132 {\r
2133         platform_driver_unregister(&serial_rk_driver);\r
2134         uart_unregister_driver(&serial_rk_reg);\r
2135 }\r
2136 \r
2137 module_init(serial_rk_init);\r
2138 module_exit(serial_rk_exit);\r
2139 \r
2140 MODULE_LICENSE("GPL");\r
2141 MODULE_DESCRIPTION("RK UART driver");