drivers/tty/serial/rk_serial.c

   1 /*\r
   2  * Driver for RK-UART controller.\r
   3  * Based on drivers/tty/serial/8250.c\r
   4  *\r
   5  * Copyright (C) 2011 Rochchip.\r
   6  *\r
   7  * This program is free software; you can redistribute it and/or modify\r
   8  * it under the terms of the GNU General Public License as published by\r
   9  * the Free Software Foundation; either version 2 of the License, or\r
  10 \r
  11  * (at your option) any later version.\r
  12  *\r
  13  * Author: hhb@rock-chips.com\r
  14  * Date: 2011.06.18\r
  15  */\r
  16 \r
  17 #ifndef CONFIG_SERIAL_RK_CONSOLE\r
  18 #if defined(CONFIG_SERIAL_RK29_CONSOLE)\r
  19 #define CONFIG_SERIAL_RK_CONSOLE\r
  20 #endif\r
  21 #endif\r
  22 \r
  23 #if defined(CONFIG_SERIAL_RK_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)\r
  24 #define SUPPORT_SYSRQ\r
  25 #endif\r
  26 \r
  27 //#define DEBUG\r
  28 #include <linux/module.h>\r
  29 #include <linux/ioport.h>\r
  30 #include <linux/init.h>\r
  31 #include <linux/console.h>\r
  32 #include <linux/sysrq.h>\r
  33 #include <linux/delay.h>\r
  34 #include <linux/platform_device.h>\r
  35 #include <linux/tty.h>\r
  36 #include <linux/ratelimit.h>\r
  37 #include <linux/tty_flip.h>\r
  38 #include <linux/serial_reg.h>\r
  39 #include <linux/serial_core.h>\r
  40 #include <linux/serial.h>\r
  41 #include <linux/serial_8250.h>\r
  42 #include <linux/nmi.h>\r
  43 #include <linux/mutex.h>\r
  44 #include <linux/slab.h>\r
  45 #include <linux/clk.h>\r
  46 #include <linux/timer.h>\r
  47 #include <linux/workqueue.h>\r
  48 #include <linux/dma-mapping.h>\r
  49 \r
  50 #include <asm/io.h>\r
  51 #include <asm/irq.h>\r
  52 \r
  53 \r
  54 #define PORT_RK         90\r
  55 #define UART_USR        0x1F    /* UART Status Register */\r
  56 #define UART_USR_BUSY (1)\r
  57 #define UART_IER_PTIME  0x80    /* Programmable THRE Interrupt Mode Enable */\r
  58 #define UART_LSR_RFE    0x80    /* receive fifo error */\r
  59 #define UART_SRR                0x22    /* software reset register */\r
  60 #define UART_RESET              0x01\r
  61 #define RX_TIMEOUT              (3000*10)  //uint ms\r
  62 \r
  63 #define BOTH_EMPTY      (UART_LSR_TEMT | UART_LSR_THRE)\r
  64 \r
  65 #define UART_NR 4   //uart port number\r
  66 #define POWER_MANEGEMENT 1\r
  67 \r
  68 /* configurate whether the port transmit-receive by DMA */\r
  69 #define OPEN_DMA      1\r
  70 #define CLOSE_DMA     0\r
  71 \r
  72 #ifdef CONFIG_UART0_DMA_RK29\r
  73 #define UART0_USE_DMA OPEN_DMA\r
  74 #else\r
  75 #define UART0_USE_DMA CLOSE_DMA\r
  76 #endif\r
  77 \r
  78 #ifdef CONFIG_UART2_DMA_RK29\r
  79 #define UART2_USE_DMA OPEN_DMA\r
  80 #else\r
  81 #define UART2_USE_DMA CLOSE_DMA\r
  82 #endif\r
  83 \r
  84 #ifdef CONFIG_UART3_DMA_RK29\r
  85 #define UART3_USE_DMA OPEN_DMA\r
  86 #else\r
  87 #define UART3_USE_DMA CLOSE_DMA\r
  88 #endif\r
  89 \r
  90 #define UART1_USE_DMA CLOSE_DMA\r
  91 \r
  92 #define USE_DMA (UART0_USE_DMA | UART1_USE_DMA | UART2_USE_DMA | UART3_USE_DMA)\r
  93 #if USE_DMA\r
  94 #ifdef CONFIG_ARCH_RK29\r
  95 #include <mach/dma-pl330.h>\r
  96 #else\r
  97 #include <plat/dma-pl330.h>\r
  98 #endif\r
  99 #endif\r
 100 \r
 101 #define DMA_TX_TRRIGE_LEVEL 30\r
 102 \r
 103 #define USE_TIMER 1           // use timer for dma transport\r
 104 #define THRE_MODE 0X00   //0yhh\r
 105 \r
 106 static struct uart_driver serial_rk_reg;\r
 107 \r
 108 /*\r
 109  * Debugging.\r
 110  */\r
 111 #define DBG_PORT 1   //DBG_PORT which uart is used to print log message\r
 112 \r
 113 #ifdef CONFIG_SERIAL_CORE_CONSOLE\r
 114 #define uart_console(port)      ((port)->cons && (port)->cons->index == (port)->line)\r
 115 #else\r
 116 #define uart_console(port)      (0)\r
 117 #endif\r
 118 \r
 119 #define DEBUG 0\r
 120 \r
 121 extern void printascii(const char *);\r
 122 static void dbg(const char *fmt, ...)\r
 123 {\r
 124         va_list va;\r
 125         char buff[256];\r
 126 \r
 127         va_start(va, fmt);\r
 128         vsprintf(buff, fmt, va);\r
 129         va_end(va);\r
 130 \r
 131         printascii(buff);\r
 132 }\r
 133 \r
 134 #if DEBUG\r
 135 #define DEBUG_INTR(fmt...)      if (!uart_console(&up->port)) dbg(fmt)\r
 136 #else\r
 137 #define DEBUG_INTR(fmt...)      do { } while (0)\r
 138 #endif\r
 139 \r
 140 \r
 141 #if USE_DMA\r
 142 /* added by hhb@rock-chips.com for uart dma transfer */\r
 143 \r
 144 struct rk29_uart_dma_t {\r
 145         u32 use_dma;            //1:used\r
 146         u32 rx_dma_start;\r
 147         enum dma_ch rx_dmach;\r
 148         enum dma_ch tx_dmach;\r
 149         u32 tx_dma_inited;\r
 150         u32 rx_dma_inited;\r
 151         spinlock_t              tx_lock;\r
 152         spinlock_t              rx_lock;\r
 153         char * rx_buffer;\r
 154         char * tx_buffer;\r
 155         dma_addr_t rx_phy_addr;\r
 156         dma_addr_t tx_phy_addr;\r
 157         u32 rx_buffer_size;\r
 158         u32 tx_buffer_size;\r
 159 \r
 160         u32 rb_cur_pos;\r
 161         u32 rb_pre_pos;\r
 162         u32 rx_size;\r
 163         char use_timer;\r
 164         char tx_dma_used;\r
 165         /* timer to poll activity on rx dma */\r
 166         struct timer_list       rx_timer;\r
 167         int                     rx_timeout;\r
 168 \r
 169 };\r
 170 #endif\r
 171 \r
 172 struct uart_rk_port {\r
 173         struct uart_port        port;\r
 174         struct platform_device  *pdev;\r
 175         struct clk              *clk;\r
 176         struct clk              *pclk;\r
 177         unsigned int            tx_loadsz;      /* transmit fifo load size */\r
 178         unsigned char           ier;\r
 179         unsigned char           lcr;\r
 180         unsigned char           mcr;\r
 181         unsigned char           iir;\r
 182         unsigned char           fcr;\r
 183         /*\r
 184          * Some bits in registers are cleared on a read, so they must\r
 185          * be saved whenever the register is read but the bits will not\r
 186          * be immediately processed.\r
 187          */\r
 188 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS\r
 189         unsigned char           lsr_saved_flags;\r
 190 #if 0\r
 191 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA\r
 192         unsigned char           msr_saved_flags;\r
 193 #endif\r
 194 \r
 195         char                    name[12];\r
 196         char                    fifo[32];\r
 197         char                    fifo_size;\r
 198         unsigned long           port_activity;\r
 199         struct work_struct uart_work;\r
 200         struct work_struct uart_work_rx;\r
 201         struct workqueue_struct *uart_wq;\r
 202 #if USE_DMA\r
 203         struct rk29_uart_dma_t *prk29_uart_dma_t;\r
 204 #endif\r
 205 };\r
 206 \r
 207 #if USE_DMA\r
 208 static void serial_rk_release_dma_tx(struct uart_port *port);\r
 209 static int serial_rk_start_tx_dma(struct uart_port *port);\r
 210 static void serial_rk_rx_timeout(unsigned long uart);\r
 211 static void serial_rk_release_dma_rx(struct uart_port *port);\r
 212 static int serial_rk_start_rx_dma(struct uart_port *port);\r
 213 #else\r
 214 static inline int serial_rk_start_tx_dma(struct uart_port *port) { return 0; }\r
 215 #endif\r
 216 static int serial_rk_startup(struct uart_port *port);\r
 217 static inline unsigned int serial_in(struct uart_rk_port *up, int offset)\r
 218 {\r
 219         offset = offset << 2;\r
 220         return __raw_readb(up->port.membase + offset);\r
 221 }\r
 222 \r
 223 /* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */\r
 224 static inline void dwapb_save_out_value(struct uart_rk_port *up, int offset,\r
 225                                         unsigned char value)\r
 226 {\r
 227         if (offset == UART_LCR)\r
 228                 up->lcr = value;\r
 229 }\r
 230 \r
 231 /* Read the IER to ensure any interrupt is cleared before returning from ISR. */\r
 232 static inline void dwapb_check_clear_ier(struct uart_rk_port *up, int offset)\r
 233 {\r
 234         if (offset == UART_TX || offset == UART_IER)\r
 235                 serial_in(up, UART_IER);\r
 236 }\r
 237 \r
 238 static inline void serial_out(struct uart_rk_port *up, int offset, unsigned char value)\r
 239 {\r
 240         dwapb_save_out_value(up, offset, value);\r
 241         __raw_writeb(value, up->port.membase + (offset << 2));\r
 242         if (offset != UART_TX)\r
 243                 dsb();\r
 244         dwapb_check_clear_ier(up, offset);\r
 245 }\r
 246 \r
 247 /* Uart divisor latch read */\r
 248 static inline int serial_dl_read(struct uart_rk_port *up)\r
 249 {\r
 250         return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;\r
 251 }\r
 252 \r
 253 /* Uart divisor latch write */\r
 254 static int serial_dl_write(struct uart_rk_port *up, unsigned int value)\r
 255 {\r
 256         unsigned int tmout = 100;\r
 257         if(up->port.line != DBG_PORT)\r
 258         {\r
 259                 while(!(serial_in(up, UART_LCR) & UART_LCR_DLAB)){\r
 260                         if (--tmout == 0){\r
 261                                 dbg("set serial.%d baudrate fail with DLAB not set\n", up->port.line);\r
 262                                 return -1;\r
 263                         }\r
 264                 }\r
 265 \r
 266                 tmout = 15000;\r
 267                 while(serial_in(up, UART_USR) & UART_USR_BUSY){\r
 268                         if (--tmout == 0){\r
 269                                 dbg("set serial.%d baudrate timeout\n", up->port.line);\r
 270                                 return -1;\r
 271                         }\r
 272                 }\r
 273         }\r
 274 \r
 275         serial_out(up, UART_DLL, value & 0xff);\r
 276         serial_out(up, UART_DLM, value >> 8 & 0xff);\r
 277 \r
 278         return 0;\r
 279 \r
 280 }\r
 281 \r
 282 static int serial_lcr_write(struct uart_rk_port *up, unsigned char value)\r
 283 {\r
 284         unsigned int tmout = 15000;\r
 285 \r
 286         if(up->port.line != DBG_PORT)\r
 287         {\r
 288                 while(serial_in(up, UART_USR) & UART_USR_BUSY){\r
 289 \r
 290                         if (--tmout == 0){\r
 291                                 dbg("set serial.%d lc r = 0x%02x timeout\n", up->port.line, value);\r
 292                                 return -1;\r
 293                         }\r
 294                         udelay(1);\r
 295                 }\r
 296         }\r
 297 \r
 298         serial_out(up, UART_LCR, value);\r
 299 \r
 300         return 0;\r
 301 }\r
 302 \r
 303 static inline void serial_rk_enable_ier_thri(struct uart_rk_port *up)\r
 304 {\r
 305         if (!(up->ier & UART_IER_THRI)) {\r
 306                 up->ier |= UART_IER_THRI;\r
 307                 serial_out(up, UART_IER, up->ier);\r
 308         }\r
 309 }\r
 310 \r
 311 \r
 312 static inline void serial_rk_disable_ier_thri(struct uart_rk_port *up)\r
 313 {\r
 314         if (up->ier & UART_IER_THRI) {\r
 315                 up->ier &= ~UART_IER_THRI;\r
 316                 serial_out(up, UART_IER, up->ier);\r
 317         }\r
 318 }\r
 319 #if 0\r
 320 static int rk29_uart_dump_register(struct uart_rk_port *up){\r
 321 \r
 322         unsigned int reg_value = 0;\r
 323 \r
 324         reg_value = serial_in(up, UART_IER);\r
 325         dbg("UART_IER = 0x%0x\n", reg_value);\r
 326         reg_value = serial_in(up, UART_IIR);\r
 327         dbg("UART_IIR = 0x%0x\n", reg_value);\r
 328     reg_value = serial_in(up, UART_LSR);\r
 329     dbg("UART_LSR = 0x%0x\n", reg_value);\r
 330     reg_value = serial_in(up, UART_MSR);\r
 331     dbg("UART_MSR = 0x%0x\n", reg_value);\r
 332     reg_value = serial_in(up, UART_MCR);\r
 333     dbg("UART_MCR = 0x%0x\n", reg_value);\r
 334     reg_value = serial_in(up, 0x21);\r
 335     dbg("UART_RFL = 0x%0x\n", reg_value);\r
 336     reg_value = serial_in(up, UART_LCR);\r
 337     dbg("UART_LCR = 0x%0x\n", reg_value);\r
 338         return 0;\r
 339 \r
 340 }\r
 341 #endif\r
 342 \r
 343 /*\r
 344  * FIFO support.\r
 345  */\r
 346 static void serial_rk_clear_fifos(struct uart_rk_port *up)\r
 347 {\r
 348         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);\r
 349         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |\r
 350                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);\r
 351         serial_out(up, UART_FCR, 0);\r
 352 }\r
 353 \r
 354 static inline void __stop_tx(struct uart_rk_port *p)\r
 355 {\r
 356         if (p->ier & UART_IER_THRI) {\r
 357                 p->ier &= ~UART_IER_THRI;\r
 358                 serial_out(p, UART_IER, p->ier);\r
 359         }\r
 360 }\r
 361 \r
 362 static void serial_rk_stop_tx(struct uart_port *port)\r
 363 {\r
 364         struct uart_rk_port *up =\r
 365                 container_of(port, struct uart_rk_port, port);\r
 366 #if USE_DMA\r
 367         struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
 368 \r
 369         if(OPEN_DMA == prk29_uart_dma_t->use_dma){\r
 370                 serial_rk_release_dma_tx(port);\r
 371         }\r
 372 #endif\r
 373         __stop_tx(up);\r
 374 }\r
 375 \r
 376 \r
 377 static void serial_rk_start_tx(struct uart_port *port)\r
 378 {\r
 379         struct uart_rk_port *up =\r
 380                 container_of(port, struct uart_rk_port, port);\r
 381 \r
 382 \r
 383         if(0 == serial_rk_start_tx_dma(port)){\r
 384                 serial_rk_enable_ier_thri(up);\r
 385         }\r
 386 \r
 387 }\r
 388 \r
 389 \r
 390 static void serial_rk_stop_rx(struct uart_port *port)\r
 391 {\r
 392         struct uart_rk_port *up =\r
 393                 container_of(port, struct uart_rk_port, port);\r
 394 #if USE_DMA\r
 395         struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
 396 \r
 397         if(OPEN_DMA == prk29_uart_dma_t->use_dma){\r
 398                 serial_rk_release_dma_rx(port);\r
 399         }\r
 400 #endif\r
 401         up->ier &= ~UART_IER_RLSI;\r
 402         up->port.read_status_mask &= ~UART_LSR_DR;\r
 403         serial_out(up, UART_IER, up->ier);\r
 404 }\r
 405 \r
 406 \r
 407 static void serial_rk_enable_ms(struct uart_port *port)\r
 408 {\r
 409         /* no MSR capabilities */\r
 410 #if 0\r
 411         struct uart_rk_port *up =\r
 412                 container_of(port, struct uart_rk_port, port);\r
 413 \r
 414         dev_dbg(port->dev, "%s\n", __func__);\r
 415         up->ier |= UART_IER_MSI;\r
 416         serial_out(up, UART_IER, up->ier);\r
 417 #endif\r
 418 }\r
 419 \r
 420 \r
 421 #if USE_DMA\r
 422 /*\r
 423  * Start transmitting by dma.\r
 424  */\r
 425 #define DMA_SERIAL_BUFFER_SIZE     UART_XMIT_SIZE\r
 426 \r
 427 /* added by hhb@rock-chips.com  for uart dma transfer*/\r
 428 static struct rk29_uart_dma_t rk29_uart_ports_dma_t[] = {\r
 429                 {UART0_USE_DMA, 0, DMACH_UART0_RX, DMACH_UART0_TX},\r
 430                 {UART1_USE_DMA, 0, DMACH_UART1_RX, DMACH_UART1_TX},\r
 431                 {UART2_USE_DMA, 0, DMACH_UART2_RX, DMACH_UART2_TX},\r
 432                 {UART3_USE_DMA, 0, DMACH_UART3_RX, DMACH_UART3_TX},\r
 433 };\r
 434 \r
 435 \r
 436 /* DMAC PL330 add by hhb@rock-chips.com */\r
 437 static struct rk29_dma_client rk29_uart_dma_client = {\r
 438         .name = "rk29xx-uart-dma",\r
 439 };\r
 440 \r
 441 /*TX*/\r
 442 \r
 443 static void serial_rk_release_dma_tx(struct uart_port *port)\r
 444 {\r
 445         struct uart_rk_port *up =\r
 446                         container_of(port, struct uart_rk_port, port);\r
 447         struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
 448         if(!port){\r
 449                 return;\r
 450         }\r
 451         if(prk29_uart_dma_t && prk29_uart_dma_t->tx_dma_inited) {\r
 452                 rk29_dma_free(prk29_uart_dma_t->tx_dmach, &rk29_uart_dma_client);\r
 453                 prk29_uart_dma_t->tx_dma_inited = 0;\r
 454         }\r
 455 }\r
 456 \r
 457 /*this function will be called every time after rk29_dma_enqueue() be invoked*/\r
 458 static void serial_rk_dma_txcb(void *buf, int size, enum rk29_dma_buffresult result) {\r
 459         struct uart_port *port = buf;\r
 460         struct uart_rk_port *up = container_of(port, struct uart_rk_port, port);\r
 461         struct circ_buf *xmit = &port->state->xmit;\r
 462 \r
 463         if(result != RK29_RES_OK){\r
 464                 return;\r
 465         }\r
 466 \r
 467         port->icount.tx += size;\r
 468         xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);\r
 469 \r
 470         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)\r
 471                 uart_write_wakeup(&up->port);\r
 472         spin_lock(&(up->prk29_uart_dma_t->tx_lock));\r
 473         up->prk29_uart_dma_t->tx_dma_used = 0;\r
 474         spin_unlock(&(up->prk29_uart_dma_t->tx_lock));\r
 475         if (!uart_circ_empty(xmit)) {\r
 476                 serial_rk_start_tx_dma(port);\r
 477         }\r
 478 \r
 479         up->port_activity = jiffies;\r
 480 //      dev_info(up->port.dev, "s:%d\n", size);\r
 481 }\r
 482 \r
 483 static int serial_rk_init_dma_tx(struct uart_port *port) {\r
 484 \r
 485         struct uart_rk_port *up =\r
 486                                 container_of(port, struct uart_rk_port, port);\r
 487         struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
 488         if(!port || !prk29_uart_dma_t){\r
 489                 dev_info(up->port.dev, "serial_rk_init_dma_tx fail\n");\r
 490                 return -1;\r
 491         }\r
 492 \r
 493         if(prk29_uart_dma_t->tx_dma_inited) {\r
 494                 return 0;\r
 495         }\r
 496 \r
 497         if (rk29_dma_request(prk29_uart_dma_t->tx_dmach, &rk29_uart_dma_client, NULL) == -EBUSY) {\r
 498                 dev_info(up->port.dev, "rk29_dma_request tx fail\n");\r
 499                 return -1;\r
 500         }\r
 501 \r
 502         if (rk29_dma_set_buffdone_fn(prk29_uart_dma_t->tx_dmach, serial_rk_dma_txcb)) {\r
 503                 dev_info(up->port.dev, "rk29_dma_set_buffdone_fn tx fail\n");\r
 504                 return -1;\r
 505         }\r
 506         if (rk29_dma_devconfig(prk29_uart_dma_t->tx_dmach, RK29_DMASRC_MEM, (unsigned long)(port->iobase + UART_TX))) {\r
 507                 dev_info(up->port.dev, "rk29_dma_devconfig tx fail\n");\r
 508                 return -1;\r
 509         }\r
 510         if (rk29_dma_config(prk29_uart_dma_t->tx_dmach, 1, 1)) {\r
 511                 dev_info(up->port.dev, "rk29_dma_config tx fail\n");\r
 512                 return -1;\r
 513         }\r
 514 \r
 515         prk29_uart_dma_t->tx_dma_inited = 1;\r
 516         dev_info(up->port.dev, "serial_rk_init_dma_tx sucess\n");\r
 517         return 0;\r
 518 \r
 519 }\r
 520 \r
 521 static int serial_rk_start_tx_dma(struct uart_port *port)\r
 522 {\r
 523 \r
 524         struct circ_buf *xmit = &port->state->xmit;\r
 525         struct uart_rk_port *up = container_of(port, struct uart_rk_port, port);\r
 526         struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
 527 \r
 528         if(0 == prk29_uart_dma_t->use_dma){\r
 529                 return CLOSE_DMA;\r
 530         }\r
 531 \r
 532         if(-1 == serial_rk_init_dma_tx(port)){\r
 533                 goto err_out;\r
 534         }\r
 535 \r
 536         if (1 == prk29_uart_dma_t->tx_dma_used){\r
 537                 return 1;\r
 538         }\r
 539         if(!uart_circ_empty(xmit)){\r
 540                 if (rk29_dma_enqueue(prk29_uart_dma_t->tx_dmach, port,\r
 541                                 prk29_uart_dma_t->tx_phy_addr + xmit->tail,\r
 542                                 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE))) {\r
 543                         goto err_out;\r
 544                 }\r
 545         }\r
 546         rk29_dma_ctrl(prk29_uart_dma_t->tx_dmach, RK29_DMAOP_START);\r
 547         spin_lock(&(prk29_uart_dma_t->tx_lock));\r
 548         up->prk29_uart_dma_t->tx_dma_used = 1;\r
 549         spin_unlock(&(prk29_uart_dma_t->tx_lock));\r
 550 \r
 551         return 1;\r
 552 err_out:\r
 553         dev_info(up->port.dev, "-serial_rk_start_tx_dma-error-\n");\r
 554         return -1;\r
 555 \r
 556 }\r
 557 \r
 558 \r
 559 \r
 560 /*RX*/\r
 561 static void serial_rk_dma_rxcb(void *buf, int size, enum rk29_dma_buffresult result) {\r
 562 \r
 563 \r
 564 }\r
 565 \r
 566 static void serial_rk_release_dma_rx(struct uart_port *port)\r
 567 {\r
 568         struct uart_rk_port *up =\r
 569                                 container_of(port, struct uart_rk_port, port);\r
 570         struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
 571         if(!port){\r
 572                 return;\r
 573         }\r
 574         if(prk29_uart_dma_t && prk29_uart_dma_t->rx_dma_inited) {\r
 575                 del_timer(&prk29_uart_dma_t->rx_timer);\r
 576                 rk29_dma_free(prk29_uart_dma_t->rx_dmach, &rk29_uart_dma_client);\r
 577                 prk29_uart_dma_t->rb_pre_pos = 0;\r
 578                 prk29_uart_dma_t->rx_dma_inited = 0;\r
 579                 prk29_uart_dma_t->rx_dma_start = 0;\r
 580         }\r
 581 }\r
 582 \r
 583 \r
 584 static int serial_rk_init_dma_rx(struct uart_port *port) {\r
 585 \r
 586         struct uart_rk_port *up =\r
 587                                 container_of(port, struct uart_rk_port, port);\r
 588         struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
 589         if(!port || !prk29_uart_dma_t){\r
 590                 dev_info(up->port.dev, "serial_rk_init_dma_rx: port fail\n");\r
 591                 return -1;\r
 592         }\r
 593         if(prk29_uart_dma_t->rx_dma_inited) {\r
 594                 return 0;\r
 595         }\r
 596 \r
 597         if (rk29_dma_request(prk29_uart_dma_t->rx_dmach, &rk29_uart_dma_client, NULL) == -EBUSY) {\r
 598                 dev_info(up->port.dev, "rk29_dma_request fail rx \n");\r
 599                 return -1;\r
 600         }\r
 601 \r
 602         if (rk29_dma_set_buffdone_fn(prk29_uart_dma_t->rx_dmach, serial_rk_dma_rxcb)) {\r
 603                 dev_info(up->port.dev, "rk29_dma_set_buffdone_fn rx fail\n");\r
 604                 return -1;\r
 605         }\r
 606         if (rk29_dma_devconfig(prk29_uart_dma_t->rx_dmach, RK29_DMASRC_HW, (unsigned long)(port->iobase + UART_RX))) {\r
 607                 dev_info(up->port.dev, "rk29_dma_devconfig rx fail\n");\r
 608                 return -1;\r
 609         }\r
 610 \r
 611         if (rk29_dma_config(prk29_uart_dma_t->rx_dmach, 1, 1)) {\r
 612                 dev_info(up->port.dev, "rk29_dma_config rx fail\n");\r
 613                 return -1;\r
 614         }\r
 615 \r
 616         rk29_dma_setflags(prk29_uart_dma_t->rx_dmach, RK29_DMAF_CIRCULAR);\r
 617 \r
 618         prk29_uart_dma_t->rx_dma_inited = 1;\r
 619         dev_info(up->port.dev, "serial_rk_init_dma_rx sucess\n");\r
 620         return 0;\r
 621 \r
 622 }\r
 623 \r
 624 static int serial_rk_start_rx_dma(struct uart_port *port)\r
 625 {\r
 626         struct uart_rk_port *up =\r
 627                                 container_of(port, struct uart_rk_port, port);\r
 628         struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
 629         if(0 == prk29_uart_dma_t->use_dma){\r
 630                 return 0;\r
 631         }\r
 632 \r
 633         if(prk29_uart_dma_t->rx_dma_start == 1){\r
 634                 return 0;\r
 635         }\r
 636 \r
 637         if(-1 == serial_rk_init_dma_rx(port)){\r
 638                 dev_info(up->port.dev, "*******serial_rk_init_dma_rx*******error*******\n");\r
 639                 return -1;\r
 640         }\r
 641 \r
 642         if (rk29_dma_enqueue(prk29_uart_dma_t->rx_dmach, (void *)up, prk29_uart_dma_t->rx_phy_addr,\r
 643                         prk29_uart_dma_t->rx_buffer_size/2)) {\r
 644                 dev_info(up->port.dev, "*******rk29_dma_enqueue fail*****\n");\r
 645                 return -1;\r
 646         }\r
 647 \r
 648         if (rk29_dma_enqueue(prk29_uart_dma_t->rx_dmach, (void *)up,\r
 649                         prk29_uart_dma_t->rx_phy_addr+prk29_uart_dma_t->rx_buffer_size/2,\r
 650                 prk29_uart_dma_t->rx_buffer_size/2)) {\r
 651                 dev_info(up->port.dev, "*******rk29_dma_enqueue fail*****\n");\r
 652                 return -1;\r
 653         }\r
 654 \r
 655         rk29_dma_ctrl(prk29_uart_dma_t->rx_dmach, RK29_DMAOP_START);\r
 656         prk29_uart_dma_t->rx_dma_start = 1;\r
 657         if(prk29_uart_dma_t->use_timer == 1){\r
 658                 mod_timer(&prk29_uart_dma_t->rx_timer, jiffies +\r
 659                                 msecs_to_jiffies(prk29_uart_dma_t->rx_timeout));\r
 660         }\r
 661         up->port_activity = jiffies;\r
 662         return 1;\r
 663 }\r
 664 \r
 665 static void serial_rk_update_rb_addr(struct uart_rk_port *up){\r
 666         dma_addr_t current_pos = 0;\r
 667         dma_addr_t rx_current_pos = 0;\r
 668         struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
 669         spin_lock(&(up->prk29_uart_dma_t->rx_lock));\r
 670         rk29_dma_getposition(prk29_uart_dma_t->rx_dmach, &current_pos, &rx_current_pos);\r
 671 \r
 672         prk29_uart_dma_t->rb_cur_pos = (rx_current_pos - prk29_uart_dma_t->rx_phy_addr);\r
 673         prk29_uart_dma_t->rx_size = CIRC_CNT(prk29_uart_dma_t->rb_cur_pos,\r
 674                         prk29_uart_dma_t->rb_pre_pos, prk29_uart_dma_t->rx_buffer_size);\r
 675 \r
 676         spin_unlock(&(up->prk29_uart_dma_t->rx_lock));\r
 677 }\r
 678 \r
 679 static void serial_rk_report_dma_rx(unsigned long uart)\r
 680 {\r
 681         struct uart_rk_port *up = (struct uart_rk_port *)uart;\r
 682         struct rk29_uart_dma_t *prk29_uart_dma_t = up->prk29_uart_dma_t;\r
 683         if(prk29_uart_dma_t->use_timer == 1){\r
 684                 serial_rk_update_rb_addr(up);\r
 685         }\r
 686         if(prk29_uart_dma_t->rx_size > 0) {\r
 687                 spin_lock(&(up->prk29_uart_dma_t->rx_lock));\r
 688 \r
 689                 if(prk29_uart_dma_t->rb_cur_pos > prk29_uart_dma_t->rb_pre_pos){\r
 690                         tty_insert_flip_string(up->port.state->port.tty, prk29_uart_dma_t->rx_buffer\r
 691                                         + prk29_uart_dma_t->rb_pre_pos, prk29_uart_dma_t->rx_size);\r
 692                         tty_flip_buffer_push(up->port.state->port.tty);\r
 693                 }\r
 694                 else if(prk29_uart_dma_t->rb_cur_pos < prk29_uart_dma_t->rb_pre_pos){\r
 695 \r
 696                         tty_insert_flip_string(up->port.state->port.tty, prk29_uart_dma_t->rx_buffer\r
 697                                         + prk29_uart_dma_t->rb_pre_pos, CIRC_CNT_TO_END(prk29_uart_dma_t->rb_cur_pos,\r
 698                                         prk29_uart_dma_t->rb_pre_pos, prk29_uart_dma_t->rx_buffer_size));\r
 699                         tty_flip_buffer_push(up->port.state->port.tty);\r
 700 \r
 701                         if(prk29_uart_dma_t->rb_cur_pos != 0){\r
 702                                 tty_insert_flip_string(up->port.state->port.tty, prk29_uart_dma_t->rx_buffer,\r
 703                                                 prk29_uart_dma_t->rb_cur_pos);\r
 704                                 tty_flip_buffer_push(up->port.state->port.tty);\r
 705                         }\r
 706                 }\r
 707 \r
 708                 prk29_uart_dma_t->rb_pre_pos = (prk29_uart_dma_t->rb_pre_pos + prk29_uart_dma_t->rx_size)\r
 709                                 & (prk29_uart_dma_t->rx_buffer_size - 1);\r
 710                 up->port.icount.rx += prk29_uart_dma_t->rx_size;\r
 711                 spin_unlock(&(up->prk29_uart_dma_t->rx_lock));\r
 712                 prk29_uart_dma_t->rx_timeout = 7;\r
 713                 up->port_activity = jiffies;\r
 714         }\r
 715 \r
 716 \r
 717 #if 1\r
 718         if (jiffies_to_msecs(jiffies - up->port_activity) < RX_TIMEOUT) {\r
 719                 if(prk29_uart_dma_t->use_timer == 1){\r
 720                         mod_timer(&prk29_uart_dma_t->rx_timer, jiffies + msecs_to_jiffies(prk29_uart_dma_t->rx_timeout));\r
 721                 }\r
 722         } else {\r
 723 \r
 724 #if 1\r
 725 \r
 726 \r
 727                 prk29_uart_dma_t->rx_timeout = 20;\r
 728                 mod_timer(&prk29_uart_dma_t->rx_timer, jiffies + msecs_to_jiffies(prk29_uart_dma_t->rx_timeout));\r
 729 #else\r
 730 //              serial_out(up, 0x2a, 0x01);\r
 731                 serial_rk_release_dma_rx(&up->port);\r
 732                 serial_out(up, 0x2a, 0x01);\r
 733                 up->ier |= (UART_IER_RDI | UART_IER_RLSI);\r
 734                 serial_out(up, UART_IER, up->ier);\r
 735 //              serial_out(up, 0x22, 0x01);\r
 736                 dev_info(up->port.dev, "*****enable recv int*****\n");\r
 737 \r
 738                 //serial_rk_start_rx_dma(&up->port);\r
 739 #endif\r
 740         }\r
 741 \r
 742 \r
 743 #else\r
 744         if(prk29_uart_dma_t->use_timer == 1){\r
 745                 mod_timer(&prk29_uart_dma_t->rx_timer, jiffies + msecs_to_jiffies(prk29_uart_dma_t->rx_timeout));\r
 746         }\r
 747 #endif\r
 748 \r
 749 }\r
 750 \r
 751 static void serial_rk_rx_timeout(unsigned long uart)\r
 752 {\r
 753         struct uart_rk_port *up = (struct uart_rk_port *)uart;\r
 754 \r
 755         //serial_rk_report_dma_rx(up);\r
 756         queue_work(up->uart_wq, &up->uart_work);\r
 757 }\r
 758 \r
 759 static void serial_rk_report_revdata_workfunc(struct work_struct *work)\r
 760 {\r
 761         struct uart_rk_port *up =\r
 762                                 container_of(work, struct uart_rk_port, uart_work);\r
 763         serial_rk_report_dma_rx((unsigned long)up);\r
 764         spin_lock(&(up->prk29_uart_dma_t->rx_lock));\r
 765 \r
 766         if(up->prk29_uart_dma_t->use_timer == 1){\r
 767 \r
 768         }else{\r
 769                 tty_insert_flip_string(up->port.state->port.tty, up->fifo, up->fifo_size);\r
 770                 tty_flip_buffer_push(up->port.state->port.tty);\r
 771                 up->port.icount.rx += up->fifo_size;\r
 772         }\r
 773 \r
 774         spin_unlock(&(up->prk29_uart_dma_t->rx_lock));\r
 775 \r
 776 }\r
 777 \r
 778 \r
 779 static void serial_rk_start_dma_rx(struct work_struct *work)\r
 780 {\r
 781         struct uart_rk_port *up =\r
 782                                         container_of(work, struct uart_rk_port, uart_work_rx);\r
 783         serial_rk_start_rx_dma(&up->port);\r
 784 }\r
 785 #endif /* USE_DMA */\r
 786 \r
 787 \r
 788 \r
 789 static void\r
 790 receive_chars(struct uart_rk_port *up, unsigned int *status)\r
 791 {\r
 792         struct tty_struct *tty = up->port.state->port.tty;\r
 793         unsigned char ch, lsr = *status;\r
 794         int max_count = 256;\r
 795         char flag;\r
 796 \r
 797         do {\r
 798                 if (likely(lsr & UART_LSR_DR)){\r
 799                         ch = serial_in(up, UART_RX);\r
 800                 }\r
 801                 else\r
 802                         /*\r
 803                          * Intel 82571 has a Serial Over Lan device that will\r
 804                          * set UART_LSR_BI without setting UART_LSR_DR when\r
 805                          * it receives a break. To avoid reading from the\r
 806                          * receive buffer without UART_LSR_DR bit set, we\r
 807                          * just force the read character to be 0\r
 808                          */\r
 809                         ch = 0;\r
 810 \r
 811                 flag = TTY_NORMAL;\r
 812                 up->port.icount.rx++;\r
 813 \r
 814                 lsr |= up->lsr_saved_flags;\r
 815                 up->lsr_saved_flags = 0;\r
 816 \r
 817                 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {\r
 818                         /*\r
 819                          * For statistics only\r
 820                          */\r
 821                         if (lsr & UART_LSR_BI) {\r
 822                                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);\r
 823                                 up->port.icount.brk++;\r
 824                                 /*\r
 825                                  * We do the SysRQ and SAK checking\r
 826                                  * here because otherwise the break\r
 827                                  * may get masked by ignore_status_mask\r
 828                                  * or read_status_mask.\r
 829                                  */\r
 830                                 if (uart_handle_break(&up->port))\r
 831                                         goto ignore_char;\r
 832                         } else if (lsr & UART_LSR_PE)\r
 833                                 up->port.icount.parity++;\r
 834                         else if (lsr & UART_LSR_FE)\r
 835                                 up->port.icount.frame++;\r
 836                         if (lsr & UART_LSR_OE)\r
 837                                 up->port.icount.overrun++;\r
 838 \r
 839 \r
 840                         /*\r
 841                          * Mask off conditions which should be ignored.\r
 842                          */\r
 843                         lsr &= up->port.read_status_mask;\r
 844 \r
 845                         if (lsr & UART_LSR_BI) {\r
 846                                 DEBUG_INTR("handling break....");\r
 847                                 flag = TTY_BREAK;\r
 848                         } else if (lsr & UART_LSR_PE)\r
 849                                 flag = TTY_PARITY;\r
 850                         else if (lsr & UART_LSR_FE)\r
 851                                 flag = TTY_FRAME;\r
 852                 }\r
 853                 if (uart_handle_sysrq_char(&up->port, ch))\r
 854                         goto ignore_char;\r
 855 \r
 856                 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);\r
 857 \r
 858 ignore_char:\r
 859                 lsr = serial_in(up, UART_LSR);\r
 860         } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));\r
 861         spin_unlock(&up->port.lock);\r
 862         tty_flip_buffer_push(tty);\r
 863         spin_lock(&up->port.lock);\r
 864         *status = lsr;\r
 865 }\r
 866 \r
 867 static void transmit_chars(struct uart_rk_port *up)\r
 868 {\r
 869         struct circ_buf *xmit = &up->port.state->xmit;\r
 870         int count;\r
 871 \r
 872         if (up->port.x_char) {\r
 873                 serial_out(up, UART_TX, up->port.x_char);\r
 874                 up->port.icount.tx++;\r
 875                 up->port.x_char = 0;\r
 876                 return;\r
 877         }\r
 878         if (uart_tx_stopped(&up->port)) {\r
 879                 __stop_tx(up);\r
 880                 return;\r
 881         }\r
 882         if (uart_circ_empty(xmit)) {\r
 883                 __stop_tx(up);\r
 884                 return;\r
 885         }\r
 886 \r
 887         count = up->tx_loadsz;\r
 888         do {\r
 889                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);\r
 890                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);\r
 891                 up->port.icount.tx++;\r
 892                 if (uart_circ_empty(xmit))\r
 893                         break;\r
 894         } while (--count > 0);\r
 895 \r
 896         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)\r
 897                 uart_write_wakeup(&up->port);\r
 898 \r
 899         DEBUG_INTR("THRE...");\r
 900 \r
 901         if (uart_circ_empty(xmit))\r
 902                 __stop_tx(up);\r
 903 }\r
 904 \r
 905 static unsigned int check_modem_status(struct uart_rk_port *up)\r
 906 {\r
 907         unsigned int status = serial_in(up, UART_MSR);\r
 908 \r
 909 #if 0\r
 910         status |= up->msr_saved_flags;\r
 911         up->msr_saved_flags = 0;\r
 912         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&\r
 913             up->port.state != NULL) {\r
 914                 if (status & UART_MSR_TERI)\r
 915                         up->port.icount.rng++;\r
 916                 if (status & UART_MSR_DDSR)\r
 917                         up->port.icount.dsr++;\r
 918                 if (status & UART_MSR_DDCD)\r
 919                         uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);\r
 920                 if (status & UART_MSR_DCTS)\r
 921                         uart_handle_cts_change(&up->port, status & UART_MSR_CTS);\r
 922 \r
 923                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);\r
 924         }\r
 925 #endif\r
 926 \r
 927         return status;\r
 928 }\r
 929 \r
 930 \r
 931 /*\r
 932  * This handles the interrupt from one port.\r
 933  */\r
 934 static void serial_rk_handle_port(struct uart_rk_port *up)\r
 935 {\r
 936         unsigned int status;\r
 937         unsigned long flags;\r
 938         spin_lock_irqsave(&up->port.lock, flags);\r
 939 \r
 940         /* reading UART_LSR can automatically clears PE FE OE bits, except receive fifo error bit*/\r
 941         status = serial_in(up, UART_LSR);\r
 942 \r
 943         DEBUG_INTR("status = %x...", status);\r
 944 #if USE_DMA\r
 945         /* DMA mode enable */\r
 946         if(up->prk29_uart_dma_t->use_dma == 1) {\r
 947 \r
 948                 if(up->iir & UART_IIR_RLSI){\r
 949                         if (status & (UART_LSR_DR | UART_LSR_BI)) {\r
 950                                 up->port_activity = jiffies;\r
 951                                 up->ier &= ~UART_IER_RLSI;\r
 952                                 up->ier &= ~UART_IER_RDI;\r
 953                                 serial_out(up, UART_IER, up->ier);\r
 954                                 //receive_chars(up, &status);\r
 955                                 //mod_timer(&up->prk29_uart_dma_t->rx_timer, jiffies +\r
 956                                 //msecs_to_jiffies(up->prk29_uart_dma_t->rx_timeout));\r
 957                                 if(serial_rk_start_rx_dma(&up->port) == -1){\r
 958                                         receive_chars(up, &status);\r
 959                                 }\r
 960                         }\r
 961                 }\r
 962 \r
 963         } else\r
 964 #endif\r
 965         {       //dma mode disable\r
 966 \r
 967                 /*\r
 968                  * when uart receive a serial of data which doesn't have stop bit and so on, that causes frame error,and\r
 969                  * set UART_LSR_RFE to one,what is worse,we couldn't read the data in the receive fifo. So if\r
 970                  * wo don't clear this bit and reset the receive fifo, the received data available interrupt would\r
 971                  * occur continuously.  added by hhb@rock-chips.com 2011-08-05\r
 972                  */\r
 973 \r
 974                 if (status & UART_LSR_RFE) {\r
 975                         \r
 976                         if(up->port.line != DBG_PORT){\r
 977                                 status = serial_in(up, UART_LSR);\r
 978                                 dev_info(up->port.dev, "error:lsr=0x%x\n", status);\r
 979                         }\r
 980                         \r
 981                         \r
 982                 //      rk29_uart_dump_register(up);\r
 983                 }\r
 984 \r
 985                 if (status & (UART_LSR_DR | UART_LSR_BI)) {\r
 986                         receive_chars(up, &status);\r
 987                 }\r
 988                 check_modem_status(up);\r
 989                 if (status & UART_LSR_THRE) {\r
 990                         transmit_chars(up);\r
 991                 }\r
 992         }\r
 993 \r
 994         spin_unlock_irqrestore(&up->port.lock, flags);\r
 995 }\r
 996 \r
 997 /*\r
 998  * This is the serial driver's interrupt routine.\r
 999  */\r
1000 \r
1001 static irqreturn_t serial_rk_interrupt(int irq, void *dev_id)\r
1002 {\r
1003         struct uart_rk_port *up = dev_id;\r
1004         int handled = 0;\r
1005         unsigned int iir;\r
1006 \r
1007         iir = serial_in(up, UART_IIR);\r
1008 \r
1009         DEBUG_INTR("%s(%d) iir = 0x%02x\n", __func__, irq, iir);\r
1010 \r
1011         up->iir = iir;\r
1012 \r
1013         if (!(iir & UART_IIR_NO_INT)) {\r
1014                 serial_rk_handle_port(up);\r
1015                 handled = 1;\r
1016         } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {\r
1017 \r
1018                 /* The DesignWare APB UART has an Busy Detect (0x07)\r
1019                  * interrupt meaning an LCR write attempt occured while the\r
1020                  * UART was busy. The interrupt must be cleared by reading\r
1021                  * the UART status register (USR) and the LCR re-written. */\r
1022 \r
1023                 if(!(serial_in(up, UART_USR) & UART_USR_BUSY)){\r
1024                         serial_out(up, UART_LCR, up->lcr);\r
1025                 }\r
1026                 handled = 1;\r
1027                 dbg("the serial.%d is busy\n", up->port.line);\r
1028         }\r
1029         DEBUG_INTR("end(%d).\n", handled);\r
1030 \r
1031         return IRQ_RETVAL(handled);\r
1032 }\r
1033 \r
1034 static unsigned int serial_rk_tx_empty(struct uart_port *port)\r
1035 {\r
1036         struct uart_rk_port *up =\r
1037                 container_of(port, struct uart_rk_port, port);\r
1038         unsigned long flags;\r
1039         unsigned int lsr;\r
1040 \r
1041         dev_dbg(port->dev, "%s\n", __func__);\r
1042         spin_lock_irqsave(&up->port.lock, flags);\r
1043         lsr = serial_in(up, UART_LSR);\r
1044         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;\r
1045         spin_unlock_irqrestore(&up->port.lock, flags);\r
1046 \r
1047         return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;\r
1048 }\r
1049 \r
1050 static unsigned int serial_rk_get_mctrl(struct uart_port *port)\r
1051 {\r
1052         struct uart_rk_port *up =\r
1053                 container_of(port, struct uart_rk_port, port);\r
1054         unsigned int status;\r
1055         unsigned int ret;\r
1056 \r
1057         status = check_modem_status(up);\r
1058 \r
1059         ret = 0;\r
1060         if (status & UART_MSR_DCD)\r
1061                 ret |= TIOCM_CAR;\r
1062         if (status & UART_MSR_RI)\r
1063                 ret |= TIOCM_RNG;\r
1064         if (status & UART_MSR_DSR)\r
1065                 ret |= TIOCM_DSR;\r
1066         if (status & UART_MSR_CTS)\r
1067                 ret |= TIOCM_CTS;\r
1068         dev_dbg(port->dev, "%s 0x%08x\n", __func__, ret);\r
1069         return ret;\r
1070 }\r
1071 \r
1072 static void serial_rk_set_mctrl(struct uart_port *port, unsigned int mctrl)\r
1073 {\r
1074         struct uart_rk_port *up =\r
1075                 container_of(port, struct uart_rk_port, port);\r
1076         unsigned char mcr = 0;\r
1077 \r
1078         dev_dbg(port->dev, "+%s\n", __func__);\r
1079         if (mctrl & TIOCM_RTS)\r
1080                 mcr |= UART_MCR_RTS;\r
1081         if (mctrl & TIOCM_DTR)\r
1082                 mcr |= UART_MCR_DTR;\r
1083         if (mctrl & TIOCM_OUT1)\r
1084                 mcr |= UART_MCR_OUT1;\r
1085         if (mctrl & TIOCM_OUT2)\r
1086                 mcr |= UART_MCR_OUT2;\r
1087         if (mctrl & TIOCM_LOOP)\r
1088                 mcr |= UART_MCR_LOOP;\r
1089 \r
1090         mcr |= up->mcr;\r
1091 \r
1092         serial_out(up, UART_MCR, mcr);\r
1093         dev_dbg(port->dev, "-serial.%d %s mcr: 0x%02x\n", port->line, __func__, mcr);\r
1094 }\r
1095 \r
1096 static void serial_rk_break_ctl(struct uart_port *port, int break_state)\r
1097 {\r
1098         struct uart_rk_port *up =\r
1099                 container_of(port, struct uart_rk_port, port);\r
1100         unsigned long flags;\r
1101 \r
1102         dev_dbg(port->dev, "+%s\n", __func__);\r
1103         spin_lock_irqsave(&up->port.lock, flags);\r
1104         if (break_state == -1)\r
1105                 up->lcr |= UART_LCR_SBC;\r
1106         else\r
1107                 up->lcr &= ~UART_LCR_SBC;\r
1108         serial_lcr_write(up, up->lcr);\r
1109         spin_unlock_irqrestore(&up->port.lock, flags);\r
1110         dev_dbg(port->dev, "-%s lcr: 0x%02x\n", __func__, up->lcr);\r
1111 }\r
1112 \r
1113 #if defined(CONFIG_SERIAL_RK_CONSOLE) || defined(CONFIG_CONSOLE_POLL)\r
1114 /*\r
1115  *      Wait for transmitter & holding register to empty\r
1116  */\r
1117 static void wait_for_xmitr(struct uart_rk_port *up, int bits)\r
1118 {\r
1119         unsigned int status, tmout = 10000;\r
1120 \r
1121         /* Wait up to 10ms for the character(s) to be sent. */\r
1122         for (;;) {\r
1123                 status = serial_in(up, UART_LSR);\r
1124 \r
1125                 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;\r
1126 \r
1127                 if ((status & bits) == bits)\r
1128                         break;\r
1129                 if (--tmout == 0)\r
1130                         break;\r
1131                 udelay(1);\r
1132         }\r
1133 }\r
1134 #endif\r
1135 \r
1136 #ifdef CONFIG_CONSOLE_POLL\r
1137 /*\r
1138  * Console polling routines for writing and reading from the uart while\r
1139  * in an interrupt or debug context.\r
1140  */\r
1141 \r
1142 static int serial_rk_get_poll_char(struct uart_port *port)\r
1143 {\r
1144         struct uart_rk_port *up =\r
1145                 container_of(port, struct uart_rk_port, port);\r
1146         unsigned char lsr = serial_in(up, UART_LSR);\r
1147 \r
1148         while (!(lsr & UART_LSR_DR))\r
1149                 lsr = serial_in(up, UART_LSR);\r
1150 \r
1151         return serial_in(up, UART_RX);\r
1152 }\r
1153 \r
1154 static void serial_rk_put_poll_char(struct uart_port *port,\r
1155                          unsigned char c)\r
1156 {\r
1157         unsigned int ier;\r
1158         struct uart_rk_port *up =\r
1159                 container_of(port, struct uart_rk_port, port);\r
1160 \r
1161         /*\r
1162          *      First save the IER then disable the interrupts\r
1163          */\r
1164         ier = serial_in(up, UART_IER);\r
1165         serial_out(up, UART_IER, 0);\r
1166 \r
1167         wait_for_xmitr(up, BOTH_EMPTY);\r
1168         /*\r
1169          *      Send the character out.\r
1170          *      If a LF, also do CR...\r
1171          */\r
1172         serial_out(up, UART_TX, c);\r
1173         if (c == 10) {\r
1174                 wait_for_xmitr(up, BOTH_EMPTY);\r
1175                 serial_out(up, UART_TX, 13);\r
1176         }\r
1177 \r
1178         /*\r
1179          *      Finally, wait for transmitter to become empty\r
1180          *      and restore the IER\r
1181          */\r
1182         wait_for_xmitr(up, BOTH_EMPTY);\r
1183         serial_out(up, UART_IER, ier);\r
1184 }\r
1185 \r
1186 #endif /* CONFIG_CONSOLE_POLL */\r
1187 \r
1188 static int serial_rk_startup(struct uart_port *port)\r
1189 {\r
1190         struct uart_rk_port *up =\r
1191                 container_of(port, struct uart_rk_port, port);\r
1192         unsigned long flags;\r
1193         int retval;\r
1194 \r
1195 \r
1196         dev_dbg(port->dev, "%s\n", __func__);\r
1197 \r
1198         /*\r
1199          * Allocate the IRQ\r
1200          */\r
1201         retval = request_irq(up->port.irq, serial_rk_interrupt, up->port.irqflags,\r
1202                                 up->name, up);\r
1203         if (retval)\r
1204                 return retval;\r
1205 \r
1206         up->mcr = 0;\r
1207 \r
1208         clk_enable(up->pclk);\r
1209         clk_enable(up->clk);  // enable the config uart clock\r
1210 \r
1211         /*\r
1212          * Clear the FIFO buffers and disable them.\r
1213          * (they will be reenabled in set_termios())\r
1214          */\r
1215         serial_rk_clear_fifos(up);\r
1216 \r
1217         /*\r
1218          * Clear the interrupt registers.\r
1219          */\r
1220         (void) serial_in(up, UART_LSR);\r
1221         (void) serial_in(up, UART_RX);\r
1222         (void) serial_in(up, UART_IIR);\r
1223         (void) serial_in(up, UART_MSR);\r
1224         (void) serial_in(up, UART_USR);\r
1225 \r
1226         /*\r
1227          * Now, initialize the UART\r
1228          */\r
1229         serial_lcr_write(up, UART_LCR_WLEN8 | UART_LCR_EPAR);\r
1230 \r
1231         spin_lock_irqsave(&up->port.lock, flags);\r
1232 \r
1233         /*\r
1234          * Most PC uarts need OUT2 raised to enable interrupts.\r
1235          */\r
1236 //      up->port.mctrl |= TIOCM_OUT2;\r
1237 \r
1238         serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1239 \r
1240         spin_unlock_irqrestore(&up->port.lock, flags);\r
1241 \r
1242         /*\r
1243          * Clear the interrupt registers again for luck, and clear the\r
1244          * saved flags to avoid getting false values from polling\r
1245          * routines or the previous session.\r
1246          */\r
1247         (void) serial_in(up, UART_LSR);\r
1248         (void) serial_in(up, UART_RX);\r
1249         (void) serial_in(up, UART_IIR);\r
1250         (void) serial_in(up, UART_MSR);\r
1251         (void) serial_in(up, UART_USR);\r
1252         up->lsr_saved_flags = 0;\r
1253 #if 0\r
1254         up->msr_saved_flags = 0;\r
1255 #endif\r
1256 \r
1257 #if USE_DMA\r
1258         if (1 == up->prk29_uart_dma_t->use_dma) {\r
1259 \r
1260                 if(up->port.state->xmit.buf != up->prk29_uart_dma_t->tx_buffer){\r
1261                         free_page((unsigned long)up->port.state->xmit.buf);\r
1262                         up->port.state->xmit.buf = up->prk29_uart_dma_t->tx_buffer;\r
1263                 }\r
1264 \r
1265 #if 1\r
1266                 serial_rk_start_rx_dma(&up->port);\r
1267 #else\r
1268                 up->ier |= UART_IER_RDI;\r
1269                 up->ier |= UART_IER_RLSI;\r
1270                 serial_out(up, UART_IER, up->ier);\r
1271 #endif\r
1272                 up->port_activity = jiffies;\r
1273 \r
1274         } else\r
1275 #endif /* USE_DMA */\r
1276         {\r
1277                 up->ier = 0;\r
1278                 serial_out(up, UART_IER, up->ier);\r
1279         }\r
1280 \r
1281         /*\r
1282          * Finally, enable interrupts.  Note: Modem status interrupts\r
1283          * are set via set_termios(), which will be occurring imminently\r
1284          * anyway, so we don't enable them here.\r
1285          */\r
1286 \r
1287         return 0;\r
1288 }\r
1289 \r
1290 \r
1291 static void serial_rk_shutdown(struct uart_port *port)\r
1292 {\r
1293         struct uart_rk_port *up =\r
1294                 container_of(port, struct uart_rk_port, port);\r
1295         unsigned long flags;\r
1296 \r
1297         dev_dbg(port->dev, "%s\n", __func__);\r
1298         /*\r
1299          * Disable interrupts from this port\r
1300          */\r
1301         up->ier = 0;\r
1302         serial_out(up, UART_IER, 0);\r
1303 \r
1304         spin_lock_irqsave(&up->port.lock, flags);\r
1305 //      up->port.mctrl &= ~TIOCM_OUT2;\r
1306         serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1307         spin_unlock_irqrestore(&up->port.lock, flags);\r
1308 \r
1309         /*\r
1310          * Disable break condition and FIFOs\r
1311          */\r
1312         serial_lcr_write(up, serial_in(up, UART_LCR) & ~UART_LCR_SBC);\r
1313         serial_rk_clear_fifos(up);\r
1314 \r
1315         /*\r
1316          * Read data port to reset things, and then free the irq\r
1317          */\r
1318         (void) serial_in(up, UART_RX);\r
1319 \r
1320         free_irq(up->port.irq, up);\r
1321         clk_disable(up->clk);\r
1322         clk_disable(up->pclk);\r
1323 }\r
1324 \r
1325 static void\r
1326 serial_rk_set_termios(struct uart_port *port, struct ktermios *termios,\r
1327                       struct ktermios *old)\r
1328 {\r
1329         struct uart_rk_port *up =\r
1330                 container_of(port, struct uart_rk_port, port);\r
1331         unsigned char cval, fcr = 0;\r
1332         unsigned long flags;\r
1333         unsigned int baud, quot;\r
1334         int timeout = 1000000;\r
1335         dev_dbg(port->dev, "+%s\n", __func__);\r
1336 \r
1337         switch (termios->c_cflag & CSIZE) {\r
1338         case CS5:\r
1339                 cval = UART_LCR_WLEN5;\r
1340                 break;\r
1341         case CS6:\r
1342                 cval = UART_LCR_WLEN6;\r
1343                 break;\r
1344         case CS7:\r
1345                 cval = UART_LCR_WLEN7;\r
1346                 break;\r
1347         case CS8:\r
1348         default:\r
1349                 cval = UART_LCR_WLEN8;\r
1350                 break;\r
1351         }\r
1352 \r
1353         if (termios->c_cflag & CSTOPB){\r
1354                 cval |= UART_LCR_STOP;\r
1355         }\r
1356         if (termios->c_cflag & PARENB){\r
1357                 cval |= UART_LCR_PARITY;\r
1358         }\r
1359         if (!(termios->c_cflag & PARODD)){\r
1360                 cval |= UART_LCR_EPAR;\r
1361         }\r
1362 #ifdef CMSPAR\r
1363         if (termios->c_cflag & CMSPAR)\r
1364                 cval |= UART_LCR_SPAR;\r
1365 #endif\r
1366 \r
1367 \r
1368         /*\r
1369          * Ask the core to calculate the divisor for us.\r
1370          */\r
1371         baud = uart_get_baud_rate(port, termios, old,\r
1372                                   port->uartclk / 16 / 0xffff,\r
1373                                   port->uartclk / 16);\r
1374 \r
1375         quot = uart_get_divisor(port, baud);\r
1376 \r
1377         dev_info(up->port.dev, "baud:%d\n", baud);\r
1378 //      dev_info(up->port.dev, "quot:%d\n", quot);\r
1379 \r
1380         /*\r
1381          * To wait long enough to avoid writting lcr when the uart is busy\r
1382          * because of data communication, so that we can set lcr and baud rate\r
1383          * successfully. added by hhb@rock-chips.com\r
1384          */\r
1385 \r
1386         while(serial_in(up, UART_USR) & UART_USR_BUSY){\r
1387                 if(--timeout == 0){\r
1388                         if(port->line != DBG_PORT){\r
1389                                 serial_out(up, UART_SRR, UART_RESET);\r
1390                         }\r
1391                         dbg("rk_serial_set_termios uart.%d timeout,irq=%d,ret=0x%x  AND uart is reseted\n",\r
1392                                         port->line, port->irq, serial_in(up, UART_USR));\r
1393                         break;\r
1394                 }\r
1395                 cpu_relax();\r
1396         }\r
1397 \r
1398 \r
1399         printk("serial.%d timeout:%d\n", up->port.line,timeout);\r
1400 \r
1401 \r
1402         if (baud < 2400){\r
1403                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;\r
1404         }\r
1405         else{\r
1406 #if USE_DMA\r
1407                 //added by hhb@rock-chips.com\r
1408                 if(up->prk29_uart_dma_t->use_timer == 1){\r
1409                         fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_01;\r
1410                 } else\r
1411 #endif\r
1412                 {\r
1413                         fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | UART_FCR_T_TRIG_01;\r
1414                 }\r
1415         }\r
1416 \r
1417         /*\r
1418          * MCR-based auto flow control.  When AFE is enabled, RTS will be\r
1419          * deasserted when the receive FIFO contains more characters than\r
1420          * the trigger, or the MCR RTS bit is cleared.  In the case where\r
1421          * the remote UART is not using CTS auto flow control, we must\r
1422          * have sufficient FIFO entries for the latency of the remote\r
1423          * UART to respond.  IOW, at least 32 bytes of FIFO.\r
1424          */\r
1425         up->mcr &= ~UART_MCR_AFE;\r
1426         if (termios->c_cflag & CRTSCTS){\r
1427                 up->mcr |= UART_MCR_AFE;\r
1428         }\r
1429 \r
1430         /*\r
1431          * Ok, we're now changing the port state.  Do it with\r
1432          * interrupts disabled.\r
1433          */\r
1434         spin_lock_irqsave(&up->port.lock, flags);\r
1435 \r
1436         /*\r
1437          * Update the per-port timeout.\r
1438          */\r
1439         uart_update_timeout(port, termios->c_cflag, baud);\r
1440 \r
1441         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;\r
1442         if (termios->c_iflag & INPCK)\r
1443                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;\r
1444         if (termios->c_iflag & (BRKINT | PARMRK))\r
1445                 up->port.read_status_mask |= UART_LSR_BI;\r
1446 \r
1447         /*\r
1448          * Characteres to ignore\r
1449          */\r
1450         up->port.ignore_status_mask = 0;\r
1451         if (termios->c_iflag & IGNPAR)\r
1452                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;\r
1453         if (termios->c_iflag & IGNBRK) {\r
1454                 up->port.ignore_status_mask |= UART_LSR_BI;\r
1455                 /*\r
1456                  * If we're ignoring parity and break indicators,\r
1457                  * ignore overruns too (for real raw support).\r
1458                  */\r
1459                 if (termios->c_iflag & IGNPAR)\r
1460                         up->port.ignore_status_mask |= UART_LSR_OE;\r
1461         }\r
1462 \r
1463         /*\r
1464          * ignore all characters if CREAD is not set\r
1465          */\r
1466         if ((termios->c_cflag & CREAD) == 0)\r
1467                 up->port.ignore_status_mask |= UART_LSR_DR;\r
1468 \r
1469         /*\r
1470          * CTS flow control flag and modem status interrupts\r
1471          */\r
1472         up->ier &= ~UART_IER_MSI;\r
1473 #if 0\r
1474         if (UART_ENABLE_MS(&up->port, termios->c_cflag))\r
1475                 up->ier |= UART_IER_MSI;\r
1476 #endif\r
1477 \r
1478         up->lcr = cval;                         /* Save LCR */\r
1479         /* set DLAB */\r
1480         if(serial_lcr_write(up, cval | UART_LCR_DLAB)){\r
1481                 dbg("serial.%d set DLAB fail\n", up->port.line);\r
1482                 serial_out(up, UART_SRR, UART_RESET);\r
1483                 goto fail;\r
1484         }\r
1485 \r
1486         /* set uart baud rate */\r
1487         if(serial_dl_write(up, quot)){\r
1488                 dbg("serial.%d set dll fail\n", up->port.line);\r
1489                 serial_out(up, UART_SRR, UART_RESET);\r
1490                 goto fail;\r
1491         }\r
1492 \r
1493         /* reset DLAB */\r
1494         if(serial_lcr_write(up, cval)){\r
1495                 dbg("serial.%d reset DLAB fail\n", up->port.line);\r
1496                 serial_out(up, UART_SRR, UART_RESET);\r
1497                 goto fail;\r
1498         }\r
1499         else{\r
1500                 serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1501                 serial_out(up, UART_FCR, fcr);          /* set fcr */\r
1502                 up->fcr = fcr;\r
1503                 /* enable the uart interrupt last */\r
1504                 up->ier |= UART_IER_RDI;\r
1505                 up->ier |= UART_IER_RLSI;\r
1506                 serial_out(up, UART_IER, up->ier);\r
1507         }\r
1508 \r
1509         spin_unlock_irqrestore(&up->port.lock, flags);\r
1510 \r
1511         /* Don't rewrite B0 */\r
1512         if (tty_termios_baud_rate(termios))\r
1513                 tty_termios_encode_baud_rate(termios, baud, baud);\r
1514         dev_dbg(port->dev, "-%s baud %d\n", __func__, baud);\r
1515 \r
1516         return;\r
1517 \r
1518 fail:\r
1519         spin_unlock_irqrestore(&up->port.lock, flags);\r
1520 \r
1521 }\r
1522 \r
1523 #if 0\r
1524 static void\r
1525 serial_rk_set_ldisc(struct uart_port *port, int new)\r
1526 {\r
1527         if (new == N_PPS) {\r
1528                 port->flags |= UPF_HARDPPS_CD;\r
1529                 serial_rk_enable_ms(port);\r
1530         } else\r
1531                 port->flags &= ~UPF_HARDPPS_CD;\r
1532 }\r
1533 #endif\r
1534 \r
1535 static void\r
1536 serial_rk_pm(struct uart_port *port, unsigned int state,\r
1537               unsigned int oldstate)\r
1538 {\r
1539         struct uart_rk_port *up =\r
1540                 container_of(port, struct uart_rk_port, port);\r
1541 \r
1542         dev_dbg(port->dev, "%s: %s\n", __func__, state ? "disable" : "enable");\r
1543         if (state) {\r
1544                 clk_disable(up->clk);\r
1545                 clk_disable(up->pclk);\r
1546         } else {\r
1547                 clk_enable(up->pclk);\r
1548                 clk_enable(up->clk);\r
1549         }\r
1550 }\r
1551 \r
1552 static void serial_rk_release_port(struct uart_port *port)\r
1553 {\r
1554         dev_dbg(port->dev, "%s\n", __func__);\r
1555 }\r
1556 \r
1557 static int serial_rk_request_port(struct uart_port *port)\r
1558 {\r
1559         dev_dbg(port->dev, "%s\n", __func__);\r
1560         return 0;\r
1561 }\r
1562 \r
1563 static void serial_rk_config_port(struct uart_port *port, int flags)\r
1564 {\r
1565         dev_dbg(port->dev, "%s\n", __func__);\r
1566         port->type = PORT_RK;\r
1567 }\r
1568 \r
1569 static int\r
1570 serial_rk_verify_port(struct uart_port *port, struct serial_struct *ser)\r
1571 {\r
1572         /* we don't want the core code to modify any port params */\r
1573         dev_dbg(port->dev, "%s\n", __func__);\r
1574         return -EINVAL;\r
1575 }\r
1576 \r
1577 static const char *\r
1578 serial_rk_type(struct uart_port *port)\r
1579 {\r
1580         struct uart_rk_port *up =\r
1581                 container_of(port, struct uart_rk_port, port);\r
1582 \r
1583         dev_dbg(port->dev, "%s: %s\n", __func__, up->name);\r
1584         return up->name;\r
1585 }\r
1586 \r
1587 static struct uart_ops serial_rk_pops = {\r
1588         .tx_empty       = serial_rk_tx_empty,\r
1589         .set_mctrl      = serial_rk_set_mctrl,\r
1590         .get_mctrl      = serial_rk_get_mctrl,\r
1591         .stop_tx        = serial_rk_stop_tx,\r
1592         .start_tx       = serial_rk_start_tx,\r
1593         .stop_rx        = serial_rk_stop_rx,\r
1594         .enable_ms      = serial_rk_enable_ms,\r
1595         .break_ctl      = serial_rk_break_ctl,\r
1596         .startup        = serial_rk_startup,\r
1597         .shutdown       = serial_rk_shutdown,\r
1598         .set_termios    = serial_rk_set_termios,\r
1599 #if 0\r
1600         .set_ldisc      = serial_rk_set_ldisc,\r
1601 #endif\r
1602         .pm             = serial_rk_pm,\r
1603         .type           = serial_rk_type,\r
1604         .release_port   = serial_rk_release_port,\r
1605         .request_port   = serial_rk_request_port,\r
1606         .config_port    = serial_rk_config_port,\r
1607         .verify_port    = serial_rk_verify_port,\r
1608 #ifdef CONFIG_CONSOLE_POLL\r
1609         .poll_get_char = serial_rk_get_poll_char,\r
1610         .poll_put_char = serial_rk_put_poll_char,\r
1611 #endif\r
1612 };\r
1613 \r
1614 #ifdef CONFIG_SERIAL_RK_CONSOLE\r
1615 \r
1616 static struct uart_rk_port *serial_rk_console_ports[UART_NR];\r
1617 \r
1618 static void serial_rk_console_putchar(struct uart_port *port, int ch)\r
1619 {\r
1620         struct uart_rk_port *up =\r
1621                 container_of(port, struct uart_rk_port, port);\r
1622 \r
1623         wait_for_xmitr(up, UART_LSR_THRE);\r
1624         serial_out(up, UART_TX, ch);\r
1625 }\r
1626 \r
1627 /*\r
1628  *      Print a string to the serial port trying not to disturb\r
1629  *      any possible real use of the port...\r
1630  *\r
1631  *      The console_lock must be held when we get here.\r
1632  */\r
1633 static void\r
1634 serial_rk_console_write(struct console *co, const char *s, unsigned int count)\r
1635 {\r
1636         struct uart_rk_port *up = serial_rk_console_ports[co->index];\r
1637         unsigned long flags;\r
1638         unsigned int ier;\r
1639         int locked = 1;\r
1640 \r
1641         touch_nmi_watchdog();\r
1642 \r
1643         local_irq_save(flags);\r
1644         if (up->port.sysrq) {\r
1645                 /* serial_rk_handle_port() already took the lock */\r
1646                 locked = 0;\r
1647         } else if (oops_in_progress) {\r
1648                 locked = spin_trylock(&up->port.lock);\r
1649         } else\r
1650                 spin_lock(&up->port.lock);\r
1651 \r
1652         /*\r
1653          *      First save the IER then disable the interrupts\r
1654          */\r
1655         ier = serial_in(up, UART_IER);\r
1656 \r
1657         serial_out(up, UART_IER, 0);\r
1658 \r
1659         uart_console_write(&up->port, s, count, serial_rk_console_putchar);\r
1660 \r
1661         /*\r
1662          *      Finally, wait for transmitter to become empty\r
1663          *      and restore the IER\r
1664          */\r
1665         wait_for_xmitr(up, BOTH_EMPTY);\r
1666         serial_out(up, UART_IER, ier);\r
1667 \r
1668 #if 0\r
1669         /*\r
1670          *      The receive handling will happen properly because the\r
1671          *      receive ready bit will still be set; it is not cleared\r
1672          *      on read.  However, modem control will not, we must\r
1673          *      call it if we have saved something in the saved flags\r
1674          *      while processing with interrupts off.\r
1675          */\r
1676         if (up->msr_saved_flags)\r
1677                 check_modem_status(up);\r
1678 #endif\r
1679 \r
1680         if (locked)\r
1681                 spin_unlock(&up->port.lock);\r
1682         local_irq_restore(flags);\r
1683 }\r
1684 \r
1685 static int __init serial_rk_console_setup(struct console *co, char *options)\r
1686 {\r
1687         struct uart_rk_port *up;\r
1688         int baud = 115200;\r
1689         int bits = 8;\r
1690         int parity = 'n';\r
1691         int flow = 'n';\r
1692 \r
1693         if (unlikely(co->index >= UART_NR || co->index < 0))\r
1694                 return -ENODEV;\r
1695 \r
1696         if (serial_rk_console_ports[co->index] == NULL)\r
1697                 return -ENODEV;\r
1698         up = serial_rk_console_ports[co->index];\r
1699 \r
1700         if (options)\r
1701                 uart_parse_options(options, &baud, &parity, &bits, &flow);\r
1702 \r
1703         return uart_set_options(&up->port, co, baud, parity, bits, flow);\r
1704 }\r
1705 \r
1706 static struct console serial_rk_console = {\r
1707         .name           = "ttyS",\r
1708         .write          = serial_rk_console_write,\r
1709         .device         = uart_console_device,\r
1710         .setup          = serial_rk_console_setup,\r
1711         .flags          = CON_PRINTBUFFER | CON_ANYTIME,\r
1712         .index          = -1,\r
1713         .data           = &serial_rk_reg,\r
1714 };\r
1715 \r
1716 static void serial_rk_add_console_port(struct uart_rk_port *up)\r
1717 {\r
1718         serial_rk_console_ports[up->pdev->id] = up;\r
1719 }\r
1720 \r
1721 #define SERIAL_CONSOLE  &serial_rk_console\r
1722 #else\r
1723 #define SERIAL_CONSOLE  NULL\r
1724 \r
1725 static inline void serial_rk_add_console_port(struct uart_rk_port *up)\r
1726 {}\r
1727 \r
1728 #endif\r
1729 \r
1730 static struct uart_driver serial_rk_reg = {\r
1731         .owner                  = THIS_MODULE,\r
1732         .driver_name            = "rk29_serial",\r
1733         .dev_name               = "ttyS",\r
1734         .major                  = TTY_MAJOR,\r
1735         .minor                  = 64,\r
1736         .cons                   = SERIAL_CONSOLE,\r
1737         .nr                     = UART_NR,\r
1738 };\r
1739 \r
1740 static int __devinit serial_rk_probe(struct platform_device *pdev)\r
1741 {\r
1742         struct uart_rk_port     *up;\r
1743         struct resource         *mem;\r
1744         int irq;\r
1745         int ret = -ENOSPC;\r
1746         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1747         if (!mem) {\r
1748                 dev_err(&pdev->dev, "no mem resource?\n");\r
1749                 return -ENODEV;\r
1750         }\r
1751 \r
1752         irq = platform_get_irq(pdev, 0);\r
1753         if (irq < 0) {\r
1754                 dev_err(&pdev->dev, "no irq resource?\n");\r
1755                 return irq;\r
1756         }\r
1757 \r
1758         if (!request_mem_region(mem->start, (mem->end - mem->start) + 1,\r
1759                                 pdev->dev.driver->name)) {\r
1760                 dev_err(&pdev->dev, "memory region already claimed\n");\r
1761                 return -EBUSY;\r
1762         }\r
1763 \r
1764         up = kzalloc(sizeof(*up), GFP_KERNEL);\r
1765         if (up == NULL) {\r
1766                 ret = -ENOMEM;\r
1767                 goto do_release_region;\r
1768         }\r
1769 \r
1770         sprintf(up->name, "rk29_serial.%d", pdev->id);\r
1771         up->pdev = pdev;\r
1772         up->pclk = clk_get(&pdev->dev, "pclk_uart");\r
1773         up->clk = clk_get(&pdev->dev, "uart");\r
1774         if (unlikely(IS_ERR(up->clk))) {\r
1775                 ret = PTR_ERR(up->clk);\r
1776                 goto do_free;\r
1777         }\r
1778         up->tx_loadsz = 30;\r
1779 #if USE_DMA\r
1780         up->prk29_uart_dma_t = &rk29_uart_ports_dma_t[pdev->id];\r
1781 #endif\r
1782         up->port.dev = &pdev->dev;\r
1783         up->port.type = PORT_RK;\r
1784         up->port.irq = irq;\r
1785         up->port.iotype = UPIO_DWAPB;\r
1786 \r
1787         up->port.regshift = 2;\r
1788         up->port.fifosize = 32;\r
1789         up->port.ops = &serial_rk_pops;\r
1790         up->port.line = pdev->id;\r
1791         up->port.iobase = mem->start;\r
1792         up->port.membase = ioremap_nocache(mem->start, mem->end - mem->start + 1);\r
1793         if (!up->port.membase) {\r
1794                 ret = -ENOMEM;\r
1795                 goto do_put_clk;\r
1796         }\r
1797         up->port.mapbase = mem->start;\r
1798         up->port.irqflags = IRQF_DISABLED;\r
1799         up->port.uartclk = clk_get_rate(up->clk);\r
1800 \r
1801 #if USE_DMA\r
1802         /* set dma config */\r
1803         if(1 == up->prk29_uart_dma_t->use_dma) {\r
1804                 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);\r
1805 \r
1806                 //timer\r
1807                 up->prk29_uart_dma_t->use_timer = USE_TIMER;\r
1808                 up->prk29_uart_dma_t->rx_timer.function = serial_rk_rx_timeout;\r
1809                 up->prk29_uart_dma_t->rx_timer.data = (unsigned long)up;\r
1810                 up->prk29_uart_dma_t->rx_timeout = 7;\r
1811                 up->prk29_uart_dma_t->rx_timer.expires = jiffies + msecs_to_jiffies(up->prk29_uart_dma_t->rx_timeout);\r
1812                 init_timer(&up->prk29_uart_dma_t->rx_timer);\r
1813                 //tx buffer\r
1814                 up->prk29_uart_dma_t->tx_buffer_size = UART_XMIT_SIZE;\r
1815                 up->prk29_uart_dma_t->tx_buffer = dmam_alloc_coherent(up->port.dev, up->prk29_uart_dma_t->tx_buffer_size,\r
1816                                 &up->prk29_uart_dma_t->tx_phy_addr, DMA_MEMORY_MAP);\r
1817                 if(!up->prk29_uart_dma_t->tx_buffer){\r
1818                         dev_info(up->port.dev, "dmam_alloc_coherent dma_tx_buffer fail\n");\r
1819                 }\r
1820                 else{\r
1821                         dev_info(up->port.dev, "dma_tx_buffer 0x%08x\n", (unsigned) up->prk29_uart_dma_t->tx_buffer);\r
1822                         dev_info(up->port.dev, "dma_tx_phy 0x%08x\n", (unsigned) up->prk29_uart_dma_t->tx_phy_addr);\r
1823                 }\r
1824                 //rx buffer\r
1825                 up->prk29_uart_dma_t->rx_buffer_size = UART_XMIT_SIZE*32;\r
1826                 up->prk29_uart_dma_t->rx_buffer = dmam_alloc_coherent(up->port.dev, up->prk29_uart_dma_t->rx_buffer_size,\r
1827                                 &up->prk29_uart_dma_t->rx_phy_addr, DMA_MEMORY_MAP);\r
1828                 up->prk29_uart_dma_t->rb_pre_pos = 0;\r
1829                 if(!up->prk29_uart_dma_t->rx_buffer){\r
1830                         dev_info(up->port.dev, "dmam_alloc_coherent dma_rx_buffer fail\n");\r
1831                 }\r
1832                 else {\r
1833                         dev_info(up->port.dev, "dma_rx_buffer 0x%08x\n", (unsigned) up->prk29_uart_dma_t->rx_buffer);\r
1834                         dev_info(up->port.dev, "up 0x%08x\n", (unsigned)up->prk29_uart_dma_t);\r
1835                 }\r
1836 \r
1837                 // work queue\r
1838                 INIT_WORK(&up->uart_work, serial_rk_report_revdata_workfunc);\r
1839                 INIT_WORK(&up->uart_work_rx, serial_rk_start_dma_rx);\r
1840                 up->uart_wq = create_singlethread_workqueue("uart_workqueue");\r
1841                 up->prk29_uart_dma_t->rx_dma_start = 0;\r
1842                 spin_lock_init(&(up->prk29_uart_dma_t->tx_lock));\r
1843                 spin_lock_init(&(up->prk29_uart_dma_t->rx_lock));\r
1844                 serial_rk_init_dma_rx(&up->port);\r
1845                 serial_rk_init_dma_tx(&up->port);\r
1846                 up->ier |= THRE_MODE;                   // enable THRE interrupt mode\r
1847                 serial_out(up, UART_IER, up->ier);\r
1848         }\r
1849 #endif\r
1850 \r
1851         serial_rk_add_console_port(up);\r
1852         ret = uart_add_one_port(&serial_rk_reg, &up->port);\r
1853         if (ret != 0)\r
1854                 goto do_iounmap;\r
1855 \r
1856         platform_set_drvdata(pdev, up);\r
1857         dev_info(&pdev->dev, "membase 0x%08x\n", (unsigned) up->port.membase);\r
1858 \r
1859         return 0;\r
1860 \r
1861 do_iounmap:\r
1862         iounmap(up->port.membase);\r
1863         up->port.membase = NULL;\r
1864 do_put_clk:\r
1865         clk_put(up->clk);\r
1866         clk_put(up->pclk);\r
1867 do_free:\r
1868         kfree(up);\r
1869 do_release_region:\r
1870         release_mem_region(mem->start, (mem->end - mem->start) + 1);\r
1871         return ret;\r
1872 }\r
1873 \r
1874 static int __devexit serial_rk_remove(struct platform_device *pdev)\r
1875 {\r
1876         struct uart_rk_port *up = platform_get_drvdata(pdev);\r
1877 \r
1878         platform_set_drvdata(pdev, NULL);\r
1879         if (up) {\r
1880                 struct resource *mem;\r
1881                 destroy_workqueue(up->uart_wq);\r
1882                 uart_remove_one_port(&serial_rk_reg, &up->port);\r
1883                 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1884                 iounmap(up->port.membase);\r
1885                 up->port.membase = NULL;\r
1886                 clk_put(up->clk);\r
1887                 clk_put(up->pclk);\r
1888                 kfree(up);\r
1889                 release_mem_region(mem->start, (mem->end - mem->start) + 1);\r
1890         }\r
1891 \r
1892         return 0;\r
1893 }\r
1894 \r
1895 static int serial_rk_suspend(struct platform_device *dev, pm_message_t state)\r
1896 {\r
1897         struct uart_rk_port *up = platform_get_drvdata(dev);\r
1898 \r
1899         if (up && up->port.line != DBG_PORT && POWER_MANEGEMENT){\r
1900                 uart_suspend_port(&serial_rk_reg, &up->port);\r
1901         }\r
1902         if(up->port.line == DBG_PORT && POWER_MANEGEMENT){\r
1903                 serial_rk_pm(&up->port, 1, 0);\r
1904         }\r
1905 \r
1906         return 0;\r
1907 }\r
1908 \r
1909 static int serial_rk_resume(struct platform_device *dev)\r
1910 {\r
1911         struct uart_rk_port *up = platform_get_drvdata(dev);\r
1912 \r
1913         if (up && up->port.line != DBG_PORT && POWER_MANEGEMENT){\r
1914                 uart_resume_port(&serial_rk_reg, &up->port);\r
1915         }\r
1916         if(up->port.line == DBG_PORT && POWER_MANEGEMENT){\r
1917                 serial_rk_pm(&up->port, 0, 1);\r
1918         }\r
1919         return 0;\r
1920 }\r
1921 \r
1922 static struct platform_driver serial_rk_driver = {\r
1923         .probe          = serial_rk_probe,\r
1924         .remove         = __devexit_p(serial_rk_remove),\r
1925         .suspend        = serial_rk_suspend,\r
1926         .resume         = serial_rk_resume,\r
1927         .driver         = {\r
1928 #if defined(CONFIG_ARCH_RK29)\r
1929                 .name   = "rk29_serial",\r
1930 #elif defined(CONFIG_SERIAL_RK2818)\r
1931                 .name   = "rk2818_serial",\r
1932 #else\r
1933                 .name   = "rk_serial",\r
1934 #endif\r
1935                 .owner  = THIS_MODULE,\r
1936         },\r
1937 };\r
1938 \r
1939 static int __init serial_rk_init(void)\r
1940 {\r
1941         int ret;\r
1942 \r
1943         ret = uart_register_driver(&serial_rk_reg);\r
1944         if (ret)\r
1945                 return ret;\r
1946 \r
1947         ret = platform_driver_register(&serial_rk_driver);\r
1948         if (ret != 0)\r
1949                 uart_unregister_driver(&serial_rk_reg);\r
1950 \r
1951         return ret;\r
1952 }\r
1953 \r
1954 static void __exit serial_rk_exit(void)\r
1955 {\r
1956         platform_driver_unregister(&serial_rk_driver);\r
1957         uart_unregister_driver(&serial_rk_reg);\r
1958 }\r
1959 \r
1960 module_init(serial_rk_init);\r
1961 module_exit(serial_rk_exit);\r
1962 \r
1963 MODULE_LICENSE("GPL");\r
1964 MODULE_DESCRIPTION("RK UART driver");\r
1965 \r