drivers/tty/serial/rk_serial.c

   1 /*\r
   2  * Driver for RK-UART controller.\r
   3  * Based on drivers/tty/serial/8250.c\r
   4  *\r
   5  * Copyright (C) 2011 Rochchip.\r
   6  *\r
   7  * This program is free software; you can redistribute it and/or modify\r
   8  * it under the terms of the GNU General Public License as published by\r
   9  * the Free Software Foundation; either version 2 of the License, or\r
  10 \r
  11  * (at your option) any later version.\r
  12  *\r
  13  * Author: hhb@rock-chips.com\r
  14  * Date: 2011.06.18\r
  15  */\r
  16 \r
  17 #ifndef CONFIG_SERIAL_RK_CONSOLE\r
  18 #if defined(CONFIG_SERIAL_RK29_CONSOLE)\r
  19 #define CONFIG_SERIAL_RK_CONSOLE\r
  20 #endif\r
  21 #endif\r
  22 \r
  23 #if defined(CONFIG_SERIAL_RK_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)\r
  24 #define SUPPORT_SYSRQ\r
  25 #endif\r
  26 \r
  27 #include <linux/module.h>\r
  28 #include <linux/ioport.h>\r
  29 #include <linux/init.h>\r
  30 #include <linux/console.h>\r
  31 #include <linux/sysrq.h>\r
  32 #include <linux/delay.h>\r
  33 #include <linux/platform_device.h>\r
  34 #include <linux/tty.h>\r
  35 #include <linux/ratelimit.h>\r
  36 #include <linux/tty_flip.h>\r
  37 #include <linux/serial_reg.h>\r
  38 #include <linux/serial_core.h>\r
  39 #include <linux/serial.h>\r
  40 #include <linux/nmi.h>\r
  41 #include <linux/mutex.h>\r
  42 #include <linux/slab.h>\r
  43 #include <linux/clk.h>\r
  44 #include <linux/timer.h>\r
  45 #include <linux/workqueue.h>\r
  46 #include <linux/dma-mapping.h>\r
  47 \r
  48 #include <asm/io.h>\r
  49 #include <asm/irq.h>\r
  50 \r
  51 /*\r
  52 *                        Driver Version Note\r
  53 *\r
  54 *v0.0 : this driver is 2.6.32 kernel driver;\r
  55 *v0.1 : this driver is 3.0.8 kernel driver;\r
  56 *v1.0 : 2012-08-09\r
  57 *               1.modify dma dirver;\r
  58 *               2.enable Programmable THRE Interrupt Mode, so we can just judge ((up->iir & 0x0f) == 0x02) when transmit\r
  59 *               3.reset uart and set it to loopback state to ensure setting baud rate sucessfully \r
  60 *v1.1 : 2012-08-23\r
  61 *               1. dma driver:make "when tx dma is only enable" work functionally  \r
  62 *v1.2 : 2012-08-28\r
  63 *               1. dma driver:serial rx use new dma interface  rk29_dma_enqueue_ring \r
  64 *v1.3 : 2012-12-14\r
  65 *               1. When enable Programmable THRE Interrupt Mode, in lsr register, only UART_LSR_TEMT means transmit empty, but\r
  66                  UART_LSR_THRE doesn't. So, the macro BOTH_EMPTY should be replaced with UART_LSR_TEMT.\r
  67 */\r
  68 #define VERSION_AND_TIME  "rk_serial.c v1.3 2012-12-14"\r
  69 \r
  70 #define PORT_RK         90\r
  71 #define UART_USR        0x1F    /* UART Status Register */\r
  72 #define UART_USR_BUSY (1)\r
  73 #define UART_IER_PTIME  0x80    /* Programmable THRE Interrupt Mode Enable */\r
  74 #define UART_LSR_RFE    0x80    /* receive fifo error */\r
  75 #define UART_SRR                0x22    /* software reset register */\r
  76 #define UART_RESET              0x01\r
  77 \r
  78 \r
  79 //#define BOTH_EMPTY    (UART_LSR_TEMT | UART_LSR_THRE)\r
  80 \r
  81 #define UART_NR 4   //uart port number\r
  82 \r
  83 \r
  84 /* configurate whether the port transmit-receive by DMA in menuconfig*/\r
  85 #define OPEN_DMA      1\r
  86 #define CLOSE_DMA     0\r
  87 \r
  88 #define TX_DMA (1)\r
  89 #define RX_DMA (2)\r
  90 \r
  91 #ifdef CONFIG_UART0_DMA_RK29 \r
  92 #define UART0_USE_DMA CONFIG_UART0_DMA_RK29\r
  93 #else\r
  94 #define UART0_USE_DMA CLOSE_DMA\r
  95 #endif\r
  96 #ifdef CONFIG_UART1_DMA_RK29\r
  97 #define UART1_USE_DMA CONFIG_UART1_DMA_RK29\r
  98 #else\r
  99 #define UART1_USE_DMA CLOSE_DMA\r
 100 #endif\r
 101 #ifdef CONFIG_UART2_DMA_RK29\r
 102 #define UART2_USE_DMA CONFIG_UART2_DMA_RK29\r
 103 #else\r
 104 #define UART2_USE_DMA CLOSE_DMA\r
 105 #endif\r
 106 #ifdef CONFIG_UART3_DMA_RK29\r
 107 #define UART3_USE_DMA CONFIG_UART3_DMA_RK29\r
 108 #else\r
 109 #define UART3_USE_DMA CLOSE_DMA\r
 110 #endif\r
 111 \r
 112 #define USE_TIMER    1           // use timer for dma transport\r
 113 #define POWER_MANEGEMENT 1\r
 114 #define RX_TIMEOUT              (3000*3)  //uint ms\r
 115 #define DMA_TX_TRRIGE_LEVEL 128\r
 116 #define SERIAL_CIRC_CNT_TO_END(xmit)   CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)\r
 117 \r
 118 \r
 119 #define USE_DMA (UART0_USE_DMA | UART1_USE_DMA | UART2_USE_DMA | UART3_USE_DMA)\r
 120 #if USE_DMA\r
 121 #ifdef CONFIG_ARCH_RK29\r
 122 #include <mach/dma-pl330.h>\r
 123 #else\r
 124 #include <plat/dma-pl330.h>\r
 125 #endif\r
 126 #endif\r
 127 \r
 128 \r
 129 \r
 130 static struct uart_driver serial_rk_reg;\r
 131 \r
 132 /*\r
 133  * Debugging.\r
 134  */\r
 135 #ifdef CONFIG_ARCH_RK29\r
 136 #define DBG_PORT 1   //DBG_PORT which uart is used to print log message\r
 137 #else\r
 138 #ifndef CONFIG_RK_DEBUG_UART   //DBG_PORT which uart is used to print log message\r
 139 #define DBG_PORT 2\r
 140 #else\r
 141 #define DBG_PORT CONFIG_RK_DEBUG_UART\r
 142 #endif\r
 143 #endif\r
 144 \r
 145 #ifdef CONFIG_SERIAL_CORE_CONSOLE\r
 146 #define uart_console(port)      ((port)->cons && (port)->cons->index == (port)->line)\r
 147 #else\r
 148 #define uart_console(port)      (0)\r
 149 #endif\r
 150 \r
 151 \r
 152 extern void printascii(const char *);\r
 153 static void dbg(const char *fmt, ...)\r
 154 {\r
 155         va_list va;\r
 156         char buff[256];\r
 157 \r
 158         va_start(va, fmt);\r
 159         vsprintf(buff, fmt, va);\r
 160         va_end(va);\r
 161 \r
 162         printascii(buff);\r
 163 }\r
 164 \r
 165 //enable log output\r
 166 #define DEBUG 0\r
 167 static int log_port = -1;\r
 168 module_param(log_port, int, S_IRUGO|S_IWUSR);\r
 169 \r
 170 #if DEBUG\r
 171 #define DEBUG_INTR(fmt...)      if (up->port.line == log_port && !uart_console(&up->port)) dbg(fmt)\r
 172 #else\r
 173 #define DEBUG_INTR(fmt...)      do { } while (0)\r
 174 #endif\r
 175 \r
 176 \r
 177 #if USE_DMA\r
 178 /* added by hhb@rock-chips.com for uart dma transfer */\r
 179 \r
 180 struct rk_uart_dma {\r
 181         u32 use_dma;            //1:used\r
 182         enum dma_ch rx_dmach;\r
 183         enum dma_ch tx_dmach;\r
 184 \r
 185         //receive and transfer buffer\r
 186         char * rx_buffer;    //visual memory\r
 187         char * tx_buffer;\r
 188         dma_addr_t rx_phy_addr;  //physical memory\r
 189         dma_addr_t tx_phy_addr;\r
 190         u32 rb_size;             //buffer size\r
 191         u32 tb_size;\r
 192 \r
 193         //regard the rx buffer as a circular buffer\r
 194         u32 rb_head;\r
 195         u32 rb_tail;\r
 196         u32 rx_size;\r
 197 \r
 198         spinlock_t              tx_lock;\r
 199         spinlock_t              rx_lock;\r
 200 \r
 201         char tx_dma_inited;   //1:dma tx channel has been init\r
 202         char rx_dma_inited;      //1:dma rx channel has been init\r
 203         char tx_dma_used;        //1:dma tx is working\r
 204         char rx_dma_used;    //1:dma rx is working\r
 205 \r
 206         /* timer to poll activity on rx dma */\r
 207         char use_timer;\r
 208         int      rx_timeout;\r
 209         struct timer_list rx_timer;\r
 210 };\r
 211 #endif\r
 212 \r
 213 struct uart_rk_port {\r
 214         struct uart_port        port;\r
 215         struct platform_device  *pdev;\r
 216         struct clk              *clk;\r
 217         struct clk              *pclk;\r
 218         unsigned int            tx_loadsz;      /* transmit fifo load size */\r
 219         unsigned char           ier;\r
 220         unsigned char           lcr;\r
 221         unsigned char           mcr;\r
 222         unsigned char           iir;\r
 223         unsigned char           fcr;\r
 224         /*\r
 225          * Some bits in registers are cleared on a read, so they must\r
 226          * be saved whenever the register is read but the bits will not\r
 227          * be immediately processed.\r
 228          */\r
 229 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS\r
 230         unsigned char           lsr_saved_flags;\r
 231 #if 0\r
 232 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA\r
 233         unsigned char           msr_saved_flags;\r
 234 #endif\r
 235 \r
 236         char                    name[12];\r
 237         char                    fifo[64];\r
 238         char                    fifo_size;\r
 239         unsigned long           port_activity;\r
 240         struct work_struct uart_work;\r
 241         struct work_struct uart_work_rx;\r
 242         struct workqueue_struct *uart_wq;\r
 243 #if USE_DMA\r
 244         struct rk_uart_dma *dma;\r
 245 #endif\r
 246 };\r
 247 \r
 248 #if USE_DMA\r
 249 static void serial_rk_release_dma_tx(struct uart_port *port);\r
 250 static int serial_rk_start_tx_dma(struct uart_port *port);\r
 251 //static void serial_rk_rx_timeout(unsigned long uart);\r
 252 static void serial_rk_release_dma_rx(struct uart_port *port);\r
 253 static int serial_rk_start_rx_dma(struct uart_port *port);\r
 254 #else\r
 255 static inline int serial_rk_start_tx_dma(struct uart_port *port) { return 0; }\r
 256 #endif\r
 257 static int serial_rk_startup(struct uart_port *port);\r
 258 \r
 259 static inline unsigned int serial_in(struct uart_rk_port *up, int offset)\r
 260 {\r
 261         offset = offset << 2;\r
 262         return __raw_readb(up->port.membase + offset);\r
 263 }\r
 264 \r
 265 /* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */\r
 266 static inline void dwapb_save_out_value(struct uart_rk_port *up, int offset,\r
 267                                         unsigned char value)\r
 268 {\r
 269         if (offset == UART_LCR)\r
 270                 up->lcr = value;\r
 271 }\r
 272 \r
 273 /* Read the IER to ensure any interrupt is cleared before returning from ISR. */\r
 274 static inline void dwapb_check_clear_ier(struct uart_rk_port *up, int offset)\r
 275 {\r
 276         if (offset == UART_TX || offset == UART_IER)\r
 277                 serial_in(up, UART_IER);\r
 278 }\r
 279 \r
 280 static inline void serial_out(struct uart_rk_port *up, int offset, unsigned char value)\r
 281 {\r
 282         dwapb_save_out_value(up, offset, value);\r
 283         __raw_writeb(value, up->port.membase + (offset << 2));\r
 284         if (offset != UART_TX)\r
 285                 dsb();\r
 286         dwapb_check_clear_ier(up, offset);\r
 287 }\r
 288 \r
 289 /* Uart divisor latch read */\r
 290 static inline int serial_dl_read(struct uart_rk_port *up)\r
 291 {\r
 292         return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;\r
 293 }\r
 294 \r
 295 /* Uart divisor latch write */\r
 296 static int serial_dl_write(struct uart_rk_port *up, unsigned int value)\r
 297 {\r
 298         unsigned int tmout = 100;\r
 299 \r
 300         while(!(serial_in(up, UART_LCR) & UART_LCR_DLAB)){\r
 301                 if (--tmout == 0){\r
 302                         if(up->port.line != DBG_PORT)\r
 303                                 dbg("set serial.%d baudrate fail with DLAB not set\n", up->port.line);\r
 304                         return -1;\r
 305                 }\r
 306         }\r
 307 \r
 308         tmout = 15000;\r
 309         while(serial_in(up, UART_USR) & UART_USR_BUSY){\r
 310                 if (--tmout == 0){\r
 311                         if(up->port.line != DBG_PORT)\r
 312                                 dbg("set serial.%d baudrate timeout\n", up->port.line);\r
 313                         return -1;\r
 314                 }\r
 315                 udelay(1);\r
 316         }\r
 317 \r
 318         serial_out(up, UART_DLL, value & 0xff);\r
 319         serial_out(up, UART_DLM, value >> 8 & 0xff);\r
 320 \r
 321         return 0;\r
 322 \r
 323 }\r
 324 \r
 325 static int serial_lcr_write(struct uart_rk_port *up, unsigned char value)\r
 326 {\r
 327         unsigned int tmout = 15000;\r
 328 \r
 329         while(serial_in(up, UART_USR) & UART_USR_BUSY){\r
 330                 if (--tmout == 0){\r
 331                         if(up->port.line != DBG_PORT)\r
 332                                 dbg("set serial.%d lc r = 0x%02x timeout\n", up->port.line, value);\r
 333                         return -1;\r
 334                 }\r
 335                 udelay(1);\r
 336         }\r
 337 \r
 338         serial_out(up, UART_LCR, value);\r
 339 \r
 340         return 0;\r
 341 }\r
 342 \r
 343 static inline void serial_rk_enable_ier_thri(struct uart_rk_port *up)\r
 344 {\r
 345         if (!(up->ier & UART_IER_THRI)) {\r
 346                 up->ier |= UART_IER_THRI;\r
 347                 serial_out(up, UART_IER, up->ier);\r
 348         }\r
 349 }\r
 350 \r
 351 \r
 352 static inline void serial_rk_disable_ier_thri(struct uart_rk_port *up)\r
 353 {\r
 354         if (up->ier & UART_IER_THRI) {\r
 355                 up->ier &= ~UART_IER_THRI;\r
 356                 serial_out(up, UART_IER, up->ier);\r
 357         }\r
 358 }\r
 359 \r
 360 static int rk29_uart_dump_register(struct uart_rk_port *up){\r
 361 \r
 362         unsigned int reg_value = 0;\r
 363 \r
 364         reg_value = serial_in(up, UART_IER);\r
 365         dbg("UART_IER = 0x%0x\n", reg_value);\r
 366         reg_value = serial_in(up, UART_IIR);\r
 367         dbg("UART_IIR = 0x%0x\n", reg_value);\r
 368     reg_value = serial_in(up, UART_LSR);\r
 369     dbg("UART_LSR = 0x%0x\n", reg_value);\r
 370     reg_value = serial_in(up, UART_MSR);\r
 371     dbg("UART_MSR = 0x%0x\n", reg_value);\r
 372     reg_value = serial_in(up, UART_MCR);\r
 373     dbg("UART_MCR = 0x%0x\n", reg_value);\r
 374     reg_value = serial_in(up, 0x21);\r
 375     dbg("UART_RFL = 0x%0x\n", reg_value);\r
 376     reg_value = serial_in(up, UART_LCR);\r
 377     dbg("UART_LCR = 0x%0x\n", reg_value);\r
 378         return 0;\r
 379 \r
 380 }\r
 381 \r
 382 /*\r
 383  * FIFO support.\r
 384  */\r
 385 static void serial_rk_clear_fifos(struct uart_rk_port *up)\r
 386 {\r
 387         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);\r
 388         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |\r
 389                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);\r
 390         serial_out(up, UART_FCR, 0);\r
 391 }\r
 392 \r
 393 static inline void __stop_tx(struct uart_rk_port *p)\r
 394 {\r
 395         if (p->ier & UART_IER_THRI) {\r
 396                 p->ier &= ~UART_IER_THRI;\r
 397                 serial_out(p, UART_IER, p->ier);\r
 398         }\r
 399 }\r
 400 \r
 401 static void serial_rk_stop_tx(struct uart_port *port)\r
 402 {\r
 403         struct uart_rk_port *up =\r
 404                 container_of(port, struct uart_rk_port, port);\r
 405 #if USE_DMA\r
 406         struct rk_uart_dma *uart_dma = up->dma;\r
 407         if(uart_dma->use_dma & TX_DMA){\r
 408                 serial_rk_release_dma_tx(port);\r
 409         }\r
 410 #endif\r
 411         __stop_tx(up);\r
 412 \r
 413 }\r
 414 \r
 415 \r
 416 static void serial_rk_start_tx(struct uart_port *port)\r
 417 {\r
 418         struct uart_rk_port *up =\r
 419                 container_of(port, struct uart_rk_port, port);\r
 420 \r
 421 #if USE_DMA\r
 422         if(up->dma->use_dma & TX_DMA) {\r
 423                 if(!up->dma->tx_dma_used)\r
 424                         serial_rk_enable_ier_thri(up);\r
 425         }else {\r
 426                 serial_rk_enable_ier_thri(up);\r
 427         }\r
 428 #else\r
 429         serial_rk_enable_ier_thri(up);\r
 430 #endif\r
 431 }\r
 432 \r
 433 \r
 434 static void serial_rk_stop_rx(struct uart_port *port)\r
 435 {\r
 436         struct uart_rk_port *up =\r
 437                 container_of(port, struct uart_rk_port, port);\r
 438 #if USE_DMA\r
 439         struct rk_uart_dma *uart_dma = up->dma;\r
 440         if(uart_dma->use_dma & RX_DMA){\r
 441                 serial_rk_release_dma_rx(port);\r
 442         }\r
 443 #endif\r
 444         up->ier &= ~UART_IER_RLSI;\r
 445         up->port.read_status_mask &= ~UART_LSR_DR;\r
 446         serial_out(up, UART_IER, up->ier);\r
 447 }\r
 448 \r
 449 \r
 450 static void serial_rk_enable_ms(struct uart_port *port)\r
 451 {\r
 452         /* no MSR capabilities */\r
 453 #if 0\r
 454         struct uart_rk_port *up =\r
 455                 container_of(port, struct uart_rk_port, port);\r
 456 \r
 457         dev_dbg(port->dev, "%s\n", __func__);\r
 458         up->ier |= UART_IER_MSI;\r
 459         serial_out(up, UART_IER, up->ier);\r
 460 #endif\r
 461 }\r
 462 \r
 463 \r
 464 #if USE_DMA\r
 465 /*\r
 466  * Start transmitting by dma.\r
 467  */\r
 468 #define DMA_SERIAL_BUFFER_SIZE     UART_XMIT_SIZE\r
 469 \r
 470 /* added by hhb@rock-chips.com  for uart dma transfer*/\r
 471 static struct rk_uart_dma rk29_uart_ports_dma[] = {\r
 472                 {UART0_USE_DMA, DMACH_UART0_RX, DMACH_UART0_TX},\r
 473                 {UART1_USE_DMA, DMACH_UART1_RX, DMACH_UART1_TX},\r
 474                 {UART2_USE_DMA, DMACH_UART2_RX, DMACH_UART2_TX},\r
 475                 {UART3_USE_DMA, DMACH_UART3_RX, DMACH_UART3_TX},\r
 476 };\r
 477 \r
 478 \r
 479 /* DMAC PL330 add by hhb@rock-chips.com */\r
 480 static struct rk29_dma_client rk29_uart_dma_client = {\r
 481         .name = "rk-uart-dma",\r
 482 };\r
 483 \r
 484 /*TX*/\r
 485 \r
 486 static void serial_rk_release_dma_tx(struct uart_port *port)\r
 487 {\r
 488         struct uart_rk_port *up =\r
 489                         container_of(port, struct uart_rk_port, port);\r
 490         struct rk_uart_dma *uart_dma = up->dma;\r
 491         if(!port){\r
 492                 return;\r
 493         }\r
 494         if(uart_dma && uart_dma->tx_dma_inited) {\r
 495                 rk29_dma_free(uart_dma->tx_dmach, &rk29_uart_dma_client);\r
 496                 uart_dma->tx_dma_inited = 0;\r
 497                 uart_dma->tx_dma_used = 0;\r
 498         }\r
 499 }\r
 500 \r
 501 /*this function will be called every time after rk29_dma_enqueue() be invoked*/\r
 502 static void serial_rk_dma_txcb(void *buf, int size, enum rk29_dma_buffresult result) {\r
 503         struct uart_port *port = buf;\r
 504         struct uart_rk_port *up = container_of(port, struct uart_rk_port, port);\r
 505         struct circ_buf *xmit = &port->state->xmit;\r
 506 \r
 507         if(result != RK29_RES_OK){\r
 508                 printk(">>>>%s:%d result:%d\n", __func__, __LINE__, result);\r
 509                 up->dma->tx_dma_used = 0;\r
 510                 return;\r
 511         }\r
 512 \r
 513         //spin_lock(&(up->dma->rx_lock));\r
 514         xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);\r
 515         port->icount.tx += size;\r
 516         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)\r
 517                 uart_write_wakeup(&up->port);\r
 518 \r
 519         //spin_lock(&(up->dma->tx_lock));\r
 520         up->dma->tx_dma_used = 0;\r
 521         //spin_unlock(&(up->dma->tx_lock));\r
 522         serial_rk_enable_ier_thri(up);\r
 523         up->port_activity = jiffies;\r
 524 //      dev_info(up->port.dev, "s:%d\n", size);\r
 525 }\r
 526 \r
 527 static int serial_rk_init_dma_tx(struct uart_port *port) {\r
 528 \r
 529         struct uart_rk_port *up =\r
 530                                 container_of(port, struct uart_rk_port, port);\r
 531         struct rk_uart_dma *uart_dma = up->dma;\r
 532 \r
 533         if(!port || !uart_dma){\r
 534                 dev_info(up->port.dev, "serial_rk_init_dma_tx fail\n");\r
 535                 return -1;\r
 536         }\r
 537 \r
 538         if(uart_dma->tx_dma_inited) {\r
 539                 return 0;\r
 540         }\r
 541 \r
 542         if (rk29_dma_request(uart_dma->tx_dmach, &rk29_uart_dma_client, NULL) == -EBUSY) {\r
 543                 dev_info(up->port.dev, "rk29_dma_request tx fail\n");\r
 544                 return -1;\r
 545         }\r
 546 \r
 547         if (rk29_dma_set_buffdone_fn(uart_dma->tx_dmach, serial_rk_dma_txcb)) {\r
 548                 dev_info(up->port.dev, "rk29_dma_set_buffdone_fn tx fail\n");\r
 549                 return -1;\r
 550         }\r
 551         \r
 552         if (rk29_dma_devconfig(uart_dma->tx_dmach, RK29_DMASRC_MEM, (unsigned long)(port->iobase + UART_TX))) {\r
 553                 dev_info(up->port.dev, "rk29_dma_devconfig tx fail\n");\r
 554                 return -1;\r
 555         }\r
 556         \r
 557         if (rk29_dma_config(uart_dma->tx_dmach, 1, 16)) {\r
 558                 dev_info(up->port.dev, "rk29_dma_config tx fail\n");\r
 559                 return -1;\r
 560         }\r
 561 \r
 562         uart_dma->tx_dma_inited = 1;\r
 563         dev_info(up->port.dev, "serial_rk_init_dma_tx sucess\n");\r
 564         return 0;\r
 565 \r
 566 }\r
 567 \r
 568 static int serial_rk_start_tx_dma(struct uart_port *port)\r
 569 {\r
 570         int count = 0;\r
 571         struct circ_buf *xmit = &port->state->xmit;\r
 572         struct uart_rk_port *up = container_of(port, struct uart_rk_port, port);\r
 573         struct rk_uart_dma *uart_dma = up->dma;\r
 574 \r
 575         if(!uart_dma->use_dma)\r
 576                 goto err_out;\r
 577 \r
 578         if(-1 == serial_rk_init_dma_tx(port))\r
 579                 goto err_out;\r
 580 \r
 581         if (1 == uart_dma->tx_dma_used)\r
 582                 return 1;\r
 583 \r
 584 //      spin_lock(&(uart_dma->tx_lock));\r
 585         __stop_tx(up);\r
 586 \r
 587         count = SERIAL_CIRC_CNT_TO_END(xmit);\r
 588         count -= count%16;\r
 589         if(count >= DMA_TX_TRRIGE_LEVEL) {\r
 590                 if (rk29_dma_enqueue(uart_dma->tx_dmach, port, uart_dma->tx_phy_addr + xmit->tail , count)) {\r
 591                         goto err_out;\r
 592                 }\r
 593                 rk29_dma_ctrl(uart_dma->tx_dmach, RK29_DMAOP_START);\r
 594                 up->dma->tx_dma_used = 1;\r
 595         }\r
 596 //      spin_unlock(&(uart_dma->tx_lock));\r
 597         return 1;\r
 598 err_out:\r
 599         dev_info(up->port.dev, "-serial_rk_start_tx_dma-error-\n");\r
 600         return -1;\r
 601 }\r
 602 \r
 603 \r
 604 \r
 605 /*RX*/\r
 606 static void serial_rk_dma_rxcb(void *buf, int size, enum rk29_dma_buffresult result) {\r
 607 \r
 608         //printk(">>%s:%d\n", __func__, result);\r
 609 }\r
 610 \r
 611 static void serial_rk_release_dma_rx(struct uart_port *port)\r
 612 {\r
 613         struct uart_rk_port *up =\r
 614                                 container_of(port, struct uart_rk_port, port);\r
 615         struct rk_uart_dma *uart_dma = up->dma;\r
 616         \r
 617         if(!port){\r
 618                 return;\r
 619         }\r
 620         \r
 621         if(uart_dma && uart_dma->rx_dma_inited) {\r
 622                 del_timer(&uart_dma->rx_timer);\r
 623                 rk29_dma_free(uart_dma->rx_dmach, &rk29_uart_dma_client);\r
 624                 uart_dma->rb_tail = 0;\r
 625                 uart_dma->rx_dma_inited = 0;\r
 626                 uart_dma->rx_dma_used = 0;\r
 627         }\r
 628 }\r
 629 \r
 630 \r
 631 static int serial_rk_init_dma_rx(struct uart_port *port) {\r
 632 \r
 633         struct uart_rk_port *up =\r
 634                                 container_of(port, struct uart_rk_port, port);\r
 635         struct rk_uart_dma *uart_dma = up->dma;\r
 636 \r
 637         if(!port || !uart_dma){\r
 638                 dev_info(up->port.dev, "serial_rk_init_dma_rx: port fail\n");\r
 639                 return -1;\r
 640         }\r
 641 \r
 642         if(uart_dma->rx_dma_inited) {\r
 643                 return 0;\r
 644         }\r
 645 \r
 646         if (rk29_dma_request(uart_dma->rx_dmach, &rk29_uart_dma_client, NULL) == -EBUSY) {\r
 647                 dev_info(up->port.dev, "rk29_dma_request fail rx \n");\r
 648                 return -1;\r
 649         }\r
 650 \r
 651         if (rk29_dma_set_buffdone_fn(uart_dma->rx_dmach, serial_rk_dma_rxcb)) {\r
 652                 dev_info(up->port.dev, "rk29_dma_set_buffdone_fn rx fail\n");\r
 653                 return -1;\r
 654         }\r
 655 \r
 656         if (rk29_dma_devconfig(uart_dma->rx_dmach, RK29_DMASRC_HW, (unsigned long)(port->iobase + UART_RX))) {\r
 657                 dev_info(up->port.dev, "rk29_dma_devconfig rx fail\n");\r
 658                 return -1;\r
 659         }\r
 660 \r
 661         if (rk29_dma_config(uart_dma->rx_dmach, 1, 1)) {\r
 662                 dev_info(up->port.dev, "rk29_dma_config rx fail 1 1 \n");\r
 663                 return -1;\r
 664         }\r
 665 \r
 666         //rk29_dma_setflags(uart_dma->rx_dmach, RK29_DMAF_CIRCULAR);\r
 667 \r
 668         uart_dma->rx_dma_inited = 1;\r
 669         dev_info(up->port.dev, "serial_rk_init_dma_rx sucess\n");\r
 670         return 0;\r
 671 \r
 672 }\r
 673 \r
 674 static int serial_rk_start_rx_dma(struct uart_port *port)\r
 675 {\r
 676         struct uart_rk_port *up =\r
 677                                 container_of(port, struct uart_rk_port, port);\r
 678         struct rk_uart_dma *uart_dma = up->dma;\r
 679         if(!uart_dma->use_dma)\r
 680                 return 0;\r
 681 \r
 682         if(uart_dma->rx_dma_used == 1)\r
 683                 return 0;\r
 684 \r
 685         if(-1 == serial_rk_init_dma_rx(port)){\r
 686                 dev_info(up->port.dev, "*******serial_rk_init_dma_rx*******error*******\n");\r
 687                 return -1;\r
 688         }\r
 689         \r
 690 #if 0   \r
 691                 if (rk29_dma_enqueue(uart_dma->rx_dmach, (void *)up, uart_dma->rx_phy_addr,\r
 692                                 uart_dma->rb_size/2)) {\r
 693                         dev_info(up->port.dev, "*******rk29_dma_enqueue fail*****\n");\r
 694                         return -1;\r
 695                 }\r
 696 \r
 697                 if (rk29_dma_enqueue(uart_dma->rx_dmach, (void *)up,\r
 698                                 uart_dma->rx_phy_addr+uart_dma->rb_size/2, uart_dma->rb_size/2)) {\r
 699                         dev_info(up->port.dev, "*******rk29_dma_enqueue fail*****\n");\r
 700                         return -1;\r
 701                 }\r
 702 \r
 703 #else\r
 704         rk29_dma_enqueue_ring(uart_dma->rx_dmach, (void *)up, uart_dma->rx_phy_addr, uart_dma->rb_size/4, 4, false);\r
 705 #endif\r
 706         rk29_dma_ctrl(uart_dma->rx_dmach, RK29_DMAOP_START);\r
 707         uart_dma->rx_dma_used = 1;\r
 708         if(uart_dma->use_timer == 1){\r
 709                 mod_timer(&uart_dma->rx_timer, jiffies + msecs_to_jiffies(uart_dma->rx_timeout));\r
 710         }\r
 711         up->port_activity = jiffies;\r
 712         return 1;\r
 713 }\r
 714 \r
 715 static void serial_rk_update_rb_addr(struct uart_rk_port *up){\r
 716         dma_addr_t current_pos = 0;\r
 717         dma_addr_t rx_current_pos = 0;\r
 718         struct rk_uart_dma *uart_dma = up->dma;\r
 719         //spin_lock(&(up->dma->rx_lock));\r
 720         uart_dma->rx_size = 0;\r
 721         if(uart_dma->rx_dma_used == 1){\r
 722                 rk29_dma_getposition(uart_dma->rx_dmach, &current_pos, &rx_current_pos);\r
 723                 uart_dma->rb_head = (rx_current_pos - uart_dma->rx_phy_addr);\r
 724                 uart_dma->rx_size = CIRC_CNT(uart_dma->rb_head, uart_dma->rb_tail, uart_dma->rb_size);\r
 725         }\r
 726         //spin_unlock(&(up->dma->rx_lock));\r
 727 }\r
 728 \r
 729 static void serial_rk_report_dma_rx(unsigned long uart)\r
 730 {\r
 731         int count, flip = 0;\r
 732         struct uart_rk_port *up = (struct uart_rk_port *)uart;\r
 733         struct rk_uart_dma *uart_dma = up->dma;\r
 734 \r
 735         if(!uart_dma->rx_dma_used || !up->port.state->port.tty)\r
 736                 return;\r
 737 \r
 738         serial_rk_update_rb_addr(up);\r
 739 \r
 740         while(1) {\r
 741                 count = CIRC_CNT_TO_END(uart_dma->rb_head, uart_dma->rb_tail, uart_dma->rb_size);\r
 742                 if(count <= 0)\r
 743                         break;\r
 744                 up->port.icount.rx += count;\r
 745                 flip = tty_insert_flip_string(up->port.state->port.tty, uart_dma->rx_buffer\r
 746                                 + uart_dma->rb_tail, count);\r
 747                 tty_flip_buffer_push(up->port.state->port.tty);\r
 748                 uart_dma->rb_tail = (uart_dma->rb_tail + count) & (uart_dma->rb_size - 1);\r
 749                 up->port_activity = jiffies;\r
 750         }\r
 751 \r
 752         //if (uart_dma->rx_size > 0)\r
 753         //      printk("rx_size:%d ADDR:%x\n", uart_dma->rx_size, uart_dma->rb_head);\r
 754 \r
 755         if(uart_dma->use_timer == 1){\r
 756                 mod_timer(&uart_dma->rx_timer, jiffies + msecs_to_jiffies(uart_dma->rx_timeout));\r
 757         }\r
 758 \r
 759 }\r
 760 #if 0\r
 761 static void serial_rk_rx_timeout(unsigned long uart)\r
 762 {\r
 763         struct uart_rk_port *up = (struct uart_rk_port *)uart;\r
 764 \r
 765         serial_rk_report_dma_rx(up);\r
 766         //queue_work(up->uart_wq, &up->uart_work);\r
 767 }\r
 768 \r
 769 static void serial_rk_report_revdata_workfunc(struct work_struct *work)\r
 770 {\r
 771         struct uart_rk_port *up =\r
 772                                 container_of(work, struct uart_rk_port, uart_work);\r
 773 \r
 774         serial_rk_report_dma_rx((unsigned long)up);\r
 775 \r
 776         //spin_lock(&(up->dma->rx_lock));\r
 777 \r
 778         if(up->port.state->port.tty && up->dma->use_timer != 1 && up->fifo_size > 0){\r
 779 \r
 780                 tty_insert_flip_string(up->port.state->port.tty, up->fifo, up->fifo_size);\r
 781                 tty_flip_buffer_push(up->port.state->port.tty);\r
 782                 up->port.icount.rx += up->fifo_size;\r
 783                 up->ier |= UART_IER_RDI;\r
 784                 serial_out(up, UART_IER, up->ier);\r
 785         }\r
 786 \r
 787         //spin_unlock(&(up->dma->rx_lock));\r
 788 \r
 789 }\r
 790 \r
 791 \r
 792 static void serial_rk_start_dma_rx(struct work_struct *work)\r
 793 {\r
 794         struct uart_rk_port *up =\r
 795                                         container_of(work, struct uart_rk_port, uart_work_rx);\r
 796 \r
 797         //mod_timer(&up->dma->rx_timer, jiffies + msecs_to_jiffies(up->dma->rx_timeout));\r
 798         //rk29_dma_ctrl(up->dma->rx_dmach, RK29_DMAOP_START);\r
 799         //serial_rk_start_rx_dma(&up->port);\r
 800 \r
 801 }\r
 802 #endif\r
 803 \r
 804 #endif /* USE_DMA */\r
 805 \r
 806 \r
 807 static void\r
 808 receive_chars(struct uart_rk_port *up, unsigned int *status)\r
 809 {\r
 810         struct tty_struct *tty = up->port.state->port.tty;\r
 811         unsigned char ch, lsr = *status;\r
 812         int max_count = 256;\r
 813         char flag;\r
 814 \r
 815         do {\r
 816                 if (likely(lsr & UART_LSR_DR)){\r
 817                         ch = serial_in(up, UART_RX);\r
 818                 }\r
 819                 else\r
 820                         /*\r
 821                          * Intel 82571 has a Serial Over Lan device that will\r
 822                          * set UART_LSR_BI without setting UART_LSR_DR when\r
 823                          * it receives a break. To avoid reading from the\r
 824                          * receive buffer without UART_LSR_DR bit set, we\r
 825                          * just force the read character to be 0\r
 826                          */\r
 827                         ch = 0;\r
 828 \r
 829                 flag = TTY_NORMAL;\r
 830                 up->port.icount.rx++;\r
 831 \r
 832                 lsr |= up->lsr_saved_flags;\r
 833                 up->lsr_saved_flags = 0;\r
 834 \r
 835                 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {\r
 836                         /*\r
 837                          * For statistics only\r
 838                          */\r
 839                         if (lsr & UART_LSR_BI) {\r
 840                                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);\r
 841                                 up->port.icount.brk++;\r
 842                                 /*\r
 843                                  * We do the SysRQ and SAK checking\r
 844                                  * here because otherwise the break\r
 845                                  * may get masked by ignore_status_mask\r
 846                                  * or read_status_mask.\r
 847                                  */\r
 848                                 if (uart_handle_break(&up->port))\r
 849                                         goto ignore_char;\r
 850                         } else if (lsr & UART_LSR_PE)\r
 851                                 up->port.icount.parity++;\r
 852                         else if (lsr & UART_LSR_FE)\r
 853                                 up->port.icount.frame++;\r
 854                         if (lsr & UART_LSR_OE)\r
 855                                 up->port.icount.overrun++;\r
 856 \r
 857 \r
 858                         /*\r
 859                          * Mask off conditions which should be ignored.\r
 860                          */\r
 861                         lsr &= up->port.read_status_mask;\r
 862 \r
 863                         if (lsr & UART_LSR_BI) {\r
 864                                 DEBUG_INTR("handling break....");\r
 865                                 flag = TTY_BREAK;\r
 866                         } else if (lsr & UART_LSR_PE)\r
 867                                 flag = TTY_PARITY;\r
 868                         else if (lsr & UART_LSR_FE)\r
 869                                 flag = TTY_FRAME;\r
 870                 }\r
 871                 if (uart_handle_sysrq_char(&up->port, ch))\r
 872                         goto ignore_char;\r
 873 \r
 874                 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);\r
 875 \r
 876 ignore_char:\r
 877                 lsr = serial_in(up, UART_LSR);\r
 878         } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));\r
 879         spin_unlock(&up->port.lock);\r
 880         tty_flip_buffer_push(tty);\r
 881         spin_lock(&up->port.lock);\r
 882         *status = lsr;\r
 883 }\r
 884 \r
 885 static void transmit_chars(struct uart_rk_port *up)\r
 886 {\r
 887         struct circ_buf *xmit = &up->port.state->xmit;\r
 888         int count;\r
 889 \r
 890         if (up->port.x_char) {\r
 891                 serial_out(up, UART_TX, up->port.x_char);\r
 892                 up->port.icount.tx++;\r
 893                 up->port.x_char = 0;\r
 894                 return;\r
 895         }\r
 896         if (uart_tx_stopped(&up->port)) {\r
 897                 __stop_tx(up);\r
 898                 return;\r
 899         }\r
 900         if (uart_circ_empty(xmit)) {\r
 901                 __stop_tx(up);\r
 902                 return;\r
 903         }\r
 904 #if USE_DMA\r
 905         //hhb\r
 906         if(up->dma->use_dma & TX_DMA){\r
 907                 if(SERIAL_CIRC_CNT_TO_END(xmit) >= DMA_TX_TRRIGE_LEVEL){\r
 908                         serial_rk_start_tx_dma(&up->port);\r
 909                         return;\r
 910                 }\r
 911         }\r
 912 #endif\r
 913         count = up->port.fifosize - serial_in(up , 0x20);\r
 914         do {\r
 915                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);\r
 916                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);\r
 917                 up->port.icount.tx++;\r
 918                 if (uart_circ_empty(xmit))\r
 919                         break;\r
 920         } while (--count > 0);\r
 921 \r
 922         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)\r
 923                 uart_write_wakeup(&up->port);\r
 924 \r
 925         DEBUG_INTR("THRE...");\r
 926 #if USE_DMA\r
 927         up->port_activity = jiffies;\r
 928 #endif\r
 929         if (uart_circ_empty(xmit))\r
 930                 __stop_tx(up);\r
 931 }\r
 932 \r
 933 static unsigned int check_modem_status(struct uart_rk_port *up)\r
 934 {\r
 935         unsigned int status = serial_in(up, UART_MSR);\r
 936 \r
 937 #if 0\r
 938         status |= up->msr_saved_flags;\r
 939         up->msr_saved_flags = 0;\r
 940         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&\r
 941             up->port.state != NULL) {\r
 942                 if (status & UART_MSR_TERI)\r
 943                         up->port.icount.rng++;\r
 944                 if (status & UART_MSR_DDSR)\r
 945                         up->port.icount.dsr++;\r
 946                 if (status & UART_MSR_DDCD)\r
 947                         uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);\r
 948                 if (status & UART_MSR_DCTS)\r
 949                         uart_handle_cts_change(&up->port, status & UART_MSR_CTS);\r
 950 \r
 951                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);\r
 952         }\r
 953 #endif\r
 954 \r
 955         return status;\r
 956 }\r
 957 \r
 958 \r
 959 /*\r
 960  * This handles the interrupt from one port.\r
 961  */\r
 962 static void serial_rk_handle_port(struct uart_rk_port *up)\r
 963 {\r
 964         unsigned int status;\r
 965         unsigned long flags;\r
 966         spin_lock_irqsave(&up->port.lock, flags);\r
 967 \r
 968         /* reading UART_LSR can automatically clears PE FE OE bits, except receive fifo error bit*/\r
 969         status = serial_in(up, UART_LSR);\r
 970 \r
 971         DEBUG_INTR("status = %x...\n", status);\r
 972 #if USE_DMA\r
 973         /* DMA mode enable */\r
 974         if(up->dma->use_dma) {\r
 975 \r
 976                 if (status & UART_LSR_RFE) {\r
 977                         if(up->port.line != DBG_PORT){\r
 978                                 dev_info(up->port.dev, "error:lsr=0x%x\n", status);\r
 979                                 status = serial_in(up, UART_LSR);\r
 980                                 DEBUG_INTR("error:lsr=0x%x\n", status);\r
 981                         }\r
 982                 }\r
 983 \r
 984                 if (status & 0x02) {\r
 985                         if(up->port.line != DBG_PORT){\r
 986                                 dev_info(up->port.dev, "error:lsr=0x%x\n", status);\r
 987                                 status = serial_in(up, UART_LSR);\r
 988                                 DEBUG_INTR("error:lsr=0x%x\n", status);\r
 989                         }\r
 990                 }\r
 991 \r
 992                 if(!(up->dma->use_dma & RX_DMA)) {\r
 993                         if (status & (UART_LSR_DR | UART_LSR_BI)) {\r
 994                                 receive_chars(up, &status);\r
 995                         }\r
 996                 }\r
 997 \r
 998                 if ((up->iir & 0x0f) == 0x02) {\r
 999                         transmit_chars(up);\r
1000                 }\r
1001         } else \r
1002 #endif\r
1003         {   //dma mode disable\r
1004 \r
1005                 /*\r
1006                  * when uart receive a serial of data which doesn't have stop bit and so on, that causes frame error,and\r
1007                  * set UART_LSR_RFE to one,what is worse,we couldn't read the data in the receive fifo. So if\r
1008                  * wo don't clear this bit and reset the receive fifo, the received data available interrupt would\r
1009                  * occur continuously.  added by hhb@rock-chips.com 2011-08-05\r
1010                  */\r
1011 \r
1012                 if (status & UART_LSR_RFE) {\r
1013                         if(up->port.line != DBG_PORT){\r
1014                                 dev_info(up->port.dev, "error:lsr=0x%x\n", status);\r
1015                                 status = serial_in(up, UART_LSR);\r
1016                                 DEBUG_INTR("error:lsr=0x%x\n", status);\r
1017                                 rk29_uart_dump_register(up);\r
1018                         }\r
1019                 }\r
1020 \r
1021                 if (status & (UART_LSR_DR | UART_LSR_BI)) {\r
1022                         receive_chars(up, &status);\r
1023                 }\r
1024                 check_modem_status(up);\r
1025                 //hhb@rock-chips.com when FIFO and THRE mode both are enabled,and FIFO TX empty trigger is set to larger than 1,\r
1026                 //,we need to add ((up->iir & 0x0f) == 0x02) to transmit_chars,because when entering interrupt,the FIFO and THR\r
1027                 //might not be 1.\r
1028                 if ((up->iir & 0x0f) == 0x02) {\r
1029                         transmit_chars(up);\r
1030                 }\r
1031         }\r
1032         spin_unlock_irqrestore(&up->port.lock, flags);\r
1033 }\r
1034 \r
1035 /*\r
1036  * This is the serial driver's interrupt routine.\r
1037  */\r
1038 \r
1039 static irqreturn_t serial_rk_interrupt(int irq, void *dev_id)\r
1040 {\r
1041         struct uart_rk_port *up = dev_id;\r
1042         int handled = 0;\r
1043         unsigned int iir;\r
1044 \r
1045         iir = serial_in(up, UART_IIR);\r
1046 \r
1047         DEBUG_INTR("%s(%d) iir = 0x%02x\n", __func__, irq, iir);\r
1048         up->iir = iir;\r
1049 \r
1050         if (!(iir & UART_IIR_NO_INT)) {\r
1051                 serial_rk_handle_port(up);\r
1052                 handled = 1;\r
1053         } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {\r
1054 \r
1055                 /* The DesignWare APB UART has an Busy Detect (0x07)\r
1056                  * interrupt meaning an LCR write attempt occured while the\r
1057                  * UART was busy. The interrupt must be cleared by reading\r
1058                  * the UART status register (USR) and the LCR re-written. */\r
1059 \r
1060                 if(!(serial_in(up, UART_USR) & UART_USR_BUSY)){\r
1061                         serial_out(up, UART_LCR, up->lcr);\r
1062                 }\r
1063                 handled = 1;\r
1064                 dbg("the serial.%d is busy\n", up->port.line);\r
1065         }\r
1066         DEBUG_INTR("end(%d).\n", handled);\r
1067 \r
1068         return IRQ_RETVAL(handled);\r
1069 }\r
1070 \r
1071 static unsigned int serial_rk_tx_empty(struct uart_port *port)\r
1072 {\r
1073         struct uart_rk_port *up =\r
1074                 container_of(port, struct uart_rk_port, port);\r
1075         unsigned long flags;\r
1076         unsigned int lsr;\r
1077 \r
1078         dev_dbg(port->dev, "%s\n", __func__);\r
1079         spin_lock_irqsave(&up->port.lock, flags);\r
1080         lsr = serial_in(up, UART_LSR);\r
1081         up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;\r
1082         spin_unlock_irqrestore(&up->port.lock, flags);\r
1083 \r
1084         return (lsr & UART_LSR_TEMT) == UART_LSR_TEMT ? TIOCSER_TEMT : 0;\r
1085 }\r
1086 \r
1087 static unsigned int serial_rk_get_mctrl(struct uart_port *port)\r
1088 {\r
1089         struct uart_rk_port *up =\r
1090                 container_of(port, struct uart_rk_port, port);\r
1091         unsigned int status;\r
1092         unsigned int ret;\r
1093 \r
1094         status = check_modem_status(up);\r
1095 \r
1096         ret = 0;\r
1097         if (status & UART_MSR_DCD)\r
1098                 ret |= TIOCM_CAR;\r
1099         if (status & UART_MSR_RI)\r
1100                 ret |= TIOCM_RNG;\r
1101         if (status & UART_MSR_DSR)\r
1102                 ret |= TIOCM_DSR;\r
1103         if (status & UART_MSR_CTS)\r
1104                 ret |= TIOCM_CTS;\r
1105         dev_dbg(port->dev, "%s 0x%08x\n", __func__, ret);\r
1106         return ret;\r
1107 }\r
1108 \r
1109 static void serial_rk_set_mctrl(struct uart_port *port, unsigned int mctrl)\r
1110 {\r
1111         struct uart_rk_port *up =\r
1112                 container_of(port, struct uart_rk_port, port);\r
1113         unsigned char mcr = 0;\r
1114 \r
1115         dev_dbg(port->dev, "+%s\n", __func__);\r
1116         if (mctrl & TIOCM_RTS)\r
1117                 mcr |= UART_MCR_RTS;\r
1118         if (mctrl & TIOCM_DTR)\r
1119                 mcr |= UART_MCR_DTR;\r
1120         if (mctrl & TIOCM_OUT1)\r
1121                 mcr |= UART_MCR_OUT1;\r
1122         if (mctrl & TIOCM_OUT2)\r
1123                 mcr |= UART_MCR_OUT2;\r
1124         if (mctrl & TIOCM_LOOP)\r
1125                 mcr |= UART_MCR_LOOP;\r
1126 \r
1127         mcr |= up->mcr;\r
1128 \r
1129         serial_out(up, UART_MCR, mcr);\r
1130         dev_dbg(port->dev, "-serial.%d %s mcr: 0x%02x\n", port->line, __func__, mcr);\r
1131 }\r
1132 \r
1133 static void serial_rk_break_ctl(struct uart_port *port, int break_state)\r
1134 {\r
1135         struct uart_rk_port *up =\r
1136                 container_of(port, struct uart_rk_port, port);\r
1137         unsigned long flags;\r
1138 \r
1139         dev_dbg(port->dev, "+%s\n", __func__);\r
1140         spin_lock_irqsave(&up->port.lock, flags);\r
1141         if (break_state == -1)\r
1142                 up->lcr |= UART_LCR_SBC;\r
1143         else\r
1144                 up->lcr &= ~UART_LCR_SBC;\r
1145         serial_lcr_write(up, up->lcr);\r
1146         spin_unlock_irqrestore(&up->port.lock, flags);\r
1147         dev_dbg(port->dev, "-%s lcr: 0x%02x\n", __func__, up->lcr);\r
1148 }\r
1149 \r
1150 #if defined(CONFIG_SERIAL_RK_CONSOLE) || defined(CONFIG_CONSOLE_POLL)\r
1151 /*\r
1152  *      Wait for transmitter & holding register to empty\r
1153  */\r
1154 static void wait_for_xmitr(struct uart_rk_port *up, int bits)\r
1155 {\r
1156         unsigned int status, tmout = 10000;\r
1157 \r
1158         /* Wait up to 10ms for the character(s) to be sent. */\r
1159         for (;;) {\r
1160                 status = serial_in(up, UART_LSR);\r
1161 \r
1162                 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;\r
1163 \r
1164                 if ((status & bits) == bits)\r
1165                         break;\r
1166                 if (--tmout == 0)\r
1167                         break;\r
1168                 udelay(1);\r
1169         }\r
1170 }\r
1171 #endif\r
1172 \r
1173 #ifdef CONFIG_CONSOLE_POLL\r
1174 /*\r
1175  * Console polling routines for writing and reading from the uart while\r
1176  * in an interrupt or debug context.\r
1177  */\r
1178 \r
1179 static int serial_rk_get_poll_char(struct uart_port *port)\r
1180 {\r
1181         struct uart_rk_port *up =\r
1182                 container_of(port, struct uart_rk_port, port);\r
1183         unsigned char lsr = serial_in(up, UART_LSR);\r
1184 \r
1185         while (!(lsr & UART_LSR_DR))\r
1186                 lsr = serial_in(up, UART_LSR);\r
1187 \r
1188         return serial_in(up, UART_RX);\r
1189 }\r
1190 \r
1191 static void serial_rk_put_poll_char(struct uart_port *port,\r
1192                          unsigned char c)\r
1193 {\r
1194         unsigned int ier;\r
1195         struct uart_rk_port *up =\r
1196                 container_of(port, struct uart_rk_port, port);\r
1197 \r
1198         /*\r
1199          *      First save the IER then disable the interrupts\r
1200          */\r
1201         ier = serial_in(up, UART_IER);\r
1202         serial_out(up, UART_IER, 0);\r
1203 \r
1204         wait_for_xmitr(up, UART_LSR_TEMT);\r
1205         /*\r
1206          *      Send the character out.\r
1207          *      If a LF, also do CR...\r
1208          */\r
1209         serial_out(up, UART_TX, c);\r
1210         if (c == 10) {\r
1211                 wait_for_xmitr(up, UART_LSR_TEMT);\r
1212                 serial_out(up, UART_TX, 13);\r
1213         }\r
1214 \r
1215         /*\r
1216          *      Finally, wait for transmitter to become empty\r
1217          *      and restore the IER\r
1218          */\r
1219         wait_for_xmitr(up, UART_LSR_TEMT);\r
1220         serial_out(up, UART_IER, ier);\r
1221 }\r
1222 \r
1223 #endif /* CONFIG_CONSOLE_POLL */\r
1224 \r
1225 static int serial_rk_startup(struct uart_port *port)\r
1226 {\r
1227         struct uart_rk_port *up =\r
1228                 container_of(port, struct uart_rk_port, port);\r
1229         unsigned long flags;\r
1230         int retval, fifosize = 0;\r
1231         \r
1232 \r
1233         dev_dbg(port->dev, "%s\n", __func__);\r
1234 \r
1235         /*\r
1236          * Allocate the IRQ\r
1237          */\r
1238         retval = request_irq(up->port.irq, serial_rk_interrupt, up->port.irqflags,\r
1239                                 up->name, up);\r
1240         if (retval)\r
1241                 return retval;\r
1242 \r
1243         up->mcr = 0;\r
1244 \r
1245         clk_enable(up->pclk);\r
1246         clk_enable(up->clk);  // enable the config uart clock\r
1247 \r
1248         /*\r
1249          * Clear the FIFO buffers and disable them.\r
1250          * (they will be reenabled in set_termios())\r
1251          */\r
1252         serial_rk_clear_fifos(up);\r
1253 \r
1254         //read uart fifo size  hhb@rock-chips.com\r
1255         fifosize = __raw_readl(up->port.membase + 0xf4);\r
1256         up->port.fifosize = ((fifosize >> 16) & 0xff) << 4;\r
1257         if(up->port.fifosize <= 0)\r
1258                 up->port.fifosize = 32;\r
1259         //printk("fifo size:%d :%08x\n", up->port.fifosize, fifosize);\r
1260 \r
1261         /*\r
1262          * Clear the interrupt registers.\r
1263          */\r
1264         (void) serial_in(up, UART_LSR);\r
1265         (void) serial_in(up, UART_RX);\r
1266         (void) serial_in(up, UART_IIR);\r
1267         (void) serial_in(up, UART_MSR);\r
1268         (void) serial_in(up, UART_USR);\r
1269 \r
1270         /*\r
1271          * Now, initialize the UART\r
1272          */\r
1273         serial_lcr_write(up, UART_LCR_WLEN8 | UART_LCR_EPAR);\r
1274 \r
1275         spin_lock_irqsave(&up->port.lock, flags);\r
1276 \r
1277         /*\r
1278          * Most PC uarts need OUT2 raised to enable interrupts.\r
1279          */\r
1280 //      up->port.mctrl |= TIOCM_OUT2;\r
1281 \r
1282         serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1283 \r
1284         spin_unlock_irqrestore(&up->port.lock, flags);\r
1285 \r
1286         /*\r
1287          * Clear the interrupt registers again for luck, and clear the\r
1288          * saved flags to avoid getting false values from polling\r
1289          * routines or the previous session.\r
1290          */\r
1291         (void) serial_in(up, UART_LSR);\r
1292         (void) serial_in(up, UART_RX);\r
1293         (void) serial_in(up, UART_IIR);\r
1294         (void) serial_in(up, UART_MSR);\r
1295         (void) serial_in(up, UART_USR);\r
1296         up->lsr_saved_flags = 0;\r
1297 #if 0\r
1298         up->msr_saved_flags = 0;\r
1299 #endif\r
1300 #if USE_DMA\r
1301         if (up->dma->use_dma & TX_DMA) {\r
1302                 if(up->port.state->xmit.buf != up->dma->tx_buffer){\r
1303                         free_page((unsigned long)up->port.state->xmit.buf);\r
1304                         up->port.state->xmit.buf = up->dma->tx_buffer;\r
1305                 }\r
1306         } else \r
1307 #endif\r
1308         {\r
1309                 up->ier = 0;\r
1310                 serial_out(up, UART_IER, up->ier);\r
1311         }\r
1312 \r
1313         /*\r
1314          * Finally, enable interrupts.  Note: Modem status interrupts\r
1315          * are set via set_termios(), which will be occurring imminently\r
1316          * anyway, so we don't enable them here.\r
1317          */\r
1318 \r
1319         return 0;\r
1320 }\r
1321 \r
1322 \r
1323 static void serial_rk_shutdown(struct uart_port *port)\r
1324 {\r
1325         struct uart_rk_port *up =\r
1326                 container_of(port, struct uart_rk_port, port);\r
1327         unsigned long flags;\r
1328 \r
1329         dev_dbg(port->dev, "%s\n", __func__);\r
1330         /*\r
1331          * Disable interrupts from this port\r
1332          */\r
1333         up->ier = 0;\r
1334         serial_out(up, UART_IER, 0);\r
1335 \r
1336         spin_lock_irqsave(&up->port.lock, flags);\r
1337 //      up->port.mctrl &= ~TIOCM_OUT2;\r
1338         serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1339         spin_unlock_irqrestore(&up->port.lock, flags);\r
1340 \r
1341         /*\r
1342          * Disable break condition and FIFOs\r
1343          */\r
1344         serial_lcr_write(up, serial_in(up, UART_LCR) & ~UART_LCR_SBC);\r
1345         serial_rk_clear_fifos(up);\r
1346 \r
1347         /*\r
1348          * Read data port to reset things, and then free the irq\r
1349          */\r
1350         (void) serial_in(up, UART_RX);\r
1351 #if USE_DMA\r
1352         //if (up->dma->use_dma & TX_DMA)\r
1353         //      up->port.state->xmit.buf = NULL;\r
1354 #endif\r
1355         free_irq(up->port.irq, up);\r
1356         clk_disable(up->clk);\r
1357         clk_disable(up->pclk);\r
1358 }\r
1359 \r
1360 static void\r
1361 serial_rk_set_termios(struct uart_port *port, struct ktermios *termios,\r
1362                       struct ktermios *old)\r
1363 {\r
1364         struct uart_rk_port *up =\r
1365                 container_of(port, struct uart_rk_port, port);\r
1366         unsigned char cval = 0, fcr = 0, mcr = 0;\r
1367         unsigned long flags;\r
1368         unsigned int baud, quot;\r
1369         dev_dbg(port->dev, "+%s\n", __func__);\r
1370 \r
1371         switch (termios->c_cflag & CSIZE) {\r
1372         case CS5:\r
1373                 cval = UART_LCR_WLEN5;\r
1374                 break;\r
1375         case CS6:\r
1376                 cval = UART_LCR_WLEN6;\r
1377                 break;\r
1378         case CS7:\r
1379                 cval = UART_LCR_WLEN7;\r
1380                 break;\r
1381         case CS8:\r
1382         default:\r
1383                 cval = UART_LCR_WLEN8;\r
1384                 break;\r
1385         }\r
1386 \r
1387         if (termios->c_cflag & CSTOPB){\r
1388                 cval |= UART_LCR_STOP;\r
1389         }\r
1390         if (termios->c_cflag & PARENB){\r
1391                 cval |= UART_LCR_PARITY;\r
1392         }\r
1393         if (!(termios->c_cflag & PARODD)){\r
1394                 cval |= UART_LCR_EPAR;\r
1395         }\r
1396 #ifdef CMSPAR\r
1397         if (termios->c_cflag & CMSPAR)\r
1398                 cval |= UART_LCR_SPAR;\r
1399 #endif\r
1400 \r
1401 \r
1402         /*\r
1403          * Ask the core to calculate the divisor for us.\r
1404          */\r
1405         baud = uart_get_baud_rate(port, termios, old,\r
1406                                   port->uartclk / 16 / 0xffff,\r
1407                                   port->uartclk / 16);\r
1408 \r
1409         quot = uart_get_divisor(port, baud);\r
1410         //dev_info(up->port.dev, "uartclk:%d\n", port->uartclk/16);\r
1411         //dev_info(up->port.dev, "baud:%d\n", baud);\r
1412         //dev_info(up->port.dev, "quot:%d\n", quot);\r
1413 \r
1414         if (baud < 2400){\r
1415                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;\r
1416         }\r
1417         else{\r
1418                 fcr = UART_FCR_ENABLE_FIFO;\r
1419 #if USE_DMA\r
1420                 //added by hhb@rock-chips.com\r
1421                 if(up->dma->use_dma & TX_DMA){\r
1422                         fcr |= UART_FCR_T_TRIG_01;\r
1423                 } else\r
1424 #endif\r
1425                 {\r
1426                         fcr |= UART_FCR_T_TRIG_01;\r
1427                 }\r
1428 \r
1429 #if USE_DMA\r
1430                 //added by hhb@rock-chips.com\r
1431                 if(up->dma->use_dma & RX_DMA){  \r
1432                         fcr |= UART_FCR_R_TRIG_00;\r
1433                 } else\r
1434 #endif\r
1435                 {\r
1436                         if (termios->c_cflag & CRTSCTS)\r
1437                                 fcr |= UART_FCR_R_TRIG_11;\r
1438                         else\r
1439                                 fcr |= UART_FCR_R_TRIG_00;\r
1440                 }\r
1441         }\r
1442 \r
1443         /*\r
1444          * MCR-based auto flow control.  When AFE is enabled, RTS will be\r
1445          * deasserted when the receive FIFO contains more characters than\r
1446          * the trigger, or the MCR RTS bit is cleared.  In the case where\r
1447          * the remote UART is not using CTS auto flow control, we must\r
1448          * have sufficient FIFO entries for the latency of the remote\r
1449          * UART to respond.  IOW, at least 32 bytes of FIFO.\r
1450          */\r
1451         up->mcr &= ~UART_MCR_AFE;\r
1452         if (termios->c_cflag & CRTSCTS){\r
1453                 up->mcr |= UART_MCR_AFE;\r
1454         }\r
1455 \r
1456         /*\r
1457          * Ok, we're now changing the port state.  Do it with\r
1458          * interrupts disabled.\r
1459          */\r
1460         spin_lock_irqsave(&up->port.lock, flags);\r
1461 \r
1462         /*\r
1463          * Update the per-port timeout.\r
1464          */\r
1465         uart_update_timeout(port, termios->c_cflag, baud);\r
1466 \r
1467         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;\r
1468         if (termios->c_iflag & INPCK)\r
1469                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;\r
1470         if (termios->c_iflag & (BRKINT | PARMRK))\r
1471                 up->port.read_status_mask |= UART_LSR_BI;\r
1472 \r
1473         /*\r
1474          * Characteres to ignore\r
1475          */\r
1476         up->port.ignore_status_mask = 0;\r
1477         if (termios->c_iflag & IGNPAR)\r
1478                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;\r
1479         if (termios->c_iflag & IGNBRK) {\r
1480                 up->port.ignore_status_mask |= UART_LSR_BI;\r
1481                 /*\r
1482                  * If we're ignoring parity and break indicators,\r
1483                  * ignore overruns too (for real raw support).\r
1484                  */\r
1485                 if (termios->c_iflag & IGNPAR)\r
1486                         up->port.ignore_status_mask |= UART_LSR_OE;\r
1487         }\r
1488 \r
1489         /*\r
1490          * ignore all characters if CREAD is not set\r
1491          */\r
1492         if ((termios->c_cflag & CREAD) == 0)\r
1493                 up->port.ignore_status_mask |= UART_LSR_DR;\r
1494 \r
1495         /*\r
1496          * CTS flow control flag and modem status interrupts\r
1497          */\r
1498         up->ier &= ~UART_IER_MSI;\r
1499 #if 0\r
1500         if (UART_ENABLE_MS(&up->port, termios->c_cflag))\r
1501                 up->ier |= UART_IER_MSI;\r
1502 #endif\r
1503 \r
1504         //to avoid uart busy when set baud rate  hhb@rock-chips.com\r
1505         serial_out(up, UART_SRR, UART_RESET);\r
1506         mcr = serial_in(up, UART_MCR);\r
1507         serial_out(up, UART_MCR, mcr | 0x10);  //loopback mode\r
1508         \r
1509         up->lcr = cval;                         /* Save LCR */\r
1510         /* set DLAB */\r
1511         if(serial_lcr_write(up, cval | UART_LCR_DLAB)) {\r
1512                 if(up->port.line != DBG_PORT)\r
1513                         dbg("serial.%d set DLAB fail\n", up->port.line);\r
1514                 serial_out(up, UART_SRR, UART_RESET);\r
1515                 goto fail;\r
1516         }\r
1517 \r
1518         /* set uart baud rate */\r
1519         if(serial_dl_write(up, quot)) {\r
1520                 if(up->port.line != DBG_PORT)\r
1521                         dbg("serial.%d set dll fail\n", up->port.line);\r
1522                 serial_out(up, UART_SRR, UART_RESET);\r
1523                 goto fail;\r
1524         }\r
1525 \r
1526         /* reset DLAB */\r
1527         if(serial_lcr_write(up, cval)) {\r
1528                 if(up->port.line != DBG_PORT)\r
1529                         dbg("serial.%d reset DLAB fail\n", up->port.line);\r
1530                 serial_out(up, UART_SRR, UART_RESET);\r
1531                 goto fail;\r
1532         }\r
1533         else {\r
1534                 serial_rk_set_mctrl(&up->port, up->port.mctrl);\r
1535                 up->fcr = fcr;\r
1536                 serial_out(up, UART_FCR, up->fcr);              /* set fcr */\r
1537                 up->ier = 0;\r
1538                 //start serial receive data\r
1539 #if USE_DMA\r
1540                 if (up->dma->use_dma) {\r
1541                         up->ier |= UART_IER_RLSI;\r
1542                         up->ier |= UART_IER_PTIME;   //Programmable THRE Interrupt Mode Enable\r
1543                         if (up->dma->use_dma & RX_DMA)\r
1544                                 serial_rk_start_rx_dma(&up->port);\r
1545                         else\r
1546                                 up->ier |= UART_IER_RDI;\r
1547                 } else\r
1548 #endif\r
1549                 {\r
1550                         //  not use dma receive\r
1551                         up->ier |= UART_IER_RDI;\r
1552                         up->ier |= UART_IER_RLSI;\r
1553                         if(up->port.line != DBG_PORT)\r
1554                                 up->ier |= UART_IER_PTIME;   //Programmable THRE Interrupt Mode Enable\r
1555 \r
1556                 }\r
1557                 serial_out(up, UART_IER, up->ier);\r
1558         }\r
1559         \r
1560         spin_unlock_irqrestore(&up->port.lock, flags);\r
1561 \r
1562         /* Don't rewrite B0 */\r
1563         if (tty_termios_baud_rate(termios))\r
1564                 tty_termios_encode_baud_rate(termios, baud, baud);\r
1565         dev_dbg(port->dev, "-%s baud %d\n", __func__, baud);\r
1566         return;\r
1567 \r
1568 fail:\r
1569         spin_unlock_irqrestore(&up->port.lock, flags);\r
1570 \r
1571 }\r
1572 \r
1573 #if 0\r
1574 static void\r
1575 serial_rk_set_ldisc(struct uart_port *port, int new)\r
1576 {\r
1577         if (new == N_PPS) {\r
1578                 port->flags |= UPF_HARDPPS_CD;\r
1579                 serial_rk_enable_ms(port);\r
1580         } else\r
1581                 port->flags &= ~UPF_HARDPPS_CD;\r
1582 }\r
1583 #endif\r
1584 \r
1585 static void\r
1586 serial_rk_pm(struct uart_port *port, unsigned int state,\r
1587               unsigned int oldstate)\r
1588 {\r
1589         struct uart_rk_port *up =\r
1590                 container_of(port, struct uart_rk_port, port);\r
1591 \r
1592         dev_dbg(port->dev, "%s: %s\n", __func__, state ? "disable" : "enable");\r
1593         if (state) {\r
1594                 clk_disable(up->clk);\r
1595                 clk_disable(up->pclk);\r
1596         } else {\r
1597                 clk_enable(up->pclk);\r
1598                 clk_enable(up->clk);\r
1599         }\r
1600 }\r
1601 \r
1602 static void serial_rk_release_port(struct uart_port *port)\r
1603 {\r
1604         dev_dbg(port->dev, "%s\n", __func__);\r
1605 }\r
1606 \r
1607 static int serial_rk_request_port(struct uart_port *port)\r
1608 {\r
1609         dev_dbg(port->dev, "%s\n", __func__);\r
1610         return 0;\r
1611 }\r
1612 \r
1613 static void serial_rk_config_port(struct uart_port *port, int flags)\r
1614 {\r
1615         dev_dbg(port->dev, "%s\n", __func__);\r
1616         port->type = PORT_RK;\r
1617 }\r
1618 \r
1619 static int\r
1620 serial_rk_verify_port(struct uart_port *port, struct serial_struct *ser)\r
1621 {\r
1622         /* we don't want the core code to modify any port params */\r
1623         dev_dbg(port->dev, "%s\n", __func__);\r
1624         return -EINVAL;\r
1625 }\r
1626 \r
1627 static const char *\r
1628 serial_rk_type(struct uart_port *port)\r
1629 {\r
1630         struct uart_rk_port *up =\r
1631                 container_of(port, struct uart_rk_port, port);\r
1632 \r
1633         dev_dbg(port->dev, "%s: %s\n", __func__, up->name);\r
1634         return up->name;\r
1635 }\r
1636 \r
1637 static struct uart_ops serial_rk_pops = {\r
1638         .tx_empty       = serial_rk_tx_empty,\r
1639         .set_mctrl      = serial_rk_set_mctrl,\r
1640         .get_mctrl      = serial_rk_get_mctrl,\r
1641         .stop_tx        = serial_rk_stop_tx,\r
1642         .start_tx       = serial_rk_start_tx,\r
1643         .stop_rx        = serial_rk_stop_rx,\r
1644         .enable_ms      = serial_rk_enable_ms,\r
1645         .break_ctl      = serial_rk_break_ctl,\r
1646         .startup        = serial_rk_startup,\r
1647         .shutdown       = serial_rk_shutdown,\r
1648         .set_termios    = serial_rk_set_termios,\r
1649 #if 0\r
1650         .set_ldisc      = serial_rk_set_ldisc,\r
1651 #endif\r
1652         .pm             = serial_rk_pm,\r
1653         .type           = serial_rk_type,\r
1654         .release_port   = serial_rk_release_port,\r
1655         .request_port   = serial_rk_request_port,\r
1656         .config_port    = serial_rk_config_port,\r
1657         .verify_port    = serial_rk_verify_port,\r
1658 #ifdef CONFIG_CONSOLE_POLL\r
1659         .poll_get_char = serial_rk_get_poll_char,\r
1660         .poll_put_char = serial_rk_put_poll_char,\r
1661 #endif\r
1662 };\r
1663 \r
1664 #ifdef CONFIG_SERIAL_RK_CONSOLE\r
1665 \r
1666 static struct uart_rk_port *serial_rk_console_ports[UART_NR];\r
1667 \r
1668 static void serial_rk_console_putchar(struct uart_port *port, int ch)\r
1669 {\r
1670         struct uart_rk_port *up =\r
1671                 container_of(port, struct uart_rk_port, port);\r
1672 \r
1673         wait_for_xmitr(up, UART_LSR_THRE);\r
1674         serial_out(up, UART_TX, ch);\r
1675 }\r
1676 \r
1677 /*\r
1678  *      Print a string to the serial port trying not to disturb\r
1679  *      any possible real use of the port...\r
1680  *\r
1681  *      The console_lock must be held when we get here.\r
1682  */\r
1683 static void\r
1684 serial_rk_console_write(struct console *co, const char *s, unsigned int count)\r
1685 {\r
1686         struct uart_rk_port *up = serial_rk_console_ports[co->index];\r
1687         unsigned long flags;\r
1688         unsigned int ier;\r
1689         int locked = 1;\r
1690 \r
1691         touch_nmi_watchdog();\r
1692 \r
1693         local_irq_save(flags);\r
1694         if (up->port.sysrq) {\r
1695                 /* serial_rk_handle_port() already took the lock */\r
1696                 locked = 0;\r
1697         } else if (oops_in_progress) {\r
1698                 locked = spin_trylock(&up->port.lock);\r
1699         } else\r
1700                 spin_lock(&up->port.lock);\r
1701 \r
1702         /*\r
1703          *      First save the IER then disable the interrupts\r
1704          */\r
1705         ier = serial_in(up, UART_IER);\r
1706 \r
1707         serial_out(up, UART_IER, 0);\r
1708 \r
1709         uart_console_write(&up->port, s, count, serial_rk_console_putchar);\r
1710 \r
1711         /*\r
1712          *      Finally, wait for transmitter to become empty\r
1713          *      and restore the IER\r
1714          */\r
1715         wait_for_xmitr(up, UART_LSR_TEMT);\r
1716         serial_out(up, UART_IER, ier);\r
1717 \r
1718 #if 0\r
1719         /*\r
1720          *      The receive handling will happen properly because the\r
1721          *      receive ready bit will still be set; it is not cleared\r
1722          *      on read.  However, modem control will not, we must\r
1723          *      call it if we have saved something in the saved flags\r
1724          *      while processing with interrupts off.\r
1725          */\r
1726         if (up->msr_saved_flags)\r
1727                 check_modem_status(up);\r
1728 #endif\r
1729 \r
1730         if (locked)\r
1731                 spin_unlock(&up->port.lock);\r
1732         local_irq_restore(flags);\r
1733 }\r
1734 \r
1735 static int __init serial_rk_console_setup(struct console *co, char *options)\r
1736 {\r
1737         struct uart_rk_port *up;\r
1738         int baud = 115200;\r
1739         int bits = 8;\r
1740         int parity = 'n';\r
1741         int flow = 'n';\r
1742 \r
1743         if (unlikely(co->index >= UART_NR || co->index < 0))\r
1744                 return -ENODEV;\r
1745 \r
1746         if (serial_rk_console_ports[co->index] == NULL)\r
1747                 return -ENODEV;\r
1748         up = serial_rk_console_ports[co->index];\r
1749 \r
1750         if (options)\r
1751                 uart_parse_options(options, &baud, &parity, &bits, &flow);\r
1752 \r
1753         return uart_set_options(&up->port, co, baud, parity, bits, flow);\r
1754 }\r
1755 \r
1756 static struct console serial_rk_console = {\r
1757         .name           = "ttyS",\r
1758         .write          = serial_rk_console_write,\r
1759         .device         = uart_console_device,\r
1760         .setup          = serial_rk_console_setup,\r
1761         .flags          = CON_PRINTBUFFER | CON_ANYTIME,\r
1762         .index          = -1,\r
1763         .data           = &serial_rk_reg,\r
1764 };\r
1765 \r
1766 static void serial_rk_add_console_port(struct uart_rk_port *up)\r
1767 {\r
1768         serial_rk_console_ports[up->pdev->id] = up;\r
1769 }\r
1770 \r
1771 #define SERIAL_CONSOLE  &serial_rk_console\r
1772 #else\r
1773 #define SERIAL_CONSOLE  NULL\r
1774 \r
1775 static inline void serial_rk_add_console_port(struct uart_rk_port *up)\r
1776 {}\r
1777 \r
1778 #endif\r
1779 \r
1780 static struct uart_driver serial_rk_reg = {\r
1781         .owner                  = THIS_MODULE,\r
1782         .driver_name            = "rk29_serial",\r
1783         .dev_name               = "ttyS",\r
1784         .major                  = TTY_MAJOR,\r
1785         .minor                  = 64,\r
1786         .cons                   = SERIAL_CONSOLE,\r
1787         .nr                     = UART_NR,\r
1788 };\r
1789 \r
1790 static int __devinit serial_rk_probe(struct platform_device *pdev)\r
1791 {\r
1792         struct uart_rk_port     *up;\r
1793         struct resource         *mem;\r
1794         int irq;\r
1795         int ret = -ENOSPC;\r
1796         \r
1797         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1798         if (!mem) {\r
1799                 dev_err(&pdev->dev, "no mem resource?\n");\r
1800                 return -ENODEV;\r
1801         }\r
1802 \r
1803         irq = platform_get_irq(pdev, 0);\r
1804         if (irq < 0) {\r
1805                 dev_err(&pdev->dev, "no irq resource?\n");\r
1806                 return irq;\r
1807         }\r
1808 \r
1809         if (!request_mem_region(mem->start, (mem->end - mem->start) + 1,\r
1810                                 pdev->dev.driver->name)) {\r
1811                 dev_err(&pdev->dev, "memory region already claimed\n");\r
1812                 return -EBUSY;\r
1813         }\r
1814 \r
1815         up = kzalloc(sizeof(*up), GFP_KERNEL);\r
1816         if (up == NULL) {\r
1817                 ret = -ENOMEM;\r
1818                 goto do_release_region;\r
1819         }\r
1820 \r
1821         sprintf(up->name, "rk29_serial.%d", pdev->id);\r
1822         up->pdev = pdev;\r
1823         up->pclk = clk_get(&pdev->dev, "pclk_uart");\r
1824         up->clk = clk_get(&pdev->dev, "uart");\r
1825         if (unlikely(IS_ERR(up->clk))) {\r
1826                 ret = PTR_ERR(up->clk);\r
1827                 goto do_free;\r
1828         }\r
1829         up->tx_loadsz = 30;\r
1830 #if USE_DMA\r
1831         up->dma = &rk29_uart_ports_dma[pdev->id];\r
1832 #endif\r
1833         up->port.dev = &pdev->dev;\r
1834         up->port.type = PORT_RK;\r
1835         up->port.irq = irq;\r
1836         up->port.iotype = UPIO_DWAPB;\r
1837 \r
1838         up->port.regshift = 2;\r
1839         //fifo size default is 32, but it will be updated later when start_up\r
1840         up->port.fifosize = 32;\r
1841         up->port.ops = &serial_rk_pops;\r
1842         up->port.line = pdev->id;\r
1843         up->port.iobase = mem->start;\r
1844         up->port.membase = ioremap_nocache(mem->start, mem->end - mem->start + 1);\r
1845         if (!up->port.membase) {\r
1846                 ret = -ENOMEM;\r
1847                 goto do_put_clk;\r
1848         }\r
1849         up->port.mapbase = mem->start;\r
1850         up->port.irqflags = IRQF_DISABLED;\r
1851         up->port.uartclk = clk_get_rate(up->clk);\r
1852 \r
1853 #if USE_DMA\r
1854         /* set dma config */\r
1855         pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);\r
1856         if(up->dma->use_dma & RX_DMA) {\r
1857                 //timer\r
1858                 up->dma->use_timer = USE_TIMER;\r
1859                 up->dma->rx_timer.function = serial_rk_report_dma_rx;\r
1860                 up->dma->rx_timer.data = (unsigned long)up;\r
1861                 up->dma->rx_timeout = 10;\r
1862                 up->dma->rx_timer.expires = jiffies + msecs_to_jiffies(up->dma->rx_timeout);\r
1863                 init_timer(&up->dma->rx_timer);\r
1864 \r
1865                 //rx buffer\r
1866                 up->dma->rb_size =  UART_XMIT_SIZE*2;\r
1867                 up->dma->rx_buffer = dmam_alloc_coherent(up->port.dev, up->dma->rb_size,\r
1868                                 &up->dma->rx_phy_addr, DMA_MEMORY_MAP);\r
1869                 up->dma->rb_tail = 0;\r
1870 \r
1871                 if(!up->dma->rx_buffer){\r
1872                         dev_info(up->port.dev, "dmam_alloc_coherent dma_rx_buffer fail\n");\r
1873                 }\r
1874                 else {\r
1875                         dev_info(up->port.dev, "dma_rx_buffer 0x%08x\n", (unsigned) up->dma->rx_buffer);\r
1876                         dev_info(up->port.dev, "dma_rx_phy 0x%08x\n", (unsigned)up->dma->rx_phy_addr);\r
1877                 }\r
1878 \r
1879                 // work queue\r
1880                 //INIT_WORK(&up->uart_work, serial_rk_report_revdata_workfunc);\r
1881                 //INIT_WORK(&up->uart_work_rx, serial_rk_start_dma_rx);\r
1882                 //up->uart_wq = create_singlethread_workqueue("uart_workqueue");\r
1883                 up->dma->rx_dma_used = 0;\r
1884                 spin_lock_init(&(up->dma->rx_lock));\r
1885                 serial_rk_init_dma_rx(&up->port);\r
1886         }\r
1887 \r
1888         if(up->dma->use_dma & TX_DMA){\r
1889                 //tx buffer\r
1890                 up->dma->tb_size = UART_XMIT_SIZE;\r
1891                 up->dma->tx_buffer = dmam_alloc_coherent(up->port.dev, up->dma->tb_size,\r
1892                                 &up->dma->tx_phy_addr, DMA_MEMORY_MAP);\r
1893                 if(!up->dma->tx_buffer){\r
1894                         dev_info(up->port.dev, "dmam_alloc_coherent dma_tx_buffer fail\n");\r
1895                 }\r
1896                 else{\r
1897                         dev_info(up->port.dev, "dma_tx_buffer 0x%08x\n", (unsigned) up->dma->tx_buffer);\r
1898                         dev_info(up->port.dev, "dma_tx_phy 0x%08x\n", (unsigned) up->dma->tx_phy_addr);\r
1899                 }\r
1900                 spin_lock_init(&(up->dma->tx_lock));\r
1901                 serial_rk_init_dma_tx(&up->port);\r
1902         }\r
1903 \r
1904 #endif\r
1905         serial_rk_add_console_port(up);\r
1906         ret = uart_add_one_port(&serial_rk_reg, &up->port);\r
1907         if (ret != 0)\r
1908                 goto do_iounmap;\r
1909 \r
1910         platform_set_drvdata(pdev, up);\r
1911         dev_info(&pdev->dev, "membase 0x%08x\n", (unsigned) up->port.membase);\r
1912 \r
1913         return 0;\r
1914 \r
1915 do_iounmap:\r
1916         iounmap(up->port.membase);\r
1917         up->port.membase = NULL;\r
1918 do_put_clk:\r
1919         clk_put(up->clk);\r
1920         clk_put(up->pclk);\r
1921 do_free:\r
1922         kfree(up);\r
1923 do_release_region:\r
1924         release_mem_region(mem->start, (mem->end - mem->start) + 1);\r
1925         return ret;\r
1926 }\r
1927 \r
1928 static int __devexit serial_rk_remove(struct platform_device *pdev)\r
1929 {\r
1930         struct uart_rk_port *up = platform_get_drvdata(pdev);\r
1931 \r
1932         platform_set_drvdata(pdev, NULL);\r
1933         if (up) {\r
1934                 struct resource *mem;\r
1935                 destroy_workqueue(up->uart_wq);\r
1936                 uart_remove_one_port(&serial_rk_reg, &up->port);\r
1937                 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);\r
1938                 iounmap(up->port.membase);\r
1939                 up->port.membase = NULL;\r
1940                 clk_put(up->clk);\r
1941                 clk_put(up->pclk);\r
1942                 kfree(up);\r
1943                 release_mem_region(mem->start, (mem->end - mem->start) + 1);\r
1944         }\r
1945 \r
1946         return 0;\r
1947 }\r
1948 \r
1949 static int serial_rk_suspend(struct platform_device *dev, pm_message_t state)\r
1950 {\r
1951         struct uart_rk_port *up = platform_get_drvdata(dev);\r
1952 \r
1953         if (up && up->port.line != DBG_PORT && POWER_MANEGEMENT){\r
1954                 uart_suspend_port(&serial_rk_reg, &up->port);\r
1955         }\r
1956         if(up->port.line == DBG_PORT && POWER_MANEGEMENT){\r
1957                 serial_rk_pm(&up->port, 1, 0);\r
1958         }\r
1959 \r
1960         return 0;\r
1961 }\r
1962 \r
1963 static int serial_rk_resume(struct platform_device *dev)\r
1964 {\r
1965         struct uart_rk_port *up = platform_get_drvdata(dev);\r
1966 \r
1967         if (up && up->port.line != DBG_PORT && POWER_MANEGEMENT){\r
1968                 uart_resume_port(&serial_rk_reg, &up->port);\r
1969         }\r
1970         if(up->port.line == DBG_PORT && POWER_MANEGEMENT){\r
1971                 serial_rk_pm(&up->port, 0, 1);\r
1972         }\r
1973         return 0;\r
1974 }\r
1975 \r
1976 static struct platform_driver serial_rk_driver = {\r
1977         .probe          = serial_rk_probe,\r
1978         .remove         = __devexit_p(serial_rk_remove),\r
1979         .suspend        = serial_rk_suspend,\r
1980         .resume         = serial_rk_resume,\r
1981         .driver         = {\r
1982 #if defined(CONFIG_ARCH_RK29)\r
1983                 .name   = "rk29_serial",\r
1984 #elif defined(CONFIG_SERIAL_RK2818)\r
1985                 .name   = "rk2818_serial",\r
1986 #else\r
1987                 .name   = "rk_serial",\r
1988 #endif\r
1989                 .owner  = THIS_MODULE,\r
1990         },\r
1991 };\r
1992 \r
1993 static int __init serial_rk_init(void)\r
1994 {\r
1995         int ret;\r
1996         //hhb@rock-chips.com\r
1997         printk("%s\n", VERSION_AND_TIME);\r
1998 \r
1999         ret = uart_register_driver(&serial_rk_reg);\r
2000         if (ret)\r
2001                 return ret;\r
2002 \r
2003         ret = platform_driver_register(&serial_rk_driver);\r
2004         if (ret != 0)\r
2005                 uart_unregister_driver(&serial_rk_reg);\r
2006 \r
2007         return ret;\r
2008 }\r
2009 \r
2010 static void __exit serial_rk_exit(void)\r
2011 {\r
2012         platform_driver_unregister(&serial_rk_driver);\r
2013         uart_unregister_driver(&serial_rk_reg);\r
2014 }\r
2015 \r
2016 module_init(serial_rk_init);\r
2017 module_exit(serial_rk_exit);\r
2018 \r
2019 MODULE_LICENSE("GPL");\r
2020 MODULE_DESCRIPTION("RK UART driver");\r
2021 \r