2 * Driver for RK-UART controller.
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3 * Based on drivers/tty/serial/8250.c
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5 * Copyright (C) 2011 Rochchip.
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7 * This program is free software; you can redistribute it and/or modify
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8 * it under the terms of the GNU General Public License as published by
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9 * the Free Software Foundation; either version 2 of the License, or
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11 * (at your option) any later version.
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13 * Author: hhb@rock-chips.com
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17 #if defined(CONFIG_SERIAL_ROCKCHIP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
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18 #define SUPPORT_SYSRQ
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21 #include <linux/module.h>
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22 #include <linux/ioport.h>
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23 #include <linux/init.h>
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24 #include <linux/console.h>
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25 #include <linux/sysrq.h>
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26 #include <linux/delay.h>
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27 #include <linux/platform_device.h>
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28 #include <linux/tty.h>
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29 #include <linux/ratelimit.h>
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30 #include <linux/tty_flip.h>
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31 #include <linux/serial_reg.h>
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32 #include <linux/serial_core.h>
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33 #include <linux/serial.h>
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34 #include <linux/nmi.h>
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35 #include <linux/mutex.h>
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36 #include <linux/slab.h>
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37 #include <linux/clk.h>
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38 #include <linux/timer.h>
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39 #include <linux/workqueue.h>
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40 #include <linux/dma-mapping.h>
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42 #include <asm/irq.h>
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44 #include <linux/dmaengine.h>
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47 #include <linux/of.h>
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52 * Driver Version Note
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54 *v0.0 : this driver is 2.6.32 kernel driver;
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55 *v0.1 : this driver is 3.0.8 kernel driver;
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57 * 1.modify dma dirver;
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58 * 2.enable Programmable THRE Interrupt Mode, so we can just judge ((up->iir & 0x0f) == 0x02) when transmit
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59 * 3.reset uart and set it to loopback state to ensure setting baud rate sucessfully
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61 * 1. dma driver:make "when tx dma is only enable" work functionally
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63 * 1. dma driver:serial rx use new dma interface rk29_dma_enqueue_ring
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65 * 1. When enable Programmable THRE Interrupt Mode, in lsr register, only UART_LSR_TEMT means transmit empty, but
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66 UART_LSR_THRE doesn't. So, the macro BOTH_EMPTY should be replaced with UART_LSR_TEMT.
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68 * 1.fix bug dma buffer free error
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70 * 1.in some case, set uart rx as gpio interrupt to wake up arm, when arm suspends
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72 migrate to kernel3.10,and fit device tree
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74 DMA use new interfaces, and use some interfaces with devm_ prefix
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76 * 1.clear receive time out interrupt request in irq handler
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78 #define VERSION_AND_TIME "rk_serial.c v1.8 2014-03-04"
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81 #define UART_USR 0x1F /* UART Status Register */
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82 #define UART_USR_BUSY (1)
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83 #define UART_IER_PTIME 0x80 /* Programmable THRE Interrupt Mode Enable */
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84 #define UART_LSR_RFE 0x80 /* receive fifo error */
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85 #define UART_SRR 0x22 /* software reset register */
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86 #define UART_RESET 0x01
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89 //#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
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90 #define UART_NR 5 //uart port number
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93 /* configurate whether the port transmit-receive by DMA in menuconfig*/
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99 #define DMA_SERIAL_BUFFER_SIZE (UART_XMIT_SIZE*2)
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100 #define CONFIG_CLOCK_CTRL 1
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102 #ifdef CONFIG_UART0_WAKEUP_RK29
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103 #define UART0_USE_WAKEUP CONFIG_UART0_WAKEUP_RK29
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105 #define UART0_USE_WAKEUP 0
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107 #ifdef CONFIG_UART1_WAKEUP_RK29
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108 #define UART1_USE_WAKEUP CONFIG_UART1_WAKEUP_RK29
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110 #define UART1_USE_WAKEUP 0
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112 #ifdef CONFIG_UART2_WAKEUP_RK29
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113 #define UART2_USE_WAKEUP CONFIG_UART2_WAKEUP_RK29
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115 #define UART2_USE_WAKEUP 0
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117 #ifdef CONFIG_UART3_WAKEUP_RK29
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118 #define UART3_USE_WAKEUP CONFIG_UART3_WAKEUP_RK29
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120 #define UART3_USE_WAKEUP 0
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123 #define USE_TIMER 1 // use timer for dma transport
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124 #define POWER_MANEGEMENT 1
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125 #define RX_TIMEOUT (3000*3) //uint ms
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126 #define DMA_TX_TRRIGE_LEVEL 128
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127 #define SERIAL_CIRC_CNT_TO_END(xmit) CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)
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129 #define USE_DMA OPEN_DMA
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131 #define USE_WAKEUP (UART0_USE_WAKEUP | UART1_USE_WAKEUP | UART2_USE_WAKEUP | UART3_USE_WAKEUP)
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134 #include <mach/iomux.h>
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135 #include <linux/wakelock.h>
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140 static struct uart_driver serial_rk_reg;
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145 #ifdef CONFIG_ARCH_RK29
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146 #define DBG_PORT 1 //DBG_PORT which uart is used to print log message
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148 #ifndef CONFIG_RK_DEBUG_UART //DBG_PORT which uart is used to print log message
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151 #define DBG_PORT CONFIG_RK_DEBUG_UART
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155 #ifdef CONFIG_SERIAL_CORE_CONSOLE
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156 #define uart_console(port) ((port)->cons && (port)->cons->index == (port)->line)
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158 #define uart_console(port) (0)
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162 extern void printascii(const char *);
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163 static void dbg(const char *fmt, ...)
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169 vsprintf(buff, fmt, va);
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172 #if defined(CONFIG_DEBUG_LL) || defined(CONFIG_RK_EARLY_PRINTK)
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177 //enable log output
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179 static int log_port = -1;
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180 module_param(log_port, int, S_IRUGO|S_IWUSR);
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183 #define DEBUG_INTR(fmt...) if (up->port.line == log_port && !uart_console(&up->port)) dbg(fmt)
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185 #define DEBUG_INTR(fmt...) do { } while (0)
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190 /* added by hhb@rock-chips.com for uart dma transfer */
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192 struct rk_uart_dma {
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193 u32 use_dma; //1:used
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194 //enum dma_ch rx_dmach;
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195 //enum dma_ch tx_dmach;
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197 //receive and transfer buffer
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198 char * rx_buffer; //visual memory
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200 dma_addr_t rx_phy_addr; //physical memory
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201 dma_addr_t tx_phy_addr;
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202 u32 rb_size; //buffer size
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205 //regard the rx buffer as a circular buffer
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210 spinlock_t tx_lock;
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211 spinlock_t rx_lock;
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213 char tx_dma_inited; //1:dma tx channel has been init
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214 char rx_dma_inited; //1:dma rx channel has been init
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215 char tx_dma_used; //1:dma tx is working
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216 char rx_dma_used; //1:dma rx is working
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218 /* timer to poll activity on rx dma */
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221 struct timer_list rx_timer;
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223 struct dma_chan *dma_chan_rx, *dma_chan_tx;
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224 struct scatterlist rx_sgl, tx_sgl;
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225 unsigned int rx_bytes, tx_bytes;
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230 struct uart_wake_up {
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231 unsigned int enable;
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232 unsigned int rx_mode;
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233 unsigned int tx_mode;
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234 unsigned int rx_pin;
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235 char rx_pin_name[32];
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236 unsigned int tx_pin;
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237 unsigned int rx_irq;
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238 char rx_irq_name[32];
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239 struct wake_lock wakelock;
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240 char wakelock_name[32];
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245 struct of_rk_serial {
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247 unsigned int use_dma;
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248 unsigned int uartclk;
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253 struct uart_rk_port {
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254 struct uart_port port;
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255 struct platform_device *pdev;
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258 unsigned int tx_loadsz; /* transmit fifo load size */
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265 * Some bits in registers are cleared on a read, so they must
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266 * be saved whenever the register is read but the bits will not
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267 * be immediately processed.
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269 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
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270 unsigned char lsr_saved_flags;
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272 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
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273 unsigned char msr_saved_flags;
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279 unsigned long port_activity;
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280 struct work_struct uart_work;
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281 struct work_struct uart_work_rx;
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282 struct workqueue_struct *uart_wq;
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283 struct rk_uart_dma *dma;
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285 struct uart_wake_up *wakeup;
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290 static void serial_rk_release_dma_tx(struct uart_rk_port *up);
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291 static int serial_rk_start_dma_tx(struct uart_rk_port *up);
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292 //static void serial_rk_rx_timeout(unsigned long uart);
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293 static void serial_rk_release_dma_rx(struct uart_rk_port *up);
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294 static int serial_rk_start_dma_rx(struct uart_rk_port *up);
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295 static void serial_rk_stop_dma_tx(struct uart_rk_port *up);
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296 static void serial_rk_stop_dma_rx(struct uart_rk_port *up);
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299 static inline int serial_rk_start_tx_dma(struct uart_port *port) { return 0; }
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301 static int serial_rk_startup(struct uart_port *port);
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303 static inline unsigned int serial_in(struct uart_rk_port *up, int offset)
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305 offset = offset << 2;
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307 return __raw_readl(up->port.membase + offset);
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310 /* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */
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311 static inline void dwapb_save_out_value(struct uart_rk_port *up, int offset,
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312 unsigned char value)
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314 if (offset == UART_LCR)
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318 /* Read the IER to ensure any interrupt is cleared before returning from ISR. */
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319 static inline void dwapb_check_clear_ier(struct uart_rk_port *up, int offset)
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321 if (offset == UART_TX || offset == UART_IER)
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322 serial_in(up, UART_IER);
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325 static inline void serial_out(struct uart_rk_port *up, int offset, unsigned char value)
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327 dwapb_save_out_value(up, offset, value);
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328 __raw_writel(value, up->port.membase + (offset << 2));
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329 if (offset != UART_TX)
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331 dwapb_check_clear_ier(up, offset);
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334 /* Uart divisor latch read */
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335 static inline int serial_dl_read(struct uart_rk_port *up)
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337 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
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340 /* Uart divisor latch write */
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341 static int serial_dl_write(struct uart_rk_port *up, unsigned int value)
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343 unsigned int tmout = 100;
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345 while(!(serial_in(up, UART_LCR) & UART_LCR_DLAB)){
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347 if(up->port.line != DBG_PORT)
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348 dbg("set serial.%d baudrate fail with DLAB not set\n", up->port.line);
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354 while(serial_in(up, UART_USR) & UART_USR_BUSY){
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356 if(up->port.line != DBG_PORT)
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357 dbg("set serial.%d baudrate timeout\n", up->port.line);
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363 serial_out(up, UART_DLL, value & 0xff);
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364 serial_out(up, UART_DLM, value >> 8 & 0xff);
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370 static int serial_lcr_write(struct uart_rk_port *up, unsigned char value)
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372 unsigned int tmout = 15000;
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374 while(serial_in(up, UART_USR) & UART_USR_BUSY){
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376 if(up->port.line != DBG_PORT)
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377 dbg("set serial.%d lc r = 0x%02x timeout\n", up->port.line, value);
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383 serial_out(up, UART_LCR, value);
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388 static inline void serial_rk_enable_ier_thri(struct uart_rk_port *up)
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390 if (!(up->ier & UART_IER_THRI)) {
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391 up->ier |= UART_IER_THRI;
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392 serial_out(up, UART_IER, up->ier);
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397 static inline void serial_rk_disable_ier_thri(struct uart_rk_port *up)
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399 if (up->ier & UART_IER_THRI) {
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400 up->ier &= ~UART_IER_THRI;
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401 serial_out(up, UART_IER, up->ier);
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405 static int rk29_uart_dump_register(struct uart_rk_port *up){
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407 unsigned int reg_value = 0;
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409 reg_value = serial_in(up, UART_IER);
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410 dbg("UART_IER = 0x%0x\n", reg_value);
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411 reg_value = serial_in(up, UART_IIR);
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412 dbg("UART_IIR = 0x%0x\n", reg_value);
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413 reg_value = serial_in(up, UART_LSR);
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414 dbg("UART_LSR = 0x%0x\n", reg_value);
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415 reg_value = serial_in(up, UART_MSR);
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416 dbg("UART_MSR = 0x%0x\n", reg_value);
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417 reg_value = serial_in(up, UART_MCR);
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418 dbg("UART_MCR = 0x%0x\n", reg_value);
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419 reg_value = serial_in(up, 0x21);
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420 dbg("UART_RFL = 0x%0x\n", reg_value);
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421 reg_value = serial_in(up, UART_LCR);
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422 dbg("UART_LCR = 0x%0x\n", reg_value);
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430 static void serial_rk_clear_fifos(struct uart_rk_port *up)
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432 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
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433 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
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434 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
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435 serial_out(up, UART_FCR, 0);
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438 static inline void __stop_tx(struct uart_rk_port *p)
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440 if (p->ier & UART_IER_THRI) {
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441 p->ier &= ~UART_IER_THRI;
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442 serial_out(p, UART_IER, p->ier);
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446 static void serial_rk_stop_tx(struct uart_port *port)
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448 struct uart_rk_port *up =
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449 container_of(port, struct uart_rk_port, port);
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451 struct rk_uart_dma *uart_dma = up->dma;
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452 if(uart_dma->use_dma & TX_DMA){
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453 serial_rk_stop_dma_tx(up);
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460 static void serial_rk_start_tx(struct uart_port *port)
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462 struct uart_rk_port *up =
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463 container_of(port, struct uart_rk_port, port);
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466 if(up->dma->use_dma & TX_DMA) {
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467 if(!up->dma->tx_dma_used)
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468 serial_rk_enable_ier_thri(up);
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470 serial_rk_enable_ier_thri(up);
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473 serial_rk_enable_ier_thri(up);
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478 static void serial_rk_stop_rx(struct uart_port *port)
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480 struct uart_rk_port *up =
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481 container_of(port, struct uart_rk_port, port);
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483 struct rk_uart_dma *uart_dma = up->dma;
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484 if(uart_dma->use_dma & RX_DMA){
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485 serial_rk_stop_dma_rx(up);
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488 up->ier &= ~UART_IER_RLSI;
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489 up->port.read_status_mask &= ~UART_LSR_DR;
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490 serial_out(up, UART_IER, up->ier);
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494 static void serial_rk_enable_ms(struct uart_port *port)
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496 /* no MSR capabilities */
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498 struct uart_rk_port *up =
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499 container_of(port, struct uart_rk_port, port);
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501 dev_dbg(port->dev, "%s\n", __func__);
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502 up->ier |= UART_IER_MSI;
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503 serial_out(up, UART_IER, up->ier);
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508 static struct uart_wake_up rk29_uart_ports_wakeup[] = {
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509 {UART0_USE_WAKEUP, UART0_SIN, UART0_SOUT},
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510 {UART1_USE_WAKEUP, UART1_SIN, UART1_SOUT},
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511 {UART2_USE_WAKEUP, UART2_SIN, UART2_SOUT},
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512 {UART3_USE_WAKEUP, UART3_SIN, UART3_SOUT},
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517 /* DMAC PL330 add by hhb@rock-chips.com */
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519 static void serial_rk_stop_dma_tx(struct uart_rk_port *up)
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521 struct rk_uart_dma *uart_dma = up->dma;
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523 if(uart_dma && uart_dma->tx_dma_used) {
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524 dmaengine_terminate_all(uart_dma->dma_chan_tx);
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525 uart_dma->tx_dma_used = 0;
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529 static void serial_rk_release_dma_tx(struct uart_rk_port *up)
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531 struct rk_uart_dma *uart_dma = up->dma;
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533 if(uart_dma && uart_dma->tx_dma_inited) {
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534 serial_rk_stop_dma_tx(up);
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535 dma_release_channel(uart_dma->dma_chan_tx);
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536 uart_dma->dma_chan_tx = NULL;
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537 uart_dma->tx_dma_inited = 0;
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541 static void dma_tx_callback(void *data)
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543 struct uart_port *port = data;
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544 struct uart_rk_port *up = container_of(port, struct uart_rk_port, port);
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545 struct circ_buf *xmit = &port->state->xmit;
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546 struct rk_uart_dma *uart_dma = up->dma;
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547 struct scatterlist *sgl = &uart_dma->tx_sgl;
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549 dma_unmap_sg(up->port.dev, sgl, 1, DMA_TO_DEVICE);
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551 xmit->tail = (xmit->tail + uart_dma->tx_bytes) & (UART_XMIT_SIZE - 1);
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552 port->icount.tx += uart_dma->tx_bytes;
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553 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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554 uart_write_wakeup(port);
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556 //spin_lock(&(up->dma->tx_lock));
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557 uart_dma->tx_dma_used = 0;
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558 //spin_unlock(&(up->dma->tx_lock));
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559 serial_rk_enable_ier_thri(up);
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560 up->port_activity = jiffies;
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561 // dev_info(up->port.dev, "s:%d\n", size);
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564 static int serial_rk_init_dma_tx(struct uart_rk_port *up) {
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566 struct dma_slave_config slave_config;
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567 struct uart_port *port = &up->port;
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568 struct rk_uart_dma *uart_dma = up->dma;
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572 dev_info(up->port.dev, "serial_rk_init_dma_tx fail\n");
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576 if(uart_dma->tx_dma_inited) {
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580 uart_dma->dma_chan_tx = dma_request_slave_channel(port->dev, "tx");
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581 if (!uart_dma->dma_chan_tx) {
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582 dev_err(port->dev, "cannot get the TX DMA channel!\n");
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586 slave_config.direction = DMA_MEM_TO_DEV;
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587 slave_config.dst_addr = port->mapbase + UART_TX;
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588 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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589 slave_config.dst_maxburst = 16;
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590 ret = dmaengine_slave_config(uart_dma->dma_chan_tx, &slave_config);
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592 dev_err(port->dev, "error in TX dma configuration.");
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596 uart_dma->tx_dma_inited = 1;
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597 dev_info(port->dev, "serial_rk_init_dma_tx sucess\n");
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601 static int serial_rk_start_dma_tx(struct uart_rk_port *up)
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604 struct uart_port *port = &up->port;
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605 struct circ_buf *xmit = &port->state->xmit;
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606 struct rk_uart_dma *uart_dma = up->dma;
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607 struct scatterlist *sgl = &uart_dma->tx_sgl;
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608 struct dma_async_tx_descriptor *desc;
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611 if(!uart_dma->use_dma)
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614 if(-1 == serial_rk_init_dma_tx(up))
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617 if (1 == uart_dma->tx_dma_used)
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620 // spin_lock(&(uart_dma->tx_lock));
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623 count = SERIAL_CIRC_CNT_TO_END(xmit);
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625 if(count >= DMA_TX_TRRIGE_LEVEL) {
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626 uart_dma->tx_bytes = count;
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627 sg_init_one(sgl, uart_dma->tx_buffer + xmit->tail, count);
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628 ret = dma_map_sg(port->dev, sgl, 1, DMA_TO_DEVICE);
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631 dev_err(port->dev, "DMA mapping error for TX.\n");
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634 desc = dmaengine_prep_slave_sg(uart_dma->dma_chan_tx, sgl, 1,
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635 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
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638 dev_err(port->dev, "We cannot prepare for the TX slave dma!\n");
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641 desc->callback = dma_tx_callback;
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642 desc->callback_param = port;
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643 dmaengine_submit(desc);
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644 dma_async_issue_pending(uart_dma->dma_chan_tx);
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645 uart_dma->tx_dma_used = 1;
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647 // spin_unlock(&(uart_dma->tx_lock));
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650 dev_info(up->port.dev, "-serial_rk_start_dma_tx-error-\n");
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658 static void serial_rk_dma_rxcb(void *buf, int size, enum rk29_dma_buffresult result) {
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660 //printk(">>%s:%d\n", __func__, result);
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664 static void serial_rk_stop_dma_rx(struct uart_rk_port *up)
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666 struct rk_uart_dma *uart_dma = up->dma;
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668 if(uart_dma && uart_dma->rx_dma_used) {
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669 del_timer(&uart_dma->rx_timer);
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670 dmaengine_terminate_all(uart_dma->dma_chan_rx);
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671 uart_dma->rb_tail = 0;
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672 uart_dma->rx_dma_used = 0;
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677 static void serial_rk_release_dma_rx(struct uart_rk_port *up)
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679 struct rk_uart_dma *uart_dma = up->dma;
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681 if(uart_dma && uart_dma->rx_dma_inited) {
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682 serial_rk_stop_dma_rx(up);
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683 dma_release_channel(uart_dma->dma_chan_rx);
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684 uart_dma->dma_chan_rx = NULL;
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685 uart_dma->rx_dma_inited = 0;
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690 static int serial_rk_init_dma_rx(struct uart_rk_port *up)
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693 struct uart_port *port = &up->port;
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694 struct dma_slave_config slave_config;
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695 struct rk_uart_dma *uart_dma = up->dma;
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698 dev_info(port->dev, "serial_rk_init_dma_rx: port fail\n");
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702 if(uart_dma->rx_dma_inited) {
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706 uart_dma->dma_chan_rx = dma_request_slave_channel(port->dev, "rx");
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707 if (!uart_dma->dma_chan_rx) {
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708 dev_err(port->dev, "cannot get the DMA channel.\n");
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712 slave_config.direction = DMA_DEV_TO_MEM;
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713 slave_config.src_addr = port->mapbase + UART_RX;
\r
714 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
\r
715 slave_config.src_maxburst = 1;
\r
716 ret = dmaengine_slave_config(uart_dma->dma_chan_rx, &slave_config);
\r
718 dev_err(port->dev, "error in RX dma configuration.\n");
\r
722 uart_dma->rx_dma_inited = 1;
\r
723 dev_info(port->dev, "serial_rk_init_dma_rx sucess\n");
\r
727 static int serial_rk_start_dma_rx(struct uart_rk_port *up)
\r
729 struct uart_port *port = &up->port;
\r
730 struct rk_uart_dma *uart_dma = up->dma;
\r
731 struct dma_async_tx_descriptor *desc;
\r
733 if(!uart_dma->use_dma)
\r
736 if(uart_dma->rx_dma_used == 1)
\r
739 if(-1 == serial_rk_init_dma_rx(up)){
\r
740 dev_info(up->port.dev, "*******serial_rk_init_dma_rx*******error*******\n");
\r
743 desc = dmaengine_prep_dma_cyclic(uart_dma->dma_chan_rx, uart_dma->rx_phy_addr, uart_dma->rb_size, uart_dma->rb_size/2,DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
\r
746 dev_err(port->dev, "We cannot prepare for the RX slave dma!\n");
\r
750 //desc->callback = dma_rx_callback;
\r
751 //desc->callback_param = port;
\r
752 dev_dbg(port->dev, "RX: prepare for the DMA.\n");
\r
753 dmaengine_submit(desc);
\r
754 dma_async_issue_pending(uart_dma->dma_chan_rx);
\r
756 uart_dma->rx_dma_used = 1;
\r
757 if(uart_dma->use_timer == 1){
\r
758 mod_timer(&uart_dma->rx_timer, jiffies + msecs_to_jiffies(uart_dma->rx_timeout));
\r
760 up->port_activity = jiffies;
\r
764 static void serial_rk_update_rb_addr(struct uart_rk_port *up)
\r
766 struct rk_uart_dma *uart_dma = up->dma;
\r
767 struct dma_tx_state state;
\r
768 //spin_lock(&(up->dma->rx_lock));
\r
769 uart_dma->rx_size = 0;
\r
770 if(uart_dma->rx_dma_used == 1) {
\r
771 dmaengine_tx_status(uart_dma->dma_chan_rx, (dma_cookie_t)0, &state);
\r
772 uart_dma->rb_head = (state.residue - uart_dma->rx_phy_addr);
\r
773 uart_dma->rx_size = CIRC_CNT(uart_dma->rb_head, uart_dma->rb_tail, uart_dma->rb_size);
\r
775 //spin_unlock(&(up->dma->rx_lock));
\r
778 static void serial_rk_report_dma_rx(unsigned long uart)
\r
780 int count, flip = 0;
\r
781 struct uart_rk_port *up = (struct uart_rk_port *)uart;
\r
782 struct uart_port *port = &up->port;
\r
783 struct rk_uart_dma *uart_dma = up->dma;
\r
785 if(!uart_dma->rx_dma_used || !port->state->port.tty)
\r
788 serial_rk_update_rb_addr(up);
\r
789 //if (uart_dma->rx_size > 0)
\r
790 // printk("rx_size:%d ADDR:%x\n", uart_dma->rx_size, uart_dma->rb_head);
\r
792 count = CIRC_CNT_TO_END(uart_dma->rb_head, uart_dma->rb_tail, uart_dma->rb_size);
\r
795 port->icount.rx += count;
\r
796 flip = tty_insert_flip_string(&port->state->port, uart_dma->rx_buffer
\r
797 + uart_dma->rb_tail, count);
\r
798 tty_flip_buffer_push(&port->state->port);
\r
799 uart_dma->rb_tail = (uart_dma->rb_tail + count) & (uart_dma->rb_size - 1);
\r
800 up->port_activity = jiffies;
\r
803 if(uart_dma->use_timer == 1)
\r
804 mod_timer(&uart_dma->rx_timer, jiffies + msecs_to_jiffies(uart_dma->rx_timeout));
\r
806 #endif /* USE_DMA */
\r
810 receive_chars(struct uart_rk_port *up, unsigned int *status)
\r
812 struct tty_struct *tty = up->port.state->port.tty;
\r
813 unsigned char ch, lsr = *status;
\r
814 int max_count = 256;
\r
818 if (likely(lsr & UART_LSR_DR)){
\r
819 ch = serial_in(up, UART_RX);
\r
823 * Intel 82571 has a Serial Over Lan device that will
\r
824 * set UART_LSR_BI without setting UART_LSR_DR when
\r
825 * it receives a break. To avoid reading from the
\r
826 * receive buffer without UART_LSR_DR bit set, we
\r
827 * just force the read character to be 0
\r
832 up->port.icount.rx++;
\r
834 lsr |= up->lsr_saved_flags;
\r
835 up->lsr_saved_flags = 0;
\r
837 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
\r
839 * For statistics only
\r
841 if (lsr & UART_LSR_BI) {
\r
842 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
\r
843 up->port.icount.brk++;
\r
845 * We do the SysRQ and SAK checking
\r
846 * here because otherwise the break
\r
847 * may get masked by ignore_status_mask
\r
848 * or read_status_mask.
\r
850 if (uart_handle_break(&up->port))
\r
852 } else if (lsr & UART_LSR_PE)
\r
853 up->port.icount.parity++;
\r
854 else if (lsr & UART_LSR_FE)
\r
855 up->port.icount.frame++;
\r
856 if (lsr & UART_LSR_OE)
\r
857 up->port.icount.overrun++;
\r
861 * Mask off conditions which should be ignored.
\r
863 lsr &= up->port.read_status_mask;
\r
865 if (lsr & UART_LSR_BI) {
\r
866 DEBUG_INTR("handling break....");
\r
868 } else if (lsr & UART_LSR_PE)
\r
870 else if (lsr & UART_LSR_FE)
\r
873 if (uart_handle_sysrq_char(&up->port, ch))
\r
876 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
\r
879 lsr = serial_in(up, UART_LSR);
\r
880 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
\r
881 spin_unlock(&up->port.lock);
\r
882 tty_flip_buffer_push(tty->port);
\r
883 spin_lock(&up->port.lock);
\r
887 static void transmit_chars(struct uart_rk_port *up)
\r
889 struct circ_buf *xmit = &up->port.state->xmit;
\r
892 if (up->port.x_char) {
\r
893 serial_out(up, UART_TX, up->port.x_char);
\r
894 up->port.icount.tx++;
\r
895 up->port.x_char = 0;
\r
898 if (uart_tx_stopped(&up->port)) {
\r
902 if (uart_circ_empty(xmit)) {
\r
908 if(up->dma->use_dma & TX_DMA){
\r
909 if(SERIAL_CIRC_CNT_TO_END(xmit) >= DMA_TX_TRRIGE_LEVEL){
\r
910 serial_rk_start_dma_tx(up);
\r
915 count = up->port.fifosize - serial_in(up , 0x20);
\r
917 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
\r
918 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
\r
919 up->port.icount.tx++;
\r
920 if (uart_circ_empty(xmit))
\r
922 } while (--count > 0);
\r
924 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
\r
925 uart_write_wakeup(&up->port);
\r
927 DEBUG_INTR("THRE...");
\r
929 up->port_activity = jiffies;
\r
931 if (uart_circ_empty(xmit))
\r
935 static unsigned int check_modem_status(struct uart_rk_port *up)
\r
937 unsigned int status = serial_in(up, UART_MSR);
\r
940 status |= up->msr_saved_flags;
\r
941 up->msr_saved_flags = 0;
\r
942 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
\r
943 up->port.state != NULL) {
\r
944 if (status & UART_MSR_TERI)
\r
945 up->port.icount.rng++;
\r
946 if (status & UART_MSR_DDSR)
\r
947 up->port.icount.dsr++;
\r
948 if (status & UART_MSR_DDCD)
\r
949 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
\r
950 if (status & UART_MSR_DCTS)
\r
951 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
\r
953 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
\r
962 * This handles the interrupt from one port.
\r
964 static void serial_rk_handle_port(struct uart_rk_port *up)
\r
966 unsigned int status;
\r
967 unsigned long flags;
\r
968 spin_lock_irqsave(&up->port.lock, flags);
\r
970 /* reading UART_LSR can automatically clears PE FE OE bits, except receive fifo error bit*/
\r
971 status = serial_in(up, UART_LSR);
\r
973 DEBUG_INTR("status = %x...\n", status);
\r
975 /* DMA mode enable */
\r
976 if(up->dma->use_dma) {
\r
978 if (status & UART_LSR_RFE) {
\r
979 if(up->port.line != DBG_PORT){
\r
980 dev_info(up->port.dev, "error:lsr=0x%x\n", status);
\r
981 status = serial_in(up, UART_LSR);
\r
982 DEBUG_INTR("error:lsr=0x%x\n", status);
\r
986 if (status & 0x02) {
\r
987 if(up->port.line != DBG_PORT){
\r
988 dev_info(up->port.dev, "error:lsr=0x%x\n", status);
\r
989 status = serial_in(up, UART_LSR);
\r
990 DEBUG_INTR("error:lsr=0x%x\n", status);
\r
994 if(!(up->dma->use_dma & RX_DMA)) {
\r
995 if (status & (UART_LSR_DR | UART_LSR_BI)) {
\r
996 receive_chars(up, &status);
\r
997 } else if ((up->iir & 0x0f) == 0x0c) {
\r
998 serial_in(up, UART_RX);
\r
1002 if ((up->iir & 0x0f) == 0x02) {
\r
1003 transmit_chars(up);
\r
1007 { //dma mode disable
\r
1010 * when uart receive a serial of data which doesn't have stop bit and so on, that causes frame error,and
\r
1011 * set UART_LSR_RFE to one,what is worse,we couldn't read the data in the receive fifo. So if
\r
1012 * wo don't clear this bit and reset the receive fifo, the received data available interrupt would
\r
1013 * occur continuously. added by hhb@rock-chips.com 2011-08-05
\r
1016 if (status & UART_LSR_RFE) {
\r
1017 if(up->port.line != DBG_PORT){
\r
1018 dev_info(up->port.dev, "error:lsr=0x%x\n", status);
\r
1019 status = serial_in(up, UART_LSR);
\r
1020 DEBUG_INTR("error:lsr=0x%x\n", status);
\r
1021 rk29_uart_dump_register(up);
\r
1025 if (status & (UART_LSR_DR | UART_LSR_BI)) {
\r
1026 receive_chars(up, &status);
\r
1027 } else if ((up->iir & 0x0f) == 0x0c) {
\r
1028 serial_in(up, UART_RX);
\r
1030 check_modem_status(up);
\r
1031 //hhb@rock-chips.com when FIFO and THRE mode both are enabled,and FIFO TX empty trigger is set to larger than 1,
\r
1032 //,we need to add ((up->iir & 0x0f) == 0x02) to transmit_chars,because when entering interrupt,the FIFO and THR
\r
1034 if ((up->iir & 0x0f) == 0x02) {
\r
1035 transmit_chars(up);
\r
1038 spin_unlock_irqrestore(&up->port.lock, flags);
\r
1042 * This is the serial driver's interrupt routine.
\r
1045 static irqreturn_t serial_rk_interrupt(int irq, void *dev_id)
\r
1047 struct uart_rk_port *up = dev_id;
\r
1051 iir = serial_in(up, UART_IIR);
\r
1053 DEBUG_INTR("%s(%d) iir = 0x%02x\n", __func__, irq, iir);
\r
1056 if (!(iir & UART_IIR_NO_INT)) {
\r
1057 serial_rk_handle_port(up);
\r
1059 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
\r
1061 /* The DesignWare APB UART has an Busy Detect (0x07)
\r
1062 * interrupt meaning an LCR write attempt occured while the
\r
1063 * UART was busy. The interrupt must be cleared by reading
\r
1064 * the UART status register (USR) and the LCR re-written. */
\r
1066 if(!(serial_in(up, UART_USR) & UART_USR_BUSY)){
\r
1067 serial_out(up, UART_LCR, up->lcr);
\r
1070 dbg("the serial.%d is busy\n", up->port.line);
\r
1072 DEBUG_INTR("end(%d).\n", handled);
\r
1074 return IRQ_RETVAL(handled);
\r
1077 static unsigned int serial_rk_tx_empty(struct uart_port *port)
\r
1079 struct uart_rk_port *up =
\r
1080 container_of(port, struct uart_rk_port, port);
\r
1081 unsigned long flags;
\r
1084 dev_dbg(port->dev, "%s\n", __func__);
\r
1085 spin_lock_irqsave(&up->port.lock, flags);
\r
1086 lsr = serial_in(up, UART_LSR);
\r
1087 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
\r
1088 spin_unlock_irqrestore(&up->port.lock, flags);
\r
1090 return (lsr & UART_LSR_TEMT) == UART_LSR_TEMT ? TIOCSER_TEMT : 0;
\r
1093 static unsigned int serial_rk_get_mctrl(struct uart_port *port)
\r
1095 struct uart_rk_port *up =
\r
1096 container_of(port, struct uart_rk_port, port);
\r
1097 unsigned int status;
\r
1100 status = check_modem_status(up);
\r
1103 if (status & UART_MSR_DCD)
\r
1105 if (status & UART_MSR_RI)
\r
1107 if (status & UART_MSR_DSR)
\r
1109 if (status & UART_MSR_CTS)
\r
1111 dev_dbg(port->dev, "%s 0x%08x\n", __func__, ret);
\r
1115 static void serial_rk_set_mctrl(struct uart_port *port, unsigned int mctrl)
\r
1117 struct uart_rk_port *up =
\r
1118 container_of(port, struct uart_rk_port, port);
\r
1119 unsigned char mcr = 0;
\r
1121 dev_dbg(port->dev, "+%s\n", __func__);
\r
1122 if (mctrl & TIOCM_RTS)
\r
1123 mcr |= UART_MCR_RTS;
\r
1124 if (mctrl & TIOCM_DTR)
\r
1125 mcr |= UART_MCR_DTR;
\r
1126 if (mctrl & TIOCM_OUT1)
\r
1127 mcr |= UART_MCR_OUT1;
\r
1128 if (mctrl & TIOCM_OUT2)
\r
1129 mcr |= UART_MCR_OUT2;
\r
1130 if (mctrl & TIOCM_LOOP)
\r
1131 mcr |= UART_MCR_LOOP;
\r
1135 serial_out(up, UART_MCR, mcr);
\r
1136 dev_dbg(port->dev, "-serial.%d %s mcr: 0x%02x\n", port->line, __func__, mcr);
\r
1139 static void serial_rk_break_ctl(struct uart_port *port, int break_state)
\r
1141 struct uart_rk_port *up =
\r
1142 container_of(port, struct uart_rk_port, port);
\r
1143 unsigned long flags;
\r
1145 dev_dbg(port->dev, "+%s\n", __func__);
\r
1146 spin_lock_irqsave(&up->port.lock, flags);
\r
1147 if (break_state == -1)
\r
1148 up->lcr |= UART_LCR_SBC;
\r
1150 up->lcr &= ~UART_LCR_SBC;
\r
1151 serial_lcr_write(up, up->lcr);
\r
1152 spin_unlock_irqrestore(&up->port.lock, flags);
\r
1153 dev_dbg(port->dev, "-%s lcr: 0x%02x\n", __func__, up->lcr);
\r
1156 #if defined(CONFIG_SERIAL_ROCKCHIP_CONSOLE) || defined(CONFIG_CONSOLE_POLL)
\r
1158 * Wait for transmitter & holding register to empty
\r
1160 static void wait_for_xmitr(struct uart_rk_port *up, int bits)
\r
1162 unsigned int status, tmout = 10000;
\r
1164 /* Wait up to 10ms for the character(s) to be sent. */
\r
1166 status = serial_in(up, UART_LSR);
\r
1168 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
\r
1170 if ((status & bits) == bits)
\r
1179 #ifdef CONFIG_CONSOLE_POLL
\r
1181 * Console polling routines for writing and reading from the uart while
\r
1182 * in an interrupt or debug context.
\r
1185 static int serial_rk_get_poll_char(struct uart_port *port)
\r
1187 struct uart_rk_port *up =
\r
1188 container_of(port, struct uart_rk_port, port);
\r
1189 unsigned char lsr = serial_in(up, UART_LSR);
\r
1191 while (!(lsr & UART_LSR_DR))
\r
1192 lsr = serial_in(up, UART_LSR);
\r
1194 return serial_in(up, UART_RX);
\r
1197 static void serial_rk_put_poll_char(struct uart_port *port,
\r
1201 struct uart_rk_port *up =
\r
1202 container_of(port, struct uart_rk_port, port);
\r
1205 * First save the IER then disable the interrupts
\r
1207 ier = serial_in(up, UART_IER);
\r
1208 serial_out(up, UART_IER, 0);
\r
1210 wait_for_xmitr(up, UART_LSR_TEMT);
\r
1212 * Send the character out.
\r
1213 * If a LF, also do CR...
\r
1215 serial_out(up, UART_TX, c);
\r
1217 wait_for_xmitr(up, UART_LSR_TEMT);
\r
1218 serial_out(up, UART_TX, 13);
\r
1222 * Finally, wait for transmitter to become empty
\r
1223 * and restore the IER
\r
1225 wait_for_xmitr(up, UART_LSR_TEMT);
\r
1226 serial_out(up, UART_IER, ier);
\r
1229 #endif /* CONFIG_CONSOLE_POLL */
\r
1231 static int serial_rk_startup(struct uart_port *port)
\r
1233 struct uart_rk_port *up =
\r
1234 container_of(port, struct uart_rk_port, port);
\r
1235 unsigned long flags;
\r
1236 int retval, fifosize = 0;
\r
1239 dev_dbg(port->dev, "%s\n", __func__);
\r
1242 * Allocate the IRQ
\r
1244 retval = request_irq(up->port.irq, serial_rk_interrupt, up->port.irqflags,
\r
1250 #ifdef CONFIG_CLOCK_CTRL
\r
1251 clk_prepare_enable(up->clk);
\r
1252 clk_prepare_enable(up->pclk); // enable the config uart clock
\r
1255 * Clear the FIFO buffers and disable them.
\r
1256 * (they will be reenabled in set_termios())
\r
1258 serial_rk_clear_fifos(up);
\r
1260 //read uart fifo size hhb@rock-chips.com
\r
1261 fifosize = __raw_readl(up->port.membase + 0xf4);
\r
1262 up->port.fifosize = ((fifosize >> 16) & 0xff) << 4;
\r
1263 if(up->port.fifosize <= 0)
\r
1264 up->port.fifosize = 32;
\r
1265 //printk("fifo size:%d :%08x\n", up->port.fifosize, fifosize);
\r
1268 * Clear the interrupt registers.
\r
1270 (void) serial_in(up, UART_LSR);
\r
1271 (void) serial_in(up, UART_RX);
\r
1272 (void) serial_in(up, UART_IIR);
\r
1273 (void) serial_in(up, UART_MSR);
\r
1274 (void) serial_in(up, UART_USR);
\r
1277 * Now, initialize the UART
\r
1279 serial_lcr_write(up, UART_LCR_WLEN8 | UART_LCR_EPAR);
\r
1281 spin_lock_irqsave(&up->port.lock, flags);
\r
1284 * Most PC uarts need OUT2 raised to enable interrupts.
\r
1286 // up->port.mctrl |= TIOCM_OUT2;
\r
1288 serial_rk_set_mctrl(&up->port, up->port.mctrl);
\r
1290 spin_unlock_irqrestore(&up->port.lock, flags);
\r
1293 * Clear the interrupt registers again for luck, and clear the
\r
1294 * saved flags to avoid getting false values from polling
\r
1295 * routines or the previous session.
\r
1297 (void) serial_in(up, UART_LSR);
\r
1298 (void) serial_in(up, UART_RX);
\r
1299 (void) serial_in(up, UART_IIR);
\r
1300 (void) serial_in(up, UART_MSR);
\r
1301 (void) serial_in(up, UART_USR);
\r
1302 up->lsr_saved_flags = 0;
\r
1304 up->msr_saved_flags = 0;
\r
1307 if (up->dma->use_dma & TX_DMA) {
\r
1308 if(up->port.state->xmit.buf != up->dma->tx_buffer){
\r
1309 free_page((unsigned long)up->port.state->xmit.buf);
\r
1310 up->port.state->xmit.buf = up->dma->tx_buffer;
\r
1316 serial_out(up, UART_IER, up->ier);
\r
1320 * Finally, enable interrupts. Note: Modem status interrupts
\r
1321 * are set via set_termios(), which will be occurring imminently
\r
1322 * anyway, so we don't enable them here.
\r
1329 static void serial_rk_shutdown(struct uart_port *port)
\r
1331 struct uart_rk_port *up =
\r
1332 container_of(port, struct uart_rk_port, port);
\r
1333 unsigned long flags;
\r
1335 dev_dbg(port->dev, "%s\n", __func__);
\r
1337 * Disable interrupts from this port
\r
1340 serial_out(up, UART_IER, 0);
\r
1342 spin_lock_irqsave(&up->port.lock, flags);
\r
1343 // up->port.mctrl &= ~TIOCM_OUT2;
\r
1344 serial_rk_set_mctrl(&up->port, up->port.mctrl);
\r
1345 spin_unlock_irqrestore(&up->port.lock, flags);
\r
1348 * Disable break condition and FIFOs
\r
1350 serial_lcr_write(up, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
\r
1351 serial_rk_clear_fifos(up);
\r
1354 * Read data port to reset things, and then free the irq
\r
1356 (void) serial_in(up, UART_RX);
\r
1358 if (up->dma->use_dma & TX_DMA)
\r
1359 up->port.state->xmit.buf = NULL;
\r
1361 free_irq(up->port.irq, up);
\r
1362 #ifdef CONFIG_CLOCK_CTRL
\r
1363 clk_disable_unprepare(up->clk);
\r
1364 clk_disable_unprepare(up->pclk);
\r
1369 serial_rk_set_termios(struct uart_port *port, struct ktermios *termios,
\r
1370 struct ktermios *old)
\r
1372 struct uart_rk_port *up =
\r
1373 container_of(port, struct uart_rk_port, port);
\r
1374 unsigned char cval = 0, fcr = 0, mcr = 0;
\r
1375 unsigned long flags;
\r
1376 unsigned int baud, quot;
\r
1378 dev_dbg(port->dev, "+%s\n", __func__);
\r
1381 //stop dma tx, which might make the uart be busy while some registers are set
\r
1382 if(up->dma->tx_dma_used) {
\r
1383 serial_rk_stop_dma_tx(up);
\r
1387 switch (termios->c_cflag & CSIZE) {
\r
1389 cval = UART_LCR_WLEN5;
\r
1392 cval = UART_LCR_WLEN6;
\r
1395 cval = UART_LCR_WLEN7;
\r
1399 cval = UART_LCR_WLEN8;
\r
1403 if (termios->c_cflag & CSTOPB){
\r
1404 cval |= UART_LCR_STOP;
\r
1406 if (termios->c_cflag & PARENB){
\r
1407 cval |= UART_LCR_PARITY;
\r
1409 if (!(termios->c_cflag & PARODD)){
\r
1410 cval |= UART_LCR_EPAR;
\r
1413 if (termios->c_cflag & CMSPAR)
\r
1414 cval |= UART_LCR_SPAR;
\r
1419 * Ask the core to calculate the divisor for us.
\r
1421 baud = uart_get_baud_rate(port, termios, old,
\r
1422 port->uartclk / 16 / 0xffff,
\r
1423 port->uartclk / 16);
\r
1425 quot = uart_get_divisor(port, baud);
\r
1426 //dev_info(up->port.dev, "uartclk:%d\n", port->uartclk/16);
\r
1427 //dev_info(up->port.dev, "baud:%d\n", baud);
\r
1428 //dev_info(up->port.dev, "quot:%d\n", quot);
\r
1431 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
\r
1434 fcr = UART_FCR_ENABLE_FIFO;
\r
1436 //added by hhb@rock-chips.com
\r
1437 if(up->dma->use_dma & TX_DMA){
\r
1438 fcr |= UART_FCR_T_TRIG_01;
\r
1442 fcr |= UART_FCR_T_TRIG_01;
\r
1446 //added by hhb@rock-chips.com
\r
1447 if(up->dma->use_dma & RX_DMA){
\r
1448 fcr |= UART_FCR_R_TRIG_00;
\r
1452 if (termios->c_cflag & CRTSCTS)
\r
1453 fcr |= UART_FCR_R_TRIG_11;
\r
1455 fcr |= UART_FCR_R_TRIG_00;
\r
1460 * MCR-based auto flow control. When AFE is enabled, RTS will be
\r
1461 * deasserted when the receive FIFO contains more characters than
\r
1462 * the trigger, or the MCR RTS bit is cleared. In the case where
\r
1463 * the remote UART is not using CTS auto flow control, we must
\r
1464 * have sufficient FIFO entries for the latency of the remote
\r
1465 * UART to respond. IOW, at least 32 bytes of FIFO.
\r
1467 up->mcr &= ~UART_MCR_AFE;
\r
1468 if (termios->c_cflag & CRTSCTS){
\r
1469 up->mcr |= UART_MCR_AFE;
\r
1473 * Ok, we're now changing the port state. Do it with
\r
1474 * interrupts disabled.
\r
1476 spin_lock_irqsave(&up->port.lock, flags);
\r
1479 * Update the per-port timeout.
\r
1481 uart_update_timeout(port, termios->c_cflag, baud);
\r
1483 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
\r
1484 if (termios->c_iflag & INPCK)
\r
1485 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
\r
1486 if (termios->c_iflag & (BRKINT | PARMRK))
\r
1487 up->port.read_status_mask |= UART_LSR_BI;
\r
1490 * Characteres to ignore
\r
1492 up->port.ignore_status_mask = 0;
\r
1493 if (termios->c_iflag & IGNPAR)
\r
1494 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
\r
1495 if (termios->c_iflag & IGNBRK) {
\r
1496 up->port.ignore_status_mask |= UART_LSR_BI;
\r
1498 * If we're ignoring parity and break indicators,
\r
1499 * ignore overruns too (for real raw support).
\r
1501 if (termios->c_iflag & IGNPAR)
\r
1502 up->port.ignore_status_mask |= UART_LSR_OE;
\r
1506 * ignore all characters if CREAD is not set
\r
1508 if ((termios->c_cflag & CREAD) == 0)
\r
1509 up->port.ignore_status_mask |= UART_LSR_DR;
\r
1512 * CTS flow control flag and modem status interrupts
\r
1514 up->ier &= ~UART_IER_MSI;
\r
1516 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
\r
1517 up->ier |= UART_IER_MSI;
\r
1520 //to avoid uart busy when set baud rate hhb@rock-chips.com
\r
1521 serial_out(up, UART_SRR, UART_RESET);
\r
1522 mcr = serial_in(up, UART_MCR);
\r
1523 serial_out(up, UART_MCR, mcr | 0x10); //loopback mode
\r
1525 up->lcr = cval; /* Save LCR */
\r
1527 if(serial_lcr_write(up, cval | UART_LCR_DLAB)) {
\r
1528 if(up->port.line != DBG_PORT)
\r
1529 dbg("serial.%d set DLAB fail\n", up->port.line);
\r
1530 serial_out(up, UART_SRR, UART_RESET);
\r
1534 /* set uart baud rate */
\r
1535 if(serial_dl_write(up, quot)) {
\r
1536 if(up->port.line != DBG_PORT)
\r
1537 dbg("serial.%d set dll fail\n", up->port.line);
\r
1538 serial_out(up, UART_SRR, UART_RESET);
\r
1543 if(serial_lcr_write(up, cval)) {
\r
1544 if(up->port.line != DBG_PORT)
\r
1545 dbg("serial.%d reset DLAB fail\n", up->port.line);
\r
1546 serial_out(up, UART_SRR, UART_RESET);
\r
1550 serial_rk_set_mctrl(&up->port, up->port.mctrl);
\r
1552 serial_out(up, UART_FCR, up->fcr); /* set fcr */
\r
1554 //start serial receive data
\r
1556 if (up->dma->use_dma) {
\r
1557 up->ier |= UART_IER_RLSI;
\r
1558 up->ier |= UART_IER_PTIME; //Programmable THRE Interrupt Mode Enable
\r
1559 if (up->dma->use_dma & RX_DMA)
\r
1560 serial_rk_start_dma_rx(up);
\r
1562 up->ier |= UART_IER_RDI;
\r
1566 // not use dma receive
\r
1567 up->ier |= UART_IER_RDI;
\r
1568 up->ier |= UART_IER_RLSI;
\r
1569 if(up->port.line != DBG_PORT)
\r
1570 up->ier |= UART_IER_PTIME; //Programmable THRE Interrupt Mode Enable
\r
1573 serial_out(up, UART_IER, up->ier);
\r
1576 spin_unlock_irqrestore(&up->port.lock, flags);
\r
1578 /* Don't rewrite B0 */
\r
1579 if (tty_termios_baud_rate(termios))
\r
1580 tty_termios_encode_baud_rate(termios, baud, baud);
\r
1581 dev_dbg(port->dev, "-%s baud %d\n", __func__, baud);
\r
1585 spin_unlock_irqrestore(&up->port.lock, flags);
\r
1591 serial_rk_set_ldisc(struct uart_port *port, int new)
\r
1593 if (new == N_PPS) {
\r
1594 port->flags |= UPF_HARDPPS_CD;
\r
1595 serial_rk_enable_ms(port);
\r
1597 port->flags &= ~UPF_HARDPPS_CD;
\r
1602 serial_rk_pm(struct uart_port *port, unsigned int state,
\r
1603 unsigned int oldstate)
\r
1605 #ifdef CONFIG_CLOCK_CTRL
\r
1606 struct uart_rk_port *up =
\r
1607 container_of(port, struct uart_rk_port, port);
\r
1609 dev_dbg(port->dev, "%s: %s\n", __func__, state ? "disable" : "enable");
\r
1611 clk_disable_unprepare(up->clk);
\r
1612 clk_disable_unprepare(up->pclk);
\r
1614 clk_prepare_enable(up->clk);
\r
1615 clk_prepare_enable(up->pclk);
\r
1620 static void serial_rk_release_port(struct uart_port *port)
\r
1622 dev_dbg(port->dev, "%s\n", __func__);
\r
1625 static int serial_rk_request_port(struct uart_port *port)
\r
1627 dev_dbg(port->dev, "%s\n", __func__);
\r
1631 static void serial_rk_config_port(struct uart_port *port, int flags)
\r
1633 dev_dbg(port->dev, "%s\n", __func__);
\r
1634 port->type = PORT_RK;
\r
1638 serial_rk_verify_port(struct uart_port *port, struct serial_struct *ser)
\r
1640 /* we don't want the core code to modify any port params */
\r
1641 dev_dbg(port->dev, "%s\n", __func__);
\r
1645 static const char *
\r
1646 serial_rk_type(struct uart_port *port)
\r
1648 struct uart_rk_port *up =
\r
1649 container_of(port, struct uart_rk_port, port);
\r
1651 dev_dbg(port->dev, "%s: %s\n", __func__, up->name);
\r
1655 static struct uart_ops serial_rk_pops = {
\r
1656 .tx_empty = serial_rk_tx_empty,
\r
1657 .set_mctrl = serial_rk_set_mctrl,
\r
1658 .get_mctrl = serial_rk_get_mctrl,
\r
1659 .stop_tx = serial_rk_stop_tx,
\r
1660 .start_tx = serial_rk_start_tx,
\r
1661 .stop_rx = serial_rk_stop_rx,
\r
1662 .enable_ms = serial_rk_enable_ms,
\r
1663 .break_ctl = serial_rk_break_ctl,
\r
1664 .startup = serial_rk_startup,
\r
1665 .shutdown = serial_rk_shutdown,
\r
1666 .set_termios = serial_rk_set_termios,
\r
1668 .set_ldisc = serial_rk_set_ldisc,
\r
1670 .pm = serial_rk_pm,
\r
1671 .type = serial_rk_type,
\r
1672 .release_port = serial_rk_release_port,
\r
1673 .request_port = serial_rk_request_port,
\r
1674 .config_port = serial_rk_config_port,
\r
1675 .verify_port = serial_rk_verify_port,
\r
1676 #ifdef CONFIG_CONSOLE_POLL
\r
1677 .poll_get_char = serial_rk_get_poll_char,
\r
1678 .poll_put_char = serial_rk_put_poll_char,
\r
1682 #ifdef CONFIG_SERIAL_ROCKCHIP_CONSOLE
\r
1684 static struct uart_rk_port *serial_rk_console_ports[UART_NR];
\r
1686 static void serial_rk_console_putchar(struct uart_port *port, int ch)
\r
1688 struct uart_rk_port *up =
\r
1689 container_of(port, struct uart_rk_port, port);
\r
1691 wait_for_xmitr(up, UART_LSR_THRE);
\r
1692 serial_out(up, UART_TX, ch);
\r
1696 * Print a string to the serial port trying not to disturb
\r
1697 * any possible real use of the port...
\r
1699 * The console_lock must be held when we get here.
\r
1702 serial_rk_console_write(struct console *co, const char *s, unsigned int count)
\r
1704 struct uart_rk_port *up = serial_rk_console_ports[co->index];
\r
1705 unsigned long flags;
\r
1709 touch_nmi_watchdog();
\r
1711 local_irq_save(flags);
\r
1712 if (up->port.sysrq) {
\r
1713 /* serial_rk_handle_port() already took the lock */
\r
1715 } else if (oops_in_progress) {
\r
1716 locked = spin_trylock(&up->port.lock);
\r
1718 spin_lock(&up->port.lock);
\r
1721 * First save the IER then disable the interrupts
\r
1723 ier = serial_in(up, UART_IER);
\r
1725 serial_out(up, UART_IER, 0);
\r
1727 uart_console_write(&up->port, s, count, serial_rk_console_putchar);
\r
1730 * Finally, wait for transmitter to become empty
\r
1731 * and restore the IER
\r
1733 wait_for_xmitr(up, UART_LSR_TEMT);
\r
1734 serial_out(up, UART_IER, ier);
\r
1738 * The receive handling will happen properly because the
\r
1739 * receive ready bit will still be set; it is not cleared
\r
1740 * on read. However, modem control will not, we must
\r
1741 * call it if we have saved something in the saved flags
\r
1742 * while processing with interrupts off.
\r
1744 if (up->msr_saved_flags)
\r
1745 check_modem_status(up);
\r
1749 spin_unlock(&up->port.lock);
\r
1750 local_irq_restore(flags);
\r
1753 static int __init serial_rk_console_setup(struct console *co, char *options)
\r
1755 struct uart_rk_port *up;
\r
1756 int baud = 115200;
\r
1761 if (unlikely(co->index >= UART_NR || co->index < 0))
\r
1764 if (serial_rk_console_ports[co->index] == NULL)
\r
1766 up = serial_rk_console_ports[co->index];
\r
1769 uart_parse_options(options, &baud, &parity, &bits, &flow);
\r
1771 return uart_set_options(&up->port, co, baud, parity, bits, flow);
\r
1774 static struct console serial_rk_console = {
\r
1776 .write = serial_rk_console_write,
\r
1777 .device = uart_console_device,
\r
1778 .setup = serial_rk_console_setup,
\r
1779 .flags = CON_PRINTBUFFER | CON_ANYTIME,
\r
1781 .data = &serial_rk_reg,
\r
1784 static void serial_rk_add_console_port(struct uart_rk_port *up)
\r
1786 serial_rk_console_ports[up->pdev->id] = up;
\r
1789 #define SERIAL_CONSOLE &serial_rk_console
\r
1791 #define SERIAL_CONSOLE NULL
\r
1793 static inline void serial_rk_add_console_port(struct uart_rk_port *up)
\r
1798 static struct uart_driver serial_rk_reg = {
\r
1799 .owner = THIS_MODULE,
\r
1800 .driver_name = "rk_serial",
\r
1801 .dev_name = "ttyS",
\r
1802 .major = TTY_MAJOR,
\r
1804 .cons = SERIAL_CONSOLE,
\r
1808 static irqreturn_t serial_rk_wakeup_handler(int irq, void *dev) {
\r
1809 struct uart_rk_port *up = dev;
\r
1810 struct uart_wake_up *wakeup = up->wakeup;
\r
1811 if(wakeup->enable == 1) {
\r
1812 iomux_set(wakeup->rx_mode);
\r
1813 wake_lock_timeout(&wakeup->wakelock, 3 * HZ);
\r
1818 static int serial_rk_setup_wakeup_irq(struct uart_rk_port *up)
\r
1821 struct uart_wake_up *wakeup = up->wakeup;
\r
1823 if(wakeup->enable == 1) {
\r
1824 memset(wakeup->wakelock_name, 0, 32);
\r
1825 sprintf(wakeup->wakelock_name, "serial.%d_wakelock", up->port.line);
\r
1826 wake_lock_init(&wakeup->wakelock, WAKE_LOCK_SUSPEND, wakeup->wakelock_name);
\r
1827 memset(wakeup->rx_pin_name, 0, 32);
\r
1828 sprintf(wakeup->rx_pin_name, "UART%d_SIN", up->port.line);
\r
1829 wakeup->rx_pin = iomux_mode_to_gpio(wakeup->rx_mode);
\r
1830 ret = gpio_request(wakeup->rx_pin, wakeup->rx_pin_name);
\r
1832 printk("request %s fail ! \n", wakeup->rx_pin_name);
\r
1835 gpio_direction_input(wakeup->rx_pin);
\r
1836 wakeup->rx_irq = gpio_to_irq(wakeup->rx_pin);
\r
1837 memset(wakeup->rx_irq_name, 0, 32);
\r
1838 sprintf(wakeup->rx_irq_name, "serial.%d_wake_up_irq", up->port.line);
\r
1839 ret = request_irq(wakeup->rx_irq, serial_rk_wakeup_handler, IRQF_TRIGGER_FALLING, wakeup->rx_irq_name, up);
\r
1841 printk("%s request fail\n", wakeup->rx_irq_name);
\r
1844 disable_irq_nosync(wakeup->rx_irq);
\r
1845 enable_irq_wake(wakeup->rx_irq);
\r
1846 iomux_set(wakeup->rx_mode);
\r
1851 static int serial_rk_enable_wakeup_irq(struct uart_rk_port *up) {
\r
1852 struct uart_wake_up *wakeup = up->wakeup;
\r
1853 if(wakeup->enable == 1) {
\r
1854 iomux_set(wakeup->rx_mode & 0xfff0);
\r
1855 enable_irq(wakeup->rx_irq);
\r
1860 static int serial_rk_disable_wakeup_irq(struct uart_rk_port *up) {
\r
1861 struct uart_wake_up *wakeup = up->wakeup;
\r
1862 if(wakeup->enable == 1) {
\r
1863 disable_irq_nosync(wakeup->rx_irq);
\r
1864 iomux_set(wakeup->rx_mode);
\r
1869 static int serial_rk_remove_wakeup_irq(struct uart_rk_port *up) {
\r
1870 struct uart_wake_up *wakeup = up->wakeup;
\r
1871 if(wakeup->enable == 1) {
\r
1872 //disable_irq_nosync(wakeup->rx_irq);
\r
1873 free_irq(wakeup->rx_irq, NULL);
\r
1874 gpio_free(wakeup->rx_pin);
\r
1875 wake_lock_destroy(&wakeup->wakelock);
\r
1882 static int of_rk_serial_parse_dt(struct device_node *np, struct of_rk_serial *rks)
\r
1884 unsigned int val = 0;
\r
1885 const char *s = NULL;
\r
1887 rks->id = of_alias_get_id(np, "serial");
\r
1888 if(!of_property_read_u32(np, "clock-frequency", &val))
\r
1889 rks->uartclk = val;
\r
1893 for(i = 0; i < 2; i++) {
\r
1894 ret = of_property_read_string_index(np, "dma-names", i, &s);
\r
1896 if(!strcmp(s, "tx"))
\r
1897 rks->use_dma |= TX_DMA;
\r
1898 else if (!strcmp(s, "rx"))
\r
1899 rks->use_dma |= RX_DMA;
\r
1907 static int serial_rk_probe(struct platform_device *pdev)
\r
1909 struct uart_rk_port *up;
\r
1910 struct resource *mem;
\r
1912 int ret = -ENOSPC;
\r
1913 struct of_rk_serial rks;
\r
1915 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
\r
1919 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
\r
1920 up->port.membase = devm_request_and_ioremap(&pdev->dev, mem);
\r
1921 if (!up->port.membase)
\r
1924 irq = platform_get_irq(pdev, 0);
\r
1926 dev_err(&pdev->dev, "no irq resource?\n");
\r
1931 of_rk_serial_parse_dt(pdev->dev.of_node, &rks);
\r
1932 pdev->id = rks.id;
\r
1935 sprintf(up->name, "rk29_serial.%d", pdev->id);
\r
1937 #ifdef CONFIG_CLOCK_CTRL
\r
1938 up->pclk = devm_clk_get(&pdev->dev, "pclk_uart");
\r
1939 up->clk = devm_clk_get(&pdev->dev, "sclk_uart");
\r
1940 if (unlikely(IS_ERR(up->clk)) || unlikely(IS_ERR(up->pclk))) {
\r
1941 dev_err(&pdev->dev, "get clock fail\n");
\r
1945 up->tx_loadsz = 30;
\r
1947 up->dma = devm_kzalloc(&pdev->dev, sizeof(struct rk_uart_dma), GFP_KERNEL);
\r
1949 dev_err(&pdev->dev, "unable to allocate mem\n");
\r
1952 up->dma->use_dma = rks.use_dma;
\r
1955 up->wakeup = &rk29_uart_ports_wakeup[pdev->id];
\r
1957 up->port.dev = &pdev->dev;
\r
1958 up->port.type = PORT_RK;
\r
1959 up->port.irq = irq;
\r
1960 up->port.iotype = UPIO_MEM;
\r
1962 up->port.regshift = 2;
\r
1963 //fifo size default is 32, but it will be updated later when start_up
\r
1964 up->port.fifosize = 32;
\r
1965 up->port.ops = &serial_rk_pops;
\r
1966 up->port.line = pdev->id;
\r
1967 up->port.iobase = mem->start;
\r
1968 up->port.mapbase = mem->start;
\r
1969 up->port.irqflags = IRQF_DISABLED;
\r
1970 #if defined(CONFIG_CLOCK_CTRL)
\r
1971 up->port.uartclk = clk_get_rate(up->clk);
\r
1972 #elif defined(CONFIG_OF)
\r
1973 up->port.uartclk = rks.uartclk;
\r
1975 up->port.uartclk = 24000000;
\r
1979 /* set dma config */
\r
1980 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
\r
1981 if(up->dma->use_dma & RX_DMA) {
\r
1983 up->dma->use_timer = USE_TIMER;
\r
1984 up->dma->rx_timer.function = serial_rk_report_dma_rx;
\r
1985 up->dma->rx_timer.data = (unsigned long)up;
\r
1986 up->dma->rx_timeout = 10;
\r
1987 up->dma->rx_timer.expires = jiffies + msecs_to_jiffies(up->dma->rx_timeout);
\r
1988 init_timer(&up->dma->rx_timer);
\r
1991 up->dma->rb_size = DMA_SERIAL_BUFFER_SIZE;
\r
1992 up->dma->rx_buffer = dmam_alloc_coherent(up->port.dev, up->dma->rb_size,
\r
1993 &up->dma->rx_phy_addr, DMA_MEMORY_MAP);
\r
1994 up->dma->rb_tail = 0;
\r
1995 up->dma->rx_dma_inited = 0;
\r
1996 up->dma->rx_dma_used = 0;
\r
1998 if(!up->dma->rx_buffer){
\r
1999 dev_info(up->port.dev, "dmam_alloc_coherent dma_rx_buffer fail\n");
\r
2002 dev_info(up->port.dev, "dma_rx_buffer %p\n", up->dma->rx_buffer);
\r
2003 dev_info(up->port.dev, "dma_rx_phy 0x%08x\n", (unsigned)up->dma->rx_phy_addr);
\r
2007 //INIT_WORK(&up->uart_work, serial_rk_report_revdata_workfunc);
\r
2008 //INIT_WORK(&up->uart_work_rx, serial_rk_start_dma_rx);
\r
2009 //up->uart_wq = create_singlethread_workqueue("uart_workqueue");
\r
2010 spin_lock_init(&(up->dma->rx_lock));
\r
2011 serial_rk_init_dma_rx(up);
\r
2014 if(up->dma->use_dma & TX_DMA){
\r
2016 up->dma->tb_size = UART_XMIT_SIZE;
\r
2017 up->dma->tx_buffer = dmam_alloc_coherent(up->port.dev, up->dma->tb_size,
\r
2018 &up->dma->tx_phy_addr, DMA_MEMORY_MAP);
\r
2019 if(!up->dma->tx_buffer){
\r
2020 dev_info(up->port.dev, "dmam_alloc_coherent dma_tx_buffer fail\n");
\r
2023 dev_info(up->port.dev, "dma_tx_buffer %p\n", up->dma->tx_buffer);
\r
2024 dev_info(up->port.dev, "dma_tx_phy 0x%08x\n", (unsigned) up->dma->tx_phy_addr);
\r
2026 spin_lock_init(&(up->dma->tx_lock));
\r
2027 serial_rk_init_dma_tx(up);
\r
2032 serial_rk_add_console_port(up);
\r
2033 ret = uart_add_one_port(&serial_rk_reg, &up->port);
\r
2036 platform_set_drvdata(pdev, up);
\r
2037 dev_info(&pdev->dev, "membase %p\n", up->port.membase);
\r
2039 serial_rk_setup_wakeup_irq(up);
\r
2044 static int serial_rk_remove(struct platform_device *pdev)
\r
2046 struct uart_rk_port *up = platform_get_drvdata(pdev);
\r
2048 platform_set_drvdata(pdev, NULL);
\r
2051 serial_rk_release_dma_tx(up);
\r
2052 serial_rk_release_dma_rx(up);
\r
2055 serial_rk_remove_wakeup_irq(up);
\r
2057 //destroy_workqueue(up->uart_wq);
\r
2058 uart_remove_one_port(&serial_rk_reg, &up->port);
\r
2059 up->port.membase = NULL;
\r
2065 static int serial_rk_suspend(struct platform_device *dev, pm_message_t state)
\r
2067 struct uart_rk_port *up = platform_get_drvdata(dev);
\r
2069 if (up && up->port.line != DBG_PORT && POWER_MANEGEMENT){
\r
2070 uart_suspend_port(&serial_rk_reg, &up->port);
\r
2072 if(up->port.line == DBG_PORT && POWER_MANEGEMENT){
\r
2073 serial_rk_pm(&up->port, 1, 0);
\r
2076 serial_rk_enable_wakeup_irq(up);
\r
2081 static int serial_rk_resume(struct platform_device *dev)
\r
2083 struct uart_rk_port *up = platform_get_drvdata(dev);
\r
2085 serial_rk_disable_wakeup_irq(up);
\r
2087 if (up && up->port.line != DBG_PORT && POWER_MANEGEMENT){
\r
2088 uart_resume_port(&serial_rk_reg, &up->port);
\r
2090 if(up->port.line == DBG_PORT && POWER_MANEGEMENT){
\r
2091 serial_rk_pm(&up->port, 0, 1);
\r
2096 static const struct of_device_id of_rk_serial_match[] = {
\r
2097 { .compatible = "rockchip,serial" },
\r
2098 { /* Sentinel */ }
\r
2101 static struct platform_driver serial_rk_driver = {
\r
2102 .probe = serial_rk_probe,
\r
2103 .remove = serial_rk_remove,
\r
2104 .suspend = serial_rk_suspend,
\r
2105 .resume = serial_rk_resume,
\r
2109 .of_match_table = of_rk_serial_match,
\r
2111 .owner = THIS_MODULE,
\r
2115 static int __init serial_rk_init(void)
\r
2118 //hhb@rock-chips.com
\r
2119 printk("%s\n", VERSION_AND_TIME);
\r
2120 ret = uart_register_driver(&serial_rk_reg);
\r
2123 ret = platform_driver_register(&serial_rk_driver);
\r
2125 uart_unregister_driver(&serial_rk_reg);
\r
2129 static void __exit serial_rk_exit(void)
\r
2131 platform_driver_unregister(&serial_rk_driver);
\r
2132 uart_unregister_driver(&serial_rk_reg);
\r
2135 module_init(serial_rk_init);
\r
2136 module_exit(serial_rk_exit);
\r
2138 MODULE_LICENSE("GPL");
\r
2139 MODULE_DESCRIPTION("RK UART driver");