drivers/tty/serial/pch_uart.c

   1 /*
   2  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  *This program is free software; you can redistribute it and/or modify
   5  *it under the terms of the GNU General Public License as published by
   6  *the Free Software Foundation; version 2 of the License.
   7  *
   8  *This program is distributed in the hope that it will be useful,
   9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *GNU General Public License for more details.
  12  *
  13  *You should have received a copy of the GNU General Public License
  14  *along with this program; if not, write to the Free Software
  15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  18 #define SUPPORT_SYSRQ
  19 #endif
  20 #include <linux/kernel.h>
  21 #include <linux/serial_reg.h>
  22 #include <linux/slab.h>
  23 #include <linux/module.h>
  24 #include <linux/pci.h>
  25 #include <linux/console.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/tty.h>
  28 #include <linux/tty_flip.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/dmi.h>
  32 #include <linux/nmi.h>
  33 #include <linux/delay.h>
  34
  35 #include <linux/debugfs.h>
  36 #include <linux/dmaengine.h>
  37 #include <linux/pch_dma.h>
  38
  39 enum {
  40         PCH_UART_HANDLED_RX_INT_SHIFT,
  41         PCH_UART_HANDLED_TX_INT_SHIFT,
  42         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  43         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  44         PCH_UART_HANDLED_MS_INT_SHIFT,
  45         PCH_UART_HANDLED_LS_INT_SHIFT,
  46 };
  47
  48 enum {
  49         PCH_UART_8LINE,
  50         PCH_UART_2LINE,
  51 };
  52
  53 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  54
  55 /* Set the max number of UART port
  56  * Intel EG20T PCH: 4 port
  57  * LAPIS Semiconductor ML7213 IOH: 3 port
  58  * LAPIS Semiconductor ML7223 IOH: 2 port
  59 */
  60 #define PCH_UART_NR     4
  61
  62 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  63 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  64 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  65                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  66 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  67                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  68 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  69
  70 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
  71
  72 #define PCH_UART_RBR            0x00
  73 #define PCH_UART_THR            0x00
  74
  75 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  76                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  77 #define PCH_UART_IER_ERBFI      0x00000001
  78 #define PCH_UART_IER_ETBEI      0x00000002
  79 #define PCH_UART_IER_ELSI       0x00000004
  80 #define PCH_UART_IER_EDSSI      0x00000008
  81
  82 #define PCH_UART_IIR_IP                 0x00000001
  83 #define PCH_UART_IIR_IID                0x00000006
  84 #define PCH_UART_IIR_MSI                0x00000000
  85 #define PCH_UART_IIR_TRI                0x00000002
  86 #define PCH_UART_IIR_RRI                0x00000004
  87 #define PCH_UART_IIR_REI                0x00000006
  88 #define PCH_UART_IIR_TOI                0x00000008
  89 #define PCH_UART_IIR_FIFO256            0x00000020
  90 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  91 #define PCH_UART_IIR_FE                 0x000000C0
  92
  93 #define PCH_UART_FCR_FIFOE              0x00000001
  94 #define PCH_UART_FCR_RFR                0x00000002
  95 #define PCH_UART_FCR_TFR                0x00000004
  96 #define PCH_UART_FCR_DMS                0x00000008
  97 #define PCH_UART_FCR_FIFO256            0x00000020
  98 #define PCH_UART_FCR_RFTL               0x000000C0
  99
 100 #define PCH_UART_FCR_RFTL1              0x00000000
 101 #define PCH_UART_FCR_RFTL64             0x00000040
 102 #define PCH_UART_FCR_RFTL128            0x00000080
 103 #define PCH_UART_FCR_RFTL224            0x000000C0
 104 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
 105 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
 106 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
 107 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
 108 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
 109 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
 110 #define PCH_UART_FCR_RFTL_SHIFT         6
 111
 112 #define PCH_UART_LCR_WLS        0x00000003
 113 #define PCH_UART_LCR_STB        0x00000004
 114 #define PCH_UART_LCR_PEN        0x00000008
 115 #define PCH_UART_LCR_EPS        0x00000010
 116 #define PCH_UART_LCR_SP         0x00000020
 117 #define PCH_UART_LCR_SB         0x00000040
 118 #define PCH_UART_LCR_DLAB       0x00000080
 119 #define PCH_UART_LCR_NP         0x00000000
 120 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 121 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 122 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 123 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 124                                 PCH_UART_LCR_SP)
 125
 126 #define PCH_UART_LCR_5BIT       0x00000000
 127 #define PCH_UART_LCR_6BIT       0x00000001
 128 #define PCH_UART_LCR_7BIT       0x00000002
 129 #define PCH_UART_LCR_8BIT       0x00000003
 130
 131 #define PCH_UART_MCR_DTR        0x00000001
 132 #define PCH_UART_MCR_RTS        0x00000002
 133 #define PCH_UART_MCR_OUT        0x0000000C
 134 #define PCH_UART_MCR_LOOP       0x00000010
 135 #define PCH_UART_MCR_AFE        0x00000020
 136
 137 #define PCH_UART_LSR_DR         0x00000001
 138 #define PCH_UART_LSR_ERR        (1<<7)
 139
 140 #define PCH_UART_MSR_DCTS       0x00000001
 141 #define PCH_UART_MSR_DDSR       0x00000002
 142 #define PCH_UART_MSR_TERI       0x00000004
 143 #define PCH_UART_MSR_DDCD       0x00000008
 144 #define PCH_UART_MSR_CTS        0x00000010
 145 #define PCH_UART_MSR_DSR        0x00000020
 146 #define PCH_UART_MSR_RI         0x00000040
 147 #define PCH_UART_MSR_DCD        0x00000080
 148 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 149                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 150
 151 #define PCH_UART_DLL            0x00
 152 #define PCH_UART_DLM            0x01
 153
 154 #define PCH_UART_BRCSR          0x0E
 155
 156 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 157 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 158 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 159 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 160 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 161
 162 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 163 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 164 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 165 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 166 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 167 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 168 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 169 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 170 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 171 #define PCH_UART_HAL_STB1               0
 172 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 173
 174 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 175 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 176 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 177                                         PCH_UART_HAL_CLR_RX_FIFO)
 178
 179 #define PCH_UART_HAL_DMA_MODE0          0
 180 #define PCH_UART_HAL_FIFO_DIS           0
 181 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 182 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 183                                         PCH_UART_FCR_FIFO256)
 184 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 185 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 186 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 187 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 188 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 189 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 190 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 191 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 192 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 193 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 194 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 195 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 196 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 197 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 198
 199 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 200 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 201 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 202 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 203 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 204
 205 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 206 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 207 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 208 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 209 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 210
 211 #define PCI_VENDOR_ID_ROHM              0x10DB
 212
 213 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 214
 215 #define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
 216 #define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
 217 #define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
 218 #define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
 219 #define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
 220 #define MINNOW_UARTCLK   50000000 /*  50.0000 MHz */
 221
 222 struct pch_uart_buffer {
 223         unsigned char *buf;
 224         int size;
 225 };
 226
 227 struct eg20t_port {
 228         struct uart_port port;
 229         int port_type;
 230         void __iomem *membase;
 231         resource_size_t mapbase;
 232         unsigned int iobase;
 233         struct pci_dev *pdev;
 234         int fifo_size;
 235         int uartclk;
 236         int start_tx;
 237         int start_rx;
 238         int tx_empty;
 239         int trigger;
 240         int trigger_level;
 241         struct pch_uart_buffer rxbuf;
 242         unsigned int dmsr;
 243         unsigned int fcr;
 244         unsigned int mcr;
 245         unsigned int use_dma;
 246         struct dma_async_tx_descriptor  *desc_tx;
 247         struct dma_async_tx_descriptor  *desc_rx;
 248         struct pch_dma_slave            param_tx;
 249         struct pch_dma_slave            param_rx;
 250         struct dma_chan                 *chan_tx;
 251         struct dma_chan                 *chan_rx;
 252         struct scatterlist              *sg_tx_p;
 253         int                             nent;
 254         struct scatterlist              sg_rx;
 255         int                             tx_dma_use;
 256         void                            *rx_buf_virt;
 257         dma_addr_t                      rx_buf_dma;
 258
 259         struct dentry   *debugfs;
 260
 261         /* protect the eg20t_port private structure and io access to membase */
 262         spinlock_t lock;
 263 };
 264
 265 /**
 266  * struct pch_uart_driver_data - private data structure for UART-DMA
 267  * @port_type:                  The number of DMA channel
 268  * @line_no:                    UART port line number (0, 1, 2...)
 269  */
 270 struct pch_uart_driver_data {
 271         int port_type;
 272         int line_no;
 273 };
 274
 275 enum pch_uart_num_t {
 276         pch_et20t_uart0 = 0,
 277         pch_et20t_uart1,
 278         pch_et20t_uart2,
 279         pch_et20t_uart3,
 280         pch_ml7213_uart0,
 281         pch_ml7213_uart1,
 282         pch_ml7213_uart2,
 283         pch_ml7223_uart0,
 284         pch_ml7223_uart1,
 285         pch_ml7831_uart0,
 286         pch_ml7831_uart1,
 287 };
 288
 289 static struct pch_uart_driver_data drv_dat[] = {
 290         [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
 291         [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
 292         [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
 293         [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
 294         [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
 295         [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
 296         [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
 297         [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
 298         [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
 299         [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
 300         [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
 301 };
 302
 303 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
 304 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
 305 #endif
 306 static unsigned int default_baud = 9600;
 307 static unsigned int user_uartclk = 0;
 308 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 309 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 310 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 311 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 312
 313 #ifdef CONFIG_DEBUG_FS
 314
 315 #define PCH_REGS_BUFSIZE        1024
 316
 317
 318 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 319                                 size_t count, loff_t *ppos)
 320 {
 321         struct eg20t_port *priv = file->private_data;
 322         char *buf;
 323         u32 len = 0;
 324         ssize_t ret;
 325         unsigned char lcr;
 326
 327         buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
 328         if (!buf)
 329                 return 0;
 330
 331         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 332                         "PCH EG20T port[%d] regs:\n", priv->port.line);
 333
 334         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 335                         "=================================\n");
 336         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 337                         "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
 338         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 339                         "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
 340         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 341                         "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
 342         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 343                         "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
 344         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 345                         "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
 346         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 347                         "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
 348         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 349                         "BRCSR: \t0x%02x\n",
 350                         ioread8(priv->membase + PCH_UART_BRCSR));
 351
 352         lcr = ioread8(priv->membase + UART_LCR);
 353         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 354         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 355                         "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
 356         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 357                         "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
 358         iowrite8(lcr, priv->membase + UART_LCR);
 359
 360         if (len > PCH_REGS_BUFSIZE)
 361                 len = PCH_REGS_BUFSIZE;
 362
 363         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 364         kfree(buf);
 365         return ret;
 366 }
 367
 368 static const struct file_operations port_regs_ops = {
 369         .owner          = THIS_MODULE,
 370         .open           = simple_open,
 371         .read           = port_show_regs,
 372         .llseek         = default_llseek,
 373 };
 374 #endif  /* CONFIG_DEBUG_FS */
 375
 376 /* Return UART clock, checking for board specific clocks. */
 377 static int pch_uart_get_uartclk(void)
 378 {
 379         const char *cmp;
 380
 381         if (user_uartclk)
 382                 return user_uartclk;
 383
 384         cmp = dmi_get_system_info(DMI_BOARD_NAME);
 385         if (cmp && strstr(cmp, "CM-iTC"))
 386                 return CMITC_UARTCLK;
 387
 388         cmp = dmi_get_system_info(DMI_BIOS_VERSION);
 389         if (cmp && strnstr(cmp, "FRI2", 4))
 390                 return FRI2_64_UARTCLK;
 391
 392         cmp = dmi_get_system_info(DMI_PRODUCT_NAME);
 393         if (cmp && strstr(cmp, "Fish River Island II"))
 394                 return FRI2_48_UARTCLK;
 395
 396         /* Kontron COMe-mTT10 (nanoETXexpress-TT) */
 397         cmp = dmi_get_system_info(DMI_BOARD_NAME);
 398         if (cmp && (strstr(cmp, "COMe-mTT") ||
 399                     strstr(cmp, "nanoETXexpress-TT")))
 400                 return NTC1_UARTCLK;
 401
 402         cmp = dmi_get_system_info(DMI_BOARD_NAME);
 403         if (cmp && strstr(cmp, "MinnowBoard"))
 404                 return MINNOW_UARTCLK;
 405
 406         return DEFAULT_UARTCLK;
 407 }
 408
 409 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 410                                           unsigned int flag)
 411 {
 412         u8 ier = ioread8(priv->membase + UART_IER);
 413         ier |= flag & PCH_UART_IER_MASK;
 414         iowrite8(ier, priv->membase + UART_IER);
 415 }
 416
 417 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 418                                            unsigned int flag)
 419 {
 420         u8 ier = ioread8(priv->membase + UART_IER);
 421         ier &= ~(flag & PCH_UART_IER_MASK);
 422         iowrite8(ier, priv->membase + UART_IER);
 423 }
 424
 425 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
 426                                  unsigned int parity, unsigned int bits,
 427                                  unsigned int stb)
 428 {
 429         unsigned int dll, dlm, lcr;
 430         int div;
 431
 432         div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
 433         if (div < 0 || USHRT_MAX <= div) {
 434                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 435                 return -EINVAL;
 436         }
 437
 438         dll = (unsigned int)div & 0x00FFU;
 439         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 440
 441         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 442                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 443                 return -EINVAL;
 444         }
 445
 446         if (bits & ~PCH_UART_LCR_WLS) {
 447                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 448                 return -EINVAL;
 449         }
 450
 451         if (stb & ~PCH_UART_LCR_STB) {
 452                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 453                 return -EINVAL;
 454         }
 455
 456         lcr = parity;
 457         lcr |= bits;
 458         lcr |= stb;
 459
 460         dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
 461                  __func__, baud, div, lcr, jiffies);
 462         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 463         iowrite8(dll, priv->membase + PCH_UART_DLL);
 464         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 465         iowrite8(lcr, priv->membase + UART_LCR);
 466
 467         return 0;
 468 }
 469
 470 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 471                                     unsigned int flag)
 472 {
 473         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 474                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 475                         __func__, flag);
 476                 return -EINVAL;
 477         }
 478
 479         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 480         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 481                  priv->membase + UART_FCR);
 482         iowrite8(priv->fcr, priv->membase + UART_FCR);
 483
 484         return 0;
 485 }
 486
 487 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 488                                  unsigned int dmamode,
 489                                  unsigned int fifo_size, unsigned int trigger)
 490 {
 491         u8 fcr;
 492
 493         if (dmamode & ~PCH_UART_FCR_DMS) {
 494                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 495                         __func__, dmamode);
 496                 return -EINVAL;
 497         }
 498
 499         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 500                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 501                         __func__, fifo_size);
 502                 return -EINVAL;
 503         }
 504
 505         if (trigger & ~PCH_UART_FCR_RFTL) {
 506                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 507                         __func__, trigger);
 508                 return -EINVAL;
 509         }
 510
 511         switch (priv->fifo_size) {
 512         case 256:
 513                 priv->trigger_level =
 514                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 515                 break;
 516         case 64:
 517                 priv->trigger_level =
 518                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 519                 break;
 520         case 16:
 521                 priv->trigger_level =
 522                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 523                 break;
 524         default:
 525                 priv->trigger_level =
 526                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 527                 break;
 528         }
 529         fcr =
 530             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 531         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 532         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 533                  priv->membase + UART_FCR);
 534         iowrite8(fcr, priv->membase + UART_FCR);
 535         priv->fcr = fcr;
 536
 537         return 0;
 538 }
 539
 540 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 541 {
 542         unsigned int msr = ioread8(priv->membase + UART_MSR);
 543         priv->dmsr = msr & PCH_UART_MSR_DELTA;
 544         return (u8)msr;
 545 }
 546
 547 static void pch_uart_hal_write(struct eg20t_port *priv,
 548                               const unsigned char *buf, int tx_size)
 549 {
 550         int i;
 551         unsigned int thr;
 552
 553         for (i = 0; i < tx_size;) {
 554                 thr = buf[i++];
 555                 iowrite8(thr, priv->membase + PCH_UART_THR);
 556         }
 557 }
 558
 559 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 560                              int rx_size)
 561 {
 562         int i;
 563         u8 rbr, lsr;
 564         struct uart_port *port = &priv->port;
 565
 566         lsr = ioread8(priv->membase + UART_LSR);
 567         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 568              i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
 569              lsr = ioread8(priv->membase + UART_LSR)) {
 570                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 571
 572                 if (lsr & UART_LSR_BI) {
 573                         port->icount.brk++;
 574                         if (uart_handle_break(port))
 575                                 continue;
 576                 }
 577 #ifdef SUPPORT_SYSRQ
 578                 if (port->sysrq) {
 579                         if (uart_handle_sysrq_char(port, rbr))
 580                                 continue;
 581                 }
 582 #endif
 583
 584                 buf[i++] = rbr;
 585         }
 586         return i;
 587 }
 588
 589 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
 590 {
 591         return ioread8(priv->membase + UART_IIR) &\
 592                       (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
 593 }
 594
 595 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 596 {
 597         return ioread8(priv->membase + UART_LSR);
 598 }
 599
 600 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 601 {
 602         unsigned int lcr;
 603
 604         lcr = ioread8(priv->membase + UART_LCR);
 605         if (on)
 606                 lcr |= PCH_UART_LCR_SB;
 607         else
 608                 lcr &= ~PCH_UART_LCR_SB;
 609
 610         iowrite8(lcr, priv->membase + UART_LCR);
 611 }
 612
 613 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 614                    int size)
 615 {
 616         struct uart_port *port = &priv->port;
 617         struct tty_port *tport = &port->state->port;
 618
 619         tty_insert_flip_string(tport, buf, size);
 620         tty_flip_buffer_push(tport);
 621
 622         return 0;
 623 }
 624
 625 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 626 {
 627         int ret = 0;
 628         struct uart_port *port = &priv->port;
 629
 630         if (port->x_char) {
 631                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 632                         __func__, port->x_char, jiffies);
 633                 buf[0] = port->x_char;
 634                 port->x_char = 0;
 635                 ret = 1;
 636         }
 637
 638         return ret;
 639 }
 640
 641 static int dma_push_rx(struct eg20t_port *priv, int size)
 642 {
 643         struct tty_struct *tty;
 644         int room;
 645         struct uart_port *port = &priv->port;
 646         struct tty_port *tport = &port->state->port;
 647
 648         port = &priv->port;
 649         tty = tty_port_tty_get(tport);
 650         if (!tty) {
 651                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 652                 return 0;
 653         }
 654
 655         room = tty_buffer_request_room(tport, size);
 656
 657         if (room < size)
 658                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 659                          size - room);
 660         if (!room)
 661                 goto out;
 662
 663         tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
 664
 665         port->icount.rx += room;
 666 out:
 667         tty_kref_put(tty);
 668
 669         return room;
 670 }
 671
 672 static void pch_free_dma(struct uart_port *port)
 673 {
 674         struct eg20t_port *priv;
 675         priv = container_of(port, struct eg20t_port, port);
 676
 677         if (priv->chan_tx) {
 678                 dma_release_channel(priv->chan_tx);
 679                 priv->chan_tx = NULL;
 680         }
 681         if (priv->chan_rx) {
 682                 dma_release_channel(priv->chan_rx);
 683                 priv->chan_rx = NULL;
 684         }
 685
 686         if (priv->rx_buf_dma) {
 687                 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
 688                                   priv->rx_buf_dma);
 689                 priv->rx_buf_virt = NULL;
 690                 priv->rx_buf_dma = 0;
 691         }
 692
 693         return;
 694 }
 695
 696 static bool filter(struct dma_chan *chan, void *slave)
 697 {
 698         struct pch_dma_slave *param = slave;
 699
 700         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 701                                                   chan->device->dev)) {
 702                 chan->private = param;
 703                 return true;
 704         } else {
 705                 return false;
 706         }
 707 }
 708
 709 static void pch_request_dma(struct uart_port *port)
 710 {
 711         dma_cap_mask_t mask;
 712         struct dma_chan *chan;
 713         struct pci_dev *dma_dev;
 714         struct pch_dma_slave *param;
 715         struct eg20t_port *priv =
 716                                 container_of(port, struct eg20t_port, port);
 717         dma_cap_zero(mask);
 718         dma_cap_set(DMA_SLAVE, mask);
 719
 720         dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
 721                                        PCI_DEVFN(0xa, 0)); /* Get DMA's dev
 722                                                                 information */
 723         /* Set Tx DMA */
 724         param = &priv->param_tx;
 725         param->dma_dev = &dma_dev->dev;
 726         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 727
 728         param->tx_reg = port->mapbase + UART_TX;
 729         chan = dma_request_channel(mask, filter, param);
 730         if (!chan) {
 731                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 732                         __func__);
 733                 return;
 734         }
 735         priv->chan_tx = chan;
 736
 737         /* Set Rx DMA */
 738         param = &priv->param_rx;
 739         param->dma_dev = &dma_dev->dev;
 740         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 741
 742         param->rx_reg = port->mapbase + UART_RX;
 743         chan = dma_request_channel(mask, filter, param);
 744         if (!chan) {
 745                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 746                         __func__);
 747                 dma_release_channel(priv->chan_tx);
 748                 priv->chan_tx = NULL;
 749                 return;
 750         }
 751
 752         /* Get Consistent memory for DMA */
 753         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 754                                     &priv->rx_buf_dma, GFP_KERNEL);
 755         priv->chan_rx = chan;
 756 }
 757
 758 static void pch_dma_rx_complete(void *arg)
 759 {
 760         struct eg20t_port *priv = arg;
 761         struct uart_port *port = &priv->port;
 762         int count;
 763
 764         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 765         count = dma_push_rx(priv, priv->trigger_level);
 766         if (count)
 767                 tty_flip_buffer_push(&port->state->port);
 768         async_tx_ack(priv->desc_rx);
 769         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
 770                                             PCH_UART_HAL_RX_ERR_INT);
 771 }
 772
 773 static void pch_dma_tx_complete(void *arg)
 774 {
 775         struct eg20t_port *priv = arg;
 776         struct uart_port *port = &priv->port;
 777         struct circ_buf *xmit = &port->state->xmit;
 778         struct scatterlist *sg = priv->sg_tx_p;
 779         int i;
 780
 781         for (i = 0; i < priv->nent; i++, sg++) {
 782                 xmit->tail += sg_dma_len(sg);
 783                 port->icount.tx += sg_dma_len(sg);
 784         }
 785         xmit->tail &= UART_XMIT_SIZE - 1;
 786         async_tx_ack(priv->desc_tx);
 787         dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
 788         priv->tx_dma_use = 0;
 789         priv->nent = 0;
 790         kfree(priv->sg_tx_p);
 791         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 792 }
 793
 794 static int pop_tx(struct eg20t_port *priv, int size)
 795 {
 796         int count = 0;
 797         struct uart_port *port = &priv->port;
 798         struct circ_buf *xmit = &port->state->xmit;
 799
 800         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 801                 goto pop_tx_end;
 802
 803         do {
 804                 int cnt_to_end =
 805                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 806                 int sz = min(size - count, cnt_to_end);
 807                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 808                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 809                 count += sz;
 810         } while (!uart_circ_empty(xmit) && count < size);
 811
 812 pop_tx_end:
 813         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 814                  count, size - count, jiffies);
 815
 816         return count;
 817 }
 818
 819 static int handle_rx_to(struct eg20t_port *priv)
 820 {
 821         struct pch_uart_buffer *buf;
 822         int rx_size;
 823         int ret;
 824         if (!priv->start_rx) {
 825                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
 826                                                      PCH_UART_HAL_RX_ERR_INT);
 827                 return 0;
 828         }
 829         buf = &priv->rxbuf;
 830         do {
 831                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 832                 ret = push_rx(priv, buf->buf, rx_size);
 833                 if (ret)
 834                         return 0;
 835         } while (rx_size == buf->size);
 836
 837         return PCH_UART_HANDLED_RX_INT;
 838 }
 839
 840 static int handle_rx(struct eg20t_port *priv)
 841 {
 842         return handle_rx_to(priv);
 843 }
 844
 845 static int dma_handle_rx(struct eg20t_port *priv)
 846 {
 847         struct uart_port *port = &priv->port;
 848         struct dma_async_tx_descriptor *desc;
 849         struct scatterlist *sg;
 850
 851         priv = container_of(port, struct eg20t_port, port);
 852         sg = &priv->sg_rx;
 853
 854         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 855
 856         sg_dma_len(sg) = priv->trigger_level;
 857
 858         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 859                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
 860                      ~PAGE_MASK);
 861
 862         sg_dma_address(sg) = priv->rx_buf_dma;
 863
 864         desc = dmaengine_prep_slave_sg(priv->chan_rx,
 865                         sg, 1, DMA_DEV_TO_MEM,
 866                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 867
 868         if (!desc)
 869                 return 0;
 870
 871         priv->desc_rx = desc;
 872         desc->callback = pch_dma_rx_complete;
 873         desc->callback_param = priv;
 874         desc->tx_submit(desc);
 875         dma_async_issue_pending(priv->chan_rx);
 876
 877         return PCH_UART_HANDLED_RX_INT;
 878 }
 879
 880 static unsigned int handle_tx(struct eg20t_port *priv)
 881 {
 882         struct uart_port *port = &priv->port;
 883         struct circ_buf *xmit = &port->state->xmit;
 884         int fifo_size;
 885         int tx_size;
 886         int size;
 887         int tx_empty;
 888
 889         if (!priv->start_tx) {
 890                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 891                         __func__, jiffies);
 892                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 893                 priv->tx_empty = 1;
 894                 return 0;
 895         }
 896
 897         fifo_size = max(priv->fifo_size, 1);
 898         tx_empty = 1;
 899         if (pop_tx_x(priv, xmit->buf)) {
 900                 pch_uart_hal_write(priv, xmit->buf, 1);
 901                 port->icount.tx++;
 902                 tx_empty = 0;
 903                 fifo_size--;
 904         }
 905         size = min(xmit->head - xmit->tail, fifo_size);
 906         if (size < 0)
 907                 size = fifo_size;
 908
 909         tx_size = pop_tx(priv, size);
 910         if (tx_size > 0) {
 911                 port->icount.tx += tx_size;
 912                 tx_empty = 0;
 913         }
 914
 915         priv->tx_empty = tx_empty;
 916
 917         if (tx_empty) {
 918                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 919                 uart_write_wakeup(port);
 920         }
 921
 922         return PCH_UART_HANDLED_TX_INT;
 923 }
 924
 925 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 926 {
 927         struct uart_port *port = &priv->port;
 928         struct circ_buf *xmit = &port->state->xmit;
 929         struct scatterlist *sg;
 930         int nent;
 931         int fifo_size;
 932         int tx_empty;
 933         struct dma_async_tx_descriptor *desc;
 934         int num;
 935         int i;
 936         int bytes;
 937         int size;
 938         int rem;
 939
 940         if (!priv->start_tx) {
 941                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 942                         __func__, jiffies);
 943                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 944                 priv->tx_empty = 1;
 945                 return 0;
 946         }
 947
 948         if (priv->tx_dma_use) {
 949                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 950                         __func__, jiffies);
 951                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 952                 priv->tx_empty = 1;
 953                 return 0;
 954         }
 955
 956         fifo_size = max(priv->fifo_size, 1);
 957         tx_empty = 1;
 958         if (pop_tx_x(priv, xmit->buf)) {
 959                 pch_uart_hal_write(priv, xmit->buf, 1);
 960                 port->icount.tx++;
 961                 tx_empty = 0;
 962                 fifo_size--;
 963         }
 964
 965         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 966                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 967                              xmit->tail, UART_XMIT_SIZE));
 968         if (!bytes) {
 969                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 970                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 971                 uart_write_wakeup(port);
 972                 return 0;
 973         }
 974
 975         if (bytes > fifo_size) {
 976                 num = bytes / fifo_size + 1;
 977                 size = fifo_size;
 978                 rem = bytes % fifo_size;
 979         } else {
 980                 num = 1;
 981                 size = bytes;
 982                 rem = bytes;
 983         }
 984
 985         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
 986                 __func__, num, size, rem);
 987
 988         priv->tx_dma_use = 1;
 989
 990         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
 991         if (!priv->sg_tx_p) {
 992                 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
 993                 return 0;
 994         }
 995
 996         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
 997         sg = priv->sg_tx_p;
 998
 999         for (i = 0; i < num; i++, sg++) {
1000                 if (i == (num - 1))
1001                         sg_set_page(sg, virt_to_page(xmit->buf),
1002                                     rem, fifo_size * i);
1003                 else
1004                         sg_set_page(sg, virt_to_page(xmit->buf),
1005                                     size, fifo_size * i);
1006         }
1007
1008         sg = priv->sg_tx_p;
1009         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1010         if (!nent) {
1011                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1012                 return 0;
1013         }
1014         priv->nent = nent;
1015
1016         for (i = 0; i < nent; i++, sg++) {
1017                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1018                               fifo_size * i;
1019                 sg_dma_address(sg) = (sg_dma_address(sg) &
1020                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
1021                 if (i == (nent - 1))
1022                         sg_dma_len(sg) = rem;
1023                 else
1024                         sg_dma_len(sg) = size;
1025         }
1026
1027         desc = dmaengine_prep_slave_sg(priv->chan_tx,
1028                                         priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1029                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1030         if (!desc) {
1031                 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
1032                         __func__);
1033                 return 0;
1034         }
1035         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1036         priv->desc_tx = desc;
1037         desc->callback = pch_dma_tx_complete;
1038         desc->callback_param = priv;
1039
1040         desc->tx_submit(desc);
1041
1042         dma_async_issue_pending(priv->chan_tx);
1043
1044         return PCH_UART_HANDLED_TX_INT;
1045 }
1046
1047 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1048 {
1049         struct uart_port *port = &priv->port;
1050         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1051         char   *error_msg[5] = {};
1052         int    i = 0;
1053
1054         if (lsr & PCH_UART_LSR_ERR)
1055                 error_msg[i++] = "Error data in FIFO\n";
1056
1057         if (lsr & UART_LSR_FE) {
1058                 port->icount.frame++;
1059                 error_msg[i++] = "  Framing Error\n";
1060         }
1061
1062         if (lsr & UART_LSR_PE) {
1063                 port->icount.parity++;
1064                 error_msg[i++] = "  Parity Error\n";
1065         }
1066
1067         if (lsr & UART_LSR_OE) {
1068                 port->icount.overrun++;
1069                 error_msg[i++] = "  Overrun Error\n";
1070         }
1071
1072         if (tty == NULL) {
1073                 for (i = 0; error_msg[i] != NULL; i++)
1074                         dev_err(&priv->pdev->dev, error_msg[i]);
1075         } else {
1076                 tty_kref_put(tty);
1077         }
1078 }
1079
1080 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1081 {
1082         struct eg20t_port *priv = dev_id;
1083         unsigned int handled;
1084         u8 lsr;
1085         int ret = 0;
1086         unsigned char iid;
1087         unsigned long flags;
1088         int next = 1;
1089         u8 msr;
1090
1091         spin_lock_irqsave(&priv->lock, flags);
1092         handled = 0;
1093         while (next) {
1094                 iid = pch_uart_hal_get_iid(priv);
1095                 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1096                         break;
1097                 switch (iid) {
1098                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
1099                         lsr = pch_uart_hal_get_line_status(priv);
1100                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1101                                                 UART_LSR_PE | UART_LSR_OE)) {
1102                                 pch_uart_err_ir(priv, lsr);
1103                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
1104                         } else {
1105                                 ret = PCH_UART_HANDLED_LS_INT;
1106                         }
1107                         break;
1108                 case PCH_UART_IID_RDR:  /* Received Data Ready */
1109                         if (priv->use_dma) {
1110                                 pch_uart_hal_disable_interrupt(priv,
1111                                                 PCH_UART_HAL_RX_INT |
1112                                                 PCH_UART_HAL_RX_ERR_INT);
1113                                 ret = dma_handle_rx(priv);
1114                                 if (!ret)
1115                                         pch_uart_hal_enable_interrupt(priv,
1116                                                 PCH_UART_HAL_RX_INT |
1117                                                 PCH_UART_HAL_RX_ERR_INT);
1118                         } else {
1119                                 ret = handle_rx(priv);
1120                         }
1121                         break;
1122                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
1123                                                    (FIFO Timeout) */
1124                         ret = handle_rx_to(priv);
1125                         break;
1126                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1127                                                    Empty */
1128                         if (priv->use_dma)
1129                                 ret = dma_handle_tx(priv);
1130                         else
1131                                 ret = handle_tx(priv);
1132                         break;
1133                 case PCH_UART_IID_MS:   /* Modem Status */
1134                         msr = pch_uart_hal_get_modem(priv);
1135                         next = 0; /* MS ir prioirty is the lowest. So, MS ir
1136                                      means final interrupt */
1137                         if ((msr & UART_MSR_ANY_DELTA) == 0)
1138                                 break;
1139                         ret |= PCH_UART_HANDLED_MS_INT;
1140                         break;
1141                 default:        /* Never junp to this label */
1142                         dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1143                                 iid, jiffies);
1144                         ret = -1;
1145                         next = 0;
1146                         break;
1147                 }
1148                 handled |= (unsigned int)ret;
1149         }
1150
1151         spin_unlock_irqrestore(&priv->lock, flags);
1152         return IRQ_RETVAL(handled);
1153 }
1154
1155 /* This function tests whether the transmitter fifo and shifter for the port
1156                                                 described by 'port' is empty. */
1157 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1158 {
1159         struct eg20t_port *priv;
1160
1161         priv = container_of(port, struct eg20t_port, port);
1162         if (priv->tx_empty)
1163                 return TIOCSER_TEMT;
1164         else
1165                 return 0;
1166 }
1167
1168 /* Returns the current state of modem control inputs. */
1169 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1170 {
1171         struct eg20t_port *priv;
1172         u8 modem;
1173         unsigned int ret = 0;
1174
1175         priv = container_of(port, struct eg20t_port, port);
1176         modem = pch_uart_hal_get_modem(priv);
1177
1178         if (modem & UART_MSR_DCD)
1179                 ret |= TIOCM_CAR;
1180
1181         if (modem & UART_MSR_RI)
1182                 ret |= TIOCM_RNG;
1183
1184         if (modem & UART_MSR_DSR)
1185                 ret |= TIOCM_DSR;
1186
1187         if (modem & UART_MSR_CTS)
1188                 ret |= TIOCM_CTS;
1189
1190         return ret;
1191 }
1192
1193 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1194 {
1195         u32 mcr = 0;
1196         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1197
1198         if (mctrl & TIOCM_DTR)
1199                 mcr |= UART_MCR_DTR;
1200         if (mctrl & TIOCM_RTS)
1201                 mcr |= UART_MCR_RTS;
1202         if (mctrl & TIOCM_LOOP)
1203                 mcr |= UART_MCR_LOOP;
1204
1205         if (priv->mcr & UART_MCR_AFE)
1206                 mcr |= UART_MCR_AFE;
1207
1208         if (mctrl)
1209                 iowrite8(mcr, priv->membase + UART_MCR);
1210 }
1211
1212 static void pch_uart_stop_tx(struct uart_port *port)
1213 {
1214         struct eg20t_port *priv;
1215         priv = container_of(port, struct eg20t_port, port);
1216         priv->start_tx = 0;
1217         priv->tx_dma_use = 0;
1218 }
1219
1220 static void pch_uart_start_tx(struct uart_port *port)
1221 {
1222         struct eg20t_port *priv;
1223
1224         priv = container_of(port, struct eg20t_port, port);
1225
1226         if (priv->use_dma) {
1227                 if (priv->tx_dma_use) {
1228                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1229                                 __func__);
1230                         return;
1231                 }
1232         }
1233
1234         priv->start_tx = 1;
1235         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1236 }
1237
1238 static void pch_uart_stop_rx(struct uart_port *port)
1239 {
1240         struct eg20t_port *priv;
1241         priv = container_of(port, struct eg20t_port, port);
1242         priv->start_rx = 0;
1243         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1244                                              PCH_UART_HAL_RX_ERR_INT);
1245 }
1246
1247 /* Enable the modem status interrupts. */
1248 static void pch_uart_enable_ms(struct uart_port *port)
1249 {
1250         struct eg20t_port *priv;
1251         priv = container_of(port, struct eg20t_port, port);
1252         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1253 }
1254
1255 /* Control the transmission of a break signal. */
1256 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1257 {
1258         struct eg20t_port *priv;
1259         unsigned long flags;
1260
1261         priv = container_of(port, struct eg20t_port, port);
1262         spin_lock_irqsave(&priv->lock, flags);
1263         pch_uart_hal_set_break(priv, ctl);
1264         spin_unlock_irqrestore(&priv->lock, flags);
1265 }
1266
1267 /* Grab any interrupt resources and initialise any low level driver state. */
1268 static int pch_uart_startup(struct uart_port *port)
1269 {
1270         struct eg20t_port *priv;
1271         int ret;
1272         int fifo_size;
1273         int trigger_level;
1274
1275         priv = container_of(port, struct eg20t_port, port);
1276         priv->tx_empty = 1;
1277
1278         if (port->uartclk)
1279                 priv->uartclk = port->uartclk;
1280         else
1281                 port->uartclk = priv->uartclk;
1282
1283         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1284         ret = pch_uart_hal_set_line(priv, default_baud,
1285                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1286                               PCH_UART_HAL_STB1);
1287         if (ret)
1288                 return ret;
1289
1290         switch (priv->fifo_size) {
1291         case 256:
1292                 fifo_size = PCH_UART_HAL_FIFO256;
1293                 break;
1294         case 64:
1295                 fifo_size = PCH_UART_HAL_FIFO64;
1296                 break;
1297         case 16:
1298                 fifo_size = PCH_UART_HAL_FIFO16;
1299                 break;
1300         case 1:
1301         default:
1302                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1303                 break;
1304         }
1305
1306         switch (priv->trigger) {
1307         case PCH_UART_HAL_TRIGGER1:
1308                 trigger_level = 1;
1309                 break;
1310         case PCH_UART_HAL_TRIGGER_L:
1311                 trigger_level = priv->fifo_size / 4;
1312                 break;
1313         case PCH_UART_HAL_TRIGGER_M:
1314                 trigger_level = priv->fifo_size / 2;
1315                 break;
1316         case PCH_UART_HAL_TRIGGER_H:
1317         default:
1318                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1319                 break;
1320         }
1321
1322         priv->trigger_level = trigger_level;
1323         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1324                                     fifo_size, priv->trigger);
1325         if (ret < 0)
1326                 return ret;
1327
1328         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1329                         KBUILD_MODNAME, priv);
1330         if (ret < 0)
1331                 return ret;
1332
1333         if (priv->use_dma)
1334                 pch_request_dma(port);
1335
1336         priv->start_rx = 1;
1337         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1338                                             PCH_UART_HAL_RX_ERR_INT);
1339         uart_update_timeout(port, CS8, default_baud);
1340
1341         return 0;
1342 }
1343
1344 static void pch_uart_shutdown(struct uart_port *port)
1345 {
1346         struct eg20t_port *priv;
1347         int ret;
1348
1349         priv = container_of(port, struct eg20t_port, port);
1350         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1351         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1352         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1353                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1354         if (ret)
1355                 dev_err(priv->port.dev,
1356                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1357
1358         pch_free_dma(port);
1359
1360         free_irq(priv->port.irq, priv);
1361 }
1362
1363 /* Change the port parameters, including word length, parity, stop
1364  *bits.  Update read_status_mask and ignore_status_mask to indicate
1365  *the types of events we are interested in receiving.  */
1366 static void pch_uart_set_termios(struct uart_port *port,
1367                                  struct ktermios *termios, struct ktermios *old)
1368 {
1369         int baud;
1370         int rtn;
1371         unsigned int parity, bits, stb;
1372         struct eg20t_port *priv;
1373         unsigned long flags;
1374
1375         priv = container_of(port, struct eg20t_port, port);
1376         switch (termios->c_cflag & CSIZE) {
1377         case CS5:
1378                 bits = PCH_UART_HAL_5BIT;
1379                 break;
1380         case CS6:
1381                 bits = PCH_UART_HAL_6BIT;
1382                 break;
1383         case CS7:
1384                 bits = PCH_UART_HAL_7BIT;
1385                 break;
1386         default:                /* CS8 */
1387                 bits = PCH_UART_HAL_8BIT;
1388                 break;
1389         }
1390         if (termios->c_cflag & CSTOPB)
1391                 stb = PCH_UART_HAL_STB2;
1392         else
1393                 stb = PCH_UART_HAL_STB1;
1394
1395         if (termios->c_cflag & PARENB) {
1396                 if (termios->c_cflag & PARODD)
1397                         parity = PCH_UART_HAL_PARITY_ODD;
1398                 else
1399                         parity = PCH_UART_HAL_PARITY_EVEN;
1400
1401         } else
1402                 parity = PCH_UART_HAL_PARITY_NONE;
1403
1404         /* Only UART0 has auto hardware flow function */
1405         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1406                 priv->mcr |= UART_MCR_AFE;
1407         else
1408                 priv->mcr &= ~UART_MCR_AFE;
1409
1410         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1411
1412         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1413
1414         spin_lock_irqsave(&priv->lock, flags);
1415         spin_lock(&port->lock);
1416
1417         uart_update_timeout(port, termios->c_cflag, baud);
1418         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1419         if (rtn)
1420                 goto out;
1421
1422         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1423         /* Don't rewrite B0 */
1424         if (tty_termios_baud_rate(termios))
1425                 tty_termios_encode_baud_rate(termios, baud, baud);
1426
1427 out:
1428         spin_unlock(&port->lock);
1429         spin_unlock_irqrestore(&priv->lock, flags);
1430 }
1431
1432 static const char *pch_uart_type(struct uart_port *port)
1433 {
1434         return KBUILD_MODNAME;
1435 }
1436
1437 static void pch_uart_release_port(struct uart_port *port)
1438 {
1439         struct eg20t_port *priv;
1440
1441         priv = container_of(port, struct eg20t_port, port);
1442         pci_iounmap(priv->pdev, priv->membase);
1443         pci_release_regions(priv->pdev);
1444 }
1445
1446 static int pch_uart_request_port(struct uart_port *port)
1447 {
1448         struct eg20t_port *priv;
1449         int ret;
1450         void __iomem *membase;
1451
1452         priv = container_of(port, struct eg20t_port, port);
1453         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1454         if (ret < 0)
1455                 return -EBUSY;
1456
1457         membase = pci_iomap(priv->pdev, 1, 0);
1458         if (!membase) {
1459                 pci_release_regions(priv->pdev);
1460                 return -EBUSY;
1461         }
1462         priv->membase = port->membase = membase;
1463
1464         return 0;
1465 }
1466
1467 static void pch_uart_config_port(struct uart_port *port, int type)
1468 {
1469         struct eg20t_port *priv;
1470
1471         priv = container_of(port, struct eg20t_port, port);
1472         if (type & UART_CONFIG_TYPE) {
1473                 port->type = priv->port_type;
1474                 pch_uart_request_port(port);
1475         }
1476 }
1477
1478 static int pch_uart_verify_port(struct uart_port *port,
1479                                 struct serial_struct *serinfo)
1480 {
1481         struct eg20t_port *priv;
1482
1483         priv = container_of(port, struct eg20t_port, port);
1484         if (serinfo->flags & UPF_LOW_LATENCY) {
1485                 dev_info(priv->port.dev,
1486                         "PCH UART : Use PIO Mode (without DMA)\n");
1487                 priv->use_dma = 0;
1488                 serinfo->flags &= ~UPF_LOW_LATENCY;
1489         } else {
1490 #ifndef CONFIG_PCH_DMA
1491                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1492                         __func__);
1493                 return -EOPNOTSUPP;
1494 #endif
1495                 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1496                 if (!priv->use_dma)
1497                         pch_request_dma(port);
1498                 priv->use_dma = 1;
1499         }
1500
1501         return 0;
1502 }
1503
1504 /*
1505  *      Wait for transmitter & holding register to empty
1506  */
1507 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1508 {
1509         unsigned int status, tmout = 10000;
1510
1511         /* Wait up to 10ms for the character(s) to be sent. */
1512         for (;;) {
1513                 status = ioread8(up->membase + UART_LSR);
1514
1515                 if ((status & bits) == bits)
1516                         break;
1517                 if (--tmout == 0)
1518                         break;
1519                 udelay(1);
1520         }
1521
1522         /* Wait up to 1s for flow control if necessary */
1523         if (up->port.flags & UPF_CONS_FLOW) {
1524                 unsigned int tmout;
1525                 for (tmout = 1000000; tmout; tmout--) {
1526                         unsigned int msr = ioread8(up->membase + UART_MSR);
1527                         if (msr & UART_MSR_CTS)
1528                                 break;
1529                         udelay(1);
1530                         touch_nmi_watchdog();
1531                 }
1532         }
1533 }
1534
1535 #ifdef CONFIG_CONSOLE_POLL
1536 /*
1537  * Console polling routines for communicate via uart while
1538  * in an interrupt or debug context.
1539  */
1540 static int pch_uart_get_poll_char(struct uart_port *port)
1541 {
1542         struct eg20t_port *priv =
1543                 container_of(port, struct eg20t_port, port);
1544         u8 lsr = ioread8(priv->membase + UART_LSR);
1545
1546         if (!(lsr & UART_LSR_DR))
1547                 return NO_POLL_CHAR;
1548
1549         return ioread8(priv->membase + PCH_UART_RBR);
1550 }
1551
1552
1553 static void pch_uart_put_poll_char(struct uart_port *port,
1554                          unsigned char c)
1555 {
1556         unsigned int ier;
1557         struct eg20t_port *priv =
1558                 container_of(port, struct eg20t_port, port);
1559
1560         /*
1561          * First save the IER then disable the interrupts
1562          */
1563         ier = ioread8(priv->membase + UART_IER);
1564         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1565
1566         wait_for_xmitr(priv, UART_LSR_THRE);
1567         /*
1568          * Send the character out.
1569          * If a LF, also do CR...
1570          */
1571         iowrite8(c, priv->membase + PCH_UART_THR);
1572         if (c == 10) {
1573                 wait_for_xmitr(priv, UART_LSR_THRE);
1574                 iowrite8(13, priv->membase + PCH_UART_THR);
1575         }
1576
1577         /*
1578          * Finally, wait for transmitter to become empty
1579          * and restore the IER
1580          */
1581         wait_for_xmitr(priv, BOTH_EMPTY);
1582         iowrite8(ier, priv->membase + UART_IER);
1583 }
1584 #endif /* CONFIG_CONSOLE_POLL */
1585
1586 static struct uart_ops pch_uart_ops = {
1587         .tx_empty = pch_uart_tx_empty,
1588         .set_mctrl = pch_uart_set_mctrl,
1589         .get_mctrl = pch_uart_get_mctrl,
1590         .stop_tx = pch_uart_stop_tx,
1591         .start_tx = pch_uart_start_tx,
1592         .stop_rx = pch_uart_stop_rx,
1593         .enable_ms = pch_uart_enable_ms,
1594         .break_ctl = pch_uart_break_ctl,
1595         .startup = pch_uart_startup,
1596         .shutdown = pch_uart_shutdown,
1597         .set_termios = pch_uart_set_termios,
1598 /*      .pm             = pch_uart_pm,          Not supported yet */
1599 /*      .set_wake       = pch_uart_set_wake,    Not supported yet */
1600         .type = pch_uart_type,
1601         .release_port = pch_uart_release_port,
1602         .request_port = pch_uart_request_port,
1603         .config_port = pch_uart_config_port,
1604         .verify_port = pch_uart_verify_port,
1605 #ifdef CONFIG_CONSOLE_POLL
1606         .poll_get_char = pch_uart_get_poll_char,
1607         .poll_put_char = pch_uart_put_poll_char,
1608 #endif
1609 };
1610
1611 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1612
1613 static void pch_console_putchar(struct uart_port *port, int ch)
1614 {
1615         struct eg20t_port *priv =
1616                 container_of(port, struct eg20t_port, port);
1617
1618         wait_for_xmitr(priv, UART_LSR_THRE);
1619         iowrite8(ch, priv->membase + PCH_UART_THR);
1620 }
1621
1622 /*
1623  *      Print a string to the serial port trying not to disturb
1624  *      any possible real use of the port...
1625  *
1626  *      The console_lock must be held when we get here.
1627  */
1628 static void
1629 pch_console_write(struct console *co, const char *s, unsigned int count)
1630 {
1631         struct eg20t_port *priv;
1632         unsigned long flags;
1633         int priv_locked = 1;
1634         int port_locked = 1;
1635         u8 ier;
1636
1637         priv = pch_uart_ports[co->index];
1638
1639         touch_nmi_watchdog();
1640
1641         local_irq_save(flags);
1642         if (priv->port.sysrq) {
1643                 /* call to uart_handle_sysrq_char already took the priv lock */
1644                 priv_locked = 0;
1645                 /* serial8250_handle_port() already took the port lock */
1646                 port_locked = 0;
1647         } else if (oops_in_progress) {
1648                 priv_locked = spin_trylock(&priv->lock);
1649                 port_locked = spin_trylock(&priv->port.lock);
1650         } else {
1651                 spin_lock(&priv->lock);
1652                 spin_lock(&priv->port.lock);
1653         }
1654
1655         /*
1656          *      First save the IER then disable the interrupts
1657          */
1658         ier = ioread8(priv->membase + UART_IER);
1659
1660         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1661
1662         uart_console_write(&priv->port, s, count, pch_console_putchar);
1663
1664         /*
1665          *      Finally, wait for transmitter to become empty
1666          *      and restore the IER
1667          */
1668         wait_for_xmitr(priv, BOTH_EMPTY);
1669         iowrite8(ier, priv->membase + UART_IER);
1670
1671         if (port_locked)
1672                 spin_unlock(&priv->port.lock);
1673         if (priv_locked)
1674                 spin_unlock(&priv->lock);
1675         local_irq_restore(flags);
1676 }
1677
1678 static int __init pch_console_setup(struct console *co, char *options)
1679 {
1680         struct uart_port *port;
1681         int baud = default_baud;
1682         int bits = 8;
1683         int parity = 'n';
1684         int flow = 'n';
1685
1686         /*
1687          * Check whether an invalid uart number has been specified, and
1688          * if so, search for the first available port that does have
1689          * console support.
1690          */
1691         if (co->index >= PCH_UART_NR)
1692                 co->index = 0;
1693         port = &pch_uart_ports[co->index]->port;
1694
1695         if (!port || (!port->iobase && !port->membase))
1696                 return -ENODEV;
1697
1698         port->uartclk = pch_uart_get_uartclk();
1699
1700         if (options)
1701                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1702
1703         return uart_set_options(port, co, baud, parity, bits, flow);
1704 }
1705
1706 static struct uart_driver pch_uart_driver;
1707
1708 static struct console pch_console = {
1709         .name           = PCH_UART_DRIVER_DEVICE,
1710         .write          = pch_console_write,
1711         .device         = uart_console_device,
1712         .setup          = pch_console_setup,
1713         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
1714         .index          = -1,
1715         .data           = &pch_uart_driver,
1716 };
1717
1718 #define PCH_CONSOLE     (&pch_console)
1719 #else
1720 #define PCH_CONSOLE     NULL
1721 #endif  /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1722
1723 static struct uart_driver pch_uart_driver = {
1724         .owner = THIS_MODULE,
1725         .driver_name = KBUILD_MODNAME,
1726         .dev_name = PCH_UART_DRIVER_DEVICE,
1727         .major = 0,
1728         .minor = 0,
1729         .nr = PCH_UART_NR,
1730         .cons = PCH_CONSOLE,
1731 };
1732
1733 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1734                                              const struct pci_device_id *id)
1735 {
1736         struct eg20t_port *priv;
1737         int ret;
1738         unsigned int iobase;
1739         unsigned int mapbase;
1740         unsigned char *rxbuf;
1741         int fifosize;
1742         int port_type;
1743         struct pch_uart_driver_data *board;
1744         char name[32];  /* for debugfs file name */
1745
1746         board = &drv_dat[id->driver_data];
1747         port_type = board->port_type;
1748
1749         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1750         if (priv == NULL)
1751                 goto init_port_alloc_err;
1752
1753         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1754         if (!rxbuf)
1755                 goto init_port_free_txbuf;
1756
1757         switch (port_type) {
1758         case PORT_UNKNOWN:
1759                 fifosize = 256; /* EG20T/ML7213: UART0 */
1760                 break;
1761         case PORT_8250:
1762                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1763                 break;
1764         default:
1765                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1766                 goto init_port_hal_free;
1767         }
1768
1769         pci_enable_msi(pdev);
1770         pci_set_master(pdev);
1771
1772         spin_lock_init(&priv->lock);
1773
1774         iobase = pci_resource_start(pdev, 0);
1775         mapbase = pci_resource_start(pdev, 1);
1776         priv->mapbase = mapbase;
1777         priv->iobase = iobase;
1778         priv->pdev = pdev;
1779         priv->tx_empty = 1;
1780         priv->rxbuf.buf = rxbuf;
1781         priv->rxbuf.size = PAGE_SIZE;
1782
1783         priv->fifo_size = fifosize;
1784         priv->uartclk = pch_uart_get_uartclk();
1785         priv->port_type = PORT_MAX_8250 + port_type + 1;
1786         priv->port.dev = &pdev->dev;
1787         priv->port.iobase = iobase;
1788         priv->port.membase = NULL;
1789         priv->port.mapbase = mapbase;
1790         priv->port.irq = pdev->irq;
1791         priv->port.iotype = UPIO_PORT;
1792         priv->port.ops = &pch_uart_ops;
1793         priv->port.flags = UPF_BOOT_AUTOCONF;
1794         priv->port.fifosize = fifosize;
1795         priv->port.line = board->line_no;
1796         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1797
1798         spin_lock_init(&priv->port.lock);
1799
1800         pci_set_drvdata(pdev, priv);
1801         priv->trigger_level = 1;
1802         priv->fcr = 0;
1803
1804 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1805         pch_uart_ports[board->line_no] = priv;
1806 #endif
1807         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1808         if (ret < 0)
1809                 goto init_port_hal_free;
1810
1811 #ifdef CONFIG_DEBUG_FS
1812         snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1813         priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1814                                 NULL, priv, &port_regs_ops);
1815 #endif
1816
1817         return priv;
1818
1819 init_port_hal_free:
1820 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1821         pch_uart_ports[board->line_no] = NULL;
1822 #endif
1823         free_page((unsigned long)rxbuf);
1824 init_port_free_txbuf:
1825         kfree(priv);
1826 init_port_alloc_err:
1827
1828         return NULL;
1829 }
1830
1831 static void pch_uart_exit_port(struct eg20t_port *priv)
1832 {
1833
1834 #ifdef CONFIG_DEBUG_FS
1835         if (priv->debugfs)
1836                 debugfs_remove(priv->debugfs);
1837 #endif
1838         uart_remove_one_port(&pch_uart_driver, &priv->port);
1839         pci_set_drvdata(priv->pdev, NULL);
1840         free_page((unsigned long)priv->rxbuf.buf);
1841 }
1842
1843 static void pch_uart_pci_remove(struct pci_dev *pdev)
1844 {
1845         struct eg20t_port *priv = pci_get_drvdata(pdev);
1846
1847         pci_disable_msi(pdev);
1848
1849 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1850         pch_uart_ports[priv->port.line] = NULL;
1851 #endif
1852         pch_uart_exit_port(priv);
1853         pci_disable_device(pdev);
1854         kfree(priv);
1855         return;
1856 }
1857 #ifdef CONFIG_PM
1858 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1859 {
1860         struct eg20t_port *priv = pci_get_drvdata(pdev);
1861
1862         uart_suspend_port(&pch_uart_driver, &priv->port);
1863
1864         pci_save_state(pdev);
1865         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1866         return 0;
1867 }
1868
1869 static int pch_uart_pci_resume(struct pci_dev *pdev)
1870 {
1871         struct eg20t_port *priv = pci_get_drvdata(pdev);
1872         int ret;
1873
1874         pci_set_power_state(pdev, PCI_D0);
1875         pci_restore_state(pdev);
1876
1877         ret = pci_enable_device(pdev);
1878         if (ret) {
1879                 dev_err(&pdev->dev,
1880                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1881                 return ret;
1882         }
1883
1884         uart_resume_port(&pch_uart_driver, &priv->port);
1885
1886         return 0;
1887 }
1888 #else
1889 #define pch_uart_pci_suspend NULL
1890 #define pch_uart_pci_resume NULL
1891 #endif
1892
1893 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1894         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1895          .driver_data = pch_et20t_uart0},
1896         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1897          .driver_data = pch_et20t_uart1},
1898         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1899          .driver_data = pch_et20t_uart2},
1900         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1901          .driver_data = pch_et20t_uart3},
1902         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1903          .driver_data = pch_ml7213_uart0},
1904         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1905          .driver_data = pch_ml7213_uart1},
1906         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1907          .driver_data = pch_ml7213_uart2},
1908         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1909          .driver_data = pch_ml7223_uart0},
1910         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1911          .driver_data = pch_ml7223_uart1},
1912         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1913          .driver_data = pch_ml7831_uart0},
1914         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1915          .driver_data = pch_ml7831_uart1},
1916         {0,},
1917 };
1918
1919 static int pch_uart_pci_probe(struct pci_dev *pdev,
1920                                         const struct pci_device_id *id)
1921 {
1922         int ret;
1923         struct eg20t_port *priv;
1924
1925         ret = pci_enable_device(pdev);
1926         if (ret < 0)
1927                 goto probe_error;
1928
1929         priv = pch_uart_init_port(pdev, id);
1930         if (!priv) {
1931                 ret = -EBUSY;
1932                 goto probe_disable_device;
1933         }
1934         pci_set_drvdata(pdev, priv);
1935
1936         return ret;
1937
1938 probe_disable_device:
1939         pci_disable_msi(pdev);
1940         pci_disable_device(pdev);
1941 probe_error:
1942         return ret;
1943 }
1944
1945 static struct pci_driver pch_uart_pci_driver = {
1946         .name = "pch_uart",
1947         .id_table = pch_uart_pci_id,
1948         .probe = pch_uart_pci_probe,
1949         .remove = pch_uart_pci_remove,
1950         .suspend = pch_uart_pci_suspend,
1951         .resume = pch_uart_pci_resume,
1952 };
1953
1954 static int __init pch_uart_module_init(void)
1955 {
1956         int ret;
1957
1958         /* register as UART driver */
1959         ret = uart_register_driver(&pch_uart_driver);
1960         if (ret < 0)
1961                 return ret;
1962
1963         /* register as PCI driver */
1964         ret = pci_register_driver(&pch_uart_pci_driver);
1965         if (ret < 0)
1966                 uart_unregister_driver(&pch_uart_driver);
1967
1968         return ret;
1969 }
1970 module_init(pch_uart_module_init);
1971
1972 static void __exit pch_uart_module_exit(void)
1973 {
1974         pci_unregister_driver(&pch_uart_pci_driver);
1975         uart_unregister_driver(&pch_uart_driver);
1976 }
1977 module_exit(pch_uart_module_exit);
1978
1979 MODULE_LICENSE("GPL v2");
1980 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1981 module_param(default_baud, uint, S_IRUGO);
1982 MODULE_PARM_DESC(default_baud,
1983                  "Default BAUD for initial driver state and console (default 9600)");
1984 module_param(user_uartclk, uint, S_IRUGO);
1985 MODULE_PARM_DESC(user_uartclk,
1986                  "Override UART default or board specific UART clock");