2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
5 * Copyright (C) 2010 Texas Instruments.
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * Note: This driver is made separate from 8250 driver as we cannot
17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/serial_reg.h>
31 #include <linux/delay.h>
32 #include <linux/slab.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/platform_device.h>
37 #include <linux/clk.h>
38 #include <linux/serial_core.h>
39 #include <linux/irq.h>
40 #include <linux/pm_runtime.h>
42 #include <linux/of_irq.h>
43 #include <linux/gpio.h>
44 #include <linux/of_gpio.h>
45 #include <linux/platform_data/serial-omap.h>
47 #include <dt-bindings/gpio/gpio.h>
49 #define OMAP_MAX_HSUART_PORTS 6
51 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
53 #define OMAP_UART_REV_42 0x0402
54 #define OMAP_UART_REV_46 0x0406
55 #define OMAP_UART_REV_52 0x0502
56 #define OMAP_UART_REV_63 0x0603
58 #define OMAP_UART_TX_WAKEUP_EN BIT(7)
61 #define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0)
63 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0)
64 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1)
66 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
68 /* SCR register bitmasks */
69 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
70 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
71 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
73 /* FCR register bitmasks */
74 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
75 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
77 /* MVR register bitmasks */
78 #define OMAP_UART_MVR_SCHEME_SHIFT 30
80 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
81 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
82 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
84 #define OMAP_UART_MVR_MAJ_MASK 0x700
85 #define OMAP_UART_MVR_MAJ_SHIFT 8
86 #define OMAP_UART_MVR_MIN_MASK 0x3f
88 #define OMAP_UART_DMA_CH_FREE -1
90 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
91 #define OMAP_MODE13X_SPEED 230400
94 * Enable module level wakeup in WER reg
96 #define OMAP_UART_WER_MOD_WKUP 0X7F
98 /* Enable XON/XOFF flow control on output */
99 #define OMAP_UART_SW_TX 0x08
101 /* Enable XON/XOFF flow control on input */
102 #define OMAP_UART_SW_RX 0x02
104 #define OMAP_UART_SW_CLR 0xF0
106 #define OMAP_UART_TCR_TRIG 0x0F
108 struct uart_omap_dma {
113 dma_addr_t rx_buf_dma_phys;
114 dma_addr_t tx_buf_dma_phys;
115 unsigned int uart_base;
117 * Buffer for rx dma.It is not required for tx because the buffer
118 * comes from port structure.
120 unsigned char *rx_buf;
121 unsigned int prev_rx_dma_pos;
127 /* timer to poll activity on rx dma */
128 struct timer_list rx_timer;
129 unsigned int rx_buf_size;
130 unsigned int rx_poll_rate;
131 unsigned int rx_timeout;
134 struct uart_omap_port {
135 struct uart_port port;
136 struct uart_omap_dma uart_dma;
153 * Some bits in registers are cleared on a read, so they must
154 * be saved whenever the register is read but the bits will not
155 * be immediately processed.
157 unsigned int lsr_break_flag;
158 unsigned char msr_saved_flags;
160 unsigned long port_activity;
161 int context_loss_cnt;
166 struct serial_rs485 rs485;
169 struct pm_qos_request pm_qos_request;
172 struct work_struct qos_work;
176 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
178 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
180 /* Forward declaration of functions */
181 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
183 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
185 offset <<= up->port.regshift;
186 return readw(up->port.membase + offset);
189 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
191 offset <<= up->port.regshift;
192 writew(value, up->port.membase + offset);
195 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
197 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
198 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
199 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
200 serial_out(up, UART_FCR, 0);
203 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
205 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
207 if (!pdata || !pdata->get_context_loss_count)
210 return pdata->get_context_loss_count(up->dev);
213 static inline void serial_omap_enable_wakeirq(struct uart_omap_port *up,
220 enable_irq(up->wakeirq);
222 disable_irq_nosync(up->wakeirq);
225 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
227 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
229 if (enable == up->wakeups_enabled)
232 serial_omap_enable_wakeirq(up, enable);
233 up->wakeups_enabled = enable;
235 if (!pdata || !pdata->enable_wakeup)
238 pdata->enable_wakeup(up->dev, enable);
242 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
243 * @port: uart port info
244 * @baud: baudrate for which mode needs to be determined
246 * Returns true if baud rate is MODE16X and false if MODE13X
247 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
248 * and Error Rates" determines modes not for all common baud rates.
249 * E.g. for 1000000 baud rate mode must be 16x, but according to that
250 * table it's determined as 13x.
253 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
255 unsigned int n13 = port->uartclk / (13 * baud);
256 unsigned int n16 = port->uartclk / (16 * baud);
257 int baudAbsDiff13 = baud - (port->uartclk / (13 * n13));
258 int baudAbsDiff16 = baud - (port->uartclk / (16 * n16));
259 if (baudAbsDiff13 < 0)
260 baudAbsDiff13 = -baudAbsDiff13;
261 if (baudAbsDiff16 < 0)
262 baudAbsDiff16 = -baudAbsDiff16;
264 return (baudAbsDiff13 >= baudAbsDiff16);
268 * serial_omap_get_divisor - calculate divisor value
269 * @port: uart port info
270 * @baud: baudrate for which divisor needs to be calculated.
273 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
277 if (!serial_omap_baud_is_mode16(port, baud))
281 return port->uartclk/(mode * baud);
284 static void serial_omap_enable_ms(struct uart_port *port)
286 struct uart_omap_port *up = to_uart_omap_port(port);
288 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
290 pm_runtime_get_sync(up->dev);
291 up->ier |= UART_IER_MSI;
292 serial_out(up, UART_IER, up->ier);
293 pm_runtime_mark_last_busy(up->dev);
294 pm_runtime_put_autosuspend(up->dev);
297 static void serial_omap_stop_tx(struct uart_port *port)
299 struct uart_omap_port *up = to_uart_omap_port(port);
302 pm_runtime_get_sync(up->dev);
305 if (up->rs485.flags & SER_RS485_ENABLED) {
306 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
307 /* THR interrupt is fired when both TX FIFO and TX
308 * shift register are empty. This means there's nothing
309 * left to transmit now, so make sure the THR interrupt
310 * is fired when TX FIFO is below the trigger level,
311 * disable THR interrupts and toggle the RS-485 GPIO
312 * data direction pin if needed.
314 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
315 serial_out(up, UART_OMAP_SCR, up->scr);
316 res = (up->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 1 : 0;
317 if (gpio_get_value(up->rts_gpio) != res) {
318 if (up->rs485.delay_rts_after_send > 0)
319 mdelay(up->rs485.delay_rts_after_send);
320 gpio_set_value(up->rts_gpio, res);
323 /* We're asked to stop, but there's still stuff in the
324 * UART FIFO, so make sure the THR interrupt is fired
325 * when both TX FIFO and TX shift register are empty.
326 * The next THR interrupt (if no transmission is started
327 * in the meantime) will indicate the end of a
328 * transmission. Therefore we _don't_ disable THR
329 * interrupts in this situation.
331 up->scr |= OMAP_UART_SCR_TX_EMPTY;
332 serial_out(up, UART_OMAP_SCR, up->scr);
337 if (up->ier & UART_IER_THRI) {
338 up->ier &= ~UART_IER_THRI;
339 serial_out(up, UART_IER, up->ier);
342 if ((up->rs485.flags & SER_RS485_ENABLED) &&
343 !(up->rs485.flags & SER_RS485_RX_DURING_TX)) {
345 * Empty the RX FIFO, we are not interested in anything
346 * received during the half-duplex transmission.
348 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR);
349 /* Re-enable RX interrupts */
350 up->ier |= UART_IER_RLSI | UART_IER_RDI;
351 up->port.read_status_mask |= UART_LSR_DR;
352 serial_out(up, UART_IER, up->ier);
355 pm_runtime_mark_last_busy(up->dev);
356 pm_runtime_put_autosuspend(up->dev);
359 static void serial_omap_stop_rx(struct uart_port *port)
361 struct uart_omap_port *up = to_uart_omap_port(port);
363 pm_runtime_get_sync(up->dev);
364 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
365 up->port.read_status_mask &= ~UART_LSR_DR;
366 serial_out(up, UART_IER, up->ier);
367 pm_runtime_mark_last_busy(up->dev);
368 pm_runtime_put_autosuspend(up->dev);
371 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
373 struct circ_buf *xmit = &up->port.state->xmit;
376 if (up->port.x_char) {
377 serial_out(up, UART_TX, up->port.x_char);
378 up->port.icount.tx++;
382 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
383 serial_omap_stop_tx(&up->port);
386 count = up->port.fifosize / 4;
388 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
389 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
390 up->port.icount.tx++;
391 if (uart_circ_empty(xmit))
393 } while (--count > 0);
395 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
396 uart_write_wakeup(&up->port);
398 if (uart_circ_empty(xmit))
399 serial_omap_stop_tx(&up->port);
402 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
404 if (!(up->ier & UART_IER_THRI)) {
405 up->ier |= UART_IER_THRI;
406 serial_out(up, UART_IER, up->ier);
410 static void serial_omap_start_tx(struct uart_port *port)
412 struct uart_omap_port *up = to_uart_omap_port(port);
415 pm_runtime_get_sync(up->dev);
418 if (up->rs485.flags & SER_RS485_ENABLED) {
419 /* Fire THR interrupts when FIFO is below trigger level */
420 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
421 serial_out(up, UART_OMAP_SCR, up->scr);
423 /* if rts not already enabled */
424 res = (up->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
425 if (gpio_get_value(up->rts_gpio) != res) {
426 gpio_set_value(up->rts_gpio, res);
427 if (up->rs485.delay_rts_before_send > 0)
428 mdelay(up->rs485.delay_rts_before_send);
432 if ((up->rs485.flags & SER_RS485_ENABLED) &&
433 !(up->rs485.flags & SER_RS485_RX_DURING_TX))
434 serial_omap_stop_rx(port);
436 serial_omap_enable_ier_thri(up);
437 pm_runtime_mark_last_busy(up->dev);
438 pm_runtime_put_autosuspend(up->dev);
441 static void serial_omap_throttle(struct uart_port *port)
443 struct uart_omap_port *up = to_uart_omap_port(port);
446 pm_runtime_get_sync(up->dev);
447 spin_lock_irqsave(&up->port.lock, flags);
448 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
449 serial_out(up, UART_IER, up->ier);
450 spin_unlock_irqrestore(&up->port.lock, flags);
451 pm_runtime_mark_last_busy(up->dev);
452 pm_runtime_put_autosuspend(up->dev);
455 static void serial_omap_unthrottle(struct uart_port *port)
457 struct uart_omap_port *up = to_uart_omap_port(port);
460 pm_runtime_get_sync(up->dev);
461 spin_lock_irqsave(&up->port.lock, flags);
462 up->ier |= UART_IER_RLSI | UART_IER_RDI;
463 serial_out(up, UART_IER, up->ier);
464 spin_unlock_irqrestore(&up->port.lock, flags);
465 pm_runtime_mark_last_busy(up->dev);
466 pm_runtime_put_autosuspend(up->dev);
469 static unsigned int check_modem_status(struct uart_omap_port *up)
473 status = serial_in(up, UART_MSR);
474 status |= up->msr_saved_flags;
475 up->msr_saved_flags = 0;
476 if ((status & UART_MSR_ANY_DELTA) == 0)
479 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
480 up->port.state != NULL) {
481 if (status & UART_MSR_TERI)
482 up->port.icount.rng++;
483 if (status & UART_MSR_DDSR)
484 up->port.icount.dsr++;
485 if (status & UART_MSR_DDCD)
486 uart_handle_dcd_change
487 (&up->port, status & UART_MSR_DCD);
488 if (status & UART_MSR_DCTS)
489 uart_handle_cts_change
490 (&up->port, status & UART_MSR_CTS);
491 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
497 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
500 unsigned char ch = 0;
502 if (likely(lsr & UART_LSR_DR))
503 ch = serial_in(up, UART_RX);
505 up->port.icount.rx++;
508 if (lsr & UART_LSR_BI) {
510 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
511 up->port.icount.brk++;
513 * We do the SysRQ and SAK checking
514 * here because otherwise the break
515 * may get masked by ignore_status_mask
516 * or read_status_mask.
518 if (uart_handle_break(&up->port))
523 if (lsr & UART_LSR_PE) {
525 up->port.icount.parity++;
528 if (lsr & UART_LSR_FE) {
530 up->port.icount.frame++;
533 if (lsr & UART_LSR_OE)
534 up->port.icount.overrun++;
536 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
537 if (up->port.line == up->port.cons->index) {
538 /* Recover the break flag from console xmit */
539 lsr |= up->lsr_break_flag;
542 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
545 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
547 unsigned char ch = 0;
550 if (!(lsr & UART_LSR_DR))
553 ch = serial_in(up, UART_RX);
555 up->port.icount.rx++;
557 if (uart_handle_sysrq_char(&up->port, ch))
560 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
564 * serial_omap_irq() - This handles the interrupt from one port
565 * @irq: uart port irq number
566 * @dev_id: uart port info
568 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
570 struct uart_omap_port *up = dev_id;
571 unsigned int iir, lsr;
573 irqreturn_t ret = IRQ_NONE;
576 spin_lock(&up->port.lock);
577 pm_runtime_get_sync(up->dev);
580 iir = serial_in(up, UART_IIR);
581 if (iir & UART_IIR_NO_INT)
585 lsr = serial_in(up, UART_LSR);
587 /* extract IRQ type from IIR register */
592 check_modem_status(up);
595 transmit_chars(up, lsr);
597 case UART_IIR_RX_TIMEOUT:
600 serial_omap_rdi(up, lsr);
603 serial_omap_rlsi(up, lsr);
605 case UART_IIR_CTS_RTS_DSR:
606 /* simply try again */
613 } while (!(iir & UART_IIR_NO_INT) && max_count--);
615 spin_unlock(&up->port.lock);
617 tty_flip_buffer_push(&up->port.state->port);
619 pm_runtime_mark_last_busy(up->dev);
620 pm_runtime_put_autosuspend(up->dev);
621 up->port_activity = jiffies;
626 static unsigned int serial_omap_tx_empty(struct uart_port *port)
628 struct uart_omap_port *up = to_uart_omap_port(port);
629 unsigned long flags = 0;
630 unsigned int ret = 0;
632 pm_runtime_get_sync(up->dev);
633 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
634 spin_lock_irqsave(&up->port.lock, flags);
635 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
636 spin_unlock_irqrestore(&up->port.lock, flags);
637 pm_runtime_mark_last_busy(up->dev);
638 pm_runtime_put_autosuspend(up->dev);
642 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
644 struct uart_omap_port *up = to_uart_omap_port(port);
646 unsigned int ret = 0;
648 pm_runtime_get_sync(up->dev);
649 status = check_modem_status(up);
650 pm_runtime_mark_last_busy(up->dev);
651 pm_runtime_put_autosuspend(up->dev);
653 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
655 if (status & UART_MSR_DCD)
657 if (status & UART_MSR_RI)
659 if (status & UART_MSR_DSR)
661 if (status & UART_MSR_CTS)
666 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
668 struct uart_omap_port *up = to_uart_omap_port(port);
669 unsigned char mcr = 0, old_mcr;
671 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
672 if (mctrl & TIOCM_RTS)
674 if (mctrl & TIOCM_DTR)
676 if (mctrl & TIOCM_OUT1)
677 mcr |= UART_MCR_OUT1;
678 if (mctrl & TIOCM_OUT2)
679 mcr |= UART_MCR_OUT2;
680 if (mctrl & TIOCM_LOOP)
681 mcr |= UART_MCR_LOOP;
683 pm_runtime_get_sync(up->dev);
684 old_mcr = serial_in(up, UART_MCR);
685 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
686 UART_MCR_DTR | UART_MCR_RTS);
687 up->mcr = old_mcr | mcr;
688 serial_out(up, UART_MCR, up->mcr);
689 pm_runtime_mark_last_busy(up->dev);
690 pm_runtime_put_autosuspend(up->dev);
693 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
695 struct uart_omap_port *up = to_uart_omap_port(port);
696 unsigned long flags = 0;
698 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
699 pm_runtime_get_sync(up->dev);
700 spin_lock_irqsave(&up->port.lock, flags);
701 if (break_state == -1)
702 up->lcr |= UART_LCR_SBC;
704 up->lcr &= ~UART_LCR_SBC;
705 serial_out(up, UART_LCR, up->lcr);
706 spin_unlock_irqrestore(&up->port.lock, flags);
707 pm_runtime_mark_last_busy(up->dev);
708 pm_runtime_put_autosuspend(up->dev);
711 static int serial_omap_startup(struct uart_port *port)
713 struct uart_omap_port *up = to_uart_omap_port(port);
714 unsigned long flags = 0;
720 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
725 /* Optional wake-up IRQ */
727 retval = request_irq(up->wakeirq, serial_omap_irq,
728 up->port.irqflags, up->name, up);
730 free_irq(up->port.irq, up);
733 disable_irq(up->wakeirq);
736 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
738 pm_runtime_get_sync(up->dev);
740 * Clear the FIFO buffers and disable them.
741 * (they will be reenabled in set_termios())
743 serial_omap_clear_fifos(up);
744 /* For Hardware flow control */
745 serial_out(up, UART_MCR, UART_MCR_RTS);
748 * Clear the interrupt registers.
750 (void) serial_in(up, UART_LSR);
751 if (serial_in(up, UART_LSR) & UART_LSR_DR)
752 (void) serial_in(up, UART_RX);
753 (void) serial_in(up, UART_IIR);
754 (void) serial_in(up, UART_MSR);
757 * Now, initialize the UART
759 serial_out(up, UART_LCR, UART_LCR_WLEN8);
760 spin_lock_irqsave(&up->port.lock, flags);
762 * Most PC uarts need OUT2 raised to enable interrupts.
764 up->port.mctrl |= TIOCM_OUT2;
765 serial_omap_set_mctrl(&up->port, up->port.mctrl);
766 spin_unlock_irqrestore(&up->port.lock, flags);
768 up->msr_saved_flags = 0;
770 * Finally, enable interrupts. Note: Modem status interrupts
771 * are set via set_termios(), which will be occurring imminently
772 * anyway, so we don't enable them here.
774 up->ier = UART_IER_RLSI | UART_IER_RDI;
775 serial_out(up, UART_IER, up->ier);
777 /* Enable module level wake up */
778 up->wer = OMAP_UART_WER_MOD_WKUP;
779 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
780 up->wer |= OMAP_UART_TX_WAKEUP_EN;
782 serial_out(up, UART_OMAP_WER, up->wer);
784 pm_runtime_mark_last_busy(up->dev);
785 pm_runtime_put_autosuspend(up->dev);
786 up->port_activity = jiffies;
790 static void serial_omap_shutdown(struct uart_port *port)
792 struct uart_omap_port *up = to_uart_omap_port(port);
793 unsigned long flags = 0;
795 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
797 pm_runtime_get_sync(up->dev);
799 * Disable interrupts from this port
802 serial_out(up, UART_IER, 0);
804 spin_lock_irqsave(&up->port.lock, flags);
805 up->port.mctrl &= ~TIOCM_OUT2;
806 serial_omap_set_mctrl(&up->port, up->port.mctrl);
807 spin_unlock_irqrestore(&up->port.lock, flags);
810 * Disable break condition and FIFOs
812 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
813 serial_omap_clear_fifos(up);
816 * Read data port to reset things, and then free the irq
818 if (serial_in(up, UART_LSR) & UART_LSR_DR)
819 (void) serial_in(up, UART_RX);
821 pm_runtime_mark_last_busy(up->dev);
822 pm_runtime_put_autosuspend(up->dev);
823 free_irq(up->port.irq, up);
825 free_irq(up->wakeirq, up);
828 static void serial_omap_uart_qos_work(struct work_struct *work)
830 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
833 pm_qos_update_request(&up->pm_qos_request, up->latency);
837 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
838 struct ktermios *old)
840 struct uart_omap_port *up = to_uart_omap_port(port);
841 unsigned char cval = 0;
842 unsigned long flags = 0;
843 unsigned int baud, quot;
845 switch (termios->c_cflag & CSIZE) {
847 cval = UART_LCR_WLEN5;
850 cval = UART_LCR_WLEN6;
853 cval = UART_LCR_WLEN7;
857 cval = UART_LCR_WLEN8;
861 if (termios->c_cflag & CSTOPB)
862 cval |= UART_LCR_STOP;
863 if (termios->c_cflag & PARENB)
864 cval |= UART_LCR_PARITY;
865 if (!(termios->c_cflag & PARODD))
866 cval |= UART_LCR_EPAR;
867 if (termios->c_cflag & CMSPAR)
868 cval |= UART_LCR_SPAR;
871 * Ask the core to calculate the divisor for us.
874 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
875 quot = serial_omap_get_divisor(port, baud);
877 /* calculate wakeup latency constraint */
878 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
879 up->latency = up->calc_latency;
880 schedule_work(&up->qos_work);
882 up->dll = quot & 0xff;
884 up->mdr1 = UART_OMAP_MDR1_DISABLE;
886 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
887 UART_FCR_ENABLE_FIFO;
890 * Ok, we're now changing the port state. Do it with
891 * interrupts disabled.
893 pm_runtime_get_sync(up->dev);
894 spin_lock_irqsave(&up->port.lock, flags);
897 * Update the per-port timeout.
899 uart_update_timeout(port, termios->c_cflag, baud);
901 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
902 if (termios->c_iflag & INPCK)
903 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
904 if (termios->c_iflag & (BRKINT | PARMRK))
905 up->port.read_status_mask |= UART_LSR_BI;
908 * Characters to ignore
910 up->port.ignore_status_mask = 0;
911 if (termios->c_iflag & IGNPAR)
912 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
913 if (termios->c_iflag & IGNBRK) {
914 up->port.ignore_status_mask |= UART_LSR_BI;
916 * If we're ignoring parity and break indicators,
917 * ignore overruns too (for real raw support).
919 if (termios->c_iflag & IGNPAR)
920 up->port.ignore_status_mask |= UART_LSR_OE;
924 * ignore all characters if CREAD is not set
926 if ((termios->c_cflag & CREAD) == 0)
927 up->port.ignore_status_mask |= UART_LSR_DR;
930 * Modem status interrupts
932 up->ier &= ~UART_IER_MSI;
933 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
934 up->ier |= UART_IER_MSI;
935 serial_out(up, UART_IER, up->ier);
936 serial_out(up, UART_LCR, cval); /* reset DLAB */
940 /* FIFOs and DMA Settings */
942 /* FCR can be changed only when the
943 * baud clock is not running
944 * DLL_REG and DLH_REG set to 0.
946 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
947 serial_out(up, UART_DLL, 0);
948 serial_out(up, UART_DLM, 0);
949 serial_out(up, UART_LCR, 0);
951 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
953 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
954 up->efr &= ~UART_EFR_SCD;
955 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
957 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
958 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
959 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
960 /* FIFO ENABLE, DMA MODE */
962 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
964 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
965 * sets Enables the granularity of 1 for TRIGGER RX
966 * level. Along with setting RX FIFO trigger level
967 * to 1 (as noted below, 16 characters) and TLR[3:0]
968 * to zero this will result RX FIFO threshold level
969 * to 1 character, instead of 16 as noted in comment
973 /* Set receive FIFO threshold to 16 characters and
974 * transmit FIFO threshold to 32 spaces
976 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
977 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
978 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
979 UART_FCR_ENABLE_FIFO;
981 serial_out(up, UART_FCR, up->fcr);
982 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
984 serial_out(up, UART_OMAP_SCR, up->scr);
986 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
987 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
988 serial_out(up, UART_MCR, up->mcr);
989 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
990 serial_out(up, UART_EFR, up->efr);
991 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
993 /* Protocol, Baud Rate, and Interrupt Settings */
995 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
996 serial_omap_mdr1_errataset(up, up->mdr1);
998 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1000 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1001 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1003 serial_out(up, UART_LCR, 0);
1004 serial_out(up, UART_IER, 0);
1005 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1007 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
1008 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
1010 serial_out(up, UART_LCR, 0);
1011 serial_out(up, UART_IER, up->ier);
1012 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1014 serial_out(up, UART_EFR, up->efr);
1015 serial_out(up, UART_LCR, cval);
1017 if (!serial_omap_baud_is_mode16(port, baud))
1018 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
1020 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
1022 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1023 serial_omap_mdr1_errataset(up, up->mdr1);
1025 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1027 /* Configure flow control */
1028 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1030 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
1031 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
1032 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
1034 /* Enable access to TCR/TLR */
1035 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
1036 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1037 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
1039 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
1041 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
1042 /* Enable AUTORTS and AUTOCTS */
1043 up->efr |= UART_EFR_CTS | UART_EFR_RTS;
1045 /* Ensure MCR RTS is asserted */
1046 up->mcr |= UART_MCR_RTS;
1048 /* Disable AUTORTS and AUTOCTS */
1049 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1052 if (up->port.flags & UPF_SOFT_FLOW) {
1053 /* clear SW control mode bits */
1054 up->efr &= OMAP_UART_SW_CLR;
1058 * Enable XON/XOFF flow control on input.
1059 * Receiver compares XON1, XOFF1.
1061 if (termios->c_iflag & IXON)
1062 up->efr |= OMAP_UART_SW_RX;
1066 * Enable XON/XOFF flow control on output.
1067 * Transmit XON1, XOFF1
1069 if (termios->c_iflag & IXOFF)
1070 up->efr |= OMAP_UART_SW_TX;
1074 * Enable any character to restart output.
1075 * Operation resumes after receiving any
1076 * character after recognition of the XOFF character
1078 if (termios->c_iflag & IXANY)
1079 up->mcr |= UART_MCR_XONANY;
1081 up->mcr &= ~UART_MCR_XONANY;
1083 serial_out(up, UART_MCR, up->mcr);
1084 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1085 serial_out(up, UART_EFR, up->efr);
1086 serial_out(up, UART_LCR, up->lcr);
1088 serial_omap_set_mctrl(&up->port, up->port.mctrl);
1090 spin_unlock_irqrestore(&up->port.lock, flags);
1091 pm_runtime_mark_last_busy(up->dev);
1092 pm_runtime_put_autosuspend(up->dev);
1093 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1097 serial_omap_pm(struct uart_port *port, unsigned int state,
1098 unsigned int oldstate)
1100 struct uart_omap_port *up = to_uart_omap_port(port);
1103 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1105 pm_runtime_get_sync(up->dev);
1106 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1107 efr = serial_in(up, UART_EFR);
1108 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1109 serial_out(up, UART_LCR, 0);
1111 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1112 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1113 serial_out(up, UART_EFR, efr);
1114 serial_out(up, UART_LCR, 0);
1116 if (!device_may_wakeup(up->dev)) {
1118 pm_runtime_forbid(up->dev);
1120 pm_runtime_allow(up->dev);
1123 pm_runtime_mark_last_busy(up->dev);
1124 pm_runtime_put_autosuspend(up->dev);
1127 static void serial_omap_release_port(struct uart_port *port)
1129 dev_dbg(port->dev, "serial_omap_release_port+\n");
1132 static int serial_omap_request_port(struct uart_port *port)
1134 dev_dbg(port->dev, "serial_omap_request_port+\n");
1138 static void serial_omap_config_port(struct uart_port *port, int flags)
1140 struct uart_omap_port *up = to_uart_omap_port(port);
1142 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1144 up->port.type = PORT_OMAP;
1145 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1149 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1151 /* we don't want the core code to modify any port params */
1152 dev_dbg(port->dev, "serial_omap_verify_port+\n");
1157 serial_omap_type(struct uart_port *port)
1159 struct uart_omap_port *up = to_uart_omap_port(port);
1161 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1165 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1167 static inline void wait_for_xmitr(struct uart_omap_port *up)
1169 unsigned int status, tmout = 10000;
1171 /* Wait up to 10ms for the character(s) to be sent. */
1173 status = serial_in(up, UART_LSR);
1175 if (status & UART_LSR_BI)
1176 up->lsr_break_flag = UART_LSR_BI;
1181 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1183 /* Wait up to 1s for flow control if necessary */
1184 if (up->port.flags & UPF_CONS_FLOW) {
1186 for (tmout = 1000000; tmout; tmout--) {
1187 unsigned int msr = serial_in(up, UART_MSR);
1189 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1190 if (msr & UART_MSR_CTS)
1198 #ifdef CONFIG_CONSOLE_POLL
1200 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1202 struct uart_omap_port *up = to_uart_omap_port(port);
1204 pm_runtime_get_sync(up->dev);
1206 serial_out(up, UART_TX, ch);
1207 pm_runtime_mark_last_busy(up->dev);
1208 pm_runtime_put_autosuspend(up->dev);
1211 static int serial_omap_poll_get_char(struct uart_port *port)
1213 struct uart_omap_port *up = to_uart_omap_port(port);
1214 unsigned int status;
1216 pm_runtime_get_sync(up->dev);
1217 status = serial_in(up, UART_LSR);
1218 if (!(status & UART_LSR_DR)) {
1219 status = NO_POLL_CHAR;
1223 status = serial_in(up, UART_RX);
1226 pm_runtime_mark_last_busy(up->dev);
1227 pm_runtime_put_autosuspend(up->dev);
1232 #endif /* CONFIG_CONSOLE_POLL */
1234 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1236 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1238 static struct uart_driver serial_omap_reg;
1240 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1242 struct uart_omap_port *up = to_uart_omap_port(port);
1245 serial_out(up, UART_TX, ch);
1249 serial_omap_console_write(struct console *co, const char *s,
1252 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1253 unsigned long flags;
1257 pm_runtime_get_sync(up->dev);
1259 local_irq_save(flags);
1262 else if (oops_in_progress)
1263 locked = spin_trylock(&up->port.lock);
1265 spin_lock(&up->port.lock);
1268 * First save the IER then disable the interrupts
1270 ier = serial_in(up, UART_IER);
1271 serial_out(up, UART_IER, 0);
1273 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1276 * Finally, wait for transmitter to become empty
1277 * and restore the IER
1280 serial_out(up, UART_IER, ier);
1282 * The receive handling will happen properly because the
1283 * receive ready bit will still be set; it is not cleared
1284 * on read. However, modem control will not, we must
1285 * call it if we have saved something in the saved flags
1286 * while processing with interrupts off.
1288 if (up->msr_saved_flags)
1289 check_modem_status(up);
1291 pm_runtime_mark_last_busy(up->dev);
1292 pm_runtime_put_autosuspend(up->dev);
1294 spin_unlock(&up->port.lock);
1295 local_irq_restore(flags);
1299 serial_omap_console_setup(struct console *co, char *options)
1301 struct uart_omap_port *up;
1307 if (serial_omap_console_ports[co->index] == NULL)
1309 up = serial_omap_console_ports[co->index];
1312 uart_parse_options(options, &baud, &parity, &bits, &flow);
1314 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1317 static struct console serial_omap_console = {
1318 .name = OMAP_SERIAL_NAME,
1319 .write = serial_omap_console_write,
1320 .device = uart_console_device,
1321 .setup = serial_omap_console_setup,
1322 .flags = CON_PRINTBUFFER,
1324 .data = &serial_omap_reg,
1327 static void serial_omap_add_console_port(struct uart_omap_port *up)
1329 serial_omap_console_ports[up->port.line] = up;
1332 #define OMAP_CONSOLE (&serial_omap_console)
1336 #define OMAP_CONSOLE NULL
1338 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1343 /* Enable or disable the rs485 support */
1345 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf)
1347 struct uart_omap_port *up = to_uart_omap_port(port);
1348 unsigned long flags;
1352 pm_runtime_get_sync(up->dev);
1353 spin_lock_irqsave(&up->port.lock, flags);
1355 /* Disable interrupts from this port */
1358 serial_out(up, UART_IER, 0);
1360 /* store new config */
1361 up->rs485 = *rs485conf;
1364 * Just as a precaution, only allow rs485
1365 * to be enabled if the gpio pin is valid
1367 if (gpio_is_valid(up->rts_gpio)) {
1368 /* enable / disable rts */
1369 val = (up->rs485.flags & SER_RS485_ENABLED) ?
1370 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1371 val = (up->rs485.flags & val) ? 1 : 0;
1372 gpio_set_value(up->rts_gpio, val);
1374 up->rs485.flags &= ~SER_RS485_ENABLED;
1376 /* Enable interrupts */
1378 serial_out(up, UART_IER, up->ier);
1380 /* If RS-485 is disabled, make sure the THR interrupt is fired when
1381 * TX FIFO is below the trigger level.
1383 if (!(up->rs485.flags & SER_RS485_ENABLED) &&
1384 (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1385 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1386 serial_out(up, UART_OMAP_SCR, up->scr);
1389 spin_unlock_irqrestore(&up->port.lock, flags);
1390 pm_runtime_mark_last_busy(up->dev);
1391 pm_runtime_put_autosuspend(up->dev);
1395 serial_omap_ioctl(struct uart_port *port, unsigned int cmd, unsigned long arg)
1397 struct serial_rs485 rs485conf;
1401 if (copy_from_user(&rs485conf, (void __user *) arg,
1405 serial_omap_config_rs485(port, &rs485conf);
1409 if (copy_to_user((void __user *) arg,
1410 &(to_uart_omap_port(port)->rs485),
1416 return -ENOIOCTLCMD;
1422 static struct uart_ops serial_omap_pops = {
1423 .tx_empty = serial_omap_tx_empty,
1424 .set_mctrl = serial_omap_set_mctrl,
1425 .get_mctrl = serial_omap_get_mctrl,
1426 .stop_tx = serial_omap_stop_tx,
1427 .start_tx = serial_omap_start_tx,
1428 .throttle = serial_omap_throttle,
1429 .unthrottle = serial_omap_unthrottle,
1430 .stop_rx = serial_omap_stop_rx,
1431 .enable_ms = serial_omap_enable_ms,
1432 .break_ctl = serial_omap_break_ctl,
1433 .startup = serial_omap_startup,
1434 .shutdown = serial_omap_shutdown,
1435 .set_termios = serial_omap_set_termios,
1436 .pm = serial_omap_pm,
1437 .type = serial_omap_type,
1438 .release_port = serial_omap_release_port,
1439 .request_port = serial_omap_request_port,
1440 .config_port = serial_omap_config_port,
1441 .verify_port = serial_omap_verify_port,
1442 .ioctl = serial_omap_ioctl,
1443 #ifdef CONFIG_CONSOLE_POLL
1444 .poll_put_char = serial_omap_poll_put_char,
1445 .poll_get_char = serial_omap_poll_get_char,
1449 static struct uart_driver serial_omap_reg = {
1450 .owner = THIS_MODULE,
1451 .driver_name = "OMAP-SERIAL",
1452 .dev_name = OMAP_SERIAL_NAME,
1453 .nr = OMAP_MAX_HSUART_PORTS,
1454 .cons = OMAP_CONSOLE,
1457 #ifdef CONFIG_PM_SLEEP
1458 static int serial_omap_prepare(struct device *dev)
1460 struct uart_omap_port *up = dev_get_drvdata(dev);
1462 up->is_suspending = true;
1467 static void serial_omap_complete(struct device *dev)
1469 struct uart_omap_port *up = dev_get_drvdata(dev);
1471 up->is_suspending = false;
1474 static int serial_omap_suspend(struct device *dev)
1476 struct uart_omap_port *up = dev_get_drvdata(dev);
1478 uart_suspend_port(&serial_omap_reg, &up->port);
1479 flush_work(&up->qos_work);
1481 if (device_may_wakeup(dev))
1482 serial_omap_enable_wakeup(up, true);
1484 serial_omap_enable_wakeup(up, false);
1489 static int serial_omap_resume(struct device *dev)
1491 struct uart_omap_port *up = dev_get_drvdata(dev);
1493 if (device_may_wakeup(dev))
1494 serial_omap_enable_wakeup(up, false);
1496 uart_resume_port(&serial_omap_reg, &up->port);
1501 #define serial_omap_prepare NULL
1502 #define serial_omap_complete NULL
1503 #endif /* CONFIG_PM_SLEEP */
1505 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1508 u16 revision, major, minor;
1510 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1512 /* Check revision register scheme */
1513 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1516 case 0: /* Legacy Scheme: OMAP2/3 */
1517 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1518 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1519 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1520 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1523 /* New Scheme: OMAP4+ */
1524 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1525 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1526 OMAP_UART_MVR_MAJ_SHIFT;
1527 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1531 "Unknown %s revision, defaulting to highest\n",
1533 /* highest possible revision */
1538 /* normalize revision for the driver */
1539 revision = UART_BUILD_REVISION(major, minor);
1542 case OMAP_UART_REV_46:
1543 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1544 UART_ERRATA_i291_DMA_FORCEIDLE);
1546 case OMAP_UART_REV_52:
1547 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1548 UART_ERRATA_i291_DMA_FORCEIDLE);
1549 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1551 case OMAP_UART_REV_63:
1552 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1553 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1560 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1562 struct omap_uart_port_info *omap_up_info;
1564 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1566 return NULL; /* out of memory */
1568 of_property_read_u32(dev->of_node, "clock-frequency",
1569 &omap_up_info->uartclk);
1570 return omap_up_info;
1573 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1574 struct device_node *np)
1576 struct serial_rs485 *rs485conf = &up->rs485;
1578 enum of_gpio_flags flags;
1581 rs485conf->flags = 0;
1582 up->rts_gpio = -EINVAL;
1587 if (of_property_read_bool(np, "rs485-rts-active-high"))
1588 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1590 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1592 /* check for tx enable gpio */
1593 up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags);
1594 if (gpio_is_valid(up->rts_gpio)) {
1595 ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial");
1598 ret = gpio_direction_output(up->rts_gpio,
1599 flags & SER_RS485_RTS_AFTER_SEND);
1602 } else if (up->rts_gpio == -EPROBE_DEFER) {
1603 return -EPROBE_DEFER;
1605 up->rts_gpio = -EINVAL;
1608 if (of_property_read_u32_array(np, "rs485-rts-delay",
1609 rs485_delay, 2) == 0) {
1610 rs485conf->delay_rts_before_send = rs485_delay[0];
1611 rs485conf->delay_rts_after_send = rs485_delay[1];
1614 if (of_property_read_bool(np, "rs485-rx-during-tx"))
1615 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1617 if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
1618 rs485conf->flags |= SER_RS485_ENABLED;
1623 static int serial_omap_probe(struct platform_device *pdev)
1625 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1626 struct uart_omap_port *up;
1627 struct resource *mem;
1633 /* The optional wakeirq may be specified in the board dts file */
1634 if (pdev->dev.of_node) {
1635 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1637 return -EPROBE_DEFER;
1638 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1639 omap_up_info = of_get_uart_port_info(&pdev->dev);
1640 pdev->dev.platform_data = omap_up_info;
1642 uartirq = platform_get_irq(pdev, 0);
1644 return -EPROBE_DEFER;
1647 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1651 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1652 base = devm_ioremap_resource(&pdev->dev, mem);
1654 return PTR_ERR(base);
1656 up->dev = &pdev->dev;
1657 up->port.dev = &pdev->dev;
1658 up->port.type = PORT_OMAP;
1659 up->port.iotype = UPIO_MEM;
1660 up->port.irq = uartirq;
1661 up->wakeirq = wakeirq;
1663 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1666 up->port.regshift = 2;
1667 up->port.fifosize = 64;
1668 up->port.ops = &serial_omap_pops;
1670 if (pdev->dev.of_node)
1671 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1673 up->port.line = pdev->id;
1675 if (up->port.line < 0) {
1676 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1682 ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
1686 sprintf(up->name, "OMAP UART%d", up->port.line);
1687 up->port.mapbase = mem->start;
1688 up->port.membase = base;
1689 up->port.flags = omap_up_info->flags;
1690 up->port.uartclk = omap_up_info->uartclk;
1691 if (!up->port.uartclk) {
1692 up->port.uartclk = DEFAULT_CLK_SPEED;
1693 dev_warn(&pdev->dev,
1694 "No clock speed specified: using default: %d\n",
1698 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1699 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1700 pm_qos_add_request(&up->pm_qos_request,
1701 PM_QOS_CPU_DMA_LATENCY, up->latency);
1702 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1704 platform_set_drvdata(pdev, up);
1705 if (omap_up_info->autosuspend_timeout == 0)
1706 omap_up_info->autosuspend_timeout = -1;
1708 device_init_wakeup(up->dev, true);
1709 pm_runtime_use_autosuspend(&pdev->dev);
1710 pm_runtime_set_autosuspend_delay(&pdev->dev,
1711 omap_up_info->autosuspend_timeout);
1713 pm_runtime_irq_safe(&pdev->dev);
1714 pm_runtime_enable(&pdev->dev);
1716 pm_runtime_get_sync(&pdev->dev);
1718 omap_serial_fill_features_erratas(up);
1720 ui[up->port.line] = up;
1721 serial_omap_add_console_port(up);
1723 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1727 pm_runtime_mark_last_busy(up->dev);
1728 pm_runtime_put_autosuspend(up->dev);
1732 pm_runtime_put(&pdev->dev);
1733 pm_runtime_disable(&pdev->dev);
1736 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1737 pdev->id, __func__, ret);
1741 static int serial_omap_remove(struct platform_device *dev)
1743 struct uart_omap_port *up = platform_get_drvdata(dev);
1745 pm_runtime_put_sync(up->dev);
1746 pm_runtime_disable(up->dev);
1747 uart_remove_one_port(&serial_omap_reg, &up->port);
1748 pm_qos_remove_request(&up->pm_qos_request);
1749 device_init_wakeup(&dev->dev, false);
1755 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1756 * The access to uart register after MDR1 Access
1757 * causes UART to corrupt data.
1760 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1761 * give 10 times as much
1763 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1767 serial_out(up, UART_OMAP_MDR1, mdr1);
1769 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1770 UART_FCR_CLEAR_RCVR);
1772 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1773 * TX_FIFO_E bit is 1.
1775 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1776 (UART_LSR_THRE | UART_LSR_DR))) {
1779 /* Should *never* happen. we warn and carry on */
1780 dev_crit(up->dev, "Errata i202: timedout %x\n",
1781 serial_in(up, UART_LSR));
1788 #ifdef CONFIG_PM_RUNTIME
1789 static void serial_omap_restore_context(struct uart_omap_port *up)
1791 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1792 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1794 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1796 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1797 serial_out(up, UART_EFR, UART_EFR_ECB);
1798 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1799 serial_out(up, UART_IER, 0x0);
1800 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1801 serial_out(up, UART_DLL, up->dll);
1802 serial_out(up, UART_DLM, up->dlh);
1803 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1804 serial_out(up, UART_IER, up->ier);
1805 serial_out(up, UART_FCR, up->fcr);
1806 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1807 serial_out(up, UART_MCR, up->mcr);
1808 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1809 serial_out(up, UART_OMAP_SCR, up->scr);
1810 serial_out(up, UART_EFR, up->efr);
1811 serial_out(up, UART_LCR, up->lcr);
1812 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1813 serial_omap_mdr1_errataset(up, up->mdr1);
1815 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1816 serial_out(up, UART_OMAP_WER, up->wer);
1819 static int serial_omap_runtime_suspend(struct device *dev)
1821 struct uart_omap_port *up = dev_get_drvdata(dev);
1827 * When using 'no_console_suspend', the console UART must not be
1828 * suspended. Since driver suspend is managed by runtime suspend,
1829 * preventing runtime suspend (by returning error) will keep device
1830 * active during suspend.
1832 if (up->is_suspending && !console_suspend_enabled &&
1833 uart_console(&up->port))
1836 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1838 serial_omap_enable_wakeup(up, true);
1840 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1841 schedule_work(&up->qos_work);
1846 static int serial_omap_runtime_resume(struct device *dev)
1848 struct uart_omap_port *up = dev_get_drvdata(dev);
1850 int loss_cnt = serial_omap_get_context_loss_count(up);
1852 serial_omap_enable_wakeup(up, false);
1855 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1857 serial_omap_restore_context(up);
1858 } else if (up->context_loss_cnt != loss_cnt) {
1859 serial_omap_restore_context(up);
1861 up->latency = up->calc_latency;
1862 schedule_work(&up->qos_work);
1868 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1869 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1870 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1871 serial_omap_runtime_resume, NULL)
1872 .prepare = serial_omap_prepare,
1873 .complete = serial_omap_complete,
1876 #if defined(CONFIG_OF)
1877 static const struct of_device_id omap_serial_of_match[] = {
1878 { .compatible = "ti,omap2-uart" },
1879 { .compatible = "ti,omap3-uart" },
1880 { .compatible = "ti,omap4-uart" },
1883 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1886 static struct platform_driver serial_omap_driver = {
1887 .probe = serial_omap_probe,
1888 .remove = serial_omap_remove,
1890 .name = DRIVER_NAME,
1891 .pm = &serial_omap_dev_pm_ops,
1892 .of_match_table = of_match_ptr(omap_serial_of_match),
1896 static int __init serial_omap_init(void)
1900 ret = uart_register_driver(&serial_omap_reg);
1903 ret = platform_driver_register(&serial_omap_driver);
1905 uart_unregister_driver(&serial_omap_reg);
1909 static void __exit serial_omap_exit(void)
1911 platform_driver_unregister(&serial_omap_driver);
1912 uart_unregister_driver(&serial_omap_reg);
1915 module_init(serial_omap_init);
1916 module_exit(serial_omap_exit);
1918 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1919 MODULE_LICENSE("GPL");
1920 MODULE_AUTHOR("Texas Instruments Inc");