2 * Freescale STMP37XX/STMP378X Application UART driver
4 * Author: dmitry pervushin <dimka@embeddedalley.com>
6 * Copyright 2008-2010 Freescale Semiconductor, Inc.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/init.h>
20 #include <linux/console.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/slab.h>
24 #include <linux/wait.h>
25 #include <linux/tty.h>
26 #include <linux/tty_driver.h>
27 #include <linux/tty_flip.h>
28 #include <linux/serial.h>
29 #include <linux/serial_core.h>
30 #include <linux/platform_device.h>
31 #include <linux/device.h>
32 #include <linux/clk.h>
33 #include <linux/delay.h>
35 #include <linux/pinctrl/consumer.h>
36 #include <linux/of_device.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/fsl/mxs-dma.h>
40 #include <asm/cacheflush.h>
42 #define MXS_AUART_PORTS 5
44 #define AUART_CTRL0 0x00000000
45 #define AUART_CTRL0_SET 0x00000004
46 #define AUART_CTRL0_CLR 0x00000008
47 #define AUART_CTRL0_TOG 0x0000000c
48 #define AUART_CTRL1 0x00000010
49 #define AUART_CTRL1_SET 0x00000014
50 #define AUART_CTRL1_CLR 0x00000018
51 #define AUART_CTRL1_TOG 0x0000001c
52 #define AUART_CTRL2 0x00000020
53 #define AUART_CTRL2_SET 0x00000024
54 #define AUART_CTRL2_CLR 0x00000028
55 #define AUART_CTRL2_TOG 0x0000002c
56 #define AUART_LINECTRL 0x00000030
57 #define AUART_LINECTRL_SET 0x00000034
58 #define AUART_LINECTRL_CLR 0x00000038
59 #define AUART_LINECTRL_TOG 0x0000003c
60 #define AUART_LINECTRL2 0x00000040
61 #define AUART_LINECTRL2_SET 0x00000044
62 #define AUART_LINECTRL2_CLR 0x00000048
63 #define AUART_LINECTRL2_TOG 0x0000004c
64 #define AUART_INTR 0x00000050
65 #define AUART_INTR_SET 0x00000054
66 #define AUART_INTR_CLR 0x00000058
67 #define AUART_INTR_TOG 0x0000005c
68 #define AUART_DATA 0x00000060
69 #define AUART_STAT 0x00000070
70 #define AUART_DEBUG 0x00000080
71 #define AUART_VERSION 0x00000090
72 #define AUART_AUTOBAUD 0x000000a0
74 #define AUART_CTRL0_SFTRST (1 << 31)
75 #define AUART_CTRL0_CLKGATE (1 << 30)
76 #define AUART_CTRL0_RXTO_ENABLE (1 << 27)
77 #define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
78 #define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
80 #define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
82 #define AUART_CTRL2_DMAONERR (1 << 26)
83 #define AUART_CTRL2_TXDMAE (1 << 25)
84 #define AUART_CTRL2_RXDMAE (1 << 24)
86 #define AUART_CTRL2_CTSEN (1 << 15)
87 #define AUART_CTRL2_RTSEN (1 << 14)
88 #define AUART_CTRL2_RTS (1 << 11)
89 #define AUART_CTRL2_RXE (1 << 9)
90 #define AUART_CTRL2_TXE (1 << 8)
91 #define AUART_CTRL2_UARTEN (1 << 0)
93 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
94 #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
95 #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
96 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
97 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
98 #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
99 #define AUART_LINECTRL_WLEN_MASK 0x00000060
100 #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
101 #define AUART_LINECTRL_FEN (1 << 4)
102 #define AUART_LINECTRL_STP2 (1 << 3)
103 #define AUART_LINECTRL_EPS (1 << 2)
104 #define AUART_LINECTRL_PEN (1 << 1)
105 #define AUART_LINECTRL_BRK (1 << 0)
107 #define AUART_INTR_RTIEN (1 << 22)
108 #define AUART_INTR_TXIEN (1 << 21)
109 #define AUART_INTR_RXIEN (1 << 20)
110 #define AUART_INTR_CTSMIEN (1 << 17)
111 #define AUART_INTR_RTIS (1 << 6)
112 #define AUART_INTR_TXIS (1 << 5)
113 #define AUART_INTR_RXIS (1 << 4)
114 #define AUART_INTR_CTSMIS (1 << 1)
116 #define AUART_STAT_BUSY (1 << 29)
117 #define AUART_STAT_CTS (1 << 28)
118 #define AUART_STAT_TXFE (1 << 27)
119 #define AUART_STAT_TXFF (1 << 25)
120 #define AUART_STAT_RXFE (1 << 24)
121 #define AUART_STAT_OERR (1 << 19)
122 #define AUART_STAT_BERR (1 << 18)
123 #define AUART_STAT_PERR (1 << 17)
124 #define AUART_STAT_FERR (1 << 16)
125 #define AUART_STAT_RXCOUNT_MASK 0xffff
127 static struct uart_driver auart_driver;
129 enum mxs_auart_type {
134 struct mxs_auart_port {
135 struct uart_port port;
137 #define MXS_AUART_DMA_CONFIG 0x1
138 #define MXS_AUART_DMA_ENABLED 0x2
139 #define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */
140 #define MXS_AUART_DMA_RX_READY 3 /* bit 3 */
143 enum mxs_auart_type devtype;
151 struct mxs_dma_data dma_data;
152 int dma_channel_rx, dma_channel_tx;
153 int dma_irq_rx, dma_irq_tx;
156 struct scatterlist tx_sgl;
157 struct dma_chan *tx_dma_chan;
160 struct scatterlist rx_sgl;
161 struct dma_chan *rx_dma_chan;
165 static struct platform_device_id mxs_auart_devtype[] = {
166 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART },
167 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART },
170 MODULE_DEVICE_TABLE(platform, mxs_auart_devtype);
172 static struct of_device_id mxs_auart_dt_ids[] = {
174 .compatible = "fsl,imx28-auart",
175 .data = &mxs_auart_devtype[IMX28_AUART]
177 .compatible = "fsl,imx23-auart",
178 .data = &mxs_auart_devtype[IMX23_AUART]
179 }, { /* sentinel */ }
181 MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
183 static inline int is_imx28_auart(struct mxs_auart_port *s)
185 return s->devtype == IMX28_AUART;
188 static inline bool auart_dma_enabled(struct mxs_auart_port *s)
190 return s->flags & MXS_AUART_DMA_ENABLED;
193 static void mxs_auart_stop_tx(struct uart_port *u);
195 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
197 static void mxs_auart_tx_chars(struct mxs_auart_port *s);
199 static void dma_tx_callback(void *param)
201 struct mxs_auart_port *s = param;
202 struct circ_buf *xmit = &s->port.state->xmit;
204 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
206 /* clear the bit used to serialize the DMA tx. */
207 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
208 smp_mb__after_clear_bit();
210 /* wake up the possible processes. */
211 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
212 uart_write_wakeup(&s->port);
214 mxs_auart_tx_chars(s);
217 static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
219 struct dma_async_tx_descriptor *desc;
220 struct scatterlist *sgl = &s->tx_sgl;
221 struct dma_chan *channel = s->tx_dma_chan;
224 /* [1] : send PIO. Note, the first pio word is CTRL1. */
225 pio = AUART_CTRL1_XFER_COUNT(size);
226 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
227 1, DMA_TRANS_NONE, 0);
229 dev_err(s->dev, "step 1 error\n");
233 /* [2] : set DMA buffer. */
234 sg_init_one(sgl, s->tx_dma_buf, size);
235 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
236 desc = dmaengine_prep_slave_sg(channel, sgl,
237 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
239 dev_err(s->dev, "step 2 error\n");
243 /* [3] : submit the DMA */
244 desc->callback = dma_tx_callback;
245 desc->callback_param = s;
246 dmaengine_submit(desc);
247 dma_async_issue_pending(channel);
251 static void mxs_auart_tx_chars(struct mxs_auart_port *s)
253 struct circ_buf *xmit = &s->port.state->xmit;
255 if (auart_dma_enabled(s)) {
258 void *buffer = s->tx_dma_buf;
260 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
263 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
264 size = min_t(u32, UART_XMIT_SIZE - i,
265 CIRC_CNT_TO_END(xmit->head,
268 memcpy(buffer + i, xmit->buf + xmit->tail, size);
269 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
272 if (i >= UART_XMIT_SIZE)
276 if (uart_tx_stopped(&s->port))
277 mxs_auart_stop_tx(&s->port);
280 mxs_auart_dma_tx(s, i);
282 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
283 smp_mb__after_clear_bit();
289 while (!(readl(s->port.membase + AUART_STAT) &
291 if (s->port.x_char) {
293 writel(s->port.x_char,
294 s->port.membase + AUART_DATA);
298 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
300 writel(xmit->buf[xmit->tail],
301 s->port.membase + AUART_DATA);
302 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
306 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
307 uart_write_wakeup(&s->port);
309 if (uart_circ_empty(&(s->port.state->xmit)))
310 writel(AUART_INTR_TXIEN,
311 s->port.membase + AUART_INTR_CLR);
313 writel(AUART_INTR_TXIEN,
314 s->port.membase + AUART_INTR_SET);
316 if (uart_tx_stopped(&s->port))
317 mxs_auart_stop_tx(&s->port);
320 static void mxs_auart_rx_char(struct mxs_auart_port *s)
326 c = readl(s->port.membase + AUART_DATA);
327 stat = readl(s->port.membase + AUART_STAT);
332 if (stat & AUART_STAT_BERR) {
333 s->port.icount.brk++;
334 if (uart_handle_break(&s->port))
336 } else if (stat & AUART_STAT_PERR) {
337 s->port.icount.parity++;
338 } else if (stat & AUART_STAT_FERR) {
339 s->port.icount.frame++;
343 * Mask off conditions which should be ingored.
345 stat &= s->port.read_status_mask;
347 if (stat & AUART_STAT_BERR) {
349 } else if (stat & AUART_STAT_PERR)
351 else if (stat & AUART_STAT_FERR)
354 if (stat & AUART_STAT_OERR)
355 s->port.icount.overrun++;
357 if (uart_handle_sysrq_char(&s->port, c))
360 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
362 writel(stat, s->port.membase + AUART_STAT);
365 static void mxs_auart_rx_chars(struct mxs_auart_port *s)
370 stat = readl(s->port.membase + AUART_STAT);
371 if (stat & AUART_STAT_RXFE)
373 mxs_auart_rx_char(s);
376 writel(stat, s->port.membase + AUART_STAT);
377 tty_flip_buffer_push(&s->port.state->port);
380 static int mxs_auart_request_port(struct uart_port *u)
385 static int mxs_auart_verify_port(struct uart_port *u,
386 struct serial_struct *ser)
388 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
393 static void mxs_auart_config_port(struct uart_port *u, int flags)
397 static const char *mxs_auart_type(struct uart_port *u)
399 struct mxs_auart_port *s = to_auart_port(u);
401 return dev_name(s->dev);
404 static void mxs_auart_release_port(struct uart_port *u)
408 static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
410 struct mxs_auart_port *s = to_auart_port(u);
412 u32 ctrl = readl(u->membase + AUART_CTRL2);
414 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
415 if (mctrl & TIOCM_RTS) {
416 if (tty_port_cts_enabled(&u->state->port))
417 ctrl |= AUART_CTRL2_RTSEN;
419 ctrl |= AUART_CTRL2_RTS;
423 writel(ctrl, u->membase + AUART_CTRL2);
426 static u32 mxs_auart_get_mctrl(struct uart_port *u)
428 struct mxs_auart_port *s = to_auart_port(u);
429 u32 stat = readl(u->membase + AUART_STAT);
430 int ctrl2 = readl(u->membase + AUART_CTRL2);
434 if (stat & AUART_STAT_CTS)
437 if (ctrl2 & AUART_CTRL2_RTS)
443 static bool mxs_auart_dma_filter(struct dma_chan *chan, void *param)
445 struct mxs_auart_port *s = param;
447 if (!mxs_dma_is_apbx(chan))
450 if (s->dma_channel == chan->chan_id) {
451 chan->private = &s->dma_data;
457 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
458 static void dma_rx_callback(void *arg)
460 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
461 struct tty_port *port = &s->port.state->port;
465 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
467 stat = readl(s->port.membase + AUART_STAT);
468 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
469 AUART_STAT_PERR | AUART_STAT_FERR);
471 count = stat & AUART_STAT_RXCOUNT_MASK;
472 tty_insert_flip_string(port, s->rx_dma_buf, count);
474 writel(stat, s->port.membase + AUART_STAT);
475 tty_flip_buffer_push(port);
477 /* start the next DMA for RX. */
478 mxs_auart_dma_prep_rx(s);
481 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
483 struct dma_async_tx_descriptor *desc;
484 struct scatterlist *sgl = &s->rx_sgl;
485 struct dma_chan *channel = s->rx_dma_chan;
489 pio[0] = AUART_CTRL0_RXTO_ENABLE
490 | AUART_CTRL0_RXTIMEOUT(0x80)
491 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
492 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
493 1, DMA_TRANS_NONE, 0);
495 dev_err(s->dev, "step 1 error\n");
499 /* [2] : send DMA request */
500 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
501 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
502 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
503 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
505 dev_err(s->dev, "step 2 error\n");
509 /* [3] : submit the DMA, but do not issue it. */
510 desc->callback = dma_rx_callback;
511 desc->callback_param = s;
512 dmaengine_submit(desc);
513 dma_async_issue_pending(channel);
517 static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
519 if (s->tx_dma_chan) {
520 dma_release_channel(s->tx_dma_chan);
521 s->tx_dma_chan = NULL;
523 if (s->rx_dma_chan) {
524 dma_release_channel(s->rx_dma_chan);
525 s->rx_dma_chan = NULL;
528 kfree(s->tx_dma_buf);
529 kfree(s->rx_dma_buf);
530 s->tx_dma_buf = NULL;
531 s->rx_dma_buf = NULL;
534 static void mxs_auart_dma_exit(struct mxs_auart_port *s)
537 writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
538 s->port.membase + AUART_CTRL2_CLR);
540 mxs_auart_dma_exit_channel(s);
541 s->flags &= ~MXS_AUART_DMA_ENABLED;
542 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
543 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
546 static int mxs_auart_dma_init(struct mxs_auart_port *s)
550 if (auart_dma_enabled(s))
553 /* We do not get the right DMA channels. */
554 if (s->dma_channel_rx == -1 || s->dma_channel_tx == -1)
559 dma_cap_set(DMA_SLAVE, mask);
560 s->dma_channel = s->dma_channel_rx;
561 s->dma_data.chan_irq = s->dma_irq_rx;
562 s->rx_dma_chan = dma_request_channel(mask, mxs_auart_dma_filter, s);
565 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
570 s->dma_channel = s->dma_channel_tx;
571 s->dma_data.chan_irq = s->dma_irq_tx;
572 s->tx_dma_chan = dma_request_channel(mask, mxs_auart_dma_filter, s);
575 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
580 s->flags |= MXS_AUART_DMA_ENABLED;
581 dev_dbg(s->dev, "enabled the DMA support.");
586 mxs_auart_dma_exit_channel(s);
591 static void mxs_auart_settermios(struct uart_port *u,
592 struct ktermios *termios,
593 struct ktermios *old)
595 struct mxs_auart_port *s = to_auart_port(u);
596 u32 bm, ctrl, ctrl2, div;
597 unsigned int cflag, baud;
599 cflag = termios->c_cflag;
601 ctrl = AUART_LINECTRL_FEN;
602 ctrl2 = readl(u->membase + AUART_CTRL2);
605 switch (cflag & CSIZE) {
622 ctrl |= AUART_LINECTRL_WLEN(bm);
625 if (cflag & PARENB) {
626 ctrl |= AUART_LINECTRL_PEN;
627 if ((cflag & PARODD) == 0)
628 ctrl |= AUART_LINECTRL_EPS;
631 u->read_status_mask = 0;
633 if (termios->c_iflag & INPCK)
634 u->read_status_mask |= AUART_STAT_PERR;
635 if (termios->c_iflag & (BRKINT | PARMRK))
636 u->read_status_mask |= AUART_STAT_BERR;
639 * Characters to ignore
641 u->ignore_status_mask = 0;
642 if (termios->c_iflag & IGNPAR)
643 u->ignore_status_mask |= AUART_STAT_PERR;
644 if (termios->c_iflag & IGNBRK) {
645 u->ignore_status_mask |= AUART_STAT_BERR;
647 * If we're ignoring parity and break indicators,
648 * ignore overruns too (for real raw support).
650 if (termios->c_iflag & IGNPAR)
651 u->ignore_status_mask |= AUART_STAT_OERR;
655 * ignore all characters if CREAD is not set
658 ctrl2 |= AUART_CTRL2_RXE;
660 ctrl2 &= ~AUART_CTRL2_RXE;
662 /* figure out the stop bits requested */
664 ctrl |= AUART_LINECTRL_STP2;
666 /* figure out the hardware flow control settings */
667 if (cflag & CRTSCTS) {
669 * The DMA has a bug(see errata:2836) in mx23.
670 * So we can not implement the DMA for auart in mx23,
671 * we can only implement the DMA support for auart
674 if (is_imx28_auart(s) && (s->flags & MXS_AUART_DMA_CONFIG)) {
675 if (!mxs_auart_dma_init(s))
676 /* enable DMA tranfer */
677 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
678 | AUART_CTRL2_DMAONERR;
680 ctrl2 |= AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN;
682 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
686 baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
687 div = u->uartclk * 32 / baud;
688 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
689 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
691 writel(ctrl, u->membase + AUART_LINECTRL);
692 writel(ctrl2, u->membase + AUART_CTRL2);
694 uart_update_timeout(u, termios->c_cflag, baud);
696 /* prepare for the DMA RX. */
697 if (auart_dma_enabled(s) &&
698 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
699 if (!mxs_auart_dma_prep_rx(s)) {
700 /* Disable the normal RX interrupt. */
701 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
702 u->membase + AUART_INTR_CLR);
704 mxs_auart_dma_exit(s);
705 dev_err(s->dev, "We can not start up the DMA.\n");
710 static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
713 struct mxs_auart_port *s = context;
714 u32 stat = readl(s->port.membase + AUART_STAT);
716 istatus = istat = readl(s->port.membase + AUART_INTR);
718 if (istat & AUART_INTR_CTSMIS) {
719 uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS);
720 writel(AUART_INTR_CTSMIS,
721 s->port.membase + AUART_INTR_CLR);
722 istat &= ~AUART_INTR_CTSMIS;
725 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
726 if (!auart_dma_enabled(s))
727 mxs_auart_rx_chars(s);
728 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
731 if (istat & AUART_INTR_TXIS) {
732 mxs_auart_tx_chars(s);
733 istat &= ~AUART_INTR_TXIS;
736 writel(istatus & (AUART_INTR_RTIS
739 | AUART_INTR_CTSMIS),
740 s->port.membase + AUART_INTR_CLR);
745 static void mxs_auart_reset(struct uart_port *u)
750 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
752 for (i = 0; i < 10000; i++) {
753 reg = readl(u->membase + AUART_CTRL0);
754 if (!(reg & AUART_CTRL0_SFTRST))
758 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
761 static int mxs_auart_startup(struct uart_port *u)
763 struct mxs_auart_port *s = to_auart_port(u);
765 clk_prepare_enable(s->clk);
767 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
769 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
771 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
772 u->membase + AUART_INTR);
775 * Enable fifo so all four bytes of a DMA word are written to
776 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes)
778 writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
783 static void mxs_auart_shutdown(struct uart_port *u)
785 struct mxs_auart_port *s = to_auart_port(u);
787 if (auart_dma_enabled(s))
788 mxs_auart_dma_exit(s);
790 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
792 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
793 u->membase + AUART_INTR_CLR);
795 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
797 clk_disable_unprepare(s->clk);
800 static unsigned int mxs_auart_tx_empty(struct uart_port *u)
802 if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
808 static void mxs_auart_start_tx(struct uart_port *u)
810 struct mxs_auart_port *s = to_auart_port(u);
812 /* enable transmitter */
813 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
815 mxs_auart_tx_chars(s);
818 static void mxs_auart_stop_tx(struct uart_port *u)
820 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
823 static void mxs_auart_stop_rx(struct uart_port *u)
825 writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
828 static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
831 writel(AUART_LINECTRL_BRK,
832 u->membase + AUART_LINECTRL_SET);
834 writel(AUART_LINECTRL_BRK,
835 u->membase + AUART_LINECTRL_CLR);
838 static void mxs_auart_enable_ms(struct uart_port *port)
843 static struct uart_ops mxs_auart_ops = {
844 .tx_empty = mxs_auart_tx_empty,
845 .start_tx = mxs_auart_start_tx,
846 .stop_tx = mxs_auart_stop_tx,
847 .stop_rx = mxs_auart_stop_rx,
848 .enable_ms = mxs_auart_enable_ms,
849 .break_ctl = mxs_auart_break_ctl,
850 .set_mctrl = mxs_auart_set_mctrl,
851 .get_mctrl = mxs_auart_get_mctrl,
852 .startup = mxs_auart_startup,
853 .shutdown = mxs_auart_shutdown,
854 .set_termios = mxs_auart_settermios,
855 .type = mxs_auart_type,
856 .release_port = mxs_auart_release_port,
857 .request_port = mxs_auart_request_port,
858 .config_port = mxs_auart_config_port,
859 .verify_port = mxs_auart_verify_port,
862 static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
864 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
865 static void mxs_auart_console_putchar(struct uart_port *port, int ch)
867 unsigned int to = 1000;
869 while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
875 writel(ch, port->membase + AUART_DATA);
879 auart_console_write(struct console *co, const char *str, unsigned int count)
881 struct mxs_auart_port *s;
882 struct uart_port *port;
883 unsigned int old_ctrl0, old_ctrl2;
884 unsigned int to = 1000;
886 if (co->index >= MXS_AUART_PORTS || co->index < 0)
889 s = auart_port[co->index];
894 /* First save the CR then disable the interrupts */
895 old_ctrl2 = readl(port->membase + AUART_CTRL2);
896 old_ctrl0 = readl(port->membase + AUART_CTRL0);
898 writel(AUART_CTRL0_CLKGATE,
899 port->membase + AUART_CTRL0_CLR);
900 writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
901 port->membase + AUART_CTRL2_SET);
903 uart_console_write(port, str, count, mxs_auart_console_putchar);
906 * Finally, wait for transmitter to become empty
907 * and restore the TCR
909 while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
915 writel(old_ctrl0, port->membase + AUART_CTRL0);
916 writel(old_ctrl2, port->membase + AUART_CTRL2);
922 auart_console_get_options(struct uart_port *port, int *baud,
923 int *parity, int *bits)
925 unsigned int lcr_h, quot;
927 if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
930 lcr_h = readl(port->membase + AUART_LINECTRL);
933 if (lcr_h & AUART_LINECTRL_PEN) {
934 if (lcr_h & AUART_LINECTRL_EPS)
940 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
945 quot = ((readl(port->membase + AUART_LINECTRL)
946 & AUART_LINECTRL_BAUD_DIVINT_MASK))
947 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
948 quot |= ((readl(port->membase + AUART_LINECTRL)
949 & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
950 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
954 *baud = (port->uartclk << 2) / quot;
958 auart_console_setup(struct console *co, char *options)
960 struct mxs_auart_port *s;
968 * Check whether an invalid uart number has been specified, and
969 * if so, search for the first available port that does have
972 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
974 s = auart_port[co->index];
978 clk_prepare_enable(s->clk);
981 uart_parse_options(options, &baud, &parity, &bits, &flow);
983 auart_console_get_options(&s->port, &baud, &parity, &bits);
985 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
987 clk_disable_unprepare(s->clk);
992 static struct console auart_console = {
994 .write = auart_console_write,
995 .device = uart_console_device,
996 .setup = auart_console_setup,
997 .flags = CON_PRINTBUFFER,
999 .data = &auart_driver,
1003 static struct uart_driver auart_driver = {
1004 .owner = THIS_MODULE,
1005 .driver_name = "ttyAPP",
1006 .dev_name = "ttyAPP",
1009 .nr = MXS_AUART_PORTS,
1010 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1011 .cons = &auart_console,
1016 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it
1017 * could successfully get all information from dt or a negative errno.
1019 static int serial_mxs_probe_dt(struct mxs_auart_port *s,
1020 struct platform_device *pdev)
1022 struct device_node *np = pdev->dev.of_node;
1027 /* no device tree device */
1030 ret = of_alias_get_id(np, "serial");
1032 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1037 s->dma_irq_rx = platform_get_irq(pdev, 1);
1038 s->dma_irq_tx = platform_get_irq(pdev, 2);
1040 ret = of_property_read_u32_array(np, "fsl,auart-dma-channel",
1043 s->dma_channel_rx = dma_channel[0];
1044 s->dma_channel_tx = dma_channel[1];
1046 s->flags |= MXS_AUART_DMA_CONFIG;
1048 s->dma_channel_rx = -1;
1049 s->dma_channel_tx = -1;
1054 static int mxs_auart_probe(struct platform_device *pdev)
1056 const struct of_device_id *of_id =
1057 of_match_device(mxs_auart_dt_ids, &pdev->dev);
1058 struct mxs_auart_port *s;
1062 struct pinctrl *pinctrl;
1064 s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
1070 ret = serial_mxs_probe_dt(s, pdev);
1072 s->port.line = pdev->id < 0 ? 0 : pdev->id;
1076 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1077 if (IS_ERR(pinctrl)) {
1078 ret = PTR_ERR(pinctrl);
1083 pdev->id_entry = of_id->data;
1084 s->devtype = pdev->id_entry->driver_data;
1087 s->clk = clk_get(&pdev->dev, NULL);
1088 if (IS_ERR(s->clk)) {
1089 ret = PTR_ERR(s->clk);
1093 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1099 s->port.mapbase = r->start;
1100 s->port.membase = ioremap(r->start, resource_size(r));
1101 s->port.ops = &mxs_auart_ops;
1102 s->port.iotype = UPIO_MEM;
1103 s->port.fifosize = 16;
1104 s->port.uartclk = clk_get_rate(s->clk);
1105 s->port.type = PORT_IMX;
1106 s->port.dev = s->dev = &pdev->dev;
1110 s->irq = platform_get_irq(pdev, 0);
1111 s->port.irq = s->irq;
1112 ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
1116 platform_set_drvdata(pdev, s);
1118 auart_port[s->port.line] = s;
1120 mxs_auart_reset(&s->port);
1122 ret = uart_add_one_port(&auart_driver, &s->port);
1126 version = readl(s->port.membase + AUART_VERSION);
1127 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1128 (version >> 24) & 0xff,
1129 (version >> 16) & 0xff, version & 0xffff);
1134 auart_port[pdev->id] = NULL;
1135 free_irq(s->irq, s);
1144 static int mxs_auart_remove(struct platform_device *pdev)
1146 struct mxs_auart_port *s = platform_get_drvdata(pdev);
1148 uart_remove_one_port(&auart_driver, &s->port);
1150 auart_port[pdev->id] = NULL;
1153 free_irq(s->irq, s);
1159 static struct platform_driver mxs_auart_driver = {
1160 .probe = mxs_auart_probe,
1161 .remove = mxs_auart_remove,
1163 .name = "mxs-auart",
1164 .owner = THIS_MODULE,
1165 .of_match_table = mxs_auart_dt_ids,
1169 static int __init mxs_auart_init(void)
1173 r = uart_register_driver(&auart_driver);
1177 r = platform_driver_register(&mxs_auart_driver);
1183 uart_unregister_driver(&auart_driver);
1188 static void __exit mxs_auart_exit(void)
1190 platform_driver_unregister(&mxs_auart_driver);
1191 uart_unregister_driver(&auart_driver);
1194 module_init(mxs_auart_init);
1195 module_exit(mxs_auart_exit);
1196 MODULE_LICENSE("GPL");
1197 MODULE_DESCRIPTION("Freescale MXS application uart driver");
1198 MODULE_ALIAS("platform:mxs-auart");