2 * High Speed Serial Ports on NXP LPC32xx SoC
4 * Authors: Kevin Wells <kevin.wells@nxp.com>
5 * Roland Stigge <stigge@antcom.de>
7 * Copyright (C) 2010 NXP Semiconductors
8 * Copyright (C) 2012 Roland Stigge
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include <linux/module.h>
22 #include <linux/ioport.h>
23 #include <linux/init.h>
24 #include <linux/console.h>
25 #include <linux/sysrq.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/serial_core.h>
29 #include <linux/serial.h>
30 #include <linux/platform_device.h>
31 #include <linux/delay.h>
32 #include <linux/nmi.h>
34 #include <linux/irq.h>
35 #include <linux/gpio.h>
37 #include <mach/platform.h>
38 #include <mach/hardware.h>
41 * High Speed UART register offsets
43 #define LPC32XX_HSUART_FIFO(x) ((x) + 0x00)
44 #define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04)
45 #define LPC32XX_HSUART_IIR(x) ((x) + 0x08)
46 #define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C)
47 #define LPC32XX_HSUART_RATE(x) ((x) + 0x10)
49 #define LPC32XX_HSU_BREAK_DATA (1 << 10)
50 #define LPC32XX_HSU_ERROR_DATA (1 << 9)
51 #define LPC32XX_HSU_RX_EMPTY (1 << 8)
53 #define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF)
54 #define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF)
56 #define LPC32XX_HSU_TX_INT_SET (1 << 6)
57 #define LPC32XX_HSU_RX_OE_INT (1 << 5)
58 #define LPC32XX_HSU_BRK_INT (1 << 4)
59 #define LPC32XX_HSU_FE_INT (1 << 3)
60 #define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2)
61 #define LPC32XX_HSU_RX_TRIG_INT (1 << 1)
62 #define LPC32XX_HSU_TX_INT (1 << 0)
64 #define LPC32XX_HSU_HRTS_INV (1 << 21)
65 #define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19)
66 #define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19)
67 #define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19)
68 #define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19)
69 #define LPC32XX_HSU_HRTS_EN (1 << 18)
70 #define LPC32XX_HSU_TMO_DISABLED (0x0 << 16)
71 #define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16)
72 #define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16)
73 #define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16)
74 #define LPC32XX_HSU_HCTS_INV (1 << 15)
75 #define LPC32XX_HSU_HCTS_EN (1 << 14)
76 #define LPC32XX_HSU_OFFSET(n) ((n) << 9)
77 #define LPC32XX_HSU_BREAK (1 << 8)
78 #define LPC32XX_HSU_ERR_INT_EN (1 << 7)
79 #define LPC32XX_HSU_RX_INT_EN (1 << 6)
80 #define LPC32XX_HSU_TX_INT_EN (1 << 5)
81 #define LPC32XX_HSU_RX_TL1B (0x0 << 2)
82 #define LPC32XX_HSU_RX_TL4B (0x1 << 2)
83 #define LPC32XX_HSU_RX_TL8B (0x2 << 2)
84 #define LPC32XX_HSU_RX_TL16B (0x3 << 2)
85 #define LPC32XX_HSU_RX_TL32B (0x4 << 2)
86 #define LPC32XX_HSU_RX_TL48B (0x5 << 2)
87 #define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0)
88 #define LPC32XX_HSU_TX_TL0B (0x0 << 0)
89 #define LPC32XX_HSU_TX_TL4B (0x1 << 0)
90 #define LPC32XX_HSU_TX_TL8B (0x2 << 0)
91 #define LPC32XX_HSU_TX_TL16B (0x3 << 0)
93 #define MODNAME "lpc32xx_hsuart"
95 struct lpc32xx_hsuart_port {
96 struct uart_port port;
99 #define FIFO_READ_LIMIT 128
101 #define LPC32XX_TTY_NAME "ttyTX"
102 static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
104 #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
105 static void wait_for_xmit_empty(struct uart_port *port)
107 unsigned int timeout = 10000;
110 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
111 port->membase))) == 0)
119 static void wait_for_xmit_ready(struct uart_port *port)
121 unsigned int timeout = 10000;
124 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
125 port->membase))) < 32)
133 static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch)
135 wait_for_xmit_ready(port);
136 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
139 static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
142 struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
146 touch_nmi_watchdog();
147 local_irq_save(flags);
150 else if (oops_in_progress)
151 locked = spin_trylock(&up->port.lock);
153 spin_lock(&up->port.lock);
155 uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
156 wait_for_xmit_empty(&up->port);
159 spin_unlock(&up->port.lock);
160 local_irq_restore(flags);
163 static int __init lpc32xx_hsuart_console_setup(struct console *co,
166 struct uart_port *port;
172 if (co->index >= MAX_PORTS)
175 port = &lpc32xx_hs_ports[co->index].port;
180 uart_parse_options(options, &baud, &parity, &bits, &flow);
182 return uart_set_options(port, co, baud, parity, bits, flow);
185 static struct uart_driver lpc32xx_hsuart_reg;
186 static struct console lpc32xx_hsuart_console = {
187 .name = LPC32XX_TTY_NAME,
188 .write = lpc32xx_hsuart_console_write,
189 .device = uart_console_device,
190 .setup = lpc32xx_hsuart_console_setup,
191 .flags = CON_PRINTBUFFER,
193 .data = &lpc32xx_hsuart_reg,
196 static int __init lpc32xx_hsuart_console_init(void)
198 register_console(&lpc32xx_hsuart_console);
201 console_initcall(lpc32xx_hsuart_console_init);
203 #define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
205 #define LPC32XX_HSUART_CONSOLE NULL
208 static struct uart_driver lpc32xx_hs_reg = {
209 .owner = THIS_MODULE,
210 .driver_name = MODNAME,
211 .dev_name = LPC32XX_TTY_NAME,
213 .cons = LPC32XX_HSUART_CONSOLE,
215 static int uarts_registered;
217 static unsigned int __serial_get_clock_div(unsigned long uartclk,
220 u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
223 /* Find the closest divider to get the desired clock rate */
224 div = uartclk / rate;
225 goodrate = hsu_rate = (div / 14) - 1;
230 l_hsu_rate = hsu_rate + 3;
231 rate_diff = 0xFFFFFFFF;
233 while (hsu_rate < l_hsu_rate) {
234 comprate = uartclk / ((hsu_rate + 1) * 14);
235 if (abs(comprate - rate) < rate_diff) {
237 rate_diff = abs(comprate - rate);
248 static void __serial_uart_flush(struct uart_port *port)
253 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
254 (cnt++ < FIFO_READ_LIMIT))
255 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
258 static void __serial_lpc32xx_rx(struct uart_port *port)
260 struct tty_port *tport = &port->state->port;
261 unsigned int tmp, flag;
263 /* Read data from FIFO and push into terminal */
264 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
265 while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
269 if (tmp & LPC32XX_HSU_ERROR_DATA) {
271 writel(LPC32XX_HSU_FE_INT,
272 LPC32XX_HSUART_IIR(port->membase));
273 port->icount.frame++;
275 tty_insert_flip_char(tport, 0, TTY_FRAME);
278 tty_insert_flip_char(tport, (tmp & 0xFF), flag);
280 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
282 tty_flip_buffer_push(tport);
285 static void __serial_lpc32xx_tx(struct uart_port *port)
287 struct circ_buf *xmit = &port->state->xmit;
291 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase));
297 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
301 while (LPC32XX_HSU_TX_LEV(readl(
302 LPC32XX_HSUART_LEVEL(port->membase))) < 64) {
303 writel((u32) xmit->buf[xmit->tail],
304 LPC32XX_HSUART_FIFO(port->membase));
305 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
307 if (uart_circ_empty(xmit))
311 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
312 uart_write_wakeup(port);
315 if (uart_circ_empty(xmit)) {
316 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
317 tmp &= ~LPC32XX_HSU_TX_INT_EN;
318 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
322 static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
324 struct uart_port *port = dev_id;
325 struct tty_port *tport = &port->state->port;
328 spin_lock(&port->lock);
330 /* Read UART status and clear latched interrupts */
331 status = readl(LPC32XX_HSUART_IIR(port->membase));
333 if (status & LPC32XX_HSU_BRK_INT) {
335 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
337 uart_handle_break(port);
341 if (status & LPC32XX_HSU_FE_INT)
342 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
344 if (status & LPC32XX_HSU_RX_OE_INT) {
345 /* Receive FIFO overrun */
346 writel(LPC32XX_HSU_RX_OE_INT,
347 LPC32XX_HSUART_IIR(port->membase));
348 port->icount.overrun++;
349 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
350 tty_schedule_flip(tport);
354 if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) {
355 __serial_lpc32xx_rx(port);
356 tty_flip_buffer_push(tport);
359 /* Transmit data request? */
360 if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
361 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
362 __serial_lpc32xx_tx(port);
365 spin_unlock(&port->lock);
370 /* port->lock is not held. */
371 static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
373 unsigned int ret = 0;
375 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
381 /* port->lock held by caller. */
382 static void serial_lpc32xx_set_mctrl(struct uart_port *port,
385 /* No signals are supported on HS UARTs */
388 /* port->lock is held by caller and interrupts are disabled. */
389 static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
391 /* No signals are supported on HS UARTs */
392 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
395 /* port->lock held by caller. */
396 static void serial_lpc32xx_stop_tx(struct uart_port *port)
400 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
401 tmp &= ~LPC32XX_HSU_TX_INT_EN;
402 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
405 /* port->lock held by caller. */
406 static void serial_lpc32xx_start_tx(struct uart_port *port)
410 __serial_lpc32xx_tx(port);
411 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
412 tmp |= LPC32XX_HSU_TX_INT_EN;
413 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
416 /* port->lock held by caller. */
417 static void serial_lpc32xx_stop_rx(struct uart_port *port)
421 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
422 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
423 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
425 writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
426 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
429 /* port->lock held by caller. */
430 static void serial_lpc32xx_enable_ms(struct uart_port *port)
432 /* Modem status is not supported */
435 /* port->lock is not held. */
436 static void serial_lpc32xx_break_ctl(struct uart_port *port,
442 spin_lock_irqsave(&port->lock, flags);
443 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
444 if (break_state != 0)
445 tmp |= LPC32XX_HSU_BREAK;
447 tmp &= ~LPC32XX_HSU_BREAK;
448 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
449 spin_unlock_irqrestore(&port->lock, flags);
452 /* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
453 static void lpc32xx_loopback_set(resource_size_t mapbase, int state)
459 case LPC32XX_HS_UART1_BASE:
462 case LPC32XX_HS_UART2_BASE:
465 case LPC32XX_HS_UART7_BASE:
469 WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
473 tmp = readl(LPC32XX_UARTCTL_CLOOP);
478 writel(tmp, LPC32XX_UARTCTL_CLOOP);
481 /* port->lock is not held. */
482 static int serial_lpc32xx_startup(struct uart_port *port)
488 spin_lock_irqsave(&port->lock, flags);
490 __serial_uart_flush(port);
492 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
493 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
494 LPC32XX_HSUART_IIR(port->membase));
496 writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
499 * Set receiver timeout, HSU offset of 20, no break, no interrupts,
500 * and default FIFO trigger levels
502 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
503 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
504 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
506 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
508 spin_unlock_irqrestore(&port->lock, flags);
510 retval = request_irq(port->irq, serial_lpc32xx_interrupt,
513 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
514 LPC32XX_HSUART_CTRL(port->membase));
519 /* port->lock is not held. */
520 static void serial_lpc32xx_shutdown(struct uart_port *port)
525 spin_lock_irqsave(&port->lock, flags);
527 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
528 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
529 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
531 lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
533 spin_unlock_irqrestore(&port->lock, flags);
535 free_irq(port->irq, port);
538 /* port->lock is not held. */
539 static void serial_lpc32xx_set_termios(struct uart_port *port,
540 struct ktermios *termios,
541 struct ktermios *old)
544 unsigned int baud, quot;
547 /* Always 8-bit, no parity, 1 stop bit */
548 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
549 termios->c_cflag |= CS8;
551 termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
553 baud = uart_get_baud_rate(port, termios, old, 0,
556 quot = __serial_get_clock_div(port->uartclk, baud);
558 spin_lock_irqsave(&port->lock, flags);
560 /* Ignore characters? */
561 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
562 if ((termios->c_cflag & CREAD) == 0)
563 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
565 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
566 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
568 writel(quot, LPC32XX_HSUART_RATE(port->membase));
570 uart_update_timeout(port, termios->c_cflag, baud);
572 spin_unlock_irqrestore(&port->lock, flags);
574 /* Don't rewrite B0 */
575 if (tty_termios_baud_rate(termios))
576 tty_termios_encode_baud_rate(termios, baud, baud);
579 static const char *serial_lpc32xx_type(struct uart_port *port)
584 static void serial_lpc32xx_release_port(struct uart_port *port)
586 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
587 if (port->flags & UPF_IOREMAP) {
588 iounmap(port->membase);
589 port->membase = NULL;
592 release_mem_region(port->mapbase, SZ_4K);
596 static int serial_lpc32xx_request_port(struct uart_port *port)
600 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
603 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
605 else if (port->flags & UPF_IOREMAP) {
606 port->membase = ioremap(port->mapbase, SZ_4K);
607 if (!port->membase) {
608 release_mem_region(port->mapbase, SZ_4K);
617 static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
621 ret = serial_lpc32xx_request_port(port);
624 port->type = PORT_UART00;
627 __serial_uart_flush(port);
629 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
630 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
631 LPC32XX_HSUART_IIR(port->membase));
633 writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
635 /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
636 and default FIFO trigger levels */
637 writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
638 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
639 LPC32XX_HSUART_CTRL(port->membase));
642 static int serial_lpc32xx_verify_port(struct uart_port *port,
643 struct serial_struct *ser)
647 if (ser->type != PORT_UART00)
653 static struct uart_ops serial_lpc32xx_pops = {
654 .tx_empty = serial_lpc32xx_tx_empty,
655 .set_mctrl = serial_lpc32xx_set_mctrl,
656 .get_mctrl = serial_lpc32xx_get_mctrl,
657 .stop_tx = serial_lpc32xx_stop_tx,
658 .start_tx = serial_lpc32xx_start_tx,
659 .stop_rx = serial_lpc32xx_stop_rx,
660 .enable_ms = serial_lpc32xx_enable_ms,
661 .break_ctl = serial_lpc32xx_break_ctl,
662 .startup = serial_lpc32xx_startup,
663 .shutdown = serial_lpc32xx_shutdown,
664 .set_termios = serial_lpc32xx_set_termios,
665 .type = serial_lpc32xx_type,
666 .release_port = serial_lpc32xx_release_port,
667 .request_port = serial_lpc32xx_request_port,
668 .config_port = serial_lpc32xx_config_port,
669 .verify_port = serial_lpc32xx_verify_port,
673 * Register a set of serial devices attached to a platform device
675 static int serial_hs_lpc32xx_probe(struct platform_device *pdev)
677 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
679 struct resource *res;
681 if (uarts_registered >= MAX_PORTS) {
683 "Error: Number of possible ports exceeded (%d)!\n",
684 uarts_registered + 1);
688 memset(p, 0, sizeof(*p));
690 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
693 "Error getting mem resource for HS UART port %d\n",
697 p->port.mapbase = res->start;
698 p->port.membase = NULL;
700 p->port.irq = platform_get_irq(pdev, 0);
701 if (p->port.irq < 0) {
702 dev_err(&pdev->dev, "Error getting irq for HS UART port %d\n",
707 p->port.iotype = UPIO_MEM32;
708 p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
709 p->port.regshift = 2;
710 p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
711 p->port.dev = &pdev->dev;
712 p->port.ops = &serial_lpc32xx_pops;
713 p->port.line = uarts_registered++;
714 spin_lock_init(&p->port.lock);
716 /* send port to loopback mode by default */
717 lpc32xx_loopback_set(p->port.mapbase, 1);
719 ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
721 platform_set_drvdata(pdev, p);
727 * Remove serial ports registered against a platform device.
729 static int serial_hs_lpc32xx_remove(struct platform_device *pdev)
731 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
733 uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
740 static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
743 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
745 uart_suspend_port(&lpc32xx_hs_reg, &p->port);
750 static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
752 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
754 uart_resume_port(&lpc32xx_hs_reg, &p->port);
759 #define serial_hs_lpc32xx_suspend NULL
760 #define serial_hs_lpc32xx_resume NULL
763 static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
764 { .compatible = "nxp,lpc3220-hsuart" },
768 MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
770 static struct platform_driver serial_hs_lpc32xx_driver = {
771 .probe = serial_hs_lpc32xx_probe,
772 .remove = serial_hs_lpc32xx_remove,
773 .suspend = serial_hs_lpc32xx_suspend,
774 .resume = serial_hs_lpc32xx_resume,
777 .owner = THIS_MODULE,
778 .of_match_table = serial_hs_lpc32xx_dt_ids,
782 static int __init lpc32xx_hsuart_init(void)
786 ret = uart_register_driver(&lpc32xx_hs_reg);
790 ret = platform_driver_register(&serial_hs_lpc32xx_driver);
792 uart_unregister_driver(&lpc32xx_hs_reg);
797 static void __exit lpc32xx_hsuart_exit(void)
799 platform_driver_unregister(&serial_hs_lpc32xx_driver);
800 uart_unregister_driver(&lpc32xx_hs_reg);
803 module_init(lpc32xx_hsuart_init);
804 module_exit(lpc32xx_hsuart_exit);
806 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
807 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
808 MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
809 MODULE_LICENSE("GPL");