2 * Driver for Atmel AT91 / AT32 Serial ports
3 * Copyright (C) 2003 Rick Bronson
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * DMA support added by Chip Coldwell.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/module.h>
26 #include <linux/tty.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/init.h>
30 #include <linux/serial.h>
31 #include <linux/clk.h>
32 #include <linux/console.h>
33 #include <linux/sysrq.h>
34 #include <linux/tty_flip.h>
35 #include <linux/platform_device.h>
37 #include <linux/of_device.h>
38 #include <linux/of_gpio.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/dmaengine.h>
41 #include <linux/atmel_pdc.h>
42 #include <linux/atmel_serial.h>
43 #include <linux/uaccess.h>
44 #include <linux/platform_data/atmel.h>
45 #include <linux/timer.h>
46 #include <linux/gpio.h>
47 #include <linux/gpio/consumer.h>
48 #include <linux/err.h>
49 #include <linux/irq.h>
50 #include <linux/suspend.h>
53 #include <asm/ioctls.h>
55 #define PDC_BUFFER_SIZE 512
56 /* Revisit: We should calculate this based on the actual port settings */
57 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
59 /* The minium number of data FIFOs should be able to contain */
60 #define ATMEL_MIN_FIFO_SIZE 8
62 * These two offsets are substracted from the RX FIFO size to define the RTS
63 * high and low thresholds
65 #define ATMEL_RTS_HIGH_OFFSET 16
66 #define ATMEL_RTS_LOW_OFFSET 20
68 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
72 #include <linux/serial_core.h>
74 #include "serial_mctrl_gpio.h"
76 static void atmel_start_rx(struct uart_port *port);
77 static void atmel_stop_rx(struct uart_port *port);
79 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
81 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
82 * should coexist with the 8250 driver, such as if we have an external 16C550
84 #define SERIAL_ATMEL_MAJOR 204
85 #define MINOR_START 154
86 #define ATMEL_DEVICENAME "ttyAT"
90 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
91 * name, but it is legally reserved for the 8250 driver. */
92 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
93 #define MINOR_START 64
94 #define ATMEL_DEVICENAME "ttyS"
98 #define ATMEL_ISR_PASS_LIMIT 256
100 struct atmel_dma_buffer {
103 unsigned int dma_size;
107 struct atmel_uart_char {
112 #define ATMEL_SERIAL_RINGSIZE 1024
115 * at91: 6 USARTs and one DBGU port (SAM9260)
118 #define ATMEL_MAX_UART 7
121 * We wrap our port structure around the generic uart_port.
123 struct atmel_uart_port {
124 struct uart_port uart; /* uart */
125 struct clk *clk; /* uart clock */
126 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
127 u32 backup_imr; /* IMR saved during suspend */
128 int break_active; /* break being received */
130 bool use_dma_rx; /* enable DMA receiver */
131 bool use_pdc_rx; /* enable PDC receiver */
132 short pdc_rx_idx; /* current PDC RX buffer */
133 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
135 bool use_dma_tx; /* enable DMA transmitter */
136 bool use_pdc_tx; /* enable PDC transmitter */
137 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
139 spinlock_t lock_tx; /* port lock */
140 spinlock_t lock_rx; /* port lock */
141 struct dma_chan *chan_tx;
142 struct dma_chan *chan_rx;
143 struct dma_async_tx_descriptor *desc_tx;
144 struct dma_async_tx_descriptor *desc_rx;
145 dma_cookie_t cookie_tx;
146 dma_cookie_t cookie_rx;
147 struct scatterlist sg_tx;
148 struct scatterlist sg_rx;
149 struct tasklet_struct tasklet;
150 unsigned int irq_status;
151 unsigned int irq_status_prev;
152 unsigned int status_change;
155 struct circ_buf rx_ring;
157 struct mctrl_gpios *gpios;
158 int gpio_irq[UART_GPIO_MAX];
159 unsigned int tx_done_mask;
164 bool is_usart; /* usart or uart */
165 struct timer_list uart_timer; /* uart timer */
168 unsigned int pending;
169 unsigned int pending_status;
170 spinlock_t lock_suspended;
172 int (*prepare_rx)(struct uart_port *port);
173 int (*prepare_tx)(struct uart_port *port);
174 void (*schedule_rx)(struct uart_port *port);
175 void (*schedule_tx)(struct uart_port *port);
176 void (*release_rx)(struct uart_port *port);
177 void (*release_tx)(struct uart_port *port);
180 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
181 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
184 static struct console atmel_console;
187 #if defined(CONFIG_OF)
188 static const struct of_device_id atmel_serial_dt_ids[] = {
189 { .compatible = "atmel,at91rm9200-usart" },
190 { .compatible = "atmel,at91sam9260-usart" },
194 MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids);
197 static inline struct atmel_uart_port *
198 to_atmel_uart_port(struct uart_port *uart)
200 return container_of(uart, struct atmel_uart_port, uart);
203 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
205 return __raw_readl(port->membase + reg);
208 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
210 __raw_writel(value, port->membase + reg);
215 /* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
216 static inline u8 atmel_uart_read_char(struct uart_port *port)
218 return __raw_readl(port->membase + ATMEL_US_RHR);
221 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
223 __raw_writel(value, port->membase + ATMEL_US_THR);
228 static inline u8 atmel_uart_read_char(struct uart_port *port)
230 return __raw_readb(port->membase + ATMEL_US_RHR);
233 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
235 __raw_writeb(value, port->membase + ATMEL_US_THR);
240 #ifdef CONFIG_SERIAL_ATMEL_PDC
241 static bool atmel_use_pdc_rx(struct uart_port *port)
243 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
245 return atmel_port->use_pdc_rx;
248 static bool atmel_use_pdc_tx(struct uart_port *port)
250 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
252 return atmel_port->use_pdc_tx;
255 static bool atmel_use_pdc_rx(struct uart_port *port)
260 static bool atmel_use_pdc_tx(struct uart_port *port)
266 static bool atmel_use_dma_tx(struct uart_port *port)
268 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
270 return atmel_port->use_dma_tx;
273 static bool atmel_use_dma_rx(struct uart_port *port)
275 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
277 return atmel_port->use_dma_rx;
280 static bool atmel_use_fifo(struct uart_port *port)
282 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
284 return atmel_port->fifo_size;
287 static unsigned int atmel_get_lines_status(struct uart_port *port)
289 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
290 unsigned int status, ret = 0;
292 status = atmel_uart_readl(port, ATMEL_US_CSR);
294 mctrl_gpio_get(atmel_port->gpios, &ret);
296 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
299 status &= ~ATMEL_US_CTS;
301 status |= ATMEL_US_CTS;
304 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
307 status &= ~ATMEL_US_DSR;
309 status |= ATMEL_US_DSR;
312 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
315 status &= ~ATMEL_US_RI;
317 status |= ATMEL_US_RI;
320 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
323 status &= ~ATMEL_US_DCD;
325 status |= ATMEL_US_DCD;
331 /* Enable or disable the rs485 support */
332 static int atmel_config_rs485(struct uart_port *port,
333 struct serial_rs485 *rs485conf)
335 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
338 /* Disable interrupts */
339 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
341 mode = atmel_uart_readl(port, ATMEL_US_MR);
343 /* Resetting serial mode to RS232 (0x0) */
344 mode &= ~ATMEL_US_USMODE;
346 port->rs485 = *rs485conf;
348 if (rs485conf->flags & SER_RS485_ENABLED) {
349 dev_dbg(port->dev, "Setting UART to RS485\n");
350 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
351 atmel_uart_writel(port, ATMEL_US_TTGR,
352 rs485conf->delay_rts_after_send);
353 mode |= ATMEL_US_USMODE_RS485;
355 dev_dbg(port->dev, "Setting UART to RS232\n");
356 if (atmel_use_pdc_tx(port))
357 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
360 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
362 atmel_uart_writel(port, ATMEL_US_MR, mode);
364 /* Enable interrupts */
365 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
371 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
373 static u_int atmel_tx_empty(struct uart_port *port)
375 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
381 * Set state of the modem control output lines
383 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
385 unsigned int control = 0;
386 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
387 unsigned int rts_paused, rts_ready;
388 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
390 /* override mode to RS485 if needed, otherwise keep the current mode */
391 if (port->rs485.flags & SER_RS485_ENABLED) {
392 atmel_uart_writel(port, ATMEL_US_TTGR,
393 port->rs485.delay_rts_after_send);
394 mode &= ~ATMEL_US_USMODE;
395 mode |= ATMEL_US_USMODE_RS485;
398 /* set the RTS line state according to the mode */
399 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
400 /* force RTS line to high level */
401 rts_paused = ATMEL_US_RTSEN;
403 /* give the control of the RTS line back to the hardware */
404 rts_ready = ATMEL_US_RTSDIS;
406 /* force RTS line to high level */
407 rts_paused = ATMEL_US_RTSDIS;
409 /* force RTS line to low level */
410 rts_ready = ATMEL_US_RTSEN;
413 if (mctrl & TIOCM_RTS)
414 control |= rts_ready;
416 control |= rts_paused;
418 if (mctrl & TIOCM_DTR)
419 control |= ATMEL_US_DTREN;
421 control |= ATMEL_US_DTRDIS;
423 atmel_uart_writel(port, ATMEL_US_CR, control);
425 mctrl_gpio_set(atmel_port->gpios, mctrl);
427 /* Local loopback mode? */
428 mode &= ~ATMEL_US_CHMODE;
429 if (mctrl & TIOCM_LOOP)
430 mode |= ATMEL_US_CHMODE_LOC_LOOP;
432 mode |= ATMEL_US_CHMODE_NORMAL;
434 atmel_uart_writel(port, ATMEL_US_MR, mode);
438 * Get state of the modem control input lines
440 static u_int atmel_get_mctrl(struct uart_port *port)
442 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
443 unsigned int ret = 0, status;
445 status = atmel_uart_readl(port, ATMEL_US_CSR);
448 * The control signals are active low.
450 if (!(status & ATMEL_US_DCD))
452 if (!(status & ATMEL_US_CTS))
454 if (!(status & ATMEL_US_DSR))
456 if (!(status & ATMEL_US_RI))
459 return mctrl_gpio_get(atmel_port->gpios, &ret);
465 static void atmel_stop_tx(struct uart_port *port)
467 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
469 if (atmel_use_pdc_tx(port)) {
470 /* disable PDC transmit */
471 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
473 /* Disable interrupts */
474 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
476 if ((port->rs485.flags & SER_RS485_ENABLED) &&
477 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
478 atmel_start_rx(port);
482 * Start transmitting.
484 static void atmel_start_tx(struct uart_port *port)
486 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
488 if (atmel_use_pdc_tx(port)) {
489 if (atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN)
490 /* The transmitter is already running. Yes, we
494 if ((port->rs485.flags & SER_RS485_ENABLED) &&
495 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
498 /* re-enable PDC transmit */
499 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
501 /* Enable interrupts */
502 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
506 * start receiving - port is in process of being opened.
508 static void atmel_start_rx(struct uart_port *port)
510 /* reset status and receiver */
511 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
513 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
515 if (atmel_use_pdc_rx(port)) {
516 /* enable PDC controller */
517 atmel_uart_writel(port, ATMEL_US_IER,
518 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
519 port->read_status_mask);
520 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
522 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
527 * Stop receiving - port is in process of being closed.
529 static void atmel_stop_rx(struct uart_port *port)
531 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
533 if (atmel_use_pdc_rx(port)) {
534 /* disable PDC receive */
535 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
536 atmel_uart_writel(port, ATMEL_US_IDR,
537 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
538 port->read_status_mask);
540 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
545 * Enable modem status interrupts
547 static void atmel_enable_ms(struct uart_port *port)
549 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
553 * Interrupt should not be enabled twice
555 if (atmel_port->ms_irq_enabled)
558 atmel_port->ms_irq_enabled = true;
560 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
561 enable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
563 ier |= ATMEL_US_CTSIC;
565 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
566 enable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
568 ier |= ATMEL_US_DSRIC;
570 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
571 enable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
573 ier |= ATMEL_US_RIIC;
575 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
576 enable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
578 ier |= ATMEL_US_DCDIC;
580 atmel_uart_writel(port, ATMEL_US_IER, ier);
584 * Disable modem status interrupts
586 static void atmel_disable_ms(struct uart_port *port)
588 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
592 * Interrupt should not be disabled twice
594 if (!atmel_port->ms_irq_enabled)
597 atmel_port->ms_irq_enabled = false;
599 if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0)
600 disable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]);
602 idr |= ATMEL_US_CTSIC;
604 if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0)
605 disable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]);
607 idr |= ATMEL_US_DSRIC;
609 if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0)
610 disable_irq(atmel_port->gpio_irq[UART_GPIO_RI]);
612 idr |= ATMEL_US_RIIC;
614 if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0)
615 disable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]);
617 idr |= ATMEL_US_DCDIC;
619 atmel_uart_writel(port, ATMEL_US_IDR, idr);
623 * Control the transmission of a break signal
625 static void atmel_break_ctl(struct uart_port *port, int break_state)
627 if (break_state != 0)
629 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
632 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
636 * Stores the incoming character in the ring buffer
639 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
642 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
643 struct circ_buf *ring = &atmel_port->rx_ring;
644 struct atmel_uart_char *c;
646 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
647 /* Buffer overflow, ignore char */
650 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
654 /* Make sure the character is stored before we update head. */
657 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
661 * Deal with parity, framing and overrun errors.
663 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
666 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
668 if (status & ATMEL_US_RXBRK) {
669 /* ignore side-effect */
670 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
673 if (status & ATMEL_US_PARE)
674 port->icount.parity++;
675 if (status & ATMEL_US_FRAME)
676 port->icount.frame++;
677 if (status & ATMEL_US_OVRE)
678 port->icount.overrun++;
682 * Characters received (called from interrupt handler)
684 static void atmel_rx_chars(struct uart_port *port)
686 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
687 unsigned int status, ch;
689 status = atmel_uart_readl(port, ATMEL_US_CSR);
690 while (status & ATMEL_US_RXRDY) {
691 ch = atmel_uart_read_char(port);
694 * note that the error handling code is
695 * out of the main execution path
697 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
698 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
699 || atmel_port->break_active)) {
702 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
704 if (status & ATMEL_US_RXBRK
705 && !atmel_port->break_active) {
706 atmel_port->break_active = 1;
707 atmel_uart_writel(port, ATMEL_US_IER,
711 * This is either the end-of-break
712 * condition or we've received at
713 * least one character without RXBRK
714 * being set. In both cases, the next
715 * RXBRK will indicate start-of-break.
717 atmel_uart_writel(port, ATMEL_US_IDR,
719 status &= ~ATMEL_US_RXBRK;
720 atmel_port->break_active = 0;
724 atmel_buffer_rx_char(port, status, ch);
725 status = atmel_uart_readl(port, ATMEL_US_CSR);
728 tasklet_schedule(&atmel_port->tasklet);
732 * Transmit characters (called from tasklet with TXRDY interrupt
735 static void atmel_tx_chars(struct uart_port *port)
737 struct circ_buf *xmit = &port->state->xmit;
738 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
741 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
742 atmel_uart_write_char(port, port->x_char);
746 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
749 while (atmel_uart_readl(port, ATMEL_US_CSR) &
750 atmel_port->tx_done_mask) {
751 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
752 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
754 if (uart_circ_empty(xmit))
758 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
759 uart_write_wakeup(port);
761 if (!uart_circ_empty(xmit))
762 /* Enable interrupts */
763 atmel_uart_writel(port, ATMEL_US_IER,
764 atmel_port->tx_done_mask);
767 static void atmel_complete_tx_dma(void *arg)
769 struct atmel_uart_port *atmel_port = arg;
770 struct uart_port *port = &atmel_port->uart;
771 struct circ_buf *xmit = &port->state->xmit;
772 struct dma_chan *chan = atmel_port->chan_tx;
775 spin_lock_irqsave(&port->lock, flags);
778 dmaengine_terminate_all(chan);
779 xmit->tail += atmel_port->tx_len;
780 xmit->tail &= UART_XMIT_SIZE - 1;
782 port->icount.tx += atmel_port->tx_len;
784 spin_lock_irq(&atmel_port->lock_tx);
785 async_tx_ack(atmel_port->desc_tx);
786 atmel_port->cookie_tx = -EINVAL;
787 atmel_port->desc_tx = NULL;
788 spin_unlock_irq(&atmel_port->lock_tx);
790 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
791 uart_write_wakeup(port);
794 * xmit is a circular buffer so, if we have just send data from
795 * xmit->tail to the end of xmit->buf, now we have to transmit the
796 * remaining data from the beginning of xmit->buf to xmit->head.
798 if (!uart_circ_empty(xmit))
799 tasklet_schedule(&atmel_port->tasklet);
801 spin_unlock_irqrestore(&port->lock, flags);
804 static void atmel_release_tx_dma(struct uart_port *port)
806 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
807 struct dma_chan *chan = atmel_port->chan_tx;
810 dmaengine_terminate_all(chan);
811 dma_release_channel(chan);
812 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
816 atmel_port->desc_tx = NULL;
817 atmel_port->chan_tx = NULL;
818 atmel_port->cookie_tx = -EINVAL;
822 * Called from tasklet with TXRDY interrupt is disabled.
824 static void atmel_tx_dma(struct uart_port *port)
826 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
827 struct circ_buf *xmit = &port->state->xmit;
828 struct dma_chan *chan = atmel_port->chan_tx;
829 struct dma_async_tx_descriptor *desc;
830 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
831 unsigned int tx_len, part1_len, part2_len, sg_len;
832 dma_addr_t phys_addr;
834 /* Make sure we have an idle channel */
835 if (atmel_port->desc_tx != NULL)
838 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
841 * Port xmit buffer is already mapped,
842 * and it is one page... Just adjust
843 * offsets and lengths. Since it is a circular buffer,
844 * we have to transmit till the end, and then the rest.
845 * Take the port lock to get a
846 * consistent xmit buffer state.
848 tx_len = CIRC_CNT_TO_END(xmit->head,
852 if (atmel_port->fifo_size) {
853 /* multi data mode */
854 part1_len = (tx_len & ~0x3); /* DWORD access */
855 part2_len = (tx_len & 0x3); /* BYTE access */
857 /* single data (legacy) mode */
859 part2_len = tx_len; /* BYTE access only */
862 sg_init_table(sgl, 2);
864 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
867 sg_dma_address(sg) = phys_addr;
868 sg_dma_len(sg) = part1_len;
870 phys_addr += part1_len;
875 sg_dma_address(sg) = phys_addr;
876 sg_dma_len(sg) = part2_len;
880 * save tx_len so atmel_complete_tx_dma() will increase
881 * xmit->tail correctly
883 atmel_port->tx_len = tx_len;
885 desc = dmaengine_prep_slave_sg(chan,
892 dev_err(port->dev, "Failed to send via dma!\n");
896 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
898 atmel_port->desc_tx = desc;
899 desc->callback = atmel_complete_tx_dma;
900 desc->callback_param = atmel_port;
901 atmel_port->cookie_tx = dmaengine_submit(desc);
904 if (port->rs485.flags & SER_RS485_ENABLED) {
905 /* DMA done, stop TX, start RX for RS485 */
906 atmel_start_rx(port);
910 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
911 uart_write_wakeup(port);
914 static int atmel_prepare_tx_dma(struct uart_port *port)
916 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
918 struct dma_slave_config config;
922 dma_cap_set(DMA_SLAVE, mask);
924 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
925 if (atmel_port->chan_tx == NULL)
927 dev_info(port->dev, "using %s for tx DMA transfers\n",
928 dma_chan_name(atmel_port->chan_tx));
930 spin_lock_init(&atmel_port->lock_tx);
931 sg_init_table(&atmel_port->sg_tx, 1);
932 /* UART circular tx buffer is an aligned page. */
933 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
934 sg_set_page(&atmel_port->sg_tx,
935 virt_to_page(port->state->xmit.buf),
937 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
938 nent = dma_map_sg(port->dev,
944 dev_dbg(port->dev, "need to release resource of dma\n");
947 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
948 sg_dma_len(&atmel_port->sg_tx),
949 port->state->xmit.buf,
950 &sg_dma_address(&atmel_port->sg_tx));
953 /* Configure the slave DMA */
954 memset(&config, 0, sizeof(config));
955 config.direction = DMA_MEM_TO_DEV;
956 config.dst_addr_width = (atmel_port->fifo_size) ?
957 DMA_SLAVE_BUSWIDTH_4_BYTES :
958 DMA_SLAVE_BUSWIDTH_1_BYTE;
959 config.dst_addr = port->mapbase + ATMEL_US_THR;
960 config.dst_maxburst = 1;
962 ret = dmaengine_slave_config(atmel_port->chan_tx,
965 dev_err(port->dev, "DMA tx slave configuration failed\n");
972 dev_err(port->dev, "TX channel not available, switch to pio\n");
973 atmel_port->use_dma_tx = 0;
974 if (atmel_port->chan_tx)
975 atmel_release_tx_dma(port);
979 static void atmel_complete_rx_dma(void *arg)
981 struct uart_port *port = arg;
982 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
984 tasklet_schedule(&atmel_port->tasklet);
987 static void atmel_release_rx_dma(struct uart_port *port)
989 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
990 struct dma_chan *chan = atmel_port->chan_rx;
993 dmaengine_terminate_all(chan);
994 dma_release_channel(chan);
995 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
999 atmel_port->desc_rx = NULL;
1000 atmel_port->chan_rx = NULL;
1001 atmel_port->cookie_rx = -EINVAL;
1004 static void atmel_rx_from_dma(struct uart_port *port)
1006 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1007 struct tty_port *tport = &port->state->port;
1008 struct circ_buf *ring = &atmel_port->rx_ring;
1009 struct dma_chan *chan = atmel_port->chan_rx;
1010 struct dma_tx_state state;
1011 enum dma_status dmastat;
1015 /* Reset the UART timeout early so that we don't miss one */
1016 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1017 dmastat = dmaengine_tx_status(chan,
1018 atmel_port->cookie_rx,
1020 /* Restart a new tasklet if DMA status is error */
1021 if (dmastat == DMA_ERROR) {
1022 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1023 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1024 tasklet_schedule(&atmel_port->tasklet);
1028 /* CPU claims ownership of RX DMA buffer */
1029 dma_sync_sg_for_cpu(port->dev,
1035 * ring->head points to the end of data already written by the DMA.
1036 * ring->tail points to the beginning of data to be read by the
1038 * The current transfer size should not be larger than the dma buffer
1041 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1042 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1044 * At this point ring->head may point to the first byte right after the
1045 * last byte of the dma buffer:
1046 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1048 * However ring->tail must always points inside the dma buffer:
1049 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1051 * Since we use a ring buffer, we have to handle the case
1052 * where head is lower than tail. In such a case, we first read from
1053 * tail to the end of the buffer then reset tail.
1055 if (ring->head < ring->tail) {
1056 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1058 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1060 port->icount.rx += count;
1063 /* Finally we read data from tail to head */
1064 if (ring->tail < ring->head) {
1065 count = ring->head - ring->tail;
1067 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1068 /* Wrap ring->head if needed */
1069 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1071 ring->tail = ring->head;
1072 port->icount.rx += count;
1075 /* USART retreives ownership of RX DMA buffer */
1076 dma_sync_sg_for_device(port->dev,
1082 * Drop the lock here since it might end up calling
1083 * uart_start(), which takes the lock.
1085 spin_unlock(&port->lock);
1086 tty_flip_buffer_push(tport);
1087 spin_lock(&port->lock);
1089 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1092 static int atmel_prepare_rx_dma(struct uart_port *port)
1094 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1095 struct dma_async_tx_descriptor *desc;
1096 dma_cap_mask_t mask;
1097 struct dma_slave_config config;
1098 struct circ_buf *ring;
1101 ring = &atmel_port->rx_ring;
1104 dma_cap_set(DMA_CYCLIC, mask);
1106 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1107 if (atmel_port->chan_rx == NULL)
1109 dev_info(port->dev, "using %s for rx DMA transfers\n",
1110 dma_chan_name(atmel_port->chan_rx));
1112 spin_lock_init(&atmel_port->lock_rx);
1113 sg_init_table(&atmel_port->sg_rx, 1);
1114 /* UART circular rx buffer is an aligned page. */
1115 BUG_ON(!PAGE_ALIGNED(ring->buf));
1116 sg_set_page(&atmel_port->sg_rx,
1117 virt_to_page(ring->buf),
1118 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1119 (unsigned long)ring->buf & ~PAGE_MASK);
1120 nent = dma_map_sg(port->dev,
1126 dev_dbg(port->dev, "need to release resource of dma\n");
1129 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1130 sg_dma_len(&atmel_port->sg_rx),
1132 &sg_dma_address(&atmel_port->sg_rx));
1135 /* Configure the slave DMA */
1136 memset(&config, 0, sizeof(config));
1137 config.direction = DMA_DEV_TO_MEM;
1138 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1139 config.src_addr = port->mapbase + ATMEL_US_RHR;
1140 config.src_maxburst = 1;
1142 ret = dmaengine_slave_config(atmel_port->chan_rx,
1145 dev_err(port->dev, "DMA rx slave configuration failed\n");
1149 * Prepare a cyclic dma transfer, assign 2 descriptors,
1150 * each one is half ring buffer size
1152 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1153 sg_dma_address(&atmel_port->sg_rx),
1154 sg_dma_len(&atmel_port->sg_rx),
1155 sg_dma_len(&atmel_port->sg_rx)/2,
1157 DMA_PREP_INTERRUPT);
1158 desc->callback = atmel_complete_rx_dma;
1159 desc->callback_param = port;
1160 atmel_port->desc_rx = desc;
1161 atmel_port->cookie_rx = dmaengine_submit(desc);
1166 dev_err(port->dev, "RX channel not available, switch to pio\n");
1167 atmel_port->use_dma_rx = 0;
1168 if (atmel_port->chan_rx)
1169 atmel_release_rx_dma(port);
1173 static void atmel_uart_timer_callback(unsigned long data)
1175 struct uart_port *port = (void *)data;
1176 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1178 tasklet_schedule(&atmel_port->tasklet);
1179 mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port));
1183 * receive interrupt handler.
1186 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1188 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1190 if (atmel_use_pdc_rx(port)) {
1192 * PDC receive. Just schedule the tasklet and let it
1193 * figure out the details.
1195 * TODO: We're not handling error flags correctly at
1198 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1199 atmel_uart_writel(port, ATMEL_US_IDR,
1200 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1201 tasklet_schedule(&atmel_port->tasklet);
1204 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1205 ATMEL_US_FRAME | ATMEL_US_PARE))
1206 atmel_pdc_rxerr(port, pending);
1209 if (atmel_use_dma_rx(port)) {
1210 if (pending & ATMEL_US_TIMEOUT) {
1211 atmel_uart_writel(port, ATMEL_US_IDR,
1213 tasklet_schedule(&atmel_port->tasklet);
1217 /* Interrupt receive */
1218 if (pending & ATMEL_US_RXRDY)
1219 atmel_rx_chars(port);
1220 else if (pending & ATMEL_US_RXBRK) {
1222 * End of break detected. If it came along with a
1223 * character, atmel_rx_chars will handle it.
1225 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1226 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1227 atmel_port->break_active = 0;
1232 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1235 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1237 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1239 if (pending & atmel_port->tx_done_mask) {
1240 /* Either PDC or interrupt transmission */
1241 atmel_uart_writel(port, ATMEL_US_IDR,
1242 atmel_port->tx_done_mask);
1243 tasklet_schedule(&atmel_port->tasklet);
1248 * status flags interrupt handler.
1251 atmel_handle_status(struct uart_port *port, unsigned int pending,
1252 unsigned int status)
1254 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1256 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1257 | ATMEL_US_CTSIC)) {
1258 atmel_port->irq_status = status;
1259 atmel_port->status_change = atmel_port->irq_status ^
1260 atmel_port->irq_status_prev;
1261 atmel_port->irq_status_prev = status;
1262 tasklet_schedule(&atmel_port->tasklet);
1269 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1271 struct uart_port *port = dev_id;
1272 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1273 unsigned int status, pending, mask, pass_counter = 0;
1274 bool gpio_handled = false;
1276 spin_lock(&atmel_port->lock_suspended);
1279 status = atmel_get_lines_status(port);
1280 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1281 pending = status & mask;
1282 if (!gpio_handled) {
1284 * Dealing with GPIO interrupt
1286 if (irq == atmel_port->gpio_irq[UART_GPIO_CTS])
1287 pending |= ATMEL_US_CTSIC;
1289 if (irq == atmel_port->gpio_irq[UART_GPIO_DSR])
1290 pending |= ATMEL_US_DSRIC;
1292 if (irq == atmel_port->gpio_irq[UART_GPIO_RI])
1293 pending |= ATMEL_US_RIIC;
1295 if (irq == atmel_port->gpio_irq[UART_GPIO_DCD])
1296 pending |= ATMEL_US_DCDIC;
1298 gpio_handled = true;
1303 if (atmel_port->suspended) {
1304 atmel_port->pending |= pending;
1305 atmel_port->pending_status = status;
1306 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1311 atmel_handle_receive(port, pending);
1312 atmel_handle_status(port, pending, status);
1313 atmel_handle_transmit(port, pending);
1314 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1316 spin_unlock(&atmel_port->lock_suspended);
1318 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1321 static void atmel_release_tx_pdc(struct uart_port *port)
1323 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1324 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1326 dma_unmap_single(port->dev,
1333 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1335 static void atmel_tx_pdc(struct uart_port *port)
1337 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1338 struct circ_buf *xmit = &port->state->xmit;
1339 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1342 /* nothing left to transmit? */
1343 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1346 xmit->tail += pdc->ofs;
1347 xmit->tail &= UART_XMIT_SIZE - 1;
1349 port->icount.tx += pdc->ofs;
1352 /* more to transmit - setup next transfer */
1354 /* disable PDC transmit */
1355 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1357 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1358 dma_sync_single_for_device(port->dev,
1363 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1366 atmel_uart_writel(port, ATMEL_PDC_TPR,
1367 pdc->dma_addr + xmit->tail);
1368 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1369 /* re-enable PDC transmit */
1370 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1371 /* Enable interrupts */
1372 atmel_uart_writel(port, ATMEL_US_IER,
1373 atmel_port->tx_done_mask);
1375 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1376 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
1377 /* DMA done, stop TX, start RX for RS485 */
1378 atmel_start_rx(port);
1382 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1383 uart_write_wakeup(port);
1386 static int atmel_prepare_tx_pdc(struct uart_port *port)
1388 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1389 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1390 struct circ_buf *xmit = &port->state->xmit;
1392 pdc->buf = xmit->buf;
1393 pdc->dma_addr = dma_map_single(port->dev,
1397 pdc->dma_size = UART_XMIT_SIZE;
1403 static void atmel_rx_from_ring(struct uart_port *port)
1405 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1406 struct circ_buf *ring = &atmel_port->rx_ring;
1408 unsigned int status;
1410 while (ring->head != ring->tail) {
1411 struct atmel_uart_char c;
1413 /* Make sure c is loaded after head. */
1416 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1418 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1425 * note that the error handling code is
1426 * out of the main execution path
1428 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1429 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1430 if (status & ATMEL_US_RXBRK) {
1431 /* ignore side-effect */
1432 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1435 if (uart_handle_break(port))
1438 if (status & ATMEL_US_PARE)
1439 port->icount.parity++;
1440 if (status & ATMEL_US_FRAME)
1441 port->icount.frame++;
1442 if (status & ATMEL_US_OVRE)
1443 port->icount.overrun++;
1445 status &= port->read_status_mask;
1447 if (status & ATMEL_US_RXBRK)
1449 else if (status & ATMEL_US_PARE)
1451 else if (status & ATMEL_US_FRAME)
1456 if (uart_handle_sysrq_char(port, c.ch))
1459 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1463 * Drop the lock here since it might end up calling
1464 * uart_start(), which takes the lock.
1466 spin_unlock(&port->lock);
1467 tty_flip_buffer_push(&port->state->port);
1468 spin_lock(&port->lock);
1471 static void atmel_release_rx_pdc(struct uart_port *port)
1473 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1476 for (i = 0; i < 2; i++) {
1477 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1479 dma_unmap_single(port->dev,
1487 static void atmel_rx_from_pdc(struct uart_port *port)
1489 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1490 struct tty_port *tport = &port->state->port;
1491 struct atmel_dma_buffer *pdc;
1492 int rx_idx = atmel_port->pdc_rx_idx;
1498 /* Reset the UART timeout early so that we don't miss one */
1499 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1501 pdc = &atmel_port->pdc_rx[rx_idx];
1502 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1505 /* If the PDC has switched buffers, RPR won't contain
1506 * any address within the current buffer. Since head
1507 * is unsigned, we just need a one-way comparison to
1510 * In this case, we just need to consume the entire
1511 * buffer and resubmit it for DMA. This will clear the
1512 * ENDRX bit as well, so that we can safely re-enable
1513 * all interrupts below.
1515 head = min(head, pdc->dma_size);
1517 if (likely(head != tail)) {
1518 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1519 pdc->dma_size, DMA_FROM_DEVICE);
1522 * head will only wrap around when we recycle
1523 * the DMA buffer, and when that happens, we
1524 * explicitly set tail to 0. So head will
1525 * always be greater than tail.
1527 count = head - tail;
1529 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1532 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1533 pdc->dma_size, DMA_FROM_DEVICE);
1535 port->icount.rx += count;
1540 * If the current buffer is full, we need to check if
1541 * the next one contains any additional data.
1543 if (head >= pdc->dma_size) {
1545 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1546 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1549 atmel_port->pdc_rx_idx = rx_idx;
1551 } while (head >= pdc->dma_size);
1554 * Drop the lock here since it might end up calling
1555 * uart_start(), which takes the lock.
1557 spin_unlock(&port->lock);
1558 tty_flip_buffer_push(tport);
1559 spin_lock(&port->lock);
1561 atmel_uart_writel(port, ATMEL_US_IER,
1562 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1565 static int atmel_prepare_rx_pdc(struct uart_port *port)
1567 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1570 for (i = 0; i < 2; i++) {
1571 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1573 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1574 if (pdc->buf == NULL) {
1576 dma_unmap_single(port->dev,
1577 atmel_port->pdc_rx[0].dma_addr,
1580 kfree(atmel_port->pdc_rx[0].buf);
1582 atmel_port->use_pdc_rx = 0;
1585 pdc->dma_addr = dma_map_single(port->dev,
1589 pdc->dma_size = PDC_BUFFER_SIZE;
1593 atmel_port->pdc_rx_idx = 0;
1595 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1596 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1598 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1599 atmel_port->pdc_rx[1].dma_addr);
1600 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1606 * tasklet handling tty stuff outside the interrupt handler.
1608 static void atmel_tasklet_func(unsigned long data)
1610 struct uart_port *port = (struct uart_port *)data;
1611 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1612 unsigned int status = atmel_port->irq_status;
1613 unsigned int status_change = atmel_port->status_change;
1615 /* The interrupt handler does not take the lock */
1616 spin_lock(&port->lock);
1618 atmel_port->schedule_tx(port);
1620 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1621 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1622 /* TODO: All reads to CSR will clear these interrupts! */
1623 if (status_change & ATMEL_US_RI)
1625 if (status_change & ATMEL_US_DSR)
1627 if (status_change & ATMEL_US_DCD)
1628 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1629 if (status_change & ATMEL_US_CTS)
1630 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1632 wake_up_interruptible(&port->state->port.delta_msr_wait);
1634 atmel_port->status_change = 0;
1637 atmel_port->schedule_rx(port);
1639 spin_unlock(&port->lock);
1642 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1643 struct platform_device *pdev)
1645 struct device_node *np = pdev->dev.of_node;
1646 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1649 /* DMA/PDC usage specification */
1650 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1651 if (of_get_property(np, "dmas", NULL)) {
1652 atmel_port->use_dma_rx = true;
1653 atmel_port->use_pdc_rx = false;
1655 atmel_port->use_dma_rx = false;
1656 atmel_port->use_pdc_rx = true;
1659 atmel_port->use_dma_rx = false;
1660 atmel_port->use_pdc_rx = false;
1663 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1664 if (of_get_property(np, "dmas", NULL)) {
1665 atmel_port->use_dma_tx = true;
1666 atmel_port->use_pdc_tx = false;
1668 atmel_port->use_dma_tx = false;
1669 atmel_port->use_pdc_tx = true;
1672 atmel_port->use_dma_tx = false;
1673 atmel_port->use_pdc_tx = false;
1677 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1678 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1679 atmel_port->use_dma_rx = false;
1680 atmel_port->use_dma_tx = false;
1685 static void atmel_init_rs485(struct uart_port *port,
1686 struct platform_device *pdev)
1688 struct device_node *np = pdev->dev.of_node;
1689 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1692 struct serial_rs485 *rs485conf = &port->rs485;
1694 /* rs485 properties */
1695 if (of_property_read_u32_array(np, "rs485-rts-delay",
1696 rs485_delay, 2) == 0) {
1697 rs485conf->delay_rts_before_send = rs485_delay[0];
1698 rs485conf->delay_rts_after_send = rs485_delay[1];
1699 rs485conf->flags = 0;
1702 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1703 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1705 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1707 rs485conf->flags |= SER_RS485_ENABLED;
1709 port->rs485 = pdata->rs485;
1714 static void atmel_set_ops(struct uart_port *port)
1716 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1718 if (atmel_use_dma_rx(port)) {
1719 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1720 atmel_port->schedule_rx = &atmel_rx_from_dma;
1721 atmel_port->release_rx = &atmel_release_rx_dma;
1722 } else if (atmel_use_pdc_rx(port)) {
1723 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1724 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1725 atmel_port->release_rx = &atmel_release_rx_pdc;
1727 atmel_port->prepare_rx = NULL;
1728 atmel_port->schedule_rx = &atmel_rx_from_ring;
1729 atmel_port->release_rx = NULL;
1732 if (atmel_use_dma_tx(port)) {
1733 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1734 atmel_port->schedule_tx = &atmel_tx_dma;
1735 atmel_port->release_tx = &atmel_release_tx_dma;
1736 } else if (atmel_use_pdc_tx(port)) {
1737 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1738 atmel_port->schedule_tx = &atmel_tx_pdc;
1739 atmel_port->release_tx = &atmel_release_tx_pdc;
1741 atmel_port->prepare_tx = NULL;
1742 atmel_port->schedule_tx = &atmel_tx_chars;
1743 atmel_port->release_tx = NULL;
1748 * Get ip name usart or uart
1750 static void atmel_get_ip_name(struct uart_port *port)
1752 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1753 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1756 /* usart and uart ascii */
1760 atmel_port->is_usart = false;
1762 if (name == usart) {
1763 dev_dbg(port->dev, "This is usart\n");
1764 atmel_port->is_usart = true;
1765 } else if (name == uart) {
1766 dev_dbg(port->dev, "This is uart\n");
1767 atmel_port->is_usart = false;
1769 /* fallback for older SoCs: use version field */
1770 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1774 dev_dbg(port->dev, "This version is usart\n");
1775 atmel_port->is_usart = true;
1779 dev_dbg(port->dev, "This version is uart\n");
1780 atmel_port->is_usart = false;
1783 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1788 static void atmel_free_gpio_irq(struct uart_port *port)
1790 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1791 enum mctrl_gpio_idx i;
1793 for (i = 0; i < UART_GPIO_MAX; i++)
1794 if (atmel_port->gpio_irq[i] >= 0)
1795 free_irq(atmel_port->gpio_irq[i], port);
1798 static int atmel_request_gpio_irq(struct uart_port *port)
1800 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1801 int *irq = atmel_port->gpio_irq;
1802 enum mctrl_gpio_idx i;
1805 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) {
1809 irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
1810 err = request_irq(irq[i], atmel_interrupt, IRQ_TYPE_EDGE_BOTH,
1811 "atmel_serial", port);
1813 dev_err(port->dev, "atmel_startup - Can't get %d irq\n",
1818 * If something went wrong, rollback.
1820 while (err && (--i >= 0))
1822 free_irq(irq[i], port);
1828 * Perform initialization and enable port for reception
1830 static int atmel_startup(struct uart_port *port)
1832 struct platform_device *pdev = to_platform_device(port->dev);
1833 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1834 struct tty_struct *tty = port->state->port.tty;
1838 * Ensure that no interrupts are enabled otherwise when
1839 * request_irq() is called we could get stuck trying to
1840 * handle an unexpected interrupt
1842 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1843 atmel_port->ms_irq_enabled = false;
1848 retval = request_irq(port->irq, atmel_interrupt,
1849 IRQF_SHARED | IRQF_COND_SUSPEND,
1850 tty ? tty->name : "atmel_serial", port);
1852 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1857 * Get the GPIO lines IRQ
1859 retval = atmel_request_gpio_irq(port);
1863 tasklet_enable(&atmel_port->tasklet);
1866 * Initialize DMA (if necessary)
1868 atmel_init_property(atmel_port, pdev);
1869 atmel_set_ops(port);
1871 if (atmel_port->prepare_rx) {
1872 retval = atmel_port->prepare_rx(port);
1874 atmel_set_ops(port);
1877 if (atmel_port->prepare_tx) {
1878 retval = atmel_port->prepare_tx(port);
1880 atmel_set_ops(port);
1884 * Enable FIFO when available
1886 if (atmel_port->fifo_size) {
1887 unsigned int txrdym = ATMEL_US_ONE_DATA;
1888 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1891 atmel_uart_writel(port, ATMEL_US_CR,
1896 if (atmel_use_dma_tx(port))
1897 txrdym = ATMEL_US_FOUR_DATA;
1899 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1900 if (atmel_port->rts_high &&
1901 atmel_port->rts_low)
1902 fmr |= ATMEL_US_FRTSC |
1903 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1904 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1906 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1909 /* Save current CSR for comparison in atmel_tasklet_func() */
1910 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1911 atmel_port->irq_status = atmel_port->irq_status_prev;
1914 * Finally, enable the serial port
1916 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1917 /* enable xmit & rcvr */
1918 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1920 setup_timer(&atmel_port->uart_timer,
1921 atmel_uart_timer_callback,
1922 (unsigned long)port);
1924 if (atmel_use_pdc_rx(port)) {
1925 /* set UART timeout */
1926 if (!atmel_port->is_usart) {
1927 mod_timer(&atmel_port->uart_timer,
1928 jiffies + uart_poll_timeout(port));
1929 /* set USART timeout */
1931 atmel_uart_writel(port, ATMEL_US_RTOR, PDC_RX_TIMEOUT);
1932 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1934 atmel_uart_writel(port, ATMEL_US_IER,
1935 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1937 /* enable PDC controller */
1938 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1939 } else if (atmel_use_dma_rx(port)) {
1940 /* set UART timeout */
1941 if (!atmel_port->is_usart) {
1942 mod_timer(&atmel_port->uart_timer,
1943 jiffies + uart_poll_timeout(port));
1944 /* set USART timeout */
1946 atmel_uart_writel(port, ATMEL_US_RTOR, PDC_RX_TIMEOUT);
1947 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1949 atmel_uart_writel(port, ATMEL_US_IER,
1953 /* enable receive only */
1954 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1960 free_irq(port->irq, port);
1966 * Flush any TX data submitted for DMA. Called when the TX circular
1969 static void atmel_flush_buffer(struct uart_port *port)
1971 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1973 if (atmel_use_pdc_tx(port)) {
1974 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1975 atmel_port->pdc_tx.ofs = 0;
1982 static void atmel_shutdown(struct uart_port *port)
1984 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1987 * Prevent any tasklets being scheduled during
1990 del_timer_sync(&atmel_port->uart_timer);
1993 * Clear out any scheduled tasklets before
1994 * we destroy the buffers
1996 tasklet_disable(&atmel_port->tasklet);
1997 tasklet_kill(&atmel_port->tasklet);
2000 * Ensure everything is stopped and
2001 * disable all interrupts, port and break condition.
2003 atmel_stop_rx(port);
2004 atmel_stop_tx(port);
2006 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2007 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2011 * Shut-down the DMA.
2013 if (atmel_port->release_rx)
2014 atmel_port->release_rx(port);
2015 if (atmel_port->release_tx)
2016 atmel_port->release_tx(port);
2019 * Reset ring buffer pointers
2021 atmel_port->rx_ring.head = 0;
2022 atmel_port->rx_ring.tail = 0;
2025 * Free the interrupts
2027 free_irq(port->irq, port);
2028 atmel_free_gpio_irq(port);
2030 atmel_port->ms_irq_enabled = false;
2032 atmel_flush_buffer(port);
2036 * Power / Clock management.
2038 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2039 unsigned int oldstate)
2041 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2046 * Enable the peripheral clock for this serial port.
2047 * This is called on uart_open() or a resume event.
2049 clk_prepare_enable(atmel_port->clk);
2051 /* re-enable interrupts if we disabled some on suspend */
2052 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2055 /* Back up the interrupt mask and disable all interrupts */
2056 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2057 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2060 * Disable the peripheral clock for this serial port.
2061 * This is called on uart_close() or a suspend event.
2063 clk_disable_unprepare(atmel_port->clk);
2066 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2071 * Change the port parameters
2073 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2074 struct ktermios *old)
2076 unsigned long flags;
2077 unsigned int old_mode, mode, imr, quot, baud;
2079 /* save the current mode register */
2080 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2082 /* reset the mode, clock divisor, parity, stop bits and data size */
2083 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2084 ATMEL_US_PAR | ATMEL_US_USMODE);
2086 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2087 quot = uart_get_divisor(port, baud);
2089 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2091 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2095 switch (termios->c_cflag & CSIZE) {
2097 mode |= ATMEL_US_CHRL_5;
2100 mode |= ATMEL_US_CHRL_6;
2103 mode |= ATMEL_US_CHRL_7;
2106 mode |= ATMEL_US_CHRL_8;
2111 if (termios->c_cflag & CSTOPB)
2112 mode |= ATMEL_US_NBSTOP_2;
2115 if (termios->c_cflag & PARENB) {
2116 /* Mark or Space parity */
2117 if (termios->c_cflag & CMSPAR) {
2118 if (termios->c_cflag & PARODD)
2119 mode |= ATMEL_US_PAR_MARK;
2121 mode |= ATMEL_US_PAR_SPACE;
2122 } else if (termios->c_cflag & PARODD)
2123 mode |= ATMEL_US_PAR_ODD;
2125 mode |= ATMEL_US_PAR_EVEN;
2127 mode |= ATMEL_US_PAR_NONE;
2129 spin_lock_irqsave(&port->lock, flags);
2131 port->read_status_mask = ATMEL_US_OVRE;
2132 if (termios->c_iflag & INPCK)
2133 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2134 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2135 port->read_status_mask |= ATMEL_US_RXBRK;
2137 if (atmel_use_pdc_rx(port))
2138 /* need to enable error interrupts */
2139 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2142 * Characters to ignore
2144 port->ignore_status_mask = 0;
2145 if (termios->c_iflag & IGNPAR)
2146 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2147 if (termios->c_iflag & IGNBRK) {
2148 port->ignore_status_mask |= ATMEL_US_RXBRK;
2150 * If we're ignoring parity and break indicators,
2151 * ignore overruns too (for real raw support).
2153 if (termios->c_iflag & IGNPAR)
2154 port->ignore_status_mask |= ATMEL_US_OVRE;
2156 /* TODO: Ignore all characters if CREAD is set.*/
2158 /* update the per-port timeout */
2159 uart_update_timeout(port, termios->c_cflag, baud);
2162 * save/disable interrupts. The tty layer will ensure that the
2163 * transmitter is empty if requested by the caller, so there's
2164 * no need to wait for it here.
2166 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2167 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2169 /* disable receiver and transmitter */
2170 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2173 if (port->rs485.flags & SER_RS485_ENABLED) {
2174 atmel_uart_writel(port, ATMEL_US_TTGR,
2175 port->rs485.delay_rts_after_send);
2176 mode |= ATMEL_US_USMODE_RS485;
2177 } else if (termios->c_cflag & CRTSCTS) {
2178 /* RS232 with hardware handshake (RTS/CTS) */
2179 if (atmel_use_dma_rx(port) && !atmel_use_fifo(port)) {
2180 dev_info(port->dev, "not enabling hardware flow control because DMA is used");
2181 termios->c_cflag &= ~CRTSCTS;
2183 mode |= ATMEL_US_USMODE_HWHS;
2186 /* RS232 without hadware handshake */
2187 mode |= ATMEL_US_USMODE_NORMAL;
2190 /* set the mode, clock divisor, parity, stop bits and data size */
2191 atmel_uart_writel(port, ATMEL_US_MR, mode);
2194 * when switching the mode, set the RTS line state according to the
2195 * new mode, otherwise keep the former state
2197 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2198 unsigned int rts_state;
2200 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2201 /* let the hardware control the RTS line */
2202 rts_state = ATMEL_US_RTSDIS;
2204 /* force RTS line to low level */
2205 rts_state = ATMEL_US_RTSEN;
2208 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2211 /* set the baud rate */
2212 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2213 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2214 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2216 /* restore interrupts */
2217 atmel_uart_writel(port, ATMEL_US_IER, imr);
2219 /* CTS flow-control and modem-status interrupts */
2220 if (UART_ENABLE_MS(port, termios->c_cflag))
2221 atmel_enable_ms(port);
2223 atmel_disable_ms(port);
2225 spin_unlock_irqrestore(&port->lock, flags);
2228 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2230 if (termios->c_line == N_PPS) {
2231 port->flags |= UPF_HARDPPS_CD;
2232 spin_lock_irq(&port->lock);
2233 atmel_enable_ms(port);
2234 spin_unlock_irq(&port->lock);
2236 port->flags &= ~UPF_HARDPPS_CD;
2237 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2238 spin_lock_irq(&port->lock);
2239 atmel_disable_ms(port);
2240 spin_unlock_irq(&port->lock);
2246 * Return string describing the specified port
2248 static const char *atmel_type(struct uart_port *port)
2250 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2254 * Release the memory region(s) being used by 'port'.
2256 static void atmel_release_port(struct uart_port *port)
2258 struct platform_device *pdev = to_platform_device(port->dev);
2259 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2261 release_mem_region(port->mapbase, size);
2263 if (port->flags & UPF_IOREMAP) {
2264 iounmap(port->membase);
2265 port->membase = NULL;
2270 * Request the memory region(s) being used by 'port'.
2272 static int atmel_request_port(struct uart_port *port)
2274 struct platform_device *pdev = to_platform_device(port->dev);
2275 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2277 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2280 if (port->flags & UPF_IOREMAP) {
2281 port->membase = ioremap(port->mapbase, size);
2282 if (port->membase == NULL) {
2283 release_mem_region(port->mapbase, size);
2292 * Configure/autoconfigure the port.
2294 static void atmel_config_port(struct uart_port *port, int flags)
2296 if (flags & UART_CONFIG_TYPE) {
2297 port->type = PORT_ATMEL;
2298 atmel_request_port(port);
2303 * Verify the new serial_struct (for TIOCSSERIAL).
2305 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2308 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2310 if (port->irq != ser->irq)
2312 if (ser->io_type != SERIAL_IO_MEM)
2314 if (port->uartclk / 16 != ser->baud_base)
2316 if (port->mapbase != (unsigned long)ser->iomem_base)
2318 if (port->iobase != ser->port)
2325 #ifdef CONFIG_CONSOLE_POLL
2326 static int atmel_poll_get_char(struct uart_port *port)
2328 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2331 return atmel_uart_read_char(port);
2334 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2336 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2339 atmel_uart_write_char(port, ch);
2343 static struct uart_ops atmel_pops = {
2344 .tx_empty = atmel_tx_empty,
2345 .set_mctrl = atmel_set_mctrl,
2346 .get_mctrl = atmel_get_mctrl,
2347 .stop_tx = atmel_stop_tx,
2348 .start_tx = atmel_start_tx,
2349 .stop_rx = atmel_stop_rx,
2350 .enable_ms = atmel_enable_ms,
2351 .break_ctl = atmel_break_ctl,
2352 .startup = atmel_startup,
2353 .shutdown = atmel_shutdown,
2354 .flush_buffer = atmel_flush_buffer,
2355 .set_termios = atmel_set_termios,
2356 .set_ldisc = atmel_set_ldisc,
2358 .release_port = atmel_release_port,
2359 .request_port = atmel_request_port,
2360 .config_port = atmel_config_port,
2361 .verify_port = atmel_verify_port,
2362 .pm = atmel_serial_pm,
2363 #ifdef CONFIG_CONSOLE_POLL
2364 .poll_get_char = atmel_poll_get_char,
2365 .poll_put_char = atmel_poll_put_char,
2370 * Configure the port from the platform device resource info.
2372 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2373 struct platform_device *pdev)
2376 struct uart_port *port = &atmel_port->uart;
2377 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2379 atmel_init_property(atmel_port, pdev);
2380 atmel_set_ops(port);
2382 atmel_init_rs485(port, pdev);
2384 port->iotype = UPIO_MEM;
2385 port->flags = UPF_BOOT_AUTOCONF;
2386 port->ops = &atmel_pops;
2388 port->dev = &pdev->dev;
2389 port->mapbase = pdev->resource[0].start;
2390 port->irq = pdev->resource[1].start;
2391 port->rs485_config = atmel_config_rs485;
2393 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
2394 (unsigned long)port);
2395 tasklet_disable(&atmel_port->tasklet);
2397 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2399 if (pdata && pdata->regs) {
2400 /* Already mapped by setup code */
2401 port->membase = pdata->regs;
2403 port->flags |= UPF_IOREMAP;
2404 port->membase = NULL;
2407 /* for console, the clock could already be configured */
2408 if (!atmel_port->clk) {
2409 atmel_port->clk = clk_get(&pdev->dev, "usart");
2410 if (IS_ERR(atmel_port->clk)) {
2411 ret = PTR_ERR(atmel_port->clk);
2412 atmel_port->clk = NULL;
2415 ret = clk_prepare_enable(atmel_port->clk);
2417 clk_put(atmel_port->clk);
2418 atmel_port->clk = NULL;
2421 port->uartclk = clk_get_rate(atmel_port->clk);
2422 clk_disable_unprepare(atmel_port->clk);
2423 /* only enable clock when USART is in use */
2426 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2427 if (port->rs485.flags & SER_RS485_ENABLED)
2428 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2429 else if (atmel_use_pdc_tx(port)) {
2430 port->fifosize = PDC_BUFFER_SIZE;
2431 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2433 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2439 struct platform_device *atmel_default_console_device; /* the serial console device */
2441 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2442 static void atmel_console_putchar(struct uart_port *port, int ch)
2444 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2446 atmel_uart_write_char(port, ch);
2450 * Interrupts are disabled on entering
2452 static void atmel_console_write(struct console *co, const char *s, u_int count)
2454 struct uart_port *port = &atmel_ports[co->index].uart;
2455 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2456 unsigned int status, imr;
2457 unsigned int pdc_tx;
2460 * First, save IMR and then disable interrupts
2462 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2463 atmel_uart_writel(port, ATMEL_US_IDR,
2464 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2466 /* Store PDC transmit status and disable it */
2467 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2468 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2470 uart_console_write(port, s, count, atmel_console_putchar);
2473 * Finally, wait for transmitter to become empty
2477 status = atmel_uart_readl(port, ATMEL_US_CSR);
2478 } while (!(status & ATMEL_US_TXRDY));
2480 /* Restore PDC transmit status */
2482 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2484 /* set interrupts back the way they were */
2485 atmel_uart_writel(port, ATMEL_US_IER, imr);
2489 * If the port was already initialised (eg, by a boot loader),
2490 * try to determine the current setup.
2492 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2493 int *parity, int *bits)
2495 unsigned int mr, quot;
2498 * If the baud rate generator isn't running, the port wasn't
2499 * initialized by the boot loader.
2501 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2505 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2506 if (mr == ATMEL_US_CHRL_8)
2511 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2512 if (mr == ATMEL_US_PAR_EVEN)
2514 else if (mr == ATMEL_US_PAR_ODD)
2518 * The serial core only rounds down when matching this to a
2519 * supported baud rate. Make sure we don't end up slightly
2520 * lower than one of those, as it would make us fall through
2521 * to a much lower baud rate than we really want.
2523 *baud = port->uartclk / (16 * (quot - 1));
2526 static int __init atmel_console_setup(struct console *co, char *options)
2529 struct uart_port *port = &atmel_ports[co->index].uart;
2535 if (port->membase == NULL) {
2536 /* Port not initialized yet - delay setup */
2540 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2544 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2545 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2546 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2549 uart_parse_options(options, &baud, &parity, &bits, &flow);
2551 atmel_console_get_options(port, &baud, &parity, &bits);
2553 return uart_set_options(port, co, baud, parity, bits, flow);
2556 static struct uart_driver atmel_uart;
2558 static struct console atmel_console = {
2559 .name = ATMEL_DEVICENAME,
2560 .write = atmel_console_write,
2561 .device = uart_console_device,
2562 .setup = atmel_console_setup,
2563 .flags = CON_PRINTBUFFER,
2565 .data = &atmel_uart,
2568 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2571 * Early console initialization (before VM subsystem initialized).
2573 static int __init atmel_console_init(void)
2576 if (atmel_default_console_device) {
2577 struct atmel_uart_data *pdata =
2578 dev_get_platdata(&atmel_default_console_device->dev);
2579 int id = pdata->num;
2580 struct atmel_uart_port *port = &atmel_ports[id];
2582 port->backup_imr = 0;
2583 port->uart.line = id;
2585 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
2586 ret = atmel_init_port(port, atmel_default_console_device);
2589 register_console(&atmel_console);
2595 console_initcall(atmel_console_init);
2598 * Late console initialization.
2600 static int __init atmel_late_console_init(void)
2602 if (atmel_default_console_device
2603 && !(atmel_console.flags & CON_ENABLED))
2604 register_console(&atmel_console);
2609 core_initcall(atmel_late_console_init);
2611 static inline bool atmel_is_console_port(struct uart_port *port)
2613 return port->cons && port->cons->index == port->line;
2617 #define ATMEL_CONSOLE_DEVICE NULL
2619 static inline bool atmel_is_console_port(struct uart_port *port)
2625 static struct uart_driver atmel_uart = {
2626 .owner = THIS_MODULE,
2627 .driver_name = "atmel_serial",
2628 .dev_name = ATMEL_DEVICENAME,
2629 .major = SERIAL_ATMEL_MAJOR,
2630 .minor = MINOR_START,
2631 .nr = ATMEL_MAX_UART,
2632 .cons = ATMEL_CONSOLE_DEVICE,
2636 static bool atmel_serial_clk_will_stop(void)
2638 #ifdef CONFIG_ARCH_AT91
2639 return at91_suspend_entering_slow_clock();
2645 static int atmel_serial_suspend(struct platform_device *pdev,
2648 struct uart_port *port = platform_get_drvdata(pdev);
2649 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2651 if (atmel_is_console_port(port) && console_suspend_enabled) {
2652 /* Drain the TX shifter */
2653 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2658 /* we can not wake up if we're running on slow clock */
2659 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2660 if (atmel_serial_clk_will_stop()) {
2661 unsigned long flags;
2663 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2664 atmel_port->suspended = true;
2665 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2666 device_set_wakeup_enable(&pdev->dev, 0);
2669 uart_suspend_port(&atmel_uart, port);
2674 static int atmel_serial_resume(struct platform_device *pdev)
2676 struct uart_port *port = platform_get_drvdata(pdev);
2677 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2678 unsigned long flags;
2680 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2681 if (atmel_port->pending) {
2682 atmel_handle_receive(port, atmel_port->pending);
2683 atmel_handle_status(port, atmel_port->pending,
2684 atmel_port->pending_status);
2685 atmel_handle_transmit(port, atmel_port->pending);
2686 atmel_port->pending = 0;
2688 atmel_port->suspended = false;
2689 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2691 uart_resume_port(&atmel_uart, port);
2692 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2697 #define atmel_serial_suspend NULL
2698 #define atmel_serial_resume NULL
2701 static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev)
2703 enum mctrl_gpio_idx i;
2704 struct gpio_desc *gpiod;
2706 p->gpios = mctrl_gpio_init_noauto(dev, 0);
2707 if (IS_ERR(p->gpios))
2708 return PTR_ERR(p->gpios);
2710 for (i = 0; i < UART_GPIO_MAX; i++) {
2711 gpiod = mctrl_gpio_to_gpiod(p->gpios, i);
2712 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN))
2713 p->gpio_irq[i] = gpiod_to_irq(gpiod);
2715 p->gpio_irq[i] = -EINVAL;
2721 static void atmel_serial_probe_fifos(struct atmel_uart_port *port,
2722 struct platform_device *pdev)
2724 port->fifo_size = 0;
2728 if (of_property_read_u32(pdev->dev.of_node,
2733 if (!port->fifo_size)
2736 if (port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2737 port->fifo_size = 0;
2738 dev_err(&pdev->dev, "Invalid FIFO size\n");
2743 * 0 <= rts_low <= rts_high <= fifo_size
2744 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2745 * to flush their internal TX FIFO, commonly up to 16 data, before
2746 * actually stopping to send new data. So we try to set the RTS High
2747 * Threshold to a reasonably high value respecting this 16 data
2748 * empirical rule when possible.
2750 port->rts_high = max_t(int, port->fifo_size >> 1,
2751 port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2752 port->rts_low = max_t(int, port->fifo_size >> 2,
2753 port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2755 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2757 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2759 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2763 static int atmel_serial_probe(struct platform_device *pdev)
2765 struct atmel_uart_port *port;
2766 struct device_node *np = pdev->dev.of_node;
2767 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
2772 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2775 ret = of_alias_get_id(np, "serial");
2781 /* port id not found in platform data nor device-tree aliases:
2782 * auto-enumerate it */
2783 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2785 if (ret >= ATMEL_MAX_UART) {
2790 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2791 /* port already in use */
2796 port = &atmel_ports[ret];
2797 port->backup_imr = 0;
2798 port->uart.line = ret;
2799 atmel_serial_probe_fifos(port, pdev);
2801 spin_lock_init(&port->lock_suspended);
2803 ret = atmel_init_gpios(port, &pdev->dev);
2805 dev_err(&pdev->dev, "Failed to initialize GPIOs.");
2809 ret = atmel_init_port(port, pdev);
2813 if (!atmel_use_pdc_rx(&port->uart)) {
2815 data = kmalloc(sizeof(struct atmel_uart_char)
2816 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
2818 goto err_alloc_ring;
2819 port->rx_ring.buf = data;
2822 rs485_enabled = port->uart.rs485.flags & SER_RS485_ENABLED;
2824 ret = uart_add_one_port(&atmel_uart, &port->uart);
2828 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2829 if (atmel_is_console_port(&port->uart)
2830 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2832 * The serial core enabled the clock for us, so undo
2833 * the clk_prepare_enable() in atmel_console_setup()
2835 clk_disable_unprepare(port->clk);
2839 device_init_wakeup(&pdev->dev, 1);
2840 platform_set_drvdata(pdev, port);
2843 * The peripheral clock has been disabled by atmel_init_port():
2844 * enable it before accessing I/O registers
2846 clk_prepare_enable(port->clk);
2848 if (rs485_enabled) {
2849 atmel_uart_writel(&port->uart, ATMEL_US_MR,
2850 ATMEL_US_USMODE_NORMAL);
2851 atmel_uart_writel(&port->uart, ATMEL_US_CR, ATMEL_US_RTSEN);
2855 * Get port name of usart or uart
2857 atmel_get_ip_name(&port->uart);
2860 * The peripheral clock can now safely be disabled till the port
2863 clk_disable_unprepare(port->clk);
2868 kfree(port->rx_ring.buf);
2869 port->rx_ring.buf = NULL;
2871 if (!atmel_is_console_port(&port->uart)) {
2876 clear_bit(port->uart.line, atmel_ports_in_use);
2881 static int atmel_serial_remove(struct platform_device *pdev)
2883 struct uart_port *port = platform_get_drvdata(pdev);
2884 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2887 tasklet_kill(&atmel_port->tasklet);
2889 device_init_wakeup(&pdev->dev, 0);
2891 ret = uart_remove_one_port(&atmel_uart, port);
2893 kfree(atmel_port->rx_ring.buf);
2895 /* "port" is allocated statically, so we shouldn't free it */
2897 clear_bit(port->line, atmel_ports_in_use);
2899 clk_put(atmel_port->clk);
2904 static struct platform_driver atmel_serial_driver = {
2905 .probe = atmel_serial_probe,
2906 .remove = atmel_serial_remove,
2907 .suspend = atmel_serial_suspend,
2908 .resume = atmel_serial_resume,
2910 .name = "atmel_usart",
2911 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2915 static int __init atmel_serial_init(void)
2919 ret = uart_register_driver(&atmel_uart);
2923 ret = platform_driver_register(&atmel_serial_driver);
2925 uart_unregister_driver(&atmel_uart);
2930 static void __exit atmel_serial_exit(void)
2932 platform_driver_unregister(&atmel_serial_driver);
2933 uart_unregister_driver(&atmel_uart);
2936 module_init(atmel_serial_init);
2937 module_exit(atmel_serial_exit);
2939 MODULE_AUTHOR("Rick Bronson");
2940 MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
2941 MODULE_LICENSE("GPL");
2942 MODULE_ALIAS("platform:atmel_usart");