2 * Probe module for 8250/16550-type PCI serial ports.
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
25 #include <asm/byteorder.h>
31 * init function returns:
32 * > 0 - number of ports
33 * = 0 - use board->num_ports
36 struct pci_serial_quirk {
41 int (*probe)(struct pci_dev *dev);
42 int (*init)(struct pci_dev *dev);
43 int (*setup)(struct serial_private *,
44 const struct pciserial_board *,
45 struct uart_8250_port *, int);
46 void (*exit)(struct pci_dev *dev);
49 #define PCI_NUM_BAR_RESOURCES 6
51 struct serial_private {
54 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
55 struct pci_serial_quirk *quirk;
59 static int pci_default_setup(struct serial_private*,
60 const struct pciserial_board*, struct uart_8250_port *, int);
62 static void moan_device(const char *str, struct pci_dev *dev)
66 "Please send the output of lspci -vv, this\n"
67 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 "manufacturer and name of serial board or\n"
69 "modem board to rmk+serial@arm.linux.org.uk.\n",
70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
75 setup_port(struct serial_private *priv, struct uart_8250_port *port,
76 int bar, int offset, int regshift)
78 struct pci_dev *dev = priv->dev;
79 unsigned long base, len;
81 if (bar >= PCI_NUM_BAR_RESOURCES)
84 base = pci_resource_start(dev, bar);
86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
87 len = pci_resource_len(dev, bar);
89 if (!priv->remapped_bar[bar])
90 priv->remapped_bar[bar] = ioremap_nocache(base, len);
91 if (!priv->remapped_bar[bar])
94 port->port.iotype = UPIO_MEM;
95 port->port.iobase = 0;
96 port->port.mapbase = base + offset;
97 port->port.membase = priv->remapped_bar[bar] + offset;
98 port->port.regshift = regshift;
100 port->port.iotype = UPIO_PORT;
101 port->port.iobase = base + offset;
102 port->port.mapbase = 0;
103 port->port.membase = NULL;
104 port->port.regshift = 0;
110 * ADDI-DATA GmbH communication cards <info@addi-data.com>
112 static int addidata_apci7800_setup(struct serial_private *priv,
113 const struct pciserial_board *board,
114 struct uart_8250_port *port, int idx)
116 unsigned int bar = 0, offset = board->first_offset;
117 bar = FL_GET_BASE(board->flags);
120 offset += idx * board->uart_offset;
121 } else if ((idx >= 2) && (idx < 4)) {
123 offset += ((idx - 2) * board->uart_offset);
124 } else if ((idx >= 4) && (idx < 6)) {
126 offset += ((idx - 4) * board->uart_offset);
127 } else if (idx >= 6) {
129 offset += ((idx - 6) * board->uart_offset);
132 return setup_port(priv, port, bar, offset, board->reg_shift);
136 * AFAVLAB uses a different mixture of BARs and offsets
137 * Not that ugly ;) -- HW
140 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
141 struct uart_8250_port *port, int idx)
143 unsigned int bar, offset = board->first_offset;
145 bar = FL_GET_BASE(board->flags);
150 offset += (idx - 4) * board->uart_offset;
153 return setup_port(priv, port, bar, offset, board->reg_shift);
157 * HP's Remote Management Console. The Diva chip came in several
158 * different versions. N-class, L2000 and A500 have two Diva chips, each
159 * with 3 UARTs (the third UART on the second chip is unused). Superdome
160 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
161 * one Diva chip, but it has been expanded to 5 UARTs.
163 static int pci_hp_diva_init(struct pci_dev *dev)
167 switch (dev->subsystem_device) {
168 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
169 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
170 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
171 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
174 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
177 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
180 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
181 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
190 * HP's Diva chip puts the 4th/5th serial port further out, and
191 * some serial ports are supposed to be hidden on certain models.
194 pci_hp_diva_setup(struct serial_private *priv,
195 const struct pciserial_board *board,
196 struct uart_8250_port *port, int idx)
198 unsigned int offset = board->first_offset;
199 unsigned int bar = FL_GET_BASE(board->flags);
201 switch (priv->dev->subsystem_device) {
202 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
206 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
216 offset += idx * board->uart_offset;
218 return setup_port(priv, port, bar, offset, board->reg_shift);
222 * Added for EKF Intel i960 serial boards
224 static int pci_inteli960ni_init(struct pci_dev *dev)
226 unsigned long oldval;
228 if (!(dev->subsystem_device & 0x1000))
231 /* is firmware started? */
232 pci_read_config_dword(dev, 0x44, (void *)&oldval);
233 if (oldval == 0x00001000L) { /* RESET value */
234 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
241 * Some PCI serial cards using the PLX 9050 PCI interface chip require
242 * that the card interrupt be explicitly enabled or disabled. This
243 * seems to be mainly needed on card using the PLX which also use I/O
246 static int pci_plx9050_init(struct pci_dev *dev)
251 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
252 moan_device("no memory in bar 0", dev);
257 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
258 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
261 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
262 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
264 * As the megawolf cards have the int pins active
265 * high, and have 2 UART chips, both ints must be
266 * enabled on the 9050. Also, the UARTS are set in
267 * 16450 mode by default, so we have to enable the
268 * 16C950 'enhanced' mode so that we can use the
273 * enable/disable interrupts
275 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
278 writel(irq_config, p + 0x4c);
281 * Read the register back to ensure that it took effect.
289 static void pci_plx9050_exit(struct pci_dev *dev)
293 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
299 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
304 * Read the register back to ensure that it took effect.
311 #define NI8420_INT_ENABLE_REG 0x38
312 #define NI8420_INT_ENABLE_BIT 0x2000
314 static void pci_ni8420_exit(struct pci_dev *dev)
317 unsigned long base, len;
318 unsigned int bar = 0;
320 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
321 moan_device("no memory in bar", dev);
325 base = pci_resource_start(dev, bar);
326 len = pci_resource_len(dev, bar);
327 p = ioremap_nocache(base, len);
331 /* Disable the CPU Interrupt */
332 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
333 p + NI8420_INT_ENABLE_REG);
339 #define MITE_IOWBSR1 0xc4
340 #define MITE_IOWCR1 0xf4
341 #define MITE_LCIMR1 0x08
342 #define MITE_LCIMR2 0x10
344 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
346 static void pci_ni8430_exit(struct pci_dev *dev)
349 unsigned long base, len;
350 unsigned int bar = 0;
352 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
353 moan_device("no memory in bar", dev);
357 base = pci_resource_start(dev, bar);
358 len = pci_resource_len(dev, bar);
359 p = ioremap_nocache(base, len);
363 /* Disable the CPU Interrupt */
364 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
368 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
370 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
371 struct uart_8250_port *port, int idx)
373 unsigned int bar, offset = board->first_offset;
378 /* first four channels map to 0, 0x100, 0x200, 0x300 */
379 offset += idx * board->uart_offset;
380 } else if (idx < 8) {
381 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
382 offset += idx * board->uart_offset + 0xC00;
383 } else /* we have only 8 ports on PMC-OCTALPRO */
386 return setup_port(priv, port, bar, offset, board->reg_shift);
390 * This does initialization for PMC OCTALPRO cards:
391 * maps the device memory, resets the UARTs (needed, bc
392 * if the module is removed and inserted again, the card
393 * is in the sleep mode) and enables global interrupt.
396 /* global control register offset for SBS PMC-OctalPro */
397 #define OCT_REG_CR_OFF 0x500
399 static int sbs_init(struct pci_dev *dev)
403 p = pci_ioremap_bar(dev, 0);
407 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
408 writeb(0x10, p + OCT_REG_CR_OFF);
410 writeb(0x0, p + OCT_REG_CR_OFF);
412 /* Set bit-2 (INTENABLE) of Control Register */
413 writeb(0x4, p + OCT_REG_CR_OFF);
420 * Disables the global interrupt of PMC-OctalPro
423 static void sbs_exit(struct pci_dev *dev)
427 p = pci_ioremap_bar(dev, 0);
428 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
430 writeb(0, p + OCT_REG_CR_OFF);
435 * SIIG serial cards have an PCI interface chip which also controls
436 * the UART clocking frequency. Each UART can be clocked independently
437 * (except cards equipped with 4 UARTs) and initial clocking settings
438 * are stored in the EEPROM chip. It can cause problems because this
439 * version of serial driver doesn't support differently clocked UART's
440 * on single PCI card. To prevent this, initialization functions set
441 * high frequency clocking for all UART's on given card. It is safe (I
442 * hope) because it doesn't touch EEPROM settings to prevent conflicts
443 * with other OSes (like M$ DOS).
445 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
447 * There is two family of SIIG serial cards with different PCI
448 * interface chip and different configuration methods:
449 * - 10x cards have control registers in IO and/or memory space;
450 * - 20x cards have control registers in standard PCI configuration space.
452 * Note: all 10x cards have PCI device ids 0x10..
453 * all 20x cards have PCI device ids 0x20..
455 * There are also Quartet Serial cards which use Oxford Semiconductor
456 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
458 * Note: some SIIG cards are probed by the parport_serial object.
461 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
462 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
464 static int pci_siig10x_init(struct pci_dev *dev)
469 switch (dev->device & 0xfff8) {
470 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
473 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
476 default: /* 1S1P, 4S */
481 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
485 writew(readw(p + 0x28) & data, p + 0x28);
491 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
492 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
494 static int pci_siig20x_init(struct pci_dev *dev)
498 /* Change clock frequency for the first UART. */
499 pci_read_config_byte(dev, 0x6f, &data);
500 pci_write_config_byte(dev, 0x6f, data & 0xef);
502 /* If this card has 2 UART, we have to do the same with second UART. */
503 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
504 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
505 pci_read_config_byte(dev, 0x73, &data);
506 pci_write_config_byte(dev, 0x73, data & 0xef);
511 static int pci_siig_init(struct pci_dev *dev)
513 unsigned int type = dev->device & 0xff00;
516 return pci_siig10x_init(dev);
517 else if (type == 0x2000)
518 return pci_siig20x_init(dev);
520 moan_device("Unknown SIIG card", dev);
524 static int pci_siig_setup(struct serial_private *priv,
525 const struct pciserial_board *board,
526 struct uart_8250_port *port, int idx)
528 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
532 offset = (idx - 4) * 8;
535 return setup_port(priv, port, bar, offset, 0);
539 * Timedia has an explosion of boards, and to avoid the PCI table from
540 * growing *huge*, we use this function to collapse some 70 entries
541 * in the PCI table into one, for sanity's and compactness's sake.
543 static const unsigned short timedia_single_port[] = {
544 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
547 static const unsigned short timedia_dual_port[] = {
548 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
549 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
550 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
551 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
555 static const unsigned short timedia_quad_port[] = {
556 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
557 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
558 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
562 static const unsigned short timedia_eight_port[] = {
563 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
564 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
567 static const struct timedia_struct {
569 const unsigned short *ids;
571 { 1, timedia_single_port },
572 { 2, timedia_dual_port },
573 { 4, timedia_quad_port },
574 { 8, timedia_eight_port }
578 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
579 * listing them individually, this driver merely grabs them all with
580 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
581 * and should be left free to be claimed by parport_serial instead.
583 static int pci_timedia_probe(struct pci_dev *dev)
586 * Check the third digit of the subdevice ID
587 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
589 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
591 "ignoring Timedia subdevice %04x for parport_serial\n",
592 dev->subsystem_device);
599 static int pci_timedia_init(struct pci_dev *dev)
601 const unsigned short *ids;
604 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
605 ids = timedia_data[i].ids;
606 for (j = 0; ids[j]; j++)
607 if (dev->subsystem_device == ids[j])
608 return timedia_data[i].num;
614 * Timedia/SUNIX uses a mixture of BARs and offsets
615 * Ugh, this is ugly as all hell --- TYT
618 pci_timedia_setup(struct serial_private *priv,
619 const struct pciserial_board *board,
620 struct uart_8250_port *port, int idx)
622 unsigned int bar = 0, offset = board->first_offset;
629 offset = board->uart_offset;
636 offset = board->uart_offset;
645 return setup_port(priv, port, bar, offset, board->reg_shift);
649 * Some Titan cards are also a little weird
652 titan_400l_800l_setup(struct serial_private *priv,
653 const struct pciserial_board *board,
654 struct uart_8250_port *port, int idx)
656 unsigned int bar, offset = board->first_offset;
667 offset = (idx - 2) * board->uart_offset;
670 return setup_port(priv, port, bar, offset, board->reg_shift);
673 static int pci_xircom_init(struct pci_dev *dev)
679 static int pci_ni8420_init(struct pci_dev *dev)
682 unsigned long base, len;
683 unsigned int bar = 0;
685 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
686 moan_device("no memory in bar", dev);
690 base = pci_resource_start(dev, bar);
691 len = pci_resource_len(dev, bar);
692 p = ioremap_nocache(base, len);
696 /* Enable CPU Interrupt */
697 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
698 p + NI8420_INT_ENABLE_REG);
704 #define MITE_IOWBSR1_WSIZE 0xa
705 #define MITE_IOWBSR1_WIN_OFFSET 0x800
706 #define MITE_IOWBSR1_WENAB (1 << 7)
707 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
708 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
709 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
711 static int pci_ni8430_init(struct pci_dev *dev)
714 unsigned long base, len;
716 unsigned int bar = 0;
718 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
719 moan_device("no memory in bar", dev);
723 base = pci_resource_start(dev, bar);
724 len = pci_resource_len(dev, bar);
725 p = ioremap_nocache(base, len);
729 /* Set device window address and size in BAR0 */
730 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
731 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
732 writel(device_window, p + MITE_IOWBSR1);
734 /* Set window access to go to RAMSEL IO address space */
735 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
738 /* Enable IO Bus Interrupt 0 */
739 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
741 /* Enable CPU Interrupt */
742 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
748 /* UART Port Control Register */
749 #define NI8430_PORTCON 0x0f
750 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
753 pci_ni8430_setup(struct serial_private *priv,
754 const struct pciserial_board *board,
755 struct uart_8250_port *port, int idx)
758 unsigned long base, len;
759 unsigned int bar, offset = board->first_offset;
761 if (idx >= board->num_ports)
764 bar = FL_GET_BASE(board->flags);
765 offset += idx * board->uart_offset;
767 base = pci_resource_start(priv->dev, bar);
768 len = pci_resource_len(priv->dev, bar);
769 p = ioremap_nocache(base, len);
771 /* enable the transceiver */
772 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
773 p + offset + NI8430_PORTCON);
777 return setup_port(priv, port, bar, offset, board->reg_shift);
780 static int pci_netmos_9900_setup(struct serial_private *priv,
781 const struct pciserial_board *board,
782 struct uart_8250_port *port, int idx)
786 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
787 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
788 /* netmos apparently orders BARs by datasheet layout, so serial
789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
793 return setup_port(priv, port, bar, 0, board->reg_shift);
795 return pci_default_setup(priv, board, port, idx);
799 /* the 99xx series comes with a range of device IDs and a variety
802 * 9900 has varying capabilities and can cascade to sub-controllers
803 * (cascading should be purely internal)
804 * 9904 is hardwired with 4 serial ports
805 * 9912 and 9922 are hardwired with 2 serial ports
807 static int pci_netmos_9900_numports(struct pci_dev *dev)
809 unsigned int c = dev->class;
811 unsigned short sub_serports;
817 } else if ((pi == 0) &&
818 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
819 /* two possibilities: 0x30ps encodes number of parallel and
820 * serial ports, or 0x1000 indicates *something*. This is not
821 * immediately obvious, since the 2s1p+4s configuration seems
822 * to offer all functionality on functions 0..2, while still
823 * advertising the same function 3 as the 4s+2s1p config.
825 sub_serports = dev->subsystem_device & 0xf;
826 if (sub_serports > 0) {
829 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
834 moan_device("unknown NetMos/Mostech program interface", dev);
838 static int pci_netmos_init(struct pci_dev *dev)
840 /* subdevice 0x00PS means <P> parallel, <S> serial */
841 unsigned int num_serial = dev->subsystem_device & 0xf;
843 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
844 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
847 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
848 dev->subsystem_device == 0x0299)
851 switch (dev->device) { /* FALLTHROUGH on all */
852 case PCI_DEVICE_ID_NETMOS_9904:
853 case PCI_DEVICE_ID_NETMOS_9912:
854 case PCI_DEVICE_ID_NETMOS_9922:
855 case PCI_DEVICE_ID_NETMOS_9900:
856 num_serial = pci_netmos_9900_numports(dev);
860 if (num_serial == 0 ) {
861 moan_device("unknown NetMos/Mostech device", dev);
872 * These chips are available with optionally one parallel port and up to
873 * two serial ports. Unfortunately they all have the same product id.
875 * Basic configuration is done over a region of 32 I/O ports. The base
876 * ioport is called INTA or INTC, depending on docs/other drivers.
878 * The region of the 32 I/O ports is configured in POSIO0R...
882 #define ITE_887x_MISCR 0x9c
883 #define ITE_887x_INTCBAR 0x78
884 #define ITE_887x_UARTBAR 0x7c
885 #define ITE_887x_PS0BAR 0x10
886 #define ITE_887x_POSIO0 0x60
889 #define ITE_887x_IOSIZE 32
890 /* I/O space size (bits 26-24; 8 bytes = 011b) */
891 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
892 /* I/O space size (bits 26-24; 32 bytes = 101b) */
893 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
894 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
895 #define ITE_887x_POSIO_SPEED (3 << 29)
896 /* enable IO_Space bit */
897 #define ITE_887x_POSIO_ENABLE (1 << 31)
899 static int pci_ite887x_init(struct pci_dev *dev)
901 /* inta_addr are the configuration addresses of the ITE */
902 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
905 struct resource *iobase = NULL;
906 u32 miscr, uartbar, ioport;
908 /* search for the base-ioport */
910 while (inta_addr[i] && iobase == NULL) {
911 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
913 if (iobase != NULL) {
914 /* write POSIO0R - speed | size | ioport */
915 pci_write_config_dword(dev, ITE_887x_POSIO0,
916 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
917 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
918 /* write INTCBAR - ioport */
919 pci_write_config_dword(dev, ITE_887x_INTCBAR,
921 ret = inb(inta_addr[i]);
923 /* ioport connected */
926 release_region(iobase->start, ITE_887x_IOSIZE);
933 dev_err(&dev->dev, "ite887x: could not find iobase\n");
937 /* start of undocumented type checking (see parport_pc.c) */
938 type = inb(iobase->start + 0x18) & 0x0f;
941 case 0x2: /* ITE8871 (1P) */
942 case 0xa: /* ITE8875 (1P) */
945 case 0xe: /* ITE8872 (2S1P) */
948 case 0x6: /* ITE8873 (1S) */
951 case 0x8: /* ITE8874 (2S) */
955 moan_device("Unknown ITE887x", dev);
959 /* configure all serial ports */
960 for (i = 0; i < ret; i++) {
961 /* read the I/O port from the device */
962 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
964 ioport &= 0x0000FF00; /* the actual base address */
965 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
966 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
967 ITE_887x_POSIO_IOSIZE_8 | ioport);
969 /* write the ioport to the UARTBAR */
970 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
971 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
972 uartbar |= (ioport << (16 * i)); /* set the ioport */
973 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
975 /* get current config */
976 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
977 /* disable interrupts (UARTx_Routing[3:0]) */
978 miscr &= ~(0xf << (12 - 4 * i));
979 /* activate the UART (UARTx_En) */
980 miscr |= 1 << (23 - i);
981 /* write new config with activated UART */
982 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
986 /* the device has no UARTs if we get here */
987 release_region(iobase->start, ITE_887x_IOSIZE);
993 static void pci_ite887x_exit(struct pci_dev *dev)
996 /* the ioport is bit 0-15 in POSIO0R */
997 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
999 release_region(ioport, ITE_887x_IOSIZE);
1003 * Oxford Semiconductor Inc.
1004 * Check that device is part of the Tornado range of devices, then determine
1005 * the number of ports available on the device.
1007 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1010 unsigned long deviceID;
1011 unsigned int number_uarts = 0;
1013 /* OxSemi Tornado devices are all 0xCxxx */
1014 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015 (dev->device & 0xF000) != 0xC000)
1018 p = pci_iomap(dev, 0, 5);
1022 deviceID = ioread32(p);
1023 /* Tornado device */
1024 if (deviceID == 0x07000200) {
1025 number_uarts = ioread8(p + 4);
1027 "%d ports detected on Oxford PCI Express device\n",
1030 pci_iounmap(dev, p);
1031 return number_uarts;
1034 static int pci_asix_setup(struct serial_private *priv,
1035 const struct pciserial_board *board,
1036 struct uart_8250_port *port, int idx)
1038 port->bugs |= UART_BUG_PARITY;
1039 return pci_default_setup(priv, board, port, idx);
1042 /* Quatech devices have their own extra interface features */
1044 struct quatech_feature {
1049 #define QPCR_TEST_FOR1 0x3F
1050 #define QPCR_TEST_GET1 0x00
1051 #define QPCR_TEST_FOR2 0x40
1052 #define QPCR_TEST_GET2 0x40
1053 #define QPCR_TEST_FOR3 0x80
1054 #define QPCR_TEST_GET3 0x40
1055 #define QPCR_TEST_FOR4 0xC0
1056 #define QPCR_TEST_GET4 0x80
1058 #define QOPR_CLOCK_X1 0x0000
1059 #define QOPR_CLOCK_X2 0x0001
1060 #define QOPR_CLOCK_X4 0x0002
1061 #define QOPR_CLOCK_X8 0x0003
1062 #define QOPR_CLOCK_RATE_MASK 0x0003
1065 static struct quatech_feature quatech_cards[] = {
1066 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1067 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1068 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1069 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1070 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1071 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1072 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1073 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1074 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1075 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1076 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1077 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1078 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1079 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1080 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1081 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1082 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1083 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1084 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1088 static int pci_quatech_amcc(u16 devid)
1090 struct quatech_feature *qf = &quatech_cards[0];
1092 if (qf->devid == devid)
1096 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1100 static int pci_quatech_rqopr(struct uart_8250_port *port)
1102 unsigned long base = port->port.iobase;
1105 LCR = inb(base + UART_LCR);
1106 outb(0xBF, base + UART_LCR);
1107 val = inb(base + UART_SCR);
1108 outb(LCR, base + UART_LCR);
1112 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1114 unsigned long base = port->port.iobase;
1117 LCR = inb(base + UART_LCR);
1118 outb(0xBF, base + UART_LCR);
1119 val = inb(base + UART_SCR);
1120 outb(qopr, base + UART_SCR);
1121 outb(LCR, base + UART_LCR);
1124 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1126 unsigned long base = port->port.iobase;
1129 LCR = inb(base + UART_LCR);
1130 outb(0xBF, base + UART_LCR);
1131 val = inb(base + UART_SCR);
1132 outb(val | 0x10, base + UART_SCR);
1133 qmcr = inb(base + UART_MCR);
1134 outb(val, base + UART_SCR);
1135 outb(LCR, base + UART_LCR);
1140 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1142 unsigned long base = port->port.iobase;
1145 LCR = inb(base + UART_LCR);
1146 outb(0xBF, base + UART_LCR);
1147 val = inb(base + UART_SCR);
1148 outb(val | 0x10, base + UART_SCR);
1149 outb(qmcr, base + UART_MCR);
1150 outb(val, base + UART_SCR);
1151 outb(LCR, base + UART_LCR);
1154 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1156 unsigned long base = port->port.iobase;
1159 LCR = inb(base + UART_LCR);
1160 outb(0xBF, base + UART_LCR);
1161 val = inb(base + UART_SCR);
1163 outb(0x80, UART_LCR);
1164 if (!(inb(UART_SCR) & 0x20)) {
1165 outb(LCR, base + UART_LCR);
1172 static int pci_quatech_test(struct uart_8250_port *port)
1175 u8 qopr = pci_quatech_rqopr(port);
1176 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1177 reg = pci_quatech_rqopr(port) & 0xC0;
1178 if (reg != QPCR_TEST_GET1)
1180 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1181 reg = pci_quatech_rqopr(port) & 0xC0;
1182 if (reg != QPCR_TEST_GET2)
1184 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1185 reg = pci_quatech_rqopr(port) & 0xC0;
1186 if (reg != QPCR_TEST_GET3)
1188 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1189 reg = pci_quatech_rqopr(port) & 0xC0;
1190 if (reg != QPCR_TEST_GET4)
1193 pci_quatech_wqopr(port, qopr);
1197 static int pci_quatech_clock(struct uart_8250_port *port)
1200 unsigned long clock;
1202 if (pci_quatech_test(port) < 0)
1205 qopr = pci_quatech_rqopr(port);
1207 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1208 reg = pci_quatech_rqopr(port);
1209 if (reg & QOPR_CLOCK_X8) {
1213 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1214 reg = pci_quatech_rqopr(port);
1215 if (!(reg & QOPR_CLOCK_X8)) {
1219 reg &= QOPR_CLOCK_X8;
1220 if (reg == QOPR_CLOCK_X2) {
1222 set = QOPR_CLOCK_X2;
1223 } else if (reg == QOPR_CLOCK_X4) {
1225 set = QOPR_CLOCK_X4;
1226 } else if (reg == QOPR_CLOCK_X8) {
1228 set = QOPR_CLOCK_X8;
1231 set = QOPR_CLOCK_X1;
1233 qopr &= ~QOPR_CLOCK_RATE_MASK;
1237 pci_quatech_wqopr(port, qopr);
1241 static int pci_quatech_rs422(struct uart_8250_port *port)
1246 if (!pci_quatech_has_qmcr(port))
1248 qmcr = pci_quatech_rqmcr(port);
1249 pci_quatech_wqmcr(port, 0xFF);
1250 if (pci_quatech_rqmcr(port))
1252 pci_quatech_wqmcr(port, qmcr);
1256 static int pci_quatech_init(struct pci_dev *dev)
1258 if (pci_quatech_amcc(dev->device)) {
1259 unsigned long base = pci_resource_start(dev, 0);
1262 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1263 tmp = inl(base + 0x3c);
1264 outl(tmp | 0x01000000, base + 0x3c);
1265 outl(tmp &= ~0x01000000, base + 0x3c);
1271 static int pci_quatech_setup(struct serial_private *priv,
1272 const struct pciserial_board *board,
1273 struct uart_8250_port *port, int idx)
1275 /* Needed by pci_quatech calls below */
1276 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1277 /* Set up the clocking */
1278 port->port.uartclk = pci_quatech_clock(port);
1279 /* For now just warn about RS422 */
1280 if (pci_quatech_rs422(port))
1281 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1282 return pci_default_setup(priv, board, port, idx);
1285 static void pci_quatech_exit(struct pci_dev *dev)
1289 static int pci_default_setup(struct serial_private *priv,
1290 const struct pciserial_board *board,
1291 struct uart_8250_port *port, int idx)
1293 unsigned int bar, offset = board->first_offset, maxnr;
1295 bar = FL_GET_BASE(board->flags);
1296 if (board->flags & FL_BASE_BARS)
1299 offset += idx * board->uart_offset;
1301 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1302 (board->reg_shift + 3);
1304 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1307 return setup_port(priv, port, bar, offset, board->reg_shift);
1310 static int pci_pericom_setup(struct serial_private *priv,
1311 const struct pciserial_board *board,
1312 struct uart_8250_port *port, int idx)
1314 unsigned int bar, offset = board->first_offset, maxnr;
1316 bar = FL_GET_BASE(board->flags);
1317 if (board->flags & FL_BASE_BARS)
1320 offset += idx * board->uart_offset;
1322 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1323 (board->reg_shift + 3);
1325 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1328 port->port.uartclk = 14745600;
1330 return setup_port(priv, port, bar, offset, board->reg_shift);
1334 ce4100_serial_setup(struct serial_private *priv,
1335 const struct pciserial_board *board,
1336 struct uart_8250_port *port, int idx)
1340 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1341 port->port.iotype = UPIO_MEM32;
1342 port->port.type = PORT_XSCALE;
1343 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1344 port->port.regshift = 2;
1349 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1350 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1352 #define BYT_PRV_CLK 0x800
1353 #define BYT_PRV_CLK_EN (1 << 0)
1354 #define BYT_PRV_CLK_M_VAL_SHIFT 1
1355 #define BYT_PRV_CLK_N_VAL_SHIFT 16
1356 #define BYT_PRV_CLK_UPDATE (1 << 31)
1358 #define BYT_TX_OVF_INT 0x820
1359 #define BYT_TX_OVF_INT_MASK (1 << 1)
1362 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1363 struct ktermios *old)
1365 unsigned int baud = tty_termios_baud_rate(termios);
1370 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1371 * dividers must be adjusted.
1373 * uartclk = (m / n) * 100 MHz, where m <= n
1382 p->uartclk = 64000000;
1387 p->uartclk = 56000000;
1393 p->uartclk = 48000000;
1398 p->uartclk = 40000000;
1403 p->uartclk = 73728000;
1406 /* Reset the clock */
1407 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1408 writel(reg, p->membase + BYT_PRV_CLK);
1409 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1410 writel(reg, p->membase + BYT_PRV_CLK);
1412 serial8250_do_set_termios(p, termios, old);
1415 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1417 return chan->chan_id == *(int *)param;
1421 byt_serial_setup(struct serial_private *priv,
1422 const struct pciserial_board *board,
1423 struct uart_8250_port *port, int idx)
1425 struct uart_8250_dma *dma;
1428 dma = devm_kzalloc(port->port.dev, sizeof(*dma), GFP_KERNEL);
1432 switch (priv->dev->device) {
1433 case PCI_DEVICE_ID_INTEL_BYT_UART1:
1434 dma->rx_chan_id = 3;
1435 dma->tx_chan_id = 2;
1437 case PCI_DEVICE_ID_INTEL_BYT_UART2:
1438 dma->rx_chan_id = 5;
1439 dma->tx_chan_id = 4;
1445 dma->rxconf.slave_id = dma->rx_chan_id;
1446 dma->rxconf.src_maxburst = 16;
1448 dma->txconf.slave_id = dma->tx_chan_id;
1449 dma->txconf.dst_maxburst = 16;
1451 dma->fn = byt_dma_filter;
1452 dma->rx_param = &dma->rx_chan_id;
1453 dma->tx_param = &dma->tx_chan_id;
1455 ret = pci_default_setup(priv, board, port, idx);
1456 port->port.iotype = UPIO_MEM;
1457 port->port.type = PORT_16550A;
1458 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1459 port->port.set_termios = byt_set_termios;
1460 port->port.fifosize = 64;
1461 port->tx_loadsz = 64;
1463 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1465 /* Disable Tx counter interrupts */
1466 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1472 pci_omegapci_setup(struct serial_private *priv,
1473 const struct pciserial_board *board,
1474 struct uart_8250_port *port, int idx)
1476 return setup_port(priv, port, 2, idx * 8, 0);
1480 pci_brcm_trumanage_setup(struct serial_private *priv,
1481 const struct pciserial_board *board,
1482 struct uart_8250_port *port, int idx)
1484 int ret = pci_default_setup(priv, board, port, idx);
1486 port->port.type = PORT_BRCM_TRUMANAGE;
1487 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1491 static int pci_fintek_setup(struct serial_private *priv,
1492 const struct pciserial_board *board,
1493 struct uart_8250_port *port, int idx)
1495 struct pci_dev *pdev = priv->dev;
1497 unsigned long iobase;
1498 unsigned long ciobase = 0;
1502 * We are supposed to be able to read these from the PCI config space,
1503 * but the values there don't seem to match what we need to use, so
1504 * just use these hard-coded values for now, as they are correct.
1507 case 0: iobase = 0xe000; config_base = 0x40; break;
1508 case 1: iobase = 0xe008; config_base = 0x48; break;
1509 case 2: iobase = 0xe010; config_base = 0x50; break;
1510 case 3: iobase = 0xe018; config_base = 0x58; break;
1511 case 4: iobase = 0xe020; config_base = 0x60; break;
1512 case 5: iobase = 0xe028; config_base = 0x68; break;
1513 case 6: iobase = 0xe030; config_base = 0x70; break;
1514 case 7: iobase = 0xe038; config_base = 0x78; break;
1515 case 8: iobase = 0xe040; config_base = 0x80; break;
1516 case 9: iobase = 0xe048; config_base = 0x88; break;
1517 case 10: iobase = 0xe050; config_base = 0x90; break;
1518 case 11: iobase = 0xe058; config_base = 0x98; break;
1520 /* Unknown number of ports, get out of here */
1525 base = pci_resource_start(priv->dev, 3);
1526 ciobase = (int)(base + (0x8 * idx));
1529 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n",
1530 __func__, idx, iobase, ciobase, config_base);
1532 /* Enable UART I/O port */
1533 pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1535 /* Select 128-byte FIFO and 8x FIFO threshold */
1536 pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1539 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1542 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1544 /* irq number, this usually fails, but the spec says to do it anyway. */
1545 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1547 port->port.iotype = UPIO_PORT;
1548 port->port.iobase = iobase;
1549 port->port.mapbase = 0;
1550 port->port.membase = NULL;
1551 port->port.regshift = 0;
1556 static int skip_tx_en_setup(struct serial_private *priv,
1557 const struct pciserial_board *board,
1558 struct uart_8250_port *port, int idx)
1560 port->port.flags |= UPF_NO_TXEN_TEST;
1561 dev_dbg(&priv->dev->dev,
1562 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1563 priv->dev->vendor, priv->dev->device,
1564 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1566 return pci_default_setup(priv, board, port, idx);
1569 static void kt_handle_break(struct uart_port *p)
1571 struct uart_8250_port *up = up_to_u8250p(p);
1573 * On receipt of a BI, serial device in Intel ME (Intel
1574 * management engine) needs to have its fifos cleared for sane
1575 * SOL (Serial Over Lan) output.
1577 serial8250_clear_and_reinit_fifos(up);
1580 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1582 struct uart_8250_port *up = up_to_u8250p(p);
1586 * When the Intel ME (management engine) gets reset its serial
1587 * port registers could return 0 momentarily. Functions like
1588 * serial8250_console_write, read and save the IER, perform
1589 * some operation and then restore it. In order to avoid
1590 * setting IER register inadvertently to 0, if the value read
1591 * is 0, double check with ier value in uart_8250_port and use
1592 * that instead. up->ier should be the same value as what is
1593 * currently configured.
1595 val = inb(p->iobase + offset);
1596 if (offset == UART_IER) {
1603 static int kt_serial_setup(struct serial_private *priv,
1604 const struct pciserial_board *board,
1605 struct uart_8250_port *port, int idx)
1607 port->port.flags |= UPF_BUG_THRE;
1608 port->port.serial_in = kt_serial_in;
1609 port->port.handle_break = kt_handle_break;
1610 return skip_tx_en_setup(priv, board, port, idx);
1613 static int pci_eg20t_init(struct pci_dev *dev)
1615 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1623 pci_xr17c154_setup(struct serial_private *priv,
1624 const struct pciserial_board *board,
1625 struct uart_8250_port *port, int idx)
1627 port->port.flags |= UPF_EXAR_EFR;
1628 return pci_default_setup(priv, board, port, idx);
1632 pci_xr17v35x_setup(struct serial_private *priv,
1633 const struct pciserial_board *board,
1634 struct uart_8250_port *port, int idx)
1638 p = pci_ioremap_bar(priv->dev, 0);
1642 port->port.flags |= UPF_EXAR_EFR;
1645 * Setup Multipurpose Input/Output pins.
1648 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1649 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1650 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1651 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1652 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1653 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1654 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1655 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1656 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1657 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1658 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1659 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1661 writeb(0x00, p + UART_EXAR_8XMODE);
1662 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1663 writeb(128, p + UART_EXAR_TXTRG);
1664 writeb(128, p + UART_EXAR_RXTRG);
1667 return pci_default_setup(priv, board, port, idx);
1670 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1671 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1672 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1673 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1676 pci_fastcom335_setup(struct serial_private *priv,
1677 const struct pciserial_board *board,
1678 struct uart_8250_port *port, int idx)
1682 p = pci_ioremap_bar(priv->dev, 0);
1686 port->port.flags |= UPF_EXAR_EFR;
1689 * Setup Multipurpose Input/Output pins.
1692 switch (priv->dev->device) {
1693 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1694 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1695 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1696 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1697 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1699 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1700 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1701 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1702 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1703 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1706 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1707 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1708 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1710 writeb(0x00, p + UART_EXAR_8XMODE);
1711 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1712 writeb(32, p + UART_EXAR_TXTRG);
1713 writeb(32, p + UART_EXAR_RXTRG);
1716 return pci_default_setup(priv, board, port, idx);
1720 pci_wch_ch353_setup(struct serial_private *priv,
1721 const struct pciserial_board *board,
1722 struct uart_8250_port *port, int idx)
1724 port->port.flags |= UPF_FIXED_TYPE;
1725 port->port.type = PORT_16550A;
1726 return pci_default_setup(priv, board, port, idx);
1729 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1730 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1731 #define PCI_DEVICE_ID_OCTPRO 0x0001
1732 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1733 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1734 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1735 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1736 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1737 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1738 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1739 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1740 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1741 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1742 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1743 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1744 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1745 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1746 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1747 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1748 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1749 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1750 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1751 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1752 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1753 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1754 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1755 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1756 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1757 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1758 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1759 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1760 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1761 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1762 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1763 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1764 #define PCI_VENDOR_ID_WCH 0x4348
1765 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1766 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1767 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1768 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1769 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1770 #define PCI_VENDOR_ID_AGESTAR 0x5372
1771 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1772 #define PCI_VENDOR_ID_ASIX 0x9710
1773 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1774 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1775 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1776 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1777 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1778 #define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
1780 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1781 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1784 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1785 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1786 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1789 * Master list of serial port init/setup/exit quirks.
1790 * This does not describe the general nature of the port.
1791 * (ie, baud base, number and location of ports, etc)
1793 * This list is ordered alphabetically by vendor then device.
1794 * Specific entries must come before more generic entries.
1796 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1798 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1801 .vendor = PCI_VENDOR_ID_AMCC,
1802 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1803 .subvendor = PCI_ANY_ID,
1804 .subdevice = PCI_ANY_ID,
1805 .setup = addidata_apci7800_setup,
1808 * AFAVLAB cards - these may be called via parport_serial
1809 * It is not clear whether this applies to all products.
1812 .vendor = PCI_VENDOR_ID_AFAVLAB,
1813 .device = PCI_ANY_ID,
1814 .subvendor = PCI_ANY_ID,
1815 .subdevice = PCI_ANY_ID,
1816 .setup = afavlab_setup,
1822 .vendor = PCI_VENDOR_ID_HP,
1823 .device = PCI_DEVICE_ID_HP_DIVA,
1824 .subvendor = PCI_ANY_ID,
1825 .subdevice = PCI_ANY_ID,
1826 .init = pci_hp_diva_init,
1827 .setup = pci_hp_diva_setup,
1833 .vendor = PCI_VENDOR_ID_INTEL,
1834 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1835 .subvendor = 0xe4bf,
1836 .subdevice = PCI_ANY_ID,
1837 .init = pci_inteli960ni_init,
1838 .setup = pci_default_setup,
1841 .vendor = PCI_VENDOR_ID_INTEL,
1842 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1843 .subvendor = PCI_ANY_ID,
1844 .subdevice = PCI_ANY_ID,
1845 .setup = skip_tx_en_setup,
1848 .vendor = PCI_VENDOR_ID_INTEL,
1849 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1850 .subvendor = PCI_ANY_ID,
1851 .subdevice = PCI_ANY_ID,
1852 .setup = skip_tx_en_setup,
1855 .vendor = PCI_VENDOR_ID_INTEL,
1856 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1857 .subvendor = PCI_ANY_ID,
1858 .subdevice = PCI_ANY_ID,
1859 .setup = skip_tx_en_setup,
1862 .vendor = PCI_VENDOR_ID_INTEL,
1863 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1864 .subvendor = PCI_ANY_ID,
1865 .subdevice = PCI_ANY_ID,
1866 .setup = ce4100_serial_setup,
1869 .vendor = PCI_VENDOR_ID_INTEL,
1870 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1871 .subvendor = PCI_ANY_ID,
1872 .subdevice = PCI_ANY_ID,
1873 .setup = kt_serial_setup,
1876 .vendor = PCI_VENDOR_ID_INTEL,
1877 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
1878 .subvendor = PCI_ANY_ID,
1879 .subdevice = PCI_ANY_ID,
1880 .setup = byt_serial_setup,
1883 .vendor = PCI_VENDOR_ID_INTEL,
1884 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
1885 .subvendor = PCI_ANY_ID,
1886 .subdevice = PCI_ANY_ID,
1887 .setup = byt_serial_setup,
1890 .vendor = PCI_VENDOR_ID_INTEL,
1891 .device = PCI_DEVICE_ID_INTEL_QRK_UART,
1892 .subvendor = PCI_ANY_ID,
1893 .subdevice = PCI_ANY_ID,
1894 .setup = pci_default_setup,
1900 .vendor = PCI_VENDOR_ID_ITE,
1901 .device = PCI_DEVICE_ID_ITE_8872,
1902 .subvendor = PCI_ANY_ID,
1903 .subdevice = PCI_ANY_ID,
1904 .init = pci_ite887x_init,
1905 .setup = pci_default_setup,
1906 .exit = pci_ite887x_exit,
1909 * National Instruments
1912 .vendor = PCI_VENDOR_ID_NI,
1913 .device = PCI_DEVICE_ID_NI_PCI23216,
1914 .subvendor = PCI_ANY_ID,
1915 .subdevice = PCI_ANY_ID,
1916 .init = pci_ni8420_init,
1917 .setup = pci_default_setup,
1918 .exit = pci_ni8420_exit,
1921 .vendor = PCI_VENDOR_ID_NI,
1922 .device = PCI_DEVICE_ID_NI_PCI2328,
1923 .subvendor = PCI_ANY_ID,
1924 .subdevice = PCI_ANY_ID,
1925 .init = pci_ni8420_init,
1926 .setup = pci_default_setup,
1927 .exit = pci_ni8420_exit,
1930 .vendor = PCI_VENDOR_ID_NI,
1931 .device = PCI_DEVICE_ID_NI_PCI2324,
1932 .subvendor = PCI_ANY_ID,
1933 .subdevice = PCI_ANY_ID,
1934 .init = pci_ni8420_init,
1935 .setup = pci_default_setup,
1936 .exit = pci_ni8420_exit,
1939 .vendor = PCI_VENDOR_ID_NI,
1940 .device = PCI_DEVICE_ID_NI_PCI2322,
1941 .subvendor = PCI_ANY_ID,
1942 .subdevice = PCI_ANY_ID,
1943 .init = pci_ni8420_init,
1944 .setup = pci_default_setup,
1945 .exit = pci_ni8420_exit,
1948 .vendor = PCI_VENDOR_ID_NI,
1949 .device = PCI_DEVICE_ID_NI_PCI2324I,
1950 .subvendor = PCI_ANY_ID,
1951 .subdevice = PCI_ANY_ID,
1952 .init = pci_ni8420_init,
1953 .setup = pci_default_setup,
1954 .exit = pci_ni8420_exit,
1957 .vendor = PCI_VENDOR_ID_NI,
1958 .device = PCI_DEVICE_ID_NI_PCI2322I,
1959 .subvendor = PCI_ANY_ID,
1960 .subdevice = PCI_ANY_ID,
1961 .init = pci_ni8420_init,
1962 .setup = pci_default_setup,
1963 .exit = pci_ni8420_exit,
1966 .vendor = PCI_VENDOR_ID_NI,
1967 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1968 .subvendor = PCI_ANY_ID,
1969 .subdevice = PCI_ANY_ID,
1970 .init = pci_ni8420_init,
1971 .setup = pci_default_setup,
1972 .exit = pci_ni8420_exit,
1975 .vendor = PCI_VENDOR_ID_NI,
1976 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1977 .subvendor = PCI_ANY_ID,
1978 .subdevice = PCI_ANY_ID,
1979 .init = pci_ni8420_init,
1980 .setup = pci_default_setup,
1981 .exit = pci_ni8420_exit,
1984 .vendor = PCI_VENDOR_ID_NI,
1985 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1986 .subvendor = PCI_ANY_ID,
1987 .subdevice = PCI_ANY_ID,
1988 .init = pci_ni8420_init,
1989 .setup = pci_default_setup,
1990 .exit = pci_ni8420_exit,
1993 .vendor = PCI_VENDOR_ID_NI,
1994 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1995 .subvendor = PCI_ANY_ID,
1996 .subdevice = PCI_ANY_ID,
1997 .init = pci_ni8420_init,
1998 .setup = pci_default_setup,
1999 .exit = pci_ni8420_exit,
2002 .vendor = PCI_VENDOR_ID_NI,
2003 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2004 .subvendor = PCI_ANY_ID,
2005 .subdevice = PCI_ANY_ID,
2006 .init = pci_ni8420_init,
2007 .setup = pci_default_setup,
2008 .exit = pci_ni8420_exit,
2011 .vendor = PCI_VENDOR_ID_NI,
2012 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2013 .subvendor = PCI_ANY_ID,
2014 .subdevice = PCI_ANY_ID,
2015 .init = pci_ni8420_init,
2016 .setup = pci_default_setup,
2017 .exit = pci_ni8420_exit,
2020 .vendor = PCI_VENDOR_ID_NI,
2021 .device = PCI_ANY_ID,
2022 .subvendor = PCI_ANY_ID,
2023 .subdevice = PCI_ANY_ID,
2024 .init = pci_ni8430_init,
2025 .setup = pci_ni8430_setup,
2026 .exit = pci_ni8430_exit,
2030 .vendor = PCI_VENDOR_ID_QUATECH,
2031 .device = PCI_ANY_ID,
2032 .subvendor = PCI_ANY_ID,
2033 .subdevice = PCI_ANY_ID,
2034 .init = pci_quatech_init,
2035 .setup = pci_quatech_setup,
2036 .exit = pci_quatech_exit,
2042 .vendor = PCI_VENDOR_ID_PANACOM,
2043 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2044 .subvendor = PCI_ANY_ID,
2045 .subdevice = PCI_ANY_ID,
2046 .init = pci_plx9050_init,
2047 .setup = pci_default_setup,
2048 .exit = pci_plx9050_exit,
2051 .vendor = PCI_VENDOR_ID_PANACOM,
2052 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2053 .subvendor = PCI_ANY_ID,
2054 .subdevice = PCI_ANY_ID,
2055 .init = pci_plx9050_init,
2056 .setup = pci_default_setup,
2057 .exit = pci_plx9050_exit,
2065 .subvendor = PCI_ANY_ID,
2066 .subdevice = PCI_ANY_ID,
2067 .setup = pci_pericom_setup,
2072 .subvendor = PCI_ANY_ID,
2073 .subdevice = PCI_ANY_ID,
2074 .setup = pci_pericom_setup,
2079 .subvendor = PCI_ANY_ID,
2080 .subdevice = PCI_ANY_ID,
2081 .setup = pci_pericom_setup,
2088 .vendor = PCI_VENDOR_ID_PLX,
2089 .device = PCI_DEVICE_ID_PLX_9030,
2090 .subvendor = PCI_SUBVENDOR_ID_PERLE,
2091 .subdevice = PCI_ANY_ID,
2092 .setup = pci_default_setup,
2095 .vendor = PCI_VENDOR_ID_PLX,
2096 .device = PCI_DEVICE_ID_PLX_9050,
2097 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2098 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2099 .init = pci_plx9050_init,
2100 .setup = pci_default_setup,
2101 .exit = pci_plx9050_exit,
2104 .vendor = PCI_VENDOR_ID_PLX,
2105 .device = PCI_DEVICE_ID_PLX_9050,
2106 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2107 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2108 .init = pci_plx9050_init,
2109 .setup = pci_default_setup,
2110 .exit = pci_plx9050_exit,
2113 .vendor = PCI_VENDOR_ID_PLX,
2114 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2115 .subvendor = PCI_VENDOR_ID_PLX,
2116 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2117 .init = pci_plx9050_init,
2118 .setup = pci_default_setup,
2119 .exit = pci_plx9050_exit,
2122 * SBS Technologies, Inc., PMC-OCTALPRO 232
2125 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2126 .device = PCI_DEVICE_ID_OCTPRO,
2127 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2128 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2134 * SBS Technologies, Inc., PMC-OCTALPRO 422
2137 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2138 .device = PCI_DEVICE_ID_OCTPRO,
2139 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2140 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2146 * SBS Technologies, Inc., P-Octal 232
2149 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2150 .device = PCI_DEVICE_ID_OCTPRO,
2151 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2152 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2158 * SBS Technologies, Inc., P-Octal 422
2161 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2162 .device = PCI_DEVICE_ID_OCTPRO,
2163 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2164 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2170 * SIIG cards - these may be called via parport_serial
2173 .vendor = PCI_VENDOR_ID_SIIG,
2174 .device = PCI_ANY_ID,
2175 .subvendor = PCI_ANY_ID,
2176 .subdevice = PCI_ANY_ID,
2177 .init = pci_siig_init,
2178 .setup = pci_siig_setup,
2184 .vendor = PCI_VENDOR_ID_TITAN,
2185 .device = PCI_DEVICE_ID_TITAN_400L,
2186 .subvendor = PCI_ANY_ID,
2187 .subdevice = PCI_ANY_ID,
2188 .setup = titan_400l_800l_setup,
2191 .vendor = PCI_VENDOR_ID_TITAN,
2192 .device = PCI_DEVICE_ID_TITAN_800L,
2193 .subvendor = PCI_ANY_ID,
2194 .subdevice = PCI_ANY_ID,
2195 .setup = titan_400l_800l_setup,
2201 .vendor = PCI_VENDOR_ID_TIMEDIA,
2202 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2203 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2204 .subdevice = PCI_ANY_ID,
2205 .probe = pci_timedia_probe,
2206 .init = pci_timedia_init,
2207 .setup = pci_timedia_setup,
2210 .vendor = PCI_VENDOR_ID_TIMEDIA,
2211 .device = PCI_ANY_ID,
2212 .subvendor = PCI_ANY_ID,
2213 .subdevice = PCI_ANY_ID,
2214 .setup = pci_timedia_setup,
2217 * SUNIX (Timedia) cards
2218 * Do not "probe" for these cards as there is at least one combination
2219 * card that should be handled by parport_pc that doesn't match the
2220 * rule in pci_timedia_probe.
2221 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2222 * There are some boards with part number SER5037AL that report
2223 * subdevice ID 0x0002.
2226 .vendor = PCI_VENDOR_ID_SUNIX,
2227 .device = PCI_DEVICE_ID_SUNIX_1999,
2228 .subvendor = PCI_VENDOR_ID_SUNIX,
2229 .subdevice = PCI_ANY_ID,
2230 .init = pci_timedia_init,
2231 .setup = pci_timedia_setup,
2237 .vendor = PCI_VENDOR_ID_EXAR,
2238 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2239 .subvendor = PCI_ANY_ID,
2240 .subdevice = PCI_ANY_ID,
2241 .setup = pci_xr17c154_setup,
2244 .vendor = PCI_VENDOR_ID_EXAR,
2245 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2246 .subvendor = PCI_ANY_ID,
2247 .subdevice = PCI_ANY_ID,
2248 .setup = pci_xr17c154_setup,
2251 .vendor = PCI_VENDOR_ID_EXAR,
2252 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2253 .subvendor = PCI_ANY_ID,
2254 .subdevice = PCI_ANY_ID,
2255 .setup = pci_xr17c154_setup,
2258 .vendor = PCI_VENDOR_ID_EXAR,
2259 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2260 .subvendor = PCI_ANY_ID,
2261 .subdevice = PCI_ANY_ID,
2262 .setup = pci_xr17v35x_setup,
2265 .vendor = PCI_VENDOR_ID_EXAR,
2266 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2267 .subvendor = PCI_ANY_ID,
2268 .subdevice = PCI_ANY_ID,
2269 .setup = pci_xr17v35x_setup,
2272 .vendor = PCI_VENDOR_ID_EXAR,
2273 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2274 .subvendor = PCI_ANY_ID,
2275 .subdevice = PCI_ANY_ID,
2276 .setup = pci_xr17v35x_setup,
2282 .vendor = PCI_VENDOR_ID_XIRCOM,
2283 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2284 .subvendor = PCI_ANY_ID,
2285 .subdevice = PCI_ANY_ID,
2286 .init = pci_xircom_init,
2287 .setup = pci_default_setup,
2290 * Netmos cards - these may be called via parport_serial
2293 .vendor = PCI_VENDOR_ID_NETMOS,
2294 .device = PCI_ANY_ID,
2295 .subvendor = PCI_ANY_ID,
2296 .subdevice = PCI_ANY_ID,
2297 .init = pci_netmos_init,
2298 .setup = pci_netmos_9900_setup,
2301 * For Oxford Semiconductor Tornado based devices
2304 .vendor = PCI_VENDOR_ID_OXSEMI,
2305 .device = PCI_ANY_ID,
2306 .subvendor = PCI_ANY_ID,
2307 .subdevice = PCI_ANY_ID,
2308 .init = pci_oxsemi_tornado_init,
2309 .setup = pci_default_setup,
2312 .vendor = PCI_VENDOR_ID_MAINPINE,
2313 .device = PCI_ANY_ID,
2314 .subvendor = PCI_ANY_ID,
2315 .subdevice = PCI_ANY_ID,
2316 .init = pci_oxsemi_tornado_init,
2317 .setup = pci_default_setup,
2320 .vendor = PCI_VENDOR_ID_DIGI,
2321 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2322 .subvendor = PCI_SUBVENDOR_ID_IBM,
2323 .subdevice = PCI_ANY_ID,
2324 .init = pci_oxsemi_tornado_init,
2325 .setup = pci_default_setup,
2328 .vendor = PCI_VENDOR_ID_INTEL,
2330 .subvendor = PCI_ANY_ID,
2331 .subdevice = PCI_ANY_ID,
2332 .init = pci_eg20t_init,
2333 .setup = pci_default_setup,
2336 .vendor = PCI_VENDOR_ID_INTEL,
2338 .subvendor = PCI_ANY_ID,
2339 .subdevice = PCI_ANY_ID,
2340 .init = pci_eg20t_init,
2341 .setup = pci_default_setup,
2344 .vendor = PCI_VENDOR_ID_INTEL,
2346 .subvendor = PCI_ANY_ID,
2347 .subdevice = PCI_ANY_ID,
2348 .init = pci_eg20t_init,
2349 .setup = pci_default_setup,
2352 .vendor = PCI_VENDOR_ID_INTEL,
2354 .subvendor = PCI_ANY_ID,
2355 .subdevice = PCI_ANY_ID,
2356 .init = pci_eg20t_init,
2357 .setup = pci_default_setup,
2362 .subvendor = PCI_ANY_ID,
2363 .subdevice = PCI_ANY_ID,
2364 .init = pci_eg20t_init,
2365 .setup = pci_default_setup,
2370 .subvendor = PCI_ANY_ID,
2371 .subdevice = PCI_ANY_ID,
2372 .init = pci_eg20t_init,
2373 .setup = pci_default_setup,
2378 .subvendor = PCI_ANY_ID,
2379 .subdevice = PCI_ANY_ID,
2380 .init = pci_eg20t_init,
2381 .setup = pci_default_setup,
2386 .subvendor = PCI_ANY_ID,
2387 .subdevice = PCI_ANY_ID,
2388 .init = pci_eg20t_init,
2389 .setup = pci_default_setup,
2394 .subvendor = PCI_ANY_ID,
2395 .subdevice = PCI_ANY_ID,
2396 .init = pci_eg20t_init,
2397 .setup = pci_default_setup,
2400 * Cronyx Omega PCI (PLX-chip based)
2403 .vendor = PCI_VENDOR_ID_PLX,
2404 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2405 .subvendor = PCI_ANY_ID,
2406 .subdevice = PCI_ANY_ID,
2407 .setup = pci_omegapci_setup,
2409 /* WCH CH353 1S1P card (16550 clone) */
2411 .vendor = PCI_VENDOR_ID_WCH,
2412 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2413 .subvendor = PCI_ANY_ID,
2414 .subdevice = PCI_ANY_ID,
2415 .setup = pci_wch_ch353_setup,
2417 /* WCH CH353 2S1P card (16550 clone) */
2419 .vendor = PCI_VENDOR_ID_WCH,
2420 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2421 .subvendor = PCI_ANY_ID,
2422 .subdevice = PCI_ANY_ID,
2423 .setup = pci_wch_ch353_setup,
2425 /* WCH CH353 4S card (16550 clone) */
2427 .vendor = PCI_VENDOR_ID_WCH,
2428 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2429 .subvendor = PCI_ANY_ID,
2430 .subdevice = PCI_ANY_ID,
2431 .setup = pci_wch_ch353_setup,
2433 /* WCH CH353 2S1PF card (16550 clone) */
2435 .vendor = PCI_VENDOR_ID_WCH,
2436 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2437 .subvendor = PCI_ANY_ID,
2438 .subdevice = PCI_ANY_ID,
2439 .setup = pci_wch_ch353_setup,
2441 /* WCH CH352 2S card (16550 clone) */
2443 .vendor = PCI_VENDOR_ID_WCH,
2444 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2445 .subvendor = PCI_ANY_ID,
2446 .subdevice = PCI_ANY_ID,
2447 .setup = pci_wch_ch353_setup,
2450 * ASIX devices with FIFO bug
2453 .vendor = PCI_VENDOR_ID_ASIX,
2454 .device = PCI_ANY_ID,
2455 .subvendor = PCI_ANY_ID,
2456 .subdevice = PCI_ANY_ID,
2457 .setup = pci_asix_setup,
2460 * Commtech, Inc. Fastcom adapters
2464 .vendor = PCI_VENDOR_ID_COMMTECH,
2465 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2466 .subvendor = PCI_ANY_ID,
2467 .subdevice = PCI_ANY_ID,
2468 .setup = pci_fastcom335_setup,
2471 .vendor = PCI_VENDOR_ID_COMMTECH,
2472 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2473 .subvendor = PCI_ANY_ID,
2474 .subdevice = PCI_ANY_ID,
2475 .setup = pci_fastcom335_setup,
2478 .vendor = PCI_VENDOR_ID_COMMTECH,
2479 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2480 .subvendor = PCI_ANY_ID,
2481 .subdevice = PCI_ANY_ID,
2482 .setup = pci_fastcom335_setup,
2485 .vendor = PCI_VENDOR_ID_COMMTECH,
2486 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2487 .subvendor = PCI_ANY_ID,
2488 .subdevice = PCI_ANY_ID,
2489 .setup = pci_fastcom335_setup,
2492 .vendor = PCI_VENDOR_ID_COMMTECH,
2493 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2494 .subvendor = PCI_ANY_ID,
2495 .subdevice = PCI_ANY_ID,
2496 .setup = pci_xr17v35x_setup,
2499 .vendor = PCI_VENDOR_ID_COMMTECH,
2500 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2501 .subvendor = PCI_ANY_ID,
2502 .subdevice = PCI_ANY_ID,
2503 .setup = pci_xr17v35x_setup,
2506 .vendor = PCI_VENDOR_ID_COMMTECH,
2507 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2508 .subvendor = PCI_ANY_ID,
2509 .subdevice = PCI_ANY_ID,
2510 .setup = pci_xr17v35x_setup,
2513 * Broadcom TruManage (NetXtreme)
2516 .vendor = PCI_VENDOR_ID_BROADCOM,
2517 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2518 .subvendor = PCI_ANY_ID,
2519 .subdevice = PCI_ANY_ID,
2520 .setup = pci_brcm_trumanage_setup,
2525 .subvendor = PCI_ANY_ID,
2526 .subdevice = PCI_ANY_ID,
2527 .setup = pci_fintek_setup,
2532 .subvendor = PCI_ANY_ID,
2533 .subdevice = PCI_ANY_ID,
2534 .setup = pci_fintek_setup,
2539 .subvendor = PCI_ANY_ID,
2540 .subdevice = PCI_ANY_ID,
2541 .setup = pci_fintek_setup,
2545 * Default "match everything" terminator entry
2548 .vendor = PCI_ANY_ID,
2549 .device = PCI_ANY_ID,
2550 .subvendor = PCI_ANY_ID,
2551 .subdevice = PCI_ANY_ID,
2552 .setup = pci_default_setup,
2556 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2558 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2561 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2563 struct pci_serial_quirk *quirk;
2565 for (quirk = pci_serial_quirks; ; quirk++)
2566 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2567 quirk_id_matches(quirk->device, dev->device) &&
2568 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2569 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2574 static inline int get_pci_irq(struct pci_dev *dev,
2575 const struct pciserial_board *board)
2577 if (board->flags & FL_NOIRQ)
2584 * This is the configuration table for all of the PCI serial boards
2585 * which we support. It is directly indexed by the pci_board_num_t enum
2586 * value, which is encoded in the pci_device_id PCI probe table's
2587 * driver_data member.
2589 * The makeup of these names are:
2590 * pbn_bn{_bt}_n_baud{_offsetinhex}
2592 * bn = PCI BAR number
2593 * bt = Index using PCI BARs
2594 * n = number of serial ports
2596 * offsetinhex = offset for each sequential port (in hex)
2598 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2600 * Please note: in theory if n = 1, _bt infix should make no difference.
2601 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2603 enum pci_board_num_t {
2620 pbn_b0_2_1152000_200,
2621 pbn_b0_4_1152000_200,
2622 pbn_b0_8_1152000_200,
2627 pbn_b0_2_1843200_200,
2628 pbn_b0_4_1843200_200,
2629 pbn_b0_8_1843200_200,
2703 * Board-specific versions.
2710 pbn_oxsemi_1_4000000,
2711 pbn_oxsemi_2_4000000,
2712 pbn_oxsemi_4_4000000,
2713 pbn_oxsemi_8_4000000,
2726 pbn_exar_ibm_saturn,
2732 pbn_ADDIDATA_PCIe_1_3906250,
2733 pbn_ADDIDATA_PCIe_2_3906250,
2734 pbn_ADDIDATA_PCIe_4_3906250,
2735 pbn_ADDIDATA_PCIe_8_3906250,
2736 pbn_ce4100_1_115200,
2740 pbn_NETMOS9900_2s_115200,
2748 * uart_offset - the space between channels
2749 * reg_shift - describes how the UART registers are mapped
2750 * to PCI memory by the card.
2751 * For example IER register on SBS, Inc. PMC-OctPro is located at
2752 * offset 0x10 from the UART base, while UART_IER is defined as 1
2753 * in include/linux/serial_reg.h,
2754 * see first lines of serial_in() and serial_out() in 8250.c
2757 static struct pciserial_board pci_boards[] = {
2761 .base_baud = 115200,
2764 [pbn_b0_1_115200] = {
2767 .base_baud = 115200,
2770 [pbn_b0_2_115200] = {
2773 .base_baud = 115200,
2776 [pbn_b0_4_115200] = {
2779 .base_baud = 115200,
2782 [pbn_b0_5_115200] = {
2785 .base_baud = 115200,
2788 [pbn_b0_8_115200] = {
2791 .base_baud = 115200,
2794 [pbn_b0_1_921600] = {
2797 .base_baud = 921600,
2800 [pbn_b0_2_921600] = {
2803 .base_baud = 921600,
2806 [pbn_b0_4_921600] = {
2809 .base_baud = 921600,
2813 [pbn_b0_2_1130000] = {
2816 .base_baud = 1130000,
2820 [pbn_b0_4_1152000] = {
2823 .base_baud = 1152000,
2827 [pbn_b0_2_1152000_200] = {
2830 .base_baud = 1152000,
2831 .uart_offset = 0x200,
2834 [pbn_b0_4_1152000_200] = {
2837 .base_baud = 1152000,
2838 .uart_offset = 0x200,
2841 [pbn_b0_8_1152000_200] = {
2844 .base_baud = 1152000,
2845 .uart_offset = 0x200,
2848 [pbn_b0_2_1843200] = {
2851 .base_baud = 1843200,
2854 [pbn_b0_4_1843200] = {
2857 .base_baud = 1843200,
2861 [pbn_b0_2_1843200_200] = {
2864 .base_baud = 1843200,
2865 .uart_offset = 0x200,
2867 [pbn_b0_4_1843200_200] = {
2870 .base_baud = 1843200,
2871 .uart_offset = 0x200,
2873 [pbn_b0_8_1843200_200] = {
2876 .base_baud = 1843200,
2877 .uart_offset = 0x200,
2879 [pbn_b0_1_4000000] = {
2882 .base_baud = 4000000,
2886 [pbn_b0_bt_1_115200] = {
2887 .flags = FL_BASE0|FL_BASE_BARS,
2889 .base_baud = 115200,
2892 [pbn_b0_bt_2_115200] = {
2893 .flags = FL_BASE0|FL_BASE_BARS,
2895 .base_baud = 115200,
2898 [pbn_b0_bt_4_115200] = {
2899 .flags = FL_BASE0|FL_BASE_BARS,
2901 .base_baud = 115200,
2904 [pbn_b0_bt_8_115200] = {
2905 .flags = FL_BASE0|FL_BASE_BARS,
2907 .base_baud = 115200,
2911 [pbn_b0_bt_1_460800] = {
2912 .flags = FL_BASE0|FL_BASE_BARS,
2914 .base_baud = 460800,
2917 [pbn_b0_bt_2_460800] = {
2918 .flags = FL_BASE0|FL_BASE_BARS,
2920 .base_baud = 460800,
2923 [pbn_b0_bt_4_460800] = {
2924 .flags = FL_BASE0|FL_BASE_BARS,
2926 .base_baud = 460800,
2930 [pbn_b0_bt_1_921600] = {
2931 .flags = FL_BASE0|FL_BASE_BARS,
2933 .base_baud = 921600,
2936 [pbn_b0_bt_2_921600] = {
2937 .flags = FL_BASE0|FL_BASE_BARS,
2939 .base_baud = 921600,
2942 [pbn_b0_bt_4_921600] = {
2943 .flags = FL_BASE0|FL_BASE_BARS,
2945 .base_baud = 921600,
2948 [pbn_b0_bt_8_921600] = {
2949 .flags = FL_BASE0|FL_BASE_BARS,
2951 .base_baud = 921600,
2955 [pbn_b1_1_115200] = {
2958 .base_baud = 115200,
2961 [pbn_b1_2_115200] = {
2964 .base_baud = 115200,
2967 [pbn_b1_4_115200] = {
2970 .base_baud = 115200,
2973 [pbn_b1_8_115200] = {
2976 .base_baud = 115200,
2979 [pbn_b1_16_115200] = {
2982 .base_baud = 115200,
2986 [pbn_b1_1_921600] = {
2989 .base_baud = 921600,
2992 [pbn_b1_2_921600] = {
2995 .base_baud = 921600,
2998 [pbn_b1_4_921600] = {
3001 .base_baud = 921600,
3004 [pbn_b1_8_921600] = {
3007 .base_baud = 921600,
3010 [pbn_b1_2_1250000] = {
3013 .base_baud = 1250000,
3017 [pbn_b1_bt_1_115200] = {
3018 .flags = FL_BASE1|FL_BASE_BARS,
3020 .base_baud = 115200,
3023 [pbn_b1_bt_2_115200] = {
3024 .flags = FL_BASE1|FL_BASE_BARS,
3026 .base_baud = 115200,
3029 [pbn_b1_bt_4_115200] = {
3030 .flags = FL_BASE1|FL_BASE_BARS,
3032 .base_baud = 115200,
3036 [pbn_b1_bt_2_921600] = {
3037 .flags = FL_BASE1|FL_BASE_BARS,
3039 .base_baud = 921600,
3043 [pbn_b1_1_1382400] = {
3046 .base_baud = 1382400,
3049 [pbn_b1_2_1382400] = {
3052 .base_baud = 1382400,
3055 [pbn_b1_4_1382400] = {
3058 .base_baud = 1382400,
3061 [pbn_b1_8_1382400] = {
3064 .base_baud = 1382400,
3068 [pbn_b2_1_115200] = {
3071 .base_baud = 115200,
3074 [pbn_b2_2_115200] = {
3077 .base_baud = 115200,
3080 [pbn_b2_4_115200] = {
3083 .base_baud = 115200,
3086 [pbn_b2_8_115200] = {
3089 .base_baud = 115200,
3093 [pbn_b2_1_460800] = {
3096 .base_baud = 460800,
3099 [pbn_b2_4_460800] = {
3102 .base_baud = 460800,
3105 [pbn_b2_8_460800] = {
3108 .base_baud = 460800,
3111 [pbn_b2_16_460800] = {
3114 .base_baud = 460800,
3118 [pbn_b2_1_921600] = {
3121 .base_baud = 921600,
3124 [pbn_b2_4_921600] = {
3127 .base_baud = 921600,
3130 [pbn_b2_8_921600] = {
3133 .base_baud = 921600,
3137 [pbn_b2_8_1152000] = {
3140 .base_baud = 1152000,
3144 [pbn_b2_bt_1_115200] = {
3145 .flags = FL_BASE2|FL_BASE_BARS,
3147 .base_baud = 115200,
3150 [pbn_b2_bt_2_115200] = {
3151 .flags = FL_BASE2|FL_BASE_BARS,
3153 .base_baud = 115200,
3156 [pbn_b2_bt_4_115200] = {
3157 .flags = FL_BASE2|FL_BASE_BARS,
3159 .base_baud = 115200,
3163 [pbn_b2_bt_2_921600] = {
3164 .flags = FL_BASE2|FL_BASE_BARS,
3166 .base_baud = 921600,
3169 [pbn_b2_bt_4_921600] = {
3170 .flags = FL_BASE2|FL_BASE_BARS,
3172 .base_baud = 921600,
3176 [pbn_b3_2_115200] = {
3179 .base_baud = 115200,
3182 [pbn_b3_4_115200] = {
3185 .base_baud = 115200,
3188 [pbn_b3_8_115200] = {
3191 .base_baud = 115200,
3195 [pbn_b4_bt_2_921600] = {
3198 .base_baud = 921600,
3201 [pbn_b4_bt_4_921600] = {
3204 .base_baud = 921600,
3207 [pbn_b4_bt_8_921600] = {
3210 .base_baud = 921600,
3215 * Entries following this are board-specific.
3224 .base_baud = 921600,
3225 .uart_offset = 0x400,
3229 .flags = FL_BASE2|FL_BASE_BARS,
3231 .base_baud = 921600,
3232 .uart_offset = 0x400,
3236 .flags = FL_BASE2|FL_BASE_BARS,
3238 .base_baud = 921600,
3239 .uart_offset = 0x400,
3243 /* I think this entry is broken - the first_offset looks wrong --rmk */
3244 [pbn_plx_romulus] = {
3247 .base_baud = 921600,
3248 .uart_offset = 8 << 2,
3250 .first_offset = 0x03,
3254 * This board uses the size of PCI Base region 0 to
3255 * signal now many ports are available
3258 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3260 .base_baud = 115200,
3263 [pbn_oxsemi_1_4000000] = {
3266 .base_baud = 4000000,
3267 .uart_offset = 0x200,
3268 .first_offset = 0x1000,
3270 [pbn_oxsemi_2_4000000] = {
3273 .base_baud = 4000000,
3274 .uart_offset = 0x200,
3275 .first_offset = 0x1000,
3277 [pbn_oxsemi_4_4000000] = {
3280 .base_baud = 4000000,
3281 .uart_offset = 0x200,
3282 .first_offset = 0x1000,
3284 [pbn_oxsemi_8_4000000] = {
3287 .base_baud = 4000000,
3288 .uart_offset = 0x200,
3289 .first_offset = 0x1000,
3294 * EKF addition for i960 Boards form EKF with serial port.
3297 [pbn_intel_i960] = {
3300 .base_baud = 921600,
3301 .uart_offset = 8 << 2,
3303 .first_offset = 0x10000,
3306 .flags = FL_BASE0|FL_NOIRQ,
3308 .base_baud = 458333,
3311 .first_offset = 0x20178,
3315 * Computone - uses IOMEM.
3317 [pbn_computone_4] = {
3320 .base_baud = 921600,
3321 .uart_offset = 0x40,
3323 .first_offset = 0x200,
3325 [pbn_computone_6] = {
3328 .base_baud = 921600,
3329 .uart_offset = 0x40,
3331 .first_offset = 0x200,
3333 [pbn_computone_8] = {
3336 .base_baud = 921600,
3337 .uart_offset = 0x40,
3339 .first_offset = 0x200,
3344 .base_baud = 460800,
3349 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3350 * Only basic 16550A support.
3351 * XR17C15[24] are not tested, but they should work.
3353 [pbn_exar_XR17C152] = {
3356 .base_baud = 921600,
3357 .uart_offset = 0x200,
3359 [pbn_exar_XR17C154] = {
3362 .base_baud = 921600,
3363 .uart_offset = 0x200,
3365 [pbn_exar_XR17C158] = {
3368 .base_baud = 921600,
3369 .uart_offset = 0x200,
3371 [pbn_exar_XR17V352] = {
3374 .base_baud = 7812500,
3375 .uart_offset = 0x400,
3379 [pbn_exar_XR17V354] = {
3382 .base_baud = 7812500,
3383 .uart_offset = 0x400,
3387 [pbn_exar_XR17V358] = {
3390 .base_baud = 7812500,
3391 .uart_offset = 0x400,
3395 [pbn_exar_ibm_saturn] = {
3398 .base_baud = 921600,
3399 .uart_offset = 0x200,
3403 * PA Semi PWRficient PA6T-1682M on-chip UART
3405 [pbn_pasemi_1682M] = {
3408 .base_baud = 8333333,
3411 * National Instruments 843x
3416 .base_baud = 3686400,
3417 .uart_offset = 0x10,
3418 .first_offset = 0x800,
3423 .base_baud = 3686400,
3424 .uart_offset = 0x10,
3425 .first_offset = 0x800,
3430 .base_baud = 3686400,
3431 .uart_offset = 0x10,
3432 .first_offset = 0x800,
3437 .base_baud = 3686400,
3438 .uart_offset = 0x10,
3439 .first_offset = 0x800,
3442 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3444 [pbn_ADDIDATA_PCIe_1_3906250] = {
3447 .base_baud = 3906250,
3448 .uart_offset = 0x200,
3449 .first_offset = 0x1000,
3451 [pbn_ADDIDATA_PCIe_2_3906250] = {
3454 .base_baud = 3906250,
3455 .uart_offset = 0x200,
3456 .first_offset = 0x1000,
3458 [pbn_ADDIDATA_PCIe_4_3906250] = {
3461 .base_baud = 3906250,
3462 .uart_offset = 0x200,
3463 .first_offset = 0x1000,
3465 [pbn_ADDIDATA_PCIe_8_3906250] = {
3468 .base_baud = 3906250,
3469 .uart_offset = 0x200,
3470 .first_offset = 0x1000,
3472 [pbn_ce4100_1_115200] = {
3473 .flags = FL_BASE_BARS,
3475 .base_baud = 921600,
3479 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3480 * but is overridden by byt_set_termios.
3485 .base_baud = 2764800,
3486 .uart_offset = 0x80,
3492 .base_baud = 2764800,
3498 .base_baud = 115200,
3499 .uart_offset = 0x200,
3501 [pbn_NETMOS9900_2s_115200] = {
3504 .base_baud = 115200,
3506 [pbn_brcm_trumanage] = {
3510 .base_baud = 115200,
3515 .base_baud = 115200,
3516 .first_offset = 0x40,
3521 .base_baud = 115200,
3522 .first_offset = 0x40,
3527 .base_baud = 115200,
3528 .first_offset = 0x40,
3532 static const struct pci_device_id blacklist[] = {
3534 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3535 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3536 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3538 /* multi-io cards handled by parport_serial */
3539 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3540 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3544 * Given a complete unknown PCI device, try to use some heuristics to
3545 * guess what the configuration might be, based on the pitiful PCI
3546 * serial specs. Returns 0 on success, 1 on failure.
3549 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3551 const struct pci_device_id *bldev;
3552 int num_iomem, num_port, first_port = -1, i;
3555 * If it is not a communications device or the programming
3556 * interface is greater than 6, give up.
3558 * (Should we try to make guesses for multiport serial devices
3561 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3562 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3563 (dev->class & 0xff) > 6)
3567 * Do not access blacklisted devices that are known not to
3568 * feature serial ports or are handled by other modules.
3570 for (bldev = blacklist;
3571 bldev < blacklist + ARRAY_SIZE(blacklist);
3573 if (dev->vendor == bldev->vendor &&
3574 dev->device == bldev->device)
3578 num_iomem = num_port = 0;
3579 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3580 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3582 if (first_port == -1)
3585 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3590 * If there is 1 or 0 iomem regions, and exactly one port,
3591 * use it. We guess the number of ports based on the IO
3594 if (num_iomem <= 1 && num_port == 1) {
3595 board->flags = first_port;
3596 board->num_ports = pci_resource_len(dev, first_port) / 8;
3601 * Now guess if we've got a board which indexes by BARs.
3602 * Each IO BAR should be 8 bytes, and they should follow
3607 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3608 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3609 pci_resource_len(dev, i) == 8 &&
3610 (first_port == -1 || (first_port + num_port) == i)) {
3612 if (first_port == -1)
3618 board->flags = first_port | FL_BASE_BARS;
3619 board->num_ports = num_port;
3627 serial_pci_matches(const struct pciserial_board *board,
3628 const struct pciserial_board *guessed)
3631 board->num_ports == guessed->num_ports &&
3632 board->base_baud == guessed->base_baud &&
3633 board->uart_offset == guessed->uart_offset &&
3634 board->reg_shift == guessed->reg_shift &&
3635 board->first_offset == guessed->first_offset;
3638 struct serial_private *
3639 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3641 struct uart_8250_port uart;
3642 struct serial_private *priv;
3643 struct pci_serial_quirk *quirk;
3644 int rc, nr_ports, i;
3646 nr_ports = board->num_ports;
3649 * Find an init and setup quirks.
3651 quirk = find_quirk(dev);
3654 * Run the new-style initialization function.
3655 * The initialization function returns:
3657 * 0 - use board->num_ports
3658 * >0 - number of ports
3661 rc = quirk->init(dev);
3670 priv = kzalloc(sizeof(struct serial_private) +
3671 sizeof(unsigned int) * nr_ports,
3674 priv = ERR_PTR(-ENOMEM);
3679 priv->quirk = quirk;
3681 memset(&uart, 0, sizeof(uart));
3682 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3683 uart.port.uartclk = board->base_baud * 16;
3684 uart.port.irq = get_pci_irq(dev, board);
3685 uart.port.dev = &dev->dev;
3687 for (i = 0; i < nr_ports; i++) {
3688 if (quirk->setup(priv, board, &uart, i))
3691 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3692 uart.port.iobase, uart.port.irq, uart.port.iotype);
3694 priv->line[i] = serial8250_register_8250_port(&uart);
3695 if (priv->line[i] < 0) {
3697 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3698 uart.port.iobase, uart.port.irq,
3699 uart.port.iotype, priv->line[i]);
3712 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3714 void pciserial_remove_ports(struct serial_private *priv)
3716 struct pci_serial_quirk *quirk;
3719 for (i = 0; i < priv->nr; i++)
3720 serial8250_unregister_port(priv->line[i]);
3722 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3723 if (priv->remapped_bar[i])
3724 iounmap(priv->remapped_bar[i]);
3725 priv->remapped_bar[i] = NULL;
3729 * Find the exit quirks.
3731 quirk = find_quirk(priv->dev);
3733 quirk->exit(priv->dev);
3737 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3739 void pciserial_suspend_ports(struct serial_private *priv)
3743 for (i = 0; i < priv->nr; i++)
3744 if (priv->line[i] >= 0)
3745 serial8250_suspend_port(priv->line[i]);
3748 * Ensure that every init quirk is properly torn down
3750 if (priv->quirk->exit)
3751 priv->quirk->exit(priv->dev);
3753 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3755 void pciserial_resume_ports(struct serial_private *priv)
3760 * Ensure that the board is correctly configured.
3762 if (priv->quirk->init)
3763 priv->quirk->init(priv->dev);
3765 for (i = 0; i < priv->nr; i++)
3766 if (priv->line[i] >= 0)
3767 serial8250_resume_port(priv->line[i]);
3769 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3772 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3773 * to the arrangement of serial ports on a PCI card.
3776 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3778 struct pci_serial_quirk *quirk;
3779 struct serial_private *priv;
3780 const struct pciserial_board *board;
3781 struct pciserial_board tmp;
3784 quirk = find_quirk(dev);
3786 rc = quirk->probe(dev);
3791 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3792 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3797 board = &pci_boards[ent->driver_data];
3799 rc = pci_enable_device(dev);
3800 pci_save_state(dev);
3804 if (ent->driver_data == pbn_default) {
3806 * Use a copy of the pci_board entry for this;
3807 * avoid changing entries in the table.
3809 memcpy(&tmp, board, sizeof(struct pciserial_board));
3813 * We matched one of our class entries. Try to
3814 * determine the parameters of this board.
3816 rc = serial_pci_guess_board(dev, &tmp);
3821 * We matched an explicit entry. If we are able to
3822 * detect this boards settings with our heuristic,
3823 * then we no longer need this entry.
3825 memcpy(&tmp, &pci_boards[pbn_default],
3826 sizeof(struct pciserial_board));
3827 rc = serial_pci_guess_board(dev, &tmp);
3828 if (rc == 0 && serial_pci_matches(board, &tmp))
3829 moan_device("Redundant entry in serial pci_table.",
3833 priv = pciserial_init_ports(dev, board);
3834 if (!IS_ERR(priv)) {
3835 pci_set_drvdata(dev, priv);
3842 pci_disable_device(dev);
3846 static void pciserial_remove_one(struct pci_dev *dev)
3848 struct serial_private *priv = pci_get_drvdata(dev);
3850 pciserial_remove_ports(priv);
3852 pci_disable_device(dev);
3856 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3858 struct serial_private *priv = pci_get_drvdata(dev);
3861 pciserial_suspend_ports(priv);
3863 pci_save_state(dev);
3864 pci_set_power_state(dev, pci_choose_state(dev, state));
3868 static int pciserial_resume_one(struct pci_dev *dev)
3871 struct serial_private *priv = pci_get_drvdata(dev);
3873 pci_set_power_state(dev, PCI_D0);
3874 pci_restore_state(dev);
3878 * The device may have been disabled. Re-enable it.
3880 err = pci_enable_device(dev);
3881 /* FIXME: We cannot simply error out here */
3883 dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n");
3884 pciserial_resume_ports(priv);
3890 static struct pci_device_id serial_pci_tbl[] = {
3891 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3892 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3893 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3895 /* Advantech also use 0x3618 and 0xf618 */
3896 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
3897 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3899 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
3900 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3902 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3903 PCI_SUBVENDOR_ID_CONNECT_TECH,
3904 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3906 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3907 PCI_SUBVENDOR_ID_CONNECT_TECH,
3908 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3910 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3911 PCI_SUBVENDOR_ID_CONNECT_TECH,
3912 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3914 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3915 PCI_SUBVENDOR_ID_CONNECT_TECH,
3916 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3918 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3919 PCI_SUBVENDOR_ID_CONNECT_TECH,
3920 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3922 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3923 PCI_SUBVENDOR_ID_CONNECT_TECH,
3924 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3926 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3927 PCI_SUBVENDOR_ID_CONNECT_TECH,
3928 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3930 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3931 PCI_SUBVENDOR_ID_CONNECT_TECH,
3932 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3934 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3935 PCI_SUBVENDOR_ID_CONNECT_TECH,
3936 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3938 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3939 PCI_SUBVENDOR_ID_CONNECT_TECH,
3940 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3942 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3943 PCI_SUBVENDOR_ID_CONNECT_TECH,
3944 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3946 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3947 PCI_SUBVENDOR_ID_CONNECT_TECH,
3948 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3950 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3951 PCI_SUBVENDOR_ID_CONNECT_TECH,
3952 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3954 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3955 PCI_SUBVENDOR_ID_CONNECT_TECH,
3956 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3958 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3959 PCI_SUBVENDOR_ID_CONNECT_TECH,
3960 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3962 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3963 PCI_SUBVENDOR_ID_CONNECT_TECH,
3964 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3966 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3967 PCI_SUBVENDOR_ID_CONNECT_TECH,
3968 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3970 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3971 PCI_VENDOR_ID_AFAVLAB,
3972 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3974 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3975 PCI_SUBVENDOR_ID_CONNECT_TECH,
3976 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3977 pbn_b0_2_1843200_200 },
3978 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3979 PCI_SUBVENDOR_ID_CONNECT_TECH,
3980 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3981 pbn_b0_4_1843200_200 },
3982 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3983 PCI_SUBVENDOR_ID_CONNECT_TECH,
3984 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3985 pbn_b0_8_1843200_200 },
3986 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3987 PCI_SUBVENDOR_ID_CONNECT_TECH,
3988 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3989 pbn_b0_2_1843200_200 },
3990 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3991 PCI_SUBVENDOR_ID_CONNECT_TECH,
3992 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3993 pbn_b0_4_1843200_200 },
3994 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3995 PCI_SUBVENDOR_ID_CONNECT_TECH,
3996 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3997 pbn_b0_8_1843200_200 },
3998 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3999 PCI_SUBVENDOR_ID_CONNECT_TECH,
4000 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4001 pbn_b0_2_1843200_200 },
4002 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4003 PCI_SUBVENDOR_ID_CONNECT_TECH,
4004 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4005 pbn_b0_4_1843200_200 },
4006 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4007 PCI_SUBVENDOR_ID_CONNECT_TECH,
4008 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4009 pbn_b0_8_1843200_200 },
4010 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4011 PCI_SUBVENDOR_ID_CONNECT_TECH,
4012 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4013 pbn_b0_2_1843200_200 },
4014 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4015 PCI_SUBVENDOR_ID_CONNECT_TECH,
4016 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4017 pbn_b0_4_1843200_200 },
4018 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4019 PCI_SUBVENDOR_ID_CONNECT_TECH,
4020 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4021 pbn_b0_8_1843200_200 },
4022 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4023 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4024 0, 0, pbn_exar_ibm_saturn },
4026 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4028 pbn_b2_bt_1_115200 },
4029 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4031 pbn_b2_bt_2_115200 },
4032 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4034 pbn_b2_bt_4_115200 },
4035 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4037 pbn_b2_bt_2_115200 },
4038 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4039 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4040 pbn_b2_bt_4_115200 },
4041 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4042 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4044 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4045 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4047 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4048 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4051 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4053 pbn_b2_bt_2_115200 },
4054 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4056 pbn_b2_bt_2_921600 },
4058 * VScom SPCOM800, from sl@s.pl
4060 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4063 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4066 /* Unknown card - subdevice 0x1584 */
4067 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4069 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4071 /* Unknown card - subdevice 0x1588 */
4072 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4074 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4076 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4077 PCI_SUBVENDOR_ID_KEYSPAN,
4078 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4080 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4083 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4086 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4087 PCI_VENDOR_ID_ESDGMBH,
4088 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4090 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4091 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4092 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4094 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4095 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4096 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4098 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4099 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4100 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4102 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4103 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4104 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4106 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4107 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4108 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4110 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4111 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4112 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4114 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4115 PCI_SUBVENDOR_ID_EXSYS,
4116 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4119 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4122 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4123 0x10b5, 0x106a, 0, 0,
4126 * Quatech cards. These actually have configurable clocks but for
4127 * now we just use the default.
4129 * 100 series are RS232, 200 series RS422,
4131 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4134 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4137 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4140 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4143 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4146 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4149 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4152 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4155 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4158 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4161 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4164 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4167 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4168 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4170 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4173 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4176 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4177 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4179 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4180 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4182 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4183 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4185 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4186 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4189 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4190 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4193 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4194 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4197 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4198 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4199 pbn_b0_bt_2_921600 },
4202 * The below card is a little controversial since it is the
4203 * subject of a PCI vendor/device ID clash. (See
4204 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4205 * For now just used the hex ID 0x950a.
4207 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4208 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4209 0, 0, pbn_b0_2_115200 },
4210 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4211 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4212 0, 0, pbn_b0_2_115200 },
4213 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4216 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4217 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4219 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4222 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4224 pbn_b0_bt_2_921600 },
4225 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4226 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4230 * Oxford Semiconductor Inc. Tornado PCI express device range.
4232 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4235 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4238 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4240 pbn_oxsemi_1_4000000 },
4241 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4242 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4243 pbn_oxsemi_1_4000000 },
4244 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4245 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4247 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4248 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4250 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4251 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4252 pbn_oxsemi_1_4000000 },
4253 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4255 pbn_oxsemi_1_4000000 },
4256 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4259 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4262 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4265 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4268 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270 pbn_oxsemi_2_4000000 },
4271 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4273 pbn_oxsemi_2_4000000 },
4274 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4276 pbn_oxsemi_4_4000000 },
4277 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4279 pbn_oxsemi_4_4000000 },
4280 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4282 pbn_oxsemi_8_4000000 },
4283 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4285 pbn_oxsemi_8_4000000 },
4286 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4288 pbn_oxsemi_1_4000000 },
4289 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4291 pbn_oxsemi_1_4000000 },
4292 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4294 pbn_oxsemi_1_4000000 },
4295 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4296 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4297 pbn_oxsemi_1_4000000 },
4298 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4300 pbn_oxsemi_1_4000000 },
4301 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4303 pbn_oxsemi_1_4000000 },
4304 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4306 pbn_oxsemi_1_4000000 },
4307 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4309 pbn_oxsemi_1_4000000 },
4310 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312 pbn_oxsemi_1_4000000 },
4313 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4314 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315 pbn_oxsemi_1_4000000 },
4316 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4317 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4318 pbn_oxsemi_1_4000000 },
4319 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4320 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4321 pbn_oxsemi_1_4000000 },
4322 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4323 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4324 pbn_oxsemi_1_4000000 },
4325 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4327 pbn_oxsemi_1_4000000 },
4328 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4330 pbn_oxsemi_1_4000000 },
4331 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4333 pbn_oxsemi_1_4000000 },
4334 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 pbn_oxsemi_1_4000000 },
4337 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 pbn_oxsemi_1_4000000 },
4340 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 pbn_oxsemi_1_4000000 },
4343 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 pbn_oxsemi_1_4000000 },
4346 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 pbn_oxsemi_1_4000000 },
4349 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351 pbn_oxsemi_1_4000000 },
4352 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354 pbn_oxsemi_1_4000000 },
4355 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357 pbn_oxsemi_1_4000000 },
4358 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4360 pbn_oxsemi_1_4000000 },
4361 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4362 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4363 pbn_oxsemi_1_4000000 },
4365 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4367 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4368 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4369 pbn_oxsemi_1_4000000 },
4370 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4371 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4372 pbn_oxsemi_2_4000000 },
4373 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4374 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4375 pbn_oxsemi_4_4000000 },
4376 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4377 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4378 pbn_oxsemi_8_4000000 },
4381 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4383 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4384 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4385 pbn_oxsemi_2_4000000 },
4388 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4389 * from skokodyn@yahoo.com
4391 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4392 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4394 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4395 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4397 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4398 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4400 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4401 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4405 * Digitan DS560-558, from jimd@esoft.com
4407 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4412 * Titan Electronic cards
4413 * The 400L and 800L have a custom setup quirk.
4415 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4421 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4424 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4430 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4432 pbn_b1_bt_2_921600 },
4433 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4435 pbn_b0_bt_4_921600 },
4436 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4438 pbn_b0_bt_8_921600 },
4439 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4441 pbn_b4_bt_2_921600 },
4442 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4444 pbn_b4_bt_4_921600 },
4445 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4447 pbn_b4_bt_8_921600 },
4448 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4459 pbn_oxsemi_1_4000000 },
4460 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4462 pbn_oxsemi_2_4000000 },
4463 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4465 pbn_oxsemi_4_4000000 },
4466 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4468 pbn_oxsemi_8_4000000 },
4469 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471 pbn_oxsemi_2_4000000 },
4472 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4474 pbn_oxsemi_2_4000000 },
4475 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4477 pbn_b0_bt_2_921600 },
4478 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4481 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4484 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4491 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4494 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4502 pbn_b2_bt_2_921600 },
4503 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4505 pbn_b2_bt_2_921600 },
4506 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4508 pbn_b2_bt_2_921600 },
4509 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4510 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4511 pbn_b2_bt_4_921600 },
4512 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4514 pbn_b2_bt_4_921600 },
4515 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517 pbn_b2_bt_4_921600 },
4518 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4521 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4524 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4527 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4529 pbn_b0_bt_2_921600 },
4530 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4532 pbn_b0_bt_2_921600 },
4533 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4535 pbn_b0_bt_2_921600 },
4536 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4538 pbn_b0_bt_4_921600 },
4539 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4541 pbn_b0_bt_4_921600 },
4542 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544 pbn_b0_bt_4_921600 },
4545 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4547 pbn_b0_bt_8_921600 },
4548 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4550 pbn_b0_bt_8_921600 },
4551 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4552 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4553 pbn_b0_bt_8_921600 },
4556 * Computone devices submitted by Doug McNash dmcnash@computone.com
4558 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4559 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4560 0, 0, pbn_computone_4 },
4561 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4562 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4563 0, 0, pbn_computone_8 },
4564 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4565 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4566 0, 0, pbn_computone_6 },
4568 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4569 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4572 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4573 pbn_b0_bt_1_921600 },
4578 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4579 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4580 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4581 pbn_b0_bt_1_921600 },
4583 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4584 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4585 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4586 pbn_b0_bt_1_921600 },
4589 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4591 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 pbn_b0_bt_8_115200 },
4594 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_b0_bt_8_115200 },
4598 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4600 pbn_b0_bt_2_115200 },
4601 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4603 pbn_b0_bt_2_115200 },
4604 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4605 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4606 pbn_b0_bt_2_115200 },
4607 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4608 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4609 pbn_b0_bt_2_115200 },
4610 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4612 pbn_b0_bt_2_115200 },
4613 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4615 pbn_b0_bt_4_460800 },
4616 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4618 pbn_b0_bt_4_460800 },
4619 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4621 pbn_b0_bt_2_460800 },
4622 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4624 pbn_b0_bt_2_460800 },
4625 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4627 pbn_b0_bt_2_460800 },
4628 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4630 pbn_b0_bt_1_115200 },
4631 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633 pbn_b0_bt_1_460800 },
4636 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4637 * Cards are identified by their subsystem vendor IDs, which
4638 * (in hex) match the model number.
4640 * Note that JC140x are RS422/485 cards which require ox950
4641 * ACR = 0x10, and as such are not currently fully supported.
4643 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4644 0x1204, 0x0004, 0, 0,
4646 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4647 0x1208, 0x0004, 0, 0,
4649 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4650 0x1402, 0x0002, 0, 0,
4651 pbn_b0_2_921600 }, */
4652 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4653 0x1404, 0x0004, 0, 0,
4654 pbn_b0_4_921600 }, */
4655 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4656 0x1208, 0x0004, 0, 0,
4659 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4660 0x1204, 0x0004, 0, 0,
4662 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4663 0x1208, 0x0004, 0, 0,
4665 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4666 0x1208, 0x0004, 0, 0,
4669 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4671 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4676 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4678 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4679 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4683 * RAStel 2 port modem, gerg@moreton.com.au
4685 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 pbn_b2_bt_2_115200 },
4690 * EKF addition for i960 Boards form EKF with serial port
4692 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4693 0xE4BF, PCI_ANY_ID, 0, 0,
4697 * Xircom Cardbus/Ethernet combos
4699 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4703 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4705 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 * Untested PCI modems, sent in from various folks...
4714 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4716 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4717 0x1048, 0x1500, 0, 0,
4720 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4727 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4728 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4730 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4733 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4740 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4741 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4743 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4748 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4750 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4751 PCI_ANY_ID, PCI_ANY_ID,
4753 0, pbn_exar_XR17C152 },
4754 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4755 PCI_ANY_ID, PCI_ANY_ID,
4757 0, pbn_exar_XR17C154 },
4758 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4759 PCI_ANY_ID, PCI_ANY_ID,
4761 0, pbn_exar_XR17C158 },
4763 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4765 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4766 PCI_ANY_ID, PCI_ANY_ID,
4768 0, pbn_exar_XR17V352 },
4769 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4770 PCI_ANY_ID, PCI_ANY_ID,
4772 0, pbn_exar_XR17V354 },
4773 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4774 PCI_ANY_ID, PCI_ANY_ID,
4776 0, pbn_exar_XR17V358 },
4779 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4781 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4782 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4788 PCI_ANY_ID, PCI_ANY_ID,
4790 pbn_b1_bt_1_115200 },
4795 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4796 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4801 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4802 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4805 * Perle PCI-RAS cards
4807 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4808 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4809 0, 0, pbn_b2_4_921600 },
4810 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4811 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4812 0, 0, pbn_b2_8_921600 },
4815 * Mainpine series cards: Fairly standard layout but fools
4816 * parts of the autodetect in some cases and uses otherwise
4817 * unmatched communications subclasses in the PCI Express case
4820 { /* RockForceDUO */
4821 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4822 PCI_VENDOR_ID_MAINPINE, 0x0200,
4823 0, 0, pbn_b0_2_115200 },
4824 { /* RockForceQUATRO */
4825 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4826 PCI_VENDOR_ID_MAINPINE, 0x0300,
4827 0, 0, pbn_b0_4_115200 },
4828 { /* RockForceDUO+ */
4829 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4830 PCI_VENDOR_ID_MAINPINE, 0x0400,
4831 0, 0, pbn_b0_2_115200 },
4832 { /* RockForceQUATRO+ */
4833 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4834 PCI_VENDOR_ID_MAINPINE, 0x0500,
4835 0, 0, pbn_b0_4_115200 },
4837 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4838 PCI_VENDOR_ID_MAINPINE, 0x0600,
4839 0, 0, pbn_b0_2_115200 },
4841 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4842 PCI_VENDOR_ID_MAINPINE, 0x0700,
4843 0, 0, pbn_b0_4_115200 },
4844 { /* RockForceOCTO+ */
4845 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4846 PCI_VENDOR_ID_MAINPINE, 0x0800,
4847 0, 0, pbn_b0_8_115200 },
4848 { /* RockForceDUO+ */
4849 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4850 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4851 0, 0, pbn_b0_2_115200 },
4852 { /* RockForceQUARTRO+ */
4853 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4854 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4855 0, 0, pbn_b0_4_115200 },
4856 { /* RockForceOCTO+ */
4857 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4858 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4859 0, 0, pbn_b0_8_115200 },
4861 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4862 PCI_VENDOR_ID_MAINPINE, 0x2000,
4863 0, 0, pbn_b0_1_115200 },
4865 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4866 PCI_VENDOR_ID_MAINPINE, 0x2100,
4867 0, 0, pbn_b0_1_115200 },
4869 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4870 PCI_VENDOR_ID_MAINPINE, 0x2200,
4871 0, 0, pbn_b0_2_115200 },
4873 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4874 PCI_VENDOR_ID_MAINPINE, 0x2300,
4875 0, 0, pbn_b0_2_115200 },
4877 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4878 PCI_VENDOR_ID_MAINPINE, 0x2400,
4879 0, 0, pbn_b0_4_115200 },
4881 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4882 PCI_VENDOR_ID_MAINPINE, 0x2500,
4883 0, 0, pbn_b0_4_115200 },
4885 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4886 PCI_VENDOR_ID_MAINPINE, 0x2600,
4887 0, 0, pbn_b0_8_115200 },
4889 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4890 PCI_VENDOR_ID_MAINPINE, 0x2700,
4891 0, 0, pbn_b0_8_115200 },
4892 { /* IQ Express D1 */
4893 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4894 PCI_VENDOR_ID_MAINPINE, 0x3000,
4895 0, 0, pbn_b0_1_115200 },
4896 { /* IQ Express F1 */
4897 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4898 PCI_VENDOR_ID_MAINPINE, 0x3100,
4899 0, 0, pbn_b0_1_115200 },
4900 { /* IQ Express D2 */
4901 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4902 PCI_VENDOR_ID_MAINPINE, 0x3200,
4903 0, 0, pbn_b0_2_115200 },
4904 { /* IQ Express F2 */
4905 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4906 PCI_VENDOR_ID_MAINPINE, 0x3300,
4907 0, 0, pbn_b0_2_115200 },
4908 { /* IQ Express D4 */
4909 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4910 PCI_VENDOR_ID_MAINPINE, 0x3400,
4911 0, 0, pbn_b0_4_115200 },
4912 { /* IQ Express F4 */
4913 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4914 PCI_VENDOR_ID_MAINPINE, 0x3500,
4915 0, 0, pbn_b0_4_115200 },
4916 { /* IQ Express D8 */
4917 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4918 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4919 0, 0, pbn_b0_8_115200 },
4920 { /* IQ Express F8 */
4921 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4922 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4923 0, 0, pbn_b0_8_115200 },
4927 * PA Semi PA6T-1682M on-chip UART
4929 { PCI_VENDOR_ID_PASEMI, 0xa004,
4930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4934 * National Instruments
4936 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4939 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4942 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944 pbn_b1_bt_4_115200 },
4945 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4947 pbn_b1_bt_2_115200 },
4948 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4950 pbn_b1_bt_4_115200 },
4951 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4953 pbn_b1_bt_2_115200 },
4954 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4957 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4960 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4962 pbn_b1_bt_4_115200 },
4963 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4965 pbn_b1_bt_2_115200 },
4966 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4968 pbn_b1_bt_4_115200 },
4969 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4971 pbn_b1_bt_2_115200 },
4972 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4975 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4978 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4981 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4984 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4987 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4990 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4993 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4996 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4999 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5002 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5005 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5010 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5012 { PCI_VENDOR_ID_ADDIDATA,
5013 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5020 { PCI_VENDOR_ID_ADDIDATA,
5021 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5028 { PCI_VENDOR_ID_ADDIDATA,
5029 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5036 { PCI_VENDOR_ID_AMCC,
5037 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5044 { PCI_VENDOR_ID_ADDIDATA,
5045 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5052 { PCI_VENDOR_ID_ADDIDATA,
5053 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5060 { PCI_VENDOR_ID_ADDIDATA,
5061 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5068 { PCI_VENDOR_ID_ADDIDATA,
5069 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5076 { PCI_VENDOR_ID_ADDIDATA,
5077 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5084 { PCI_VENDOR_ID_ADDIDATA,
5085 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5092 { PCI_VENDOR_ID_ADDIDATA,
5093 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5100 { PCI_VENDOR_ID_ADDIDATA,
5101 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5106 pbn_ADDIDATA_PCIe_4_3906250 },
5108 { PCI_VENDOR_ID_ADDIDATA,
5109 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5114 pbn_ADDIDATA_PCIe_2_3906250 },
5116 { PCI_VENDOR_ID_ADDIDATA,
5117 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5122 pbn_ADDIDATA_PCIe_1_3906250 },
5124 { PCI_VENDOR_ID_ADDIDATA,
5125 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5130 pbn_ADDIDATA_PCIe_8_3906250 },
5132 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5133 PCI_VENDOR_ID_IBM, 0x0299,
5134 0, 0, pbn_b0_bt_2_115200 },
5137 * other NetMos 9835 devices are most likely handled by the
5138 * parport_serial driver, check drivers/parport/parport_serial.c
5139 * before adding them here.
5142 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5144 0, 0, pbn_b0_1_115200 },
5146 /* the 9901 is a rebranded 9912 */
5147 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5149 0, 0, pbn_b0_1_115200 },
5151 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5153 0, 0, pbn_b0_1_115200 },
5155 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5157 0, 0, pbn_b0_1_115200 },
5159 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5161 0, 0, pbn_b0_1_115200 },
5163 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5165 0, 0, pbn_NETMOS9900_2s_115200 },
5168 * Best Connectivity and Rosewill PCI Multi I/O cards
5171 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5173 0, 0, pbn_b0_1_115200 },
5175 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5177 0, 0, pbn_b0_bt_2_115200 },
5179 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5181 0, 0, pbn_b0_bt_4_115200 },
5183 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5184 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5185 pbn_ce4100_1_115200 },
5186 /* Intel BayTrail */
5187 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5188 PCI_ANY_ID, PCI_ANY_ID,
5189 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5191 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5192 PCI_ANY_ID, PCI_ANY_ID,
5193 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5199 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5205 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5210 * Broadcom TruManage
5212 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5214 pbn_brcm_trumanage },
5217 * AgeStar as-prs2-009
5219 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5220 PCI_ANY_ID, PCI_ANY_ID,
5221 0, 0, pbn_b0_bt_2_115200 },
5224 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5225 * so not listed here.
5227 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5228 PCI_ANY_ID, PCI_ANY_ID,
5229 0, 0, pbn_b0_bt_4_115200 },
5231 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5232 PCI_ANY_ID, PCI_ANY_ID,
5233 0, 0, pbn_b0_bt_2_115200 },
5235 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
5236 PCI_ANY_ID, PCI_ANY_ID,
5237 0, 0, pbn_b0_bt_2_115200 },
5240 * Commtech, Inc. Fastcom adapters
5242 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5243 PCI_ANY_ID, PCI_ANY_ID,
5245 0, pbn_b0_2_1152000_200 },
5246 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5247 PCI_ANY_ID, PCI_ANY_ID,
5249 0, pbn_b0_4_1152000_200 },
5250 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5251 PCI_ANY_ID, PCI_ANY_ID,
5253 0, pbn_b0_4_1152000_200 },
5254 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5255 PCI_ANY_ID, PCI_ANY_ID,
5257 0, pbn_b0_8_1152000_200 },
5258 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5259 PCI_ANY_ID, PCI_ANY_ID,
5261 0, pbn_exar_XR17V352 },
5262 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5263 PCI_ANY_ID, PCI_ANY_ID,
5265 0, pbn_exar_XR17V354 },
5266 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5267 PCI_ANY_ID, PCI_ANY_ID,
5269 0, pbn_exar_XR17V358 },
5271 /* Fintek PCI serial cards */
5272 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5273 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5274 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5277 * These entries match devices with class COMMUNICATION_SERIAL,
5278 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5280 { PCI_ANY_ID, PCI_ANY_ID,
5281 PCI_ANY_ID, PCI_ANY_ID,
5282 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5283 0xffff00, pbn_default },
5284 { PCI_ANY_ID, PCI_ANY_ID,
5285 PCI_ANY_ID, PCI_ANY_ID,
5286 PCI_CLASS_COMMUNICATION_MODEM << 8,
5287 0xffff00, pbn_default },
5288 { PCI_ANY_ID, PCI_ANY_ID,
5289 PCI_ANY_ID, PCI_ANY_ID,
5290 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5291 0xffff00, pbn_default },
5295 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5296 pci_channel_state_t state)
5298 struct serial_private *priv = pci_get_drvdata(dev);
5300 if (state == pci_channel_io_perm_failure)
5301 return PCI_ERS_RESULT_DISCONNECT;
5304 pciserial_suspend_ports(priv);
5306 pci_disable_device(dev);
5308 return PCI_ERS_RESULT_NEED_RESET;
5311 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5315 rc = pci_enable_device(dev);
5318 return PCI_ERS_RESULT_DISCONNECT;
5320 pci_restore_state(dev);
5321 pci_save_state(dev);
5323 return PCI_ERS_RESULT_RECOVERED;
5326 static void serial8250_io_resume(struct pci_dev *dev)
5328 struct serial_private *priv = pci_get_drvdata(dev);
5331 pciserial_resume_ports(priv);
5334 static const struct pci_error_handlers serial8250_err_handler = {
5335 .error_detected = serial8250_io_error_detected,
5336 .slot_reset = serial8250_io_slot_reset,
5337 .resume = serial8250_io_resume,
5340 static struct pci_driver serial_pci_driver = {
5342 .probe = pciserial_init_one,
5343 .remove = pciserial_remove_one,
5345 .suspend = pciserial_suspend_one,
5346 .resume = pciserial_resume_one,
5348 .id_table = serial_pci_tbl,
5349 .err_handler = &serial8250_err_handler,
5352 module_pci_driver(serial_pci_driver);
5354 MODULE_LICENSE("GPL");
5355 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5356 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);