2 * 8250-core based driver for the OMAP internal UART
4 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
6 * Copyright (C) 2014 Sebastian Andrzej Siewior
10 #include <linux/device.h>
12 #include <linux/module.h>
13 #include <linux/serial_8250.h>
14 #include <linux/serial_reg.h>
15 #include <linux/tty_flip.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
19 #include <linux/of_gpio.h>
20 #include <linux/of_irq.h>
21 #include <linux/delay.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/console.h>
24 #include <linux/pm_qos.h>
25 #include <linux/dma-mapping.h>
29 #define DEFAULT_CLK_SPEED 48000000
31 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
32 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
33 #define OMAP_DMA_TX_KICK (1 << 2)
35 #define OMAP_UART_FCR_RX_TRIG 6
36 #define OMAP_UART_FCR_TX_TRIG 4
38 /* SCR register bitmasks */
39 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
40 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
41 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
42 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
43 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
44 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
46 /* MVR register bitmasks */
47 #define OMAP_UART_MVR_SCHEME_SHIFT 30
48 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
49 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
50 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
51 #define OMAP_UART_MVR_MAJ_MASK 0x700
52 #define OMAP_UART_MVR_MAJ_SHIFT 8
53 #define OMAP_UART_MVR_MIN_MASK 0x3f
55 #define UART_TI752_TLR_TX 0
56 #define UART_TI752_TLR_RX 4
58 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
59 #define TRIGGER_FCR_MASK(x) (x & 3)
61 /* Enable XON/XOFF flow control on output */
62 #define OMAP_UART_SW_TX 0x08
63 /* Enable XON/XOFF flow control on input */
64 #define OMAP_UART_SW_RX 0x02
66 #define OMAP_UART_WER_MOD_WKUP 0x7f
67 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
72 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
73 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
75 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
77 #define OMAP_UART_REV_46 0x0406
78 #define OMAP_UART_REV_52 0x0502
79 #define OMAP_UART_REV_63 0x0603
81 struct omap8250_priv {
98 struct pm_qos_request pm_qos_request;
99 struct work_struct qos_work;
100 struct uart_8250_dma omap8250_dma;
103 static u32 uart_read(struct uart_8250_port *up, u32 reg)
105 return readl(up->port.membase + (reg << up->port.regshift));
108 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
110 struct uart_8250_port *up = up_to_u8250p(port);
111 struct omap8250_priv *priv = up->port.private_data;
114 serial8250_do_set_mctrl(port, mctrl);
117 * Turn off autoRTS if RTS is lowered and restore autoRTS setting
120 lcr = serial_in(up, UART_LCR);
121 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
122 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
123 priv->efr |= UART_EFR_RTS;
125 priv->efr &= ~UART_EFR_RTS;
126 serial_out(up, UART_EFR, priv->efr);
127 serial_out(up, UART_LCR, lcr);
131 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
132 * The access to uart register after MDR1 Access
133 * causes UART to corrupt data.
136 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
137 * give 10 times as much
139 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
140 struct omap8250_priv *priv)
145 old_mdr1 = serial_in(up, UART_OMAP_MDR1);
146 if (old_mdr1 == priv->mdr1)
149 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
151 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
152 UART_FCR_CLEAR_RCVR);
154 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
155 * TX_FIFO_E bit is 1.
157 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
158 (UART_LSR_THRE | UART_LSR_DR))) {
161 /* Should *never* happen. we warn and carry on */
162 dev_crit(up->port.dev, "Errata i202: timedout %x\n",
163 serial_in(up, UART_LSR));
170 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
171 struct omap8250_priv *priv)
173 unsigned int uartclk = port->uartclk;
174 unsigned int div_13, div_16;
175 unsigned int abs_d13, abs_d16;
178 * Old custom speed handling.
180 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
181 priv->quot = port->custom_divisor & 0xffff;
183 * I assume that nobody is using this. But hey, if somebody
184 * would like to specify the divisor _and_ the mode then the
185 * driver is ready and waiting for it.
187 if (port->custom_divisor & (1 << 16))
188 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
190 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
193 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
194 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
201 abs_d13 = abs(baud - uartclk / 13 / div_13);
202 abs_d16 = abs(baud - uartclk / 16 / div_16);
204 if (abs_d13 >= abs_d16) {
205 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
208 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
213 static void omap8250_update_scr(struct uart_8250_port *up,
214 struct omap8250_priv *priv)
218 old_scr = serial_in(up, UART_OMAP_SCR);
219 if (old_scr == priv->scr)
223 * The manual recommends not to enable the DMA mode selector in the SCR
224 * (instead of the FCR) register _and_ selecting the DMA mode as one
225 * register write because this may lead to malfunction.
227 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
228 serial_out(up, UART_OMAP_SCR,
229 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
230 serial_out(up, UART_OMAP_SCR, priv->scr);
233 static void omap8250_restore_regs(struct uart_8250_port *up)
235 struct omap8250_priv *priv = up->port.private_data;
236 struct uart_8250_dma *dma = up->dma;
238 if (dma && dma->tx_running) {
240 * TCSANOW requests the change to occur immediately however if
241 * we have a TX-DMA operation in progress then it has been
242 * observed that it might stall and never complete. Therefore we
243 * delay DMA completes to prevent this hang from happen.
245 priv->delayed_restore = 1;
249 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
250 serial_out(up, UART_EFR, UART_EFR_ECB);
252 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
253 serial_out(up, UART_MCR, UART_MCR_TCRTLR);
254 serial_out(up, UART_FCR, up->fcr);
256 omap8250_update_scr(up, priv);
258 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
260 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
261 OMAP_UART_TCR_HALT(52));
262 serial_out(up, UART_TI752_TLR,
263 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX |
264 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
266 serial_out(up, UART_LCR, 0);
268 /* drop TCR + TLR access, we setup XON/XOFF later */
269 serial_out(up, UART_MCR, up->mcr);
270 serial_out(up, UART_IER, up->ier);
272 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
273 serial_dl_write(up, priv->quot);
275 serial_out(up, UART_EFR, priv->efr);
277 /* Configure flow control */
278 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
279 serial_out(up, UART_XON1, priv->xon);
280 serial_out(up, UART_XOFF1, priv->xoff);
282 serial_out(up, UART_LCR, up->lcr);
283 /* need mode A for FCR */
284 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
285 omap_8250_mdr1_errataset(up, priv);
287 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
288 up->port.ops->set_mctrl(&up->port, up->port.mctrl);
292 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
293 * some differences in how we want to handle flow control.
295 static void omap_8250_set_termios(struct uart_port *port,
296 struct ktermios *termios,
297 struct ktermios *old)
299 struct uart_8250_port *up =
300 container_of(port, struct uart_8250_port, port);
301 struct omap8250_priv *priv = up->port.private_data;
302 unsigned char cval = 0;
305 switch (termios->c_cflag & CSIZE) {
307 cval = UART_LCR_WLEN5;
310 cval = UART_LCR_WLEN6;
313 cval = UART_LCR_WLEN7;
317 cval = UART_LCR_WLEN8;
321 if (termios->c_cflag & CSTOPB)
322 cval |= UART_LCR_STOP;
323 if (termios->c_cflag & PARENB)
324 cval |= UART_LCR_PARITY;
325 if (!(termios->c_cflag & PARODD))
326 cval |= UART_LCR_EPAR;
327 if (termios->c_cflag & CMSPAR)
328 cval |= UART_LCR_SPAR;
331 * Ask the core to calculate the divisor for us.
333 baud = uart_get_baud_rate(port, termios, old,
334 port->uartclk / 16 / 0xffff,
336 omap_8250_get_divisor(port, baud, priv);
339 * Ok, we're now changing the port state. Do it with
340 * interrupts disabled.
342 pm_runtime_get_sync(port->dev);
343 spin_lock_irq(&port->lock);
346 * Update the per-port timeout.
348 uart_update_timeout(port, termios->c_cflag, baud);
350 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
351 if (termios->c_iflag & INPCK)
352 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
353 if (termios->c_iflag & (IGNBRK | PARMRK))
354 up->port.read_status_mask |= UART_LSR_BI;
357 * Characters to ignore
359 up->port.ignore_status_mask = 0;
360 if (termios->c_iflag & IGNPAR)
361 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
362 if (termios->c_iflag & IGNBRK) {
363 up->port.ignore_status_mask |= UART_LSR_BI;
365 * If we're ignoring parity and break indicators,
366 * ignore overruns too (for real raw support).
368 if (termios->c_iflag & IGNPAR)
369 up->port.ignore_status_mask |= UART_LSR_OE;
373 * ignore all characters if CREAD is not set
375 if ((termios->c_cflag & CREAD) == 0)
376 up->port.ignore_status_mask |= UART_LSR_DR;
379 * Modem status interrupts
381 up->ier &= ~UART_IER_MSI;
382 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
383 up->ier |= UART_IER_MSI;
386 /* Up to here it was mostly serial8250_do_set_termios() */
389 * We enable TRIG_GRANU for RX and TX and additionaly we set
390 * SCR_TX_EMPTY bit. The result is the following:
391 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
392 * - less than RX_TRIGGER number of bytes will also cause an interrupt
393 * once the UART decides that there no new bytes arriving.
394 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
395 * empty - the trigger level is ignored here.
397 * Once DMA is enabled:
398 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
399 * bytes in the TX FIFO. On each assert the DMA engine will move
400 * TX_TRIGGER bytes into the FIFO.
401 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
402 * the FIFO and move RX_TRIGGER bytes.
403 * This is because threshold and trigger values are the same.
405 up->fcr = UART_FCR_ENABLE_FIFO;
406 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
407 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
409 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
410 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
413 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
414 OMAP_UART_SCR_DMAMODE_CTL;
416 priv->xon = termios->c_cc[VSTART];
417 priv->xoff = termios->c_cc[VSTOP];
420 up->mcr &= ~(UART_MCR_RTS | UART_MCR_XONANY);
421 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
423 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
424 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
425 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
426 priv->efr |= UART_EFR_CTS;
427 } else if (up->port.flags & UPF_SOFT_FLOW) {
430 * Enable XON/XOFF flow control on input.
431 * Receiver compares XON1, XOFF1.
433 if (termios->c_iflag & IXON)
434 priv->efr |= OMAP_UART_SW_RX;
438 * Enable XON/XOFF flow control on output.
439 * Transmit XON1, XOFF1
441 if (termios->c_iflag & IXOFF) {
442 up->port.status |= UPSTAT_AUTOXOFF;
443 priv->efr |= OMAP_UART_SW_TX;
448 * Enable any character to restart output.
449 * Operation resumes after receiving any
450 * character after recognition of the XOFF character
452 if (termios->c_iflag & IXANY)
453 up->mcr |= UART_MCR_XONANY;
455 omap8250_restore_regs(up);
457 spin_unlock_irq(&up->port.lock);
458 pm_runtime_mark_last_busy(port->dev);
459 pm_runtime_put_autosuspend(port->dev);
461 /* calculate wakeup latency constraint */
462 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
463 priv->latency = priv->calc_latency;
465 schedule_work(&priv->qos_work);
467 /* Don't rewrite B0 */
468 if (tty_termios_baud_rate(termios))
469 tty_termios_encode_baud_rate(termios, baud, baud);
472 /* same as 8250 except that we may have extra flow bits set in EFR */
473 static void omap_8250_pm(struct uart_port *port, unsigned int state,
474 unsigned int oldstate)
476 struct uart_8250_port *up = up_to_u8250p(port);
479 pm_runtime_get_sync(port->dev);
480 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
481 efr = serial_in(up, UART_EFR);
482 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
483 serial_out(up, UART_LCR, 0);
485 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
486 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
487 serial_out(up, UART_EFR, efr);
488 serial_out(up, UART_LCR, 0);
490 pm_runtime_mark_last_busy(port->dev);
491 pm_runtime_put_autosuspend(port->dev);
494 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
495 struct omap8250_priv *priv)
498 u16 revision, major, minor;
500 mvr = uart_read(up, UART_OMAP_MVER);
502 /* Check revision register scheme */
503 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
506 case 0: /* Legacy Scheme: OMAP2/3 */
507 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
508 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
509 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
510 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
513 /* New Scheme: OMAP4+ */
514 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
515 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
516 OMAP_UART_MVR_MAJ_SHIFT;
517 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
520 dev_warn(up->port.dev,
521 "Unknown revision, defaulting to highest\n");
522 /* highest possible revision */
526 /* normalize revision for the driver */
527 revision = UART_BUILD_REVISION(major, minor);
530 case OMAP_UART_REV_46:
531 priv->habit = UART_ERRATA_i202_MDR1_ACCESS;
533 case OMAP_UART_REV_52:
534 priv->habit = UART_ERRATA_i202_MDR1_ACCESS |
535 OMAP_UART_WER_HAS_TX_WAKEUP;
537 case OMAP_UART_REV_63:
538 priv->habit = UART_ERRATA_i202_MDR1_ACCESS |
539 OMAP_UART_WER_HAS_TX_WAKEUP;
546 static void omap8250_uart_qos_work(struct work_struct *work)
548 struct omap8250_priv *priv;
550 priv = container_of(work, struct omap8250_priv, qos_work);
551 pm_qos_update_request(&priv->pm_qos_request, priv->latency);
554 static irqreturn_t omap_wake_irq(int irq, void *dev_id)
556 struct uart_port *port = dev_id;
559 ret = port->handle_irq(port);
565 static int omap_8250_startup(struct uart_port *port)
567 struct uart_8250_port *up =
568 container_of(port, struct uart_8250_port, port);
569 struct omap8250_priv *priv = port->private_data;
574 ret = request_irq(priv->wakeirq, omap_wake_irq,
575 port->irqflags, "uart wakeup irq", port);
578 disable_irq(priv->wakeirq);
581 pm_runtime_get_sync(port->dev);
583 ret = serial8250_do_startup(port);
588 up->capabilities |= UART_CAP_RPM;
591 /* Enable module level wake up */
592 priv->wer = OMAP_UART_WER_MOD_WKUP;
593 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
594 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
595 serial_out(up, UART_OMAP_WER, priv->wer);
598 up->dma->rx_dma(up, 0);
600 pm_runtime_mark_last_busy(port->dev);
601 pm_runtime_put_autosuspend(port->dev);
604 pm_runtime_mark_last_busy(port->dev);
605 pm_runtime_put_autosuspend(port->dev);
607 free_irq(priv->wakeirq, port);
611 static void omap_8250_shutdown(struct uart_port *port)
613 struct uart_8250_port *up =
614 container_of(port, struct uart_8250_port, port);
615 struct omap8250_priv *priv = port->private_data;
617 flush_work(&priv->qos_work);
619 up->dma->rx_dma(up, UART_IIR_RX_TIMEOUT);
621 pm_runtime_get_sync(port->dev);
623 serial_out(up, UART_OMAP_WER, 0);
624 serial8250_do_shutdown(port);
626 pm_runtime_mark_last_busy(port->dev);
627 pm_runtime_put_autosuspend(port->dev);
630 free_irq(priv->wakeirq, port);
633 static void omap_8250_throttle(struct uart_port *port)
636 struct uart_8250_port *up =
637 container_of(port, struct uart_8250_port, port);
639 pm_runtime_get_sync(port->dev);
641 spin_lock_irqsave(&port->lock, flags);
642 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
643 serial_out(up, UART_IER, up->ier);
644 spin_unlock_irqrestore(&port->lock, flags);
646 pm_runtime_mark_last_busy(port->dev);
647 pm_runtime_put_autosuspend(port->dev);
650 static void omap_8250_unthrottle(struct uart_port *port)
653 struct uart_8250_port *up =
654 container_of(port, struct uart_8250_port, port);
656 pm_runtime_get_sync(port->dev);
658 spin_lock_irqsave(&port->lock, flags);
659 up->ier |= UART_IER_RLSI | UART_IER_RDI;
660 serial_out(up, UART_IER, up->ier);
661 spin_unlock_irqrestore(&port->lock, flags);
663 pm_runtime_mark_last_busy(port->dev);
664 pm_runtime_put_autosuspend(port->dev);
667 #ifdef CONFIG_SERIAL_8250_DMA
668 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir);
670 static void __dma_rx_do_complete(struct uart_8250_port *p, bool error)
672 struct uart_8250_dma *dma = p->dma;
673 struct tty_port *tty_port = &p->port.state->port;
674 struct dma_tx_state state;
677 dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr,
678 dma->rx_size, DMA_FROM_DEVICE);
681 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
682 dmaengine_terminate_all(dma->rxchan);
684 count = dma->rx_size - state.residue;
686 tty_insert_flip_string(tty_port, dma->rx_buf, count);
687 p->port.icount.rx += count;
689 omap_8250_rx_dma(p, 0);
691 tty_flip_buffer_push(tty_port);
694 static void __dma_rx_complete(void *param)
696 __dma_rx_do_complete(param, false);
699 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir)
701 struct uart_8250_dma *dma = p->dma;
702 struct dma_async_tx_descriptor *desc;
704 switch (iir & 0x3f) {
706 /* 8250_core handles errors and break interrupts */
707 if (dma->rx_running) {
708 dmaengine_pause(dma->rxchan);
709 __dma_rx_do_complete(p, true);
712 case UART_IIR_RX_TIMEOUT:
714 * If RCVR FIFO trigger level was not reached, complete the
715 * transfer and let 8250_core copy the remaining data.
717 if (dma->rx_running) {
718 dmaengine_pause(dma->rxchan);
719 __dma_rx_do_complete(p, true);
724 * The OMAP UART is a special BEAST. If we receive RDI we _have_
725 * a DMA transfer programmed but it didn't work. One reason is
726 * that we were too slow and there were too many bytes in the
727 * FIFO, the UART counted wrong and never kicked the DMA engine
728 * to do anything. That means once we receive RDI on OMAP then
729 * the DMA won't do anything soon so we have to cancel the DMA
730 * transfer and purge the FIFO manually.
732 if (dma->rx_running) {
733 dmaengine_pause(dma->rxchan);
734 __dma_rx_do_complete(p, true);
745 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
746 dma->rx_size, DMA_DEV_TO_MEM,
747 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
752 desc->callback = __dma_rx_complete;
753 desc->callback_param = p;
755 dma->rx_cookie = dmaengine_submit(desc);
757 dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr,
758 dma->rx_size, DMA_FROM_DEVICE);
760 dma_async_issue_pending(dma->rxchan);
764 static int omap_8250_tx_dma(struct uart_8250_port *p);
766 static void omap_8250_dma_tx_complete(void *param)
768 struct uart_8250_port *p = param;
769 struct uart_8250_dma *dma = p->dma;
770 struct circ_buf *xmit = &p->port.state->xmit;
772 bool en_thri = false;
773 struct omap8250_priv *priv = p->port.private_data;
775 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
776 UART_XMIT_SIZE, DMA_TO_DEVICE);
778 spin_lock_irqsave(&p->port.lock, flags);
782 xmit->tail += dma->tx_size;
783 xmit->tail &= UART_XMIT_SIZE - 1;
784 p->port.icount.tx += dma->tx_size;
786 if (priv->delayed_restore) {
787 priv->delayed_restore = 0;
788 omap8250_restore_regs(p);
791 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
792 uart_write_wakeup(&p->port);
794 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
797 ret = omap_8250_tx_dma(p);
801 } else if (p->capabilities & UART_CAP_RPM) {
807 p->ier |= UART_IER_THRI;
808 serial_port_out(&p->port, UART_IER, p->ier);
811 spin_unlock_irqrestore(&p->port.lock, flags);
814 static int omap_8250_tx_dma(struct uart_8250_port *p)
816 struct uart_8250_dma *dma = p->dma;
817 struct omap8250_priv *priv = p->port.private_data;
818 struct circ_buf *xmit = &p->port.state->xmit;
819 struct dma_async_tx_descriptor *desc;
820 unsigned int skip_byte = 0;
825 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
828 * Even if no data, we need to return an error for the two cases
829 * below so serial8250_tx_chars() is invoked and properly clears
830 * THRI and/or runtime suspend.
832 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
836 if (p->ier & UART_IER_THRI) {
837 p->ier &= ~UART_IER_THRI;
838 serial_out(p, UART_IER, p->ier);
843 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
844 if (priv->habit & OMAP_DMA_TX_KICK) {
848 * We need to put the first byte into the FIFO in order to start
849 * the DMA transfer. For transfers smaller than four bytes we
850 * don't bother doing DMA at all. It seem not matter if there
851 * are still bytes in the FIFO from the last transfer (in case
852 * we got here directly from omap_8250_dma_tx_complete()). Bytes
853 * leaving the FIFO seem not to trigger the DMA transfer. It is
854 * really the byte that we put into the FIFO.
855 * If the FIFO is already full then we most likely got here from
856 * omap_8250_dma_tx_complete(). And this means the DMA engine
857 * just completed its work. We don't have to wait the complete
858 * 86us at 115200,8n1 but around 60us (not to mention lower
859 * baudrates). So in that case we take the interrupt and try
860 * again with an empty FIFO.
862 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
863 if (tx_lvl == p->tx_loadsz) {
867 if (dma->tx_size < 4) {
874 desc = dmaengine_prep_slave_single(dma->txchan,
875 dma->tx_addr + xmit->tail + skip_byte,
876 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
877 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
885 desc->callback = omap_8250_dma_tx_complete;
886 desc->callback_param = p;
888 dma->tx_cookie = dmaengine_submit(desc);
890 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
891 UART_XMIT_SIZE, DMA_TO_DEVICE);
893 dma_async_issue_pending(dma->txchan);
897 if (p->ier & UART_IER_THRI) {
898 p->ier &= ~UART_IER_THRI;
899 serial_out(p, UART_IER, p->ier);
902 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
910 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
911 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
912 * use the default routine in the non-DMA case and this one for with DMA.
914 static int omap_8250_dma_handle_irq(struct uart_port *port)
916 struct uart_8250_port *up = up_to_u8250p(port);
917 unsigned char status;
922 serial8250_rpm_get(up);
924 iir = serial_port_in(port, UART_IIR);
925 if (iir & UART_IIR_NO_INT) {
926 serial8250_rpm_put(up);
930 spin_lock_irqsave(&port->lock, flags);
932 status = serial_port_in(port, UART_LSR);
934 if (status & (UART_LSR_DR | UART_LSR_BI)) {
936 dma_err = omap_8250_rx_dma(up, iir);
938 status = serial8250_rx_chars(up, status);
939 omap_8250_rx_dma(up, 0);
942 serial8250_modem_status(up);
943 if (status & UART_LSR_THRE && up->dma->tx_err) {
944 if (uart_tx_stopped(&up->port) ||
945 uart_circ_empty(&up->port.state->xmit)) {
947 serial8250_tx_chars(up);
950 * try again due to an earlier failer which
951 * might have been resolved by now.
953 dma_err = omap_8250_tx_dma(up);
955 serial8250_tx_chars(up);
959 spin_unlock_irqrestore(&port->lock, flags);
960 serial8250_rpm_put(up);
964 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
971 static inline int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir)
977 static int omap8250_probe(struct platform_device *pdev)
979 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
980 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
981 struct omap8250_priv *priv;
982 struct uart_8250_port up;
984 void __iomem *membase;
987 dev_err(&pdev->dev, "missing registers or irq\n");
991 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
995 membase = devm_ioremap_nocache(&pdev->dev, regs->start,
996 resource_size(regs));
1000 memset(&up, 0, sizeof(up));
1001 up.port.dev = &pdev->dev;
1002 up.port.mapbase = regs->start;
1003 up.port.membase = membase;
1004 up.port.irq = irq->start;
1006 * It claims to be 16C750 compatible however it is a little different.
1007 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1008 * have) is enabled via EFR instead of MCR. The type is set here 8250
1009 * just to get things going. UNKNOWN does not work for a few reasons and
1010 * we don't need our own type since we don't use 8250's set_termios()
1013 up.port.type = PORT_8250;
1014 up.port.iotype = UPIO_MEM;
1015 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1017 up.port.private_data = priv;
1019 up.port.regshift = 2;
1020 up.port.fifosize = 64;
1022 up.capabilities = UART_CAP_FIFO;
1025 * Runtime PM is mostly transparent. However to do it right we need to a
1026 * TX empty interrupt before we can put the device to auto idle. So if
1027 * PM is not enabled we don't add that flag and can spare that one extra
1028 * interrupt in the TX path.
1030 up.capabilities |= UART_CAP_RPM;
1032 up.port.set_termios = omap_8250_set_termios;
1033 up.port.set_mctrl = omap8250_set_mctrl;
1034 up.port.pm = omap_8250_pm;
1035 up.port.startup = omap_8250_startup;
1036 up.port.shutdown = omap_8250_shutdown;
1037 up.port.throttle = omap_8250_throttle;
1038 up.port.unthrottle = omap_8250_unthrottle;
1040 if (pdev->dev.of_node) {
1041 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1043 of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1045 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1050 dev_err(&pdev->dev, "failed to get alias/pdev id\n");
1055 if (!up.port.uartclk) {
1056 up.port.uartclk = DEFAULT_CLK_SPEED;
1057 dev_warn(&pdev->dev,
1058 "No clock speed specified: using default: %d\n",
1062 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1063 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1064 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1066 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1068 device_init_wakeup(&pdev->dev, true);
1069 pm_runtime_use_autosuspend(&pdev->dev);
1070 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1072 pm_runtime_irq_safe(&pdev->dev);
1073 pm_runtime_enable(&pdev->dev);
1075 pm_runtime_get_sync(&pdev->dev);
1077 omap_serial_fill_features_erratas(&up, priv);
1078 #ifdef CONFIG_SERIAL_8250_DMA
1079 if (pdev->dev.of_node) {
1081 * Oh DMA support. If there are no DMA properties in the DT then
1082 * we will fall back to a generic DMA channel which does not
1083 * really work here. To ensure that we do not get a generic DMA
1084 * channel assigned, we have the the_no_dma_filter_fn() here.
1085 * To avoid "failed to request DMA" messages we check for DMA
1088 ret = of_property_count_strings(pdev->dev.of_node, "dma-names");
1090 up.dma = &priv->omap8250_dma;
1091 up.port.handle_irq = omap_8250_dma_handle_irq;
1092 priv->omap8250_dma.fn = the_no_dma_filter_fn;
1093 priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1094 priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1095 priv->omap8250_dma.rx_size = RX_TRIGGER;
1096 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1097 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1099 if (of_machine_is_compatible("ti,am33xx"))
1100 priv->habit |= OMAP_DMA_TX_KICK;
1104 ret = serial8250_register_8250_port(&up);
1106 dev_err(&pdev->dev, "unable to register 8250 port\n");
1110 platform_set_drvdata(pdev, priv);
1111 pm_runtime_mark_last_busy(&pdev->dev);
1112 pm_runtime_put_autosuspend(&pdev->dev);
1115 pm_runtime_put(&pdev->dev);
1116 pm_runtime_disable(&pdev->dev);
1120 static int omap8250_remove(struct platform_device *pdev)
1122 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1124 pm_runtime_put_sync(&pdev->dev);
1125 pm_runtime_disable(&pdev->dev);
1126 serial8250_unregister_port(priv->line);
1127 pm_qos_remove_request(&priv->pm_qos_request);
1128 device_init_wakeup(&pdev->dev, false);
1134 static inline void omap8250_enable_wakeirq(struct omap8250_priv *priv,
1141 enable_irq(priv->wakeirq);
1143 disable_irq_nosync(priv->wakeirq);
1146 static void omap8250_enable_wakeup(struct omap8250_priv *priv,
1149 if (enable == priv->wakeups_enabled)
1152 omap8250_enable_wakeirq(priv, enable);
1153 priv->wakeups_enabled = enable;
1157 #ifdef CONFIG_PM_SLEEP
1158 static int omap8250_prepare(struct device *dev)
1160 struct omap8250_priv *priv = dev_get_drvdata(dev);
1164 priv->is_suspending = true;
1168 static void omap8250_complete(struct device *dev)
1170 struct omap8250_priv *priv = dev_get_drvdata(dev);
1174 priv->is_suspending = false;
1177 static int omap8250_suspend(struct device *dev)
1179 struct omap8250_priv *priv = dev_get_drvdata(dev);
1181 serial8250_suspend_port(priv->line);
1182 flush_work(&priv->qos_work);
1184 if (device_may_wakeup(dev))
1185 omap8250_enable_wakeup(priv, true);
1187 omap8250_enable_wakeup(priv, false);
1191 static int omap8250_resume(struct device *dev)
1193 struct omap8250_priv *priv = dev_get_drvdata(dev);
1195 if (device_may_wakeup(dev))
1196 omap8250_enable_wakeup(priv, false);
1198 serial8250_resume_port(priv->line);
1202 #define omap8250_prepare NULL
1203 #define omap8250_complete NULL
1207 static int omap8250_lost_context(struct uart_8250_port *up)
1211 val = serial_in(up, UART_OMAP_MDR1);
1213 * If we lose context, then MDR1 is set to its reset value which is
1214 * UART_OMAP_MDR1_DISABLE. After set_termios() we set it either to 13x
1215 * or 16x but never to disable again.
1217 if (val == UART_OMAP_MDR1_DISABLE)
1222 static int omap8250_runtime_suspend(struct device *dev)
1224 struct omap8250_priv *priv = dev_get_drvdata(dev);
1225 struct uart_8250_port *up;
1227 up = serial8250_get_port(priv->line);
1229 * When using 'no_console_suspend', the console UART must not be
1230 * suspended. Since driver suspend is managed by runtime suspend,
1231 * preventing runtime suspend (by returning error) will keep device
1232 * active during suspend.
1234 if (priv->is_suspending && !console_suspend_enabled) {
1235 if (uart_console(&up->port))
1239 omap8250_enable_wakeup(priv, true);
1241 omap_8250_rx_dma(up, UART_IIR_RX_TIMEOUT);
1243 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1244 schedule_work(&priv->qos_work);
1249 static int omap8250_runtime_resume(struct device *dev)
1251 struct omap8250_priv *priv = dev_get_drvdata(dev);
1252 struct uart_8250_port *up;
1255 /* In case runtime-pm tries this before we are setup */
1259 up = serial8250_get_port(priv->line);
1260 omap8250_enable_wakeup(priv, false);
1261 loss_cntx = omap8250_lost_context(up);
1264 omap8250_restore_regs(up);
1267 omap_8250_rx_dma(up, 0);
1269 priv->latency = priv->calc_latency;
1270 schedule_work(&priv->qos_work);
1275 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1276 static int __init omap8250_console_fixup(void)
1282 if (strstr(boot_command_line, "console=ttyS"))
1283 /* user set a ttyS based name for the console */
1286 omap_str = strstr(boot_command_line, "console=ttyO");
1288 /* user did not set ttyO based console, so we don't care */
1292 if ('0' <= *omap_str && *omap_str <= '9')
1293 idx = *omap_str - '0';
1298 if (omap_str[0] == ',') {
1305 add_preferred_console("ttyS", idx, options);
1306 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1308 pr_err("This ensures that you still see kernel messages. Please\n");
1309 pr_err("update your kernel commandline.\n");
1312 console_initcall(omap8250_console_fixup);
1315 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1316 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1317 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1318 omap8250_runtime_resume, NULL)
1319 .prepare = omap8250_prepare,
1320 .complete = omap8250_complete,
1323 static const struct of_device_id omap8250_dt_ids[] = {
1324 { .compatible = "ti,omap2-uart" },
1325 { .compatible = "ti,omap3-uart" },
1326 { .compatible = "ti,omap4-uart" },
1329 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1331 static struct platform_driver omap8250_platform_driver = {
1334 .pm = &omap8250_dev_pm_ops,
1335 .of_match_table = omap8250_dt_ids,
1337 .probe = omap8250_probe,
1338 .remove = omap8250_remove,
1340 module_platform_driver(omap8250_platform_driver);
1342 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1343 MODULE_DESCRIPTION("OMAP 8250 Driver");
1344 MODULE_LICENSE("GPL v2");