2 * Synopsys DesignWare 8250 driver.
4 * Copyright 2011 Picochip, Jamie Iles.
5 * Copyright 2013 Intel Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
13 * LCR is written whilst busy. If it is, then a busy detect interrupt is
14 * raised, the LCR needs to be rewritten and the uart status register read.
16 #include <linux/device.h>
18 #include <linux/module.h>
19 #include <linux/serial_8250.h>
20 #include <linux/serial_core.h>
21 #include <linux/serial_reg.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_platform.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/acpi.h>
28 #include <linux/clk.h>
29 #include <linux/reset.h>
30 #include <linux/pm_runtime.h>
32 #include <asm/byteorder.h>
36 /* Offsets for the DesignWare specific registers */
37 #define DW_UART_USR 0x1f /* UART Status Register */
38 #define DW_UART_CPR 0xf4 /* Component Parameter Register */
39 #define DW_UART_UCV 0xf8 /* UART Component Version */
41 /* Component Parameter Register bits */
42 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
43 #define DW_UART_CPR_AFCE_MODE (1 << 4)
44 #define DW_UART_CPR_THRE_MODE (1 << 5)
45 #define DW_UART_CPR_SIR_MODE (1 << 6)
46 #define DW_UART_CPR_SIR_LP_MODE (1 << 7)
47 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
48 #define DW_UART_CPR_FIFO_ACCESS (1 << 9)
49 #define DW_UART_CPR_FIFO_STAT (1 << 10)
50 #define DW_UART_CPR_SHADOW (1 << 11)
51 #define DW_UART_CPR_ENCODED_PARMS (1 << 12)
52 #define DW_UART_CPR_DMA_EXTRA (1 << 13)
53 #define DW_UART_CPR_FIFO_MODE (0xff << 16)
54 /* Helper for fifo size calculation */
55 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
66 struct reset_control *rst;
67 struct uart_8250_dma dma;
70 #define BYT_PRV_CLK 0x800
71 #define BYT_PRV_CLK_EN (1 << 0)
72 #define BYT_PRV_CLK_M_VAL_SHIFT 1
73 #define BYT_PRV_CLK_N_VAL_SHIFT 16
74 #define BYT_PRV_CLK_UPDATE (1 << 31)
76 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
78 struct dw8250_data *d = p->private_data;
80 /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
81 if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
82 value |= UART_MSR_CTS;
83 value &= ~UART_MSR_DCTS;
86 /* Override any modem control signals if needed */
87 if (offset == UART_MSR) {
88 value |= d->msr_mask_on;
89 value &= ~d->msr_mask_off;
95 static void dw8250_force_idle(struct uart_port *p)
97 struct uart_8250_port *up = up_to_u8250p(p);
99 serial8250_clear_and_reinit_fifos(up);
100 (void)p->serial_in(p, UART_RX);
103 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
105 struct dw8250_data *d = p->private_data;
107 if (offset == UART_MCR)
110 writeb(value, p->membase + (offset << p->regshift));
112 /* Make sure LCR write wasn't ignored */
113 if (offset == UART_LCR) {
116 unsigned int lcr = p->serial_in(p, UART_LCR);
117 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
119 dw8250_force_idle(p);
120 writeb(value, p->membase + (UART_LCR << p->regshift));
123 * FIXME: this deadlocks if port->lock is already held
124 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
129 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
131 unsigned int value = readb(p->membase + (offset << p->regshift));
133 return dw8250_modify_msr(p, offset, value);
137 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
141 value = (u8)__raw_readq(p->membase + (offset << p->regshift));
143 return dw8250_modify_msr(p, offset, value);
146 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
148 struct dw8250_data *d = p->private_data;
150 if (offset == UART_MCR)
154 __raw_writeq(value, p->membase + (offset << p->regshift));
155 /* Read back to ensure register write ordering. */
156 __raw_readq(p->membase + (UART_LCR << p->regshift));
158 /* Make sure LCR write wasn't ignored */
159 if (offset == UART_LCR) {
162 unsigned int lcr = p->serial_in(p, UART_LCR);
163 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
165 dw8250_force_idle(p);
166 __raw_writeq(value & 0xff,
167 p->membase + (UART_LCR << p->regshift));
170 * FIXME: this deadlocks if port->lock is already held
171 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
175 #endif /* CONFIG_64BIT */
177 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
179 struct dw8250_data *d = p->private_data;
181 if (offset == UART_MCR)
184 writel(value, p->membase + (offset << p->regshift));
186 /* Make sure LCR write wasn't ignored */
187 if (offset == UART_LCR) {
190 unsigned int lcr = p->serial_in(p, UART_LCR);
191 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
193 dw8250_force_idle(p);
194 writel(value, p->membase + (UART_LCR << p->regshift));
197 * FIXME: this deadlocks if port->lock is already held
198 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
203 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
205 unsigned int value = readl(p->membase + (offset << p->regshift));
207 return dw8250_modify_msr(p, offset, value);
210 static int dw8250_handle_irq(struct uart_port *p)
212 struct dw8250_data *d = p->private_data;
213 unsigned int iir = p->serial_in(p, UART_IIR);
215 if (serial8250_handle_irq(p, iir)) {
217 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
219 (void)p->serial_in(p, d->usr_reg);
228 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
231 pm_runtime_get_sync(port->dev);
233 serial8250_do_pm(port, state, old);
236 pm_runtime_put_sync_suspend(port->dev);
239 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
240 struct ktermios *old)
242 unsigned int baud = tty_termios_baud_rate(termios);
243 struct dw8250_data *d = p->private_data;
247 if (IS_ERR(d->clk) || !old)
250 /* Not requesting clock rates below 1.8432Mhz */
254 clk_disable_unprepare(d->clk);
255 rate = clk_round_rate(d->clk, baud * 16);
256 ret = clk_set_rate(d->clk, rate);
257 clk_prepare_enable(d->clk);
262 serial8250_do_set_termios(p, termios, old);
265 static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
270 static void dw8250_setup_port(struct uart_8250_port *up)
272 struct uart_port *p = &up->port;
273 u32 reg = readl(p->membase + DW_UART_UCV);
276 * If the Component Version Register returns zero, we know that
277 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
282 dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
283 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
285 reg = readl(p->membase + DW_UART_CPR);
289 /* Select the type based on fifo */
290 if (reg & DW_UART_CPR_FIFO_MODE) {
291 p->type = PORT_16550A;
292 p->flags |= UPF_FIXED_TYPE;
293 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
294 up->tx_loadsz = p->fifosize;
295 up->capabilities = UART_CAP_FIFO;
298 if (reg & DW_UART_CPR_AFCE_MODE)
299 up->capabilities |= UART_CAP_AFE;
302 static int dw8250_probe_of(struct uart_port *p,
303 struct dw8250_data *data)
305 struct device_node *np = p->dev->of_node;
306 struct uart_8250_port *up = up_to_u8250p(p);
312 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
313 p->serial_in = dw8250_serial_inq;
314 p->serial_out = dw8250_serial_outq;
315 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
316 p->type = PORT_OCTEON;
317 data->usr_reg = 0x27;
321 if (!of_property_read_u32(np, "reg-io-width", &val)) {
326 p->iotype = UPIO_MEM32;
327 p->serial_in = dw8250_serial_in32;
328 p->serial_out = dw8250_serial_out32;
331 dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
336 dw8250_setup_port(up);
338 /* if we have a valid fifosize, try hooking up DMA here */
340 up->dma = &data->dma;
342 up->dma->rxconf.src_maxburst = p->fifosize / 4;
343 up->dma->txconf.dst_maxburst = p->fifosize / 4;
346 if (!of_property_read_u32(np, "reg-shift", &val))
349 /* get index of serial line, if found in DT aliases */
350 id = of_alias_get_id(np, "serial");
354 if (of_property_read_bool(np, "dcd-override")) {
355 /* Always report DCD as active */
356 data->msr_mask_on |= UART_MSR_DCD;
357 data->msr_mask_off |= UART_MSR_DDCD;
360 if (of_property_read_bool(np, "dsr-override")) {
361 /* Always report DSR as active */
362 data->msr_mask_on |= UART_MSR_DSR;
363 data->msr_mask_off |= UART_MSR_DDSR;
366 if (of_property_read_bool(np, "cts-override")) {
367 /* Always report DSR as active */
368 data->msr_mask_on |= UART_MSR_DSR;
369 data->msr_mask_off |= UART_MSR_DDSR;
372 if (of_property_read_bool(np, "ri-override")) {
373 /* Always report Ring indicator as inactive */
374 data->msr_mask_off |= UART_MSR_RI;
375 data->msr_mask_off |= UART_MSR_TERI;
378 /* clock got configured through clk api, all done */
382 /* try to find out clock frequency from DT as fallback */
383 if (of_property_read_u32(np, "clock-frequency", &val)) {
384 dev_err(p->dev, "clk or clock-frequency not defined\n");
392 static int dw8250_probe_acpi(struct uart_8250_port *up,
393 struct dw8250_data *data)
395 const struct acpi_device_id *id;
396 struct uart_port *p = &up->port;
398 dw8250_setup_port(up);
400 id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
405 if (device_property_read_u32(p->dev, "clock-frequency",
409 p->iotype = UPIO_MEM32;
410 p->serial_in = dw8250_serial_in32;
411 p->serial_out = dw8250_serial_out32;
414 up->dma = &data->dma;
416 up->dma->rxconf.src_maxburst = p->fifosize / 4;
417 up->dma->txconf.dst_maxburst = p->fifosize / 4;
419 up->port.set_termios = dw8250_set_termios;
424 static int dw8250_probe(struct platform_device *pdev)
426 struct uart_8250_port uart = {};
427 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
428 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
429 struct dw8250_data *data;
433 dev_err(&pdev->dev, "no registers/irq defined\n");
437 spin_lock_init(&uart.port.lock);
438 uart.port.mapbase = regs->start;
439 uart.port.irq = irq->start;
440 uart.port.handle_irq = dw8250_handle_irq;
441 uart.port.pm = dw8250_do_pm;
442 uart.port.type = PORT_8250;
443 uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
444 uart.port.dev = &pdev->dev;
446 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
447 resource_size(regs));
448 if (!uart.port.membase)
451 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
455 data->usr_reg = DW_UART_USR;
456 data->clk = devm_clk_get(&pdev->dev, "baudclk");
457 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
458 data->clk = devm_clk_get(&pdev->dev, NULL);
459 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
460 return -EPROBE_DEFER;
461 if (!IS_ERR(data->clk)) {
462 err = clk_prepare_enable(data->clk);
464 dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n",
467 uart.port.uartclk = clk_get_rate(data->clk);
470 data->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
471 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) {
475 if (!IS_ERR(data->pclk)) {
476 err = clk_prepare_enable(data->pclk);
478 dev_err(&pdev->dev, "could not enable apb_pclk\n");
483 data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
484 if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) {
488 if (!IS_ERR(data->rst))
489 reset_control_deassert(data->rst);
491 data->dma.rx_param = data;
492 data->dma.tx_param = data;
493 data->dma.fn = dw8250_dma_filter;
495 uart.port.iotype = UPIO_MEM;
496 uart.port.serial_in = dw8250_serial_in;
497 uart.port.serial_out = dw8250_serial_out;
498 uart.port.private_data = data;
500 if (pdev->dev.of_node) {
501 err = dw8250_probe_of(&uart.port, data);
504 } else if (ACPI_HANDLE(&pdev->dev)) {
505 err = dw8250_probe_acpi(&uart, data);
513 data->line = serial8250_register_8250_port(&uart);
514 if (data->line < 0) {
519 platform_set_drvdata(pdev, data);
521 pm_runtime_set_active(&pdev->dev);
522 pm_runtime_enable(&pdev->dev);
527 if (!IS_ERR(data->rst))
528 reset_control_assert(data->rst);
531 if (!IS_ERR(data->pclk))
532 clk_disable_unprepare(data->pclk);
535 if (!IS_ERR(data->clk))
536 clk_disable_unprepare(data->clk);
541 static int dw8250_remove(struct platform_device *pdev)
543 struct dw8250_data *data = platform_get_drvdata(pdev);
545 pm_runtime_get_sync(&pdev->dev);
547 serial8250_unregister_port(data->line);
549 if (!IS_ERR(data->rst))
550 reset_control_assert(data->rst);
552 if (!IS_ERR(data->pclk))
553 clk_disable_unprepare(data->pclk);
555 if (!IS_ERR(data->clk))
556 clk_disable_unprepare(data->clk);
558 pm_runtime_disable(&pdev->dev);
559 pm_runtime_put_noidle(&pdev->dev);
564 #ifdef CONFIG_PM_SLEEP
565 static int dw8250_suspend(struct device *dev)
567 struct dw8250_data *data = dev_get_drvdata(dev);
569 serial8250_suspend_port(data->line);
574 static int dw8250_resume(struct device *dev)
576 struct dw8250_data *data = dev_get_drvdata(dev);
578 serial8250_resume_port(data->line);
582 #endif /* CONFIG_PM_SLEEP */
585 static int dw8250_runtime_suspend(struct device *dev)
587 struct dw8250_data *data = dev_get_drvdata(dev);
589 if (!IS_ERR(data->clk))
590 clk_disable_unprepare(data->clk);
592 if (!IS_ERR(data->pclk))
593 clk_disable_unprepare(data->pclk);
598 static int dw8250_runtime_resume(struct device *dev)
600 struct dw8250_data *data = dev_get_drvdata(dev);
602 if (!IS_ERR(data->pclk))
603 clk_prepare_enable(data->pclk);
605 if (!IS_ERR(data->clk))
606 clk_prepare_enable(data->clk);
612 static const struct dev_pm_ops dw8250_pm_ops = {
613 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
614 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
617 static const struct of_device_id dw8250_of_match[] = {
618 { .compatible = "snps,dw-apb-uart" },
619 { .compatible = "cavium,octeon-3860-uart" },
622 MODULE_DEVICE_TABLE(of, dw8250_of_match);
624 static const struct acpi_device_id dw8250_acpi_match[] = {
634 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
636 static struct platform_driver dw8250_platform_driver = {
638 .name = "dw-apb-uart",
639 .pm = &dw8250_pm_ops,
640 .of_match_table = dw8250_of_match,
641 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
643 .probe = dw8250_probe,
644 .remove = dw8250_remove,
647 module_platform_driver(dw8250_platform_driver);
649 MODULE_AUTHOR("Jamie Iles");
650 MODULE_LICENSE("GPL");
651 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");