drivers/thermal/samsung/exynos_tmu_data.c

   1 /*
   2  * exynos_tmu_data.c - Samsung EXYNOS tmu data file
   3  *
   4  *  Copyright (C) 2013 Samsung Electronics
   5  *  Amit Daniel Kachhap <amit.daniel@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  */
  22
  23 #include "exynos_thermal_common.h"
  24 #include "exynos_tmu.h"
  25 #include "exynos_tmu_data.h"
  26
  27 #if defined(CONFIG_CPU_EXYNOS4210)
  28 static const struct exynos_tmu_registers exynos4210_tmu_registers = {
  29         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
  30         .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
  31         .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
  32         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
  33         .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
  34         .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
  35         .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
  36         .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
  37         .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
  38         .tmu_status = EXYNOS_TMU_REG_STATUS,
  39         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
  40         .threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
  41         .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
  42         .tmu_inten = EXYNOS_TMU_REG_INTEN,
  43         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
  44         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
  45         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
  46         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
  47         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
  48         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
  49         .intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
  50 };
  51
  52 struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
  53         .tmu_data = {
  54                 {
  55                 .threshold = 80,
  56                 .trigger_levels[0] = 5,
  57                 .trigger_levels[1] = 20,
  58                 .trigger_levels[2] = 30,
  59                 .trigger_enable[0] = true,
  60                 .trigger_enable[1] = true,
  61                 .trigger_enable[2] = true,
  62                 .trigger_enable[3] = false,
  63                 .trigger_type[0] = THROTTLE_ACTIVE,
  64                 .trigger_type[1] = THROTTLE_ACTIVE,
  65                 .trigger_type[2] = SW_TRIP,
  66                 .max_trigger_level = 4,
  67                 .gain = 15,
  68                 .reference_voltage = 7,
  69                 .cal_type = TYPE_ONE_POINT_TRIMMING,
  70                 .min_efuse_value = 40,
  71                 .max_efuse_value = 100,
  72                 .first_point_trim = 25,
  73                 .second_point_trim = 85,
  74                 .default_temp_offset = 50,
  75                 .freq_tab[0] = {
  76                         .freq_clip_max = 800 * 1000,
  77                         .temp_level = 85,
  78                         },
  79                 .freq_tab[1] = {
  80                         .freq_clip_max = 200 * 1000,
  81                         .temp_level = 100,
  82                 },
  83                 .freq_tab_count = 2,
  84                 .type = SOC_ARCH_EXYNOS4210,
  85                 .registers = &exynos4210_tmu_registers,
  86                 .features = TMU_SUPPORT_READY_STATUS,
  87                 },
  88         },
  89         .tmu_count = 1,
  90 };
  91 #endif
  92
  93 #if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
  94 static const struct exynos_tmu_registers exynos4412_tmu_registers = {
  95         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
  96         .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
  97         .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
  98         .triminfo_ctrl = EXYNOS_TMU_TRIMINFO_CON,
  99         .triminfo_reload_shift = EXYNOS_TRIMINFO_RELOAD_SHIFT,
 100         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 101         .test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
 102         .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
 103         .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
 104         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 105         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 106         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 107         .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
 108         .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
 109         .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
 110         .tmu_status = EXYNOS_TMU_REG_STATUS,
 111         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 112         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 113         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 114         .tmu_inten = EXYNOS_TMU_REG_INTEN,
 115         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 116         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 117         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 118         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 119         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 120         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 121         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 122         .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
 123         .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
 124         .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
 125         .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
 126         .emul_con = EXYNOS_EMUL_CON,
 127         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 128         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 129         .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
 130 };
 131
 132 #define EXYNOS4412_TMU_DATA \
 133         .threshold_falling = 10, \
 134         .trigger_levels[0] = 70, \
 135         .trigger_levels[1] = 95, \
 136         .trigger_levels[2] = 110, \
 137         .trigger_levels[3] = 120, \
 138         .trigger_enable[0] = true, \
 139         .trigger_enable[1] = true, \
 140         .trigger_enable[2] = true, \
 141         .trigger_enable[3] = false, \
 142         .trigger_type[0] = THROTTLE_ACTIVE, \
 143         .trigger_type[1] = THROTTLE_ACTIVE, \
 144         .trigger_type[2] = SW_TRIP, \
 145         .trigger_type[3] = HW_TRIP, \
 146         .max_trigger_level = 4, \
 147         .gain = 8, \
 148         .reference_voltage = 16, \
 149         .noise_cancel_mode = 4, \
 150         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 151         .efuse_value = 55, \
 152         .min_efuse_value = 40, \
 153         .max_efuse_value = 100, \
 154         .first_point_trim = 25, \
 155         .second_point_trim = 85, \
 156         .default_temp_offset = 50, \
 157         .freq_tab[0] = { \
 158                 .freq_clip_max = 1400 * 1000, \
 159                 .temp_level = 70, \
 160         }, \
 161         .freq_tab[1] = { \
 162                 .freq_clip_max = 400 * 1000, \
 163                 .temp_level = 95, \
 164         }, \
 165         .freq_tab_count = 2, \
 166         .registers = &exynos4412_tmu_registers, \
 167         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
 168                         TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
 169                         TMU_SUPPORT_EMUL_TIME)
 170 #endif
 171
 172 #if defined(CONFIG_SOC_EXYNOS4412)
 173 struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
 174         .tmu_data = {
 175                 {
 176                         EXYNOS4412_TMU_DATA,
 177                         .type = SOC_ARCH_EXYNOS4412,
 178                         .test_mux = EXYNOS4412_MUX_ADDR_VALUE,
 179                 },
 180         },
 181         .tmu_count = 1,
 182 };
 183 #endif
 184
 185 #if defined(CONFIG_SOC_EXYNOS5250)
 186 struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 187         .tmu_data = {
 188                 {
 189                         EXYNOS4412_TMU_DATA,
 190                         .type = SOC_ARCH_EXYNOS5250,
 191                 },
 192         },
 193         .tmu_count = 1,
 194 };
 195 #endif
 196
 197 #if defined(CONFIG_SOC_EXYNOS5260)
 198 static const struct exynos_tmu_registers exynos5260_tmu_registers = {
 199         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
 200         .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
 201         .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
 202         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 203         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL1,
 204         .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
 205         .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
 206         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 207         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 208         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 209         .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
 210         .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
 211         .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
 212         .tmu_status = EXYNOS_TMU_REG_STATUS,
 213         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 214         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 215         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 216         .tmu_inten = EXYNOS5260_TMU_REG_INTEN,
 217         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 218         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 219         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 220         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 221         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 222         .tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT,
 223         .tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR,
 224         .intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
 225         .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
 226         .intclr_rise_mask = EXYNOS5260_TMU_RISE_INT_MASK,
 227         .intclr_fall_mask = EXYNOS5260_TMU_FALL_INT_MASK,
 228         .emul_con = EXYNOS5260_EMUL_CON,
 229         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 230         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 231         .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
 232 };
 233
 234 #define __EXYNOS5260_TMU_DATA   \
 235         .threshold_falling = 10, \
 236         .trigger_levels[0] = 85, \
 237         .trigger_levels[1] = 103, \
 238         .trigger_levels[2] = 110, \
 239         .trigger_levels[3] = 120, \
 240         .trigger_enable[0] = true, \
 241         .trigger_enable[1] = true, \
 242         .trigger_enable[2] = true, \
 243         .trigger_enable[3] = false, \
 244         .trigger_type[0] = THROTTLE_ACTIVE, \
 245         .trigger_type[1] = THROTTLE_ACTIVE, \
 246         .trigger_type[2] = SW_TRIP, \
 247         .trigger_type[3] = HW_TRIP, \
 248         .max_trigger_level = 4, \
 249         .gain = 8, \
 250         .reference_voltage = 16, \
 251         .noise_cancel_mode = 4, \
 252         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 253         .efuse_value = 55, \
 254         .min_efuse_value = 40, \
 255         .max_efuse_value = 100, \
 256         .first_point_trim = 25, \
 257         .second_point_trim = 85, \
 258         .default_temp_offset = 50, \
 259         .freq_tab[0] = { \
 260                 .freq_clip_max = 800 * 1000, \
 261                 .temp_level = 85, \
 262         }, \
 263         .freq_tab[1] = { \
 264                 .freq_clip_max = 200 * 1000, \
 265                 .temp_level = 103, \
 266         }, \
 267         .freq_tab_count = 2, \
 268         .registers = &exynos5260_tmu_registers, \
 269
 270 #define EXYNOS5260_TMU_DATA \
 271         __EXYNOS5260_TMU_DATA \
 272         .type = SOC_ARCH_EXYNOS5260, \
 273         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
 274                         TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
 275                         TMU_SUPPORT_EMUL_TIME)
 276
 277 struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
 278         .tmu_data = {
 279                 { EXYNOS5260_TMU_DATA },
 280                 { EXYNOS5260_TMU_DATA },
 281                 { EXYNOS5260_TMU_DATA },
 282                 { EXYNOS5260_TMU_DATA },
 283                 { EXYNOS5260_TMU_DATA },
 284         },
 285         .tmu_count = 5,
 286 };
 287 #endif
 288
 289 #if defined(CONFIG_SOC_EXYNOS5420)
 290 static const struct exynos_tmu_registers exynos5420_tmu_registers = {
 291         .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
 292         .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
 293         .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
 294         .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
 295         .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
 296         .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
 297         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 298         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 299         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 300         .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
 301         .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
 302         .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
 303         .tmu_status = EXYNOS_TMU_REG_STATUS,
 304         .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
 305         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
 306         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
 307         .tmu_inten = EXYNOS_TMU_REG_INTEN,
 308         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 309         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 310         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 311         /* INTEN_RISE3 Not availble in exynos5420 */
 312         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 313         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 314         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 315         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
 316         .intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
 317         .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
 318         .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
 319         .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
 320         .emul_con = EXYNOS_EMUL_CON,
 321         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 322         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
 323         .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
 324 };
 325
 326 #define __EXYNOS5420_TMU_DATA   \
 327         .threshold_falling = 10, \
 328         .trigger_levels[0] = 85, \
 329         .trigger_levels[1] = 103, \
 330         .trigger_levels[2] = 110, \
 331         .trigger_levels[3] = 120, \
 332         .trigger_enable[0] = true, \
 333         .trigger_enable[1] = true, \
 334         .trigger_enable[2] = true, \
 335         .trigger_enable[3] = false, \
 336         .trigger_type[0] = THROTTLE_ACTIVE, \
 337         .trigger_type[1] = THROTTLE_ACTIVE, \
 338         .trigger_type[2] = SW_TRIP, \
 339         .trigger_type[3] = HW_TRIP, \
 340         .max_trigger_level = 4, \
 341         .gain = 8, \
 342         .reference_voltage = 16, \
 343         .noise_cancel_mode = 4, \
 344         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 345         .efuse_value = 55, \
 346         .min_efuse_value = 40, \
 347         .max_efuse_value = 100, \
 348         .first_point_trim = 25, \
 349         .second_point_trim = 85, \
 350         .default_temp_offset = 50, \
 351         .freq_tab[0] = { \
 352                 .freq_clip_max = 800 * 1000, \
 353                 .temp_level = 85, \
 354         }, \
 355         .freq_tab[1] = { \
 356                 .freq_clip_max = 200 * 1000, \
 357                 .temp_level = 103, \
 358         }, \
 359         .freq_tab_count = 2, \
 360         .registers = &exynos5420_tmu_registers, \
 361
 362 #define EXYNOS5420_TMU_DATA \
 363         __EXYNOS5420_TMU_DATA \
 364         .type = SOC_ARCH_EXYNOS5250, \
 365         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
 366                         TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
 367                         TMU_SUPPORT_EMUL_TIME)
 368
 369 #define EXYNOS5420_TMU_DATA_SHARED \
 370         __EXYNOS5420_TMU_DATA \
 371         .type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
 372         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
 373                         TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
 374                         TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
 375
 376 struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
 377         .tmu_data = {
 378                 { EXYNOS5420_TMU_DATA },
 379                 { EXYNOS5420_TMU_DATA },
 380                 { EXYNOS5420_TMU_DATA_SHARED },
 381                 { EXYNOS5420_TMU_DATA_SHARED },
 382                 { EXYNOS5420_TMU_DATA_SHARED },
 383         },
 384         .tmu_count = 5,
 385 };
 386 #endif
 387
 388 #if defined(CONFIG_SOC_EXYNOS5440)
 389 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 390         .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
 391         .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
 392         .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
 393         .tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL,
 394         .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
 395         .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
 396         .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
 397         .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
 398         .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
 399         .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
 400         .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
 401         .calib_mode_shift = EXYNOS_TMU_CALIB_MODE_SHIFT,
 402         .calib_mode_mask = EXYNOS_TMU_CALIB_MODE_MASK,
 403         .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
 404         .tmu_status = EXYNOS5440_TMU_S0_7_STATUS,
 405         .tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
 406         .threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
 407         .threshold_th1 = EXYNOS5440_TMU_S0_7_TH1,
 408         .threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
 409         .threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
 410         .tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
 411         .inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
 412         .inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
 413         .inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
 414         .inten_rise3_shift = EXYNOS5440_TMU_INTEN_RISE3_SHIFT,
 415         .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 416         .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 417         .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
 418         .intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
 419         .intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
 420         .intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
 421         .intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
 422         .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
 423         .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 424         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 425         .tmu_pmin = EXYNOS5440_TMU_PMIN,
 426 };
 427
 428 #define EXYNOS5440_TMU_DATA \
 429         .trigger_levels[0] = 100, \
 430         .trigger_levels[4] = 105, \
 431         .trigger_enable[0] = 1, \
 432         .trigger_type[0] = SW_TRIP, \
 433         .trigger_type[4] = HW_TRIP, \
 434         .max_trigger_level = 5, \
 435         .gain = 5, \
 436         .reference_voltage = 16, \
 437         .noise_cancel_mode = 4, \
 438         .cal_type = TYPE_ONE_POINT_TRIMMING, \
 439         .cal_mode = 0, \
 440         .efuse_value = 0x5b2d, \
 441         .min_efuse_value = 16, \
 442         .max_efuse_value = 76, \
 443         .first_point_trim = 25, \
 444         .second_point_trim = 70, \
 445         .default_temp_offset = 25, \
 446         .type = SOC_ARCH_EXYNOS5440, \
 447         .registers = &exynos5440_tmu_registers, \
 448         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
 449                         TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 450
 451 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 452         .tmu_data = {
 453                 { EXYNOS5440_TMU_DATA } ,
 454                 { EXYNOS5440_TMU_DATA } ,
 455                 { EXYNOS5440_TMU_DATA } ,
 456         },
 457         .tmu_count = 3,
 458 };
 459 #endif