2 * exynos_tmu.h - Samsung EXYNOS TMU (Thermal Management Unit)
4 * Copyright (C) 2011 Samsung Electronics
5 * Donggeun Kim <dg77.kim@samsung.com>
6 * Amit Daniel Kachhap <amit.daniel@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/cpu_cooling.h>
27 #include "exynos_thermal_common.h"
29 enum calibration_type {
30 TYPE_ONE_POINT_TRIMMING,
31 TYPE_ONE_POINT_TRIMMING_25,
32 TYPE_ONE_POINT_TRIMMING_85,
33 TYPE_TWO_POINT_TRIMMING,
37 enum calibration_mode {
43 SOC_ARCH_EXYNOS3250 = 1,
48 SOC_ARCH_EXYNOS5420_TRIMINFO,
53 * EXYNOS TMU supported features.
54 * TMU_SUPPORT_EMULATION - This features is used to set user defined
55 * temperature to the TMU controller.
56 * TMU_SUPPORT_MULTI_INST - This features denotes that the soc
57 * has many instances of TMU.
58 * TMU_SUPPORT_TRIM_RELOAD - This features shows that trimming can
60 * TMU_SUPPORT_FALLING_TRIP - This features shows that interrupt can
61 * be registered for falling trips also.
62 * TMU_SUPPORT_READY_STATUS - This feature tells that the TMU current
63 * state(active/idle) can be checked.
64 * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
66 * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
67 * sensors shares some common registers.
68 * TMU_SUPPORT - macro to compare the above features with the supplied.
70 #define TMU_SUPPORT_EMULATION BIT(0)
71 #define TMU_SUPPORT_MULTI_INST BIT(1)
72 #define TMU_SUPPORT_TRIM_RELOAD BIT(2)
73 #define TMU_SUPPORT_FALLING_TRIP BIT(3)
74 #define TMU_SUPPORT_READY_STATUS BIT(4)
75 #define TMU_SUPPORT_EMUL_TIME BIT(5)
76 #define TMU_SUPPORT_ADDRESS_MULTIPLE BIT(6)
78 #define TMU_SUPPORTS(a, b) (a->features & TMU_SUPPORT_ ## b)
81 * struct exynos_tmu_register - register descriptors to access registers and
82 * bitfields. The register validity, offsets and bitfield values may vary
83 * slightly across different exynos SOC's.
84 * @triminfo_data: register containing 2 pont trimming data
85 * @triminfo_25_shift: shift bit of the 25 C trim value in triminfo_data reg.
86 * @triminfo_85_shift: shift bit of the 85 C trim value in triminfo_data reg.
87 * @triminfo_ctrl: trim info controller register.
88 * @triminfo_reload_shift: shift of triminfo reload enable bit in triminfo_ctrl
90 * @tmu_ctrl: TMU main controller register.
91 * @test_mux_addr_shift: shift bits of test mux address.
92 * @buf_vref_sel_shift: shift bits of reference voltage in tmu_ctrl register.
93 * @buf_vref_sel_mask: mask bits of reference voltage in tmu_ctrl register.
94 * @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register.
95 * @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register.
96 * @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register.
97 * @buf_slope_sel_shift: shift bits of amplifier gain value in tmu_ctrl
99 * @buf_slope_sel_mask: mask bits of amplifier gain value in tmu_ctrl register.
100 * @calib_mode_shift: shift bits of calibration mode value in tmu_ctrl
102 * @calib_mode_mask: mask bits of calibration mode value in tmu_ctrl
104 * @therm_trip_tq_en_shift: shift bits of thermal trip enable by TQ pin in
106 * @core_en_shift: shift bits of TMU core enable bit in tmu_ctrl register.
107 * @tmu_status: register drescribing the TMU status.
108 * @tmu_cur_temp: register containing the current temperature of the TMU.
109 * @tmu_cur_temp_shift: shift bits of current temp value in tmu_cur_temp
111 * @threshold_temp: register containing the base threshold level.
112 * @threshold_th0: Register containing first set of rising levels.
113 * @threshold_th0_l0_shift: shift bits of level0 threshold temperature.
114 * @threshold_th0_l1_shift: shift bits of level1 threshold temperature.
115 * @threshold_th0_l2_shift: shift bits of level2 threshold temperature.
116 * @threshold_th0_l3_shift: shift bits of level3 threshold temperature.
117 * @threshold_th1: Register containing second set of rising levels.
118 * @threshold_th1_l0_shift: shift bits of level0 threshold temperature.
119 * @threshold_th1_l1_shift: shift bits of level1 threshold temperature.
120 * @threshold_th1_l2_shift: shift bits of level2 threshold temperature.
121 * @threshold_th1_l3_shift: shift bits of level3 threshold temperature.
122 * @threshold_th2: Register containing third set of rising levels.
123 * @threshold_th2_l0_shift: shift bits of level0 threshold temperature.
124 * @threshold_th3: Register containing fourth set of rising levels.
125 * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
126 * @tmu_inten: register containing the different threshold interrupt
128 * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
129 * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
130 * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
131 * @inten_rise3_shift: shift bits of rising 3 interrupt bits.
132 * @inten_fall0_shift: shift bits of falling 0 interrupt bits.
133 * @inten_fall1_shift: shift bits of falling 1 interrupt bits.
134 * @inten_fall2_shift: shift bits of falling 2 interrupt bits.
135 * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
136 * @tmu_intstat: Register containing the interrupt status values.
137 * @tmu_intclear: Register for clearing the raised interrupt status.
138 * @intclr_fall_shift: shift bits for interrupt clear fall 0
139 * @intclr_rise_shift: shift bits of all rising interrupt bits.
140 * @intclr_rise_mask: mask bits of all rising interrupt bits.
141 * @intclr_fall_mask: mask bits of all rising interrupt bits.
142 * @emul_con: TMU emulation controller register.
143 * @emul_temp_shift: shift bits of emulation temperature.
144 * @emul_time_shift: shift bits of emulation time.
145 * @emul_time_mask: mask bits of emulation time.
146 * @tmu_irqstatus: register to find which TMU generated interrupts.
147 * @tmu_pmin: register to get/set the Pmin value.
149 struct exynos_tmu_registers {
151 u32 triminfo_25_shift;
152 u32 triminfo_85_shift;
156 u32 triminfo_reload_shift;
159 u32 test_mux_addr_shift;
160 u32 buf_vref_sel_shift;
161 u32 buf_vref_sel_mask;
162 u32 therm_trip_mode_shift;
163 u32 therm_trip_mode_mask;
164 u32 therm_trip_en_shift;
165 u32 buf_slope_sel_shift;
166 u32 buf_slope_sel_mask;
167 u32 calib_mode_shift;
169 u32 therm_trip_tq_en_shift;
175 u32 tmu_cur_temp_shift;
180 u32 threshold_th0_l0_shift;
181 u32 threshold_th0_l1_shift;
182 u32 threshold_th0_l2_shift;
183 u32 threshold_th0_l3_shift;
186 u32 threshold_th1_l0_shift;
187 u32 threshold_th1_l1_shift;
188 u32 threshold_th1_l2_shift;
189 u32 threshold_th1_l3_shift;
192 u32 threshold_th2_l0_shift;
195 u32 threshold_th3_l0_shift;
198 u32 inten_rise0_shift;
199 u32 inten_rise1_shift;
200 u32 inten_rise2_shift;
201 u32 inten_rise3_shift;
202 u32 inten_fall0_shift;
203 u32 inten_fall1_shift;
204 u32 inten_fall2_shift;
205 u32 inten_fall3_shift;
210 u32 intclr_fall_shift;
211 u32 intclr_rise_shift;
212 u32 intclr_fall_mask;
213 u32 intclr_rise_mask;
225 * struct exynos_tmu_platform_data
226 * @threshold: basic temperature for generating interrupt
227 * 25 <= threshold <= 125 [unit: degree Celsius]
228 * @threshold_falling: differntial value for setting threshold
229 * of temperature falling interrupt.
230 * @trigger_levels: array for each interrupt levels
231 * [unit: degree Celsius]
232 * 0: temperature for trigger_level0 interrupt
233 * condition for trigger_level0 interrupt:
234 * current temperature > threshold + trigger_levels[0]
235 * 1: temperature for trigger_level1 interrupt
236 * condition for trigger_level1 interrupt:
237 * current temperature > threshold + trigger_levels[1]
238 * 2: temperature for trigger_level2 interrupt
239 * condition for trigger_level2 interrupt:
240 * current temperature > threshold + trigger_levels[2]
241 * 3: temperature for trigger_level3 interrupt
242 * condition for trigger_level3 interrupt:
243 * current temperature > threshold + trigger_levels[3]
244 * @trigger_type: defines the type of trigger. Possible values are,
245 * THROTTLE_ACTIVE trigger type
246 * THROTTLE_PASSIVE trigger type
247 * SW_TRIP trigger type
249 * @trigger_enable[]: array to denote which trigger levels are enabled.
250 * 1 = enable trigger_level[] interrupt,
251 * 0 = disable trigger_level[] interrupt
252 * @max_trigger_level: max trigger level supported by the TMU
253 * @gain: gain of amplifier in the positive-TC generator block
255 * @reference_voltage: reference voltage of amplifier
256 * in the positive-TC generator block
257 * 0 <= reference_voltage <= 31
258 * @noise_cancel_mode: noise cancellation mode
259 * 000, 100, 101, 110 and 111 can be different modes
260 * @type: determines the type of SOC
261 * @efuse_value: platform defined fuse value
262 * @min_efuse_value: minimum valid trimming data
263 * @max_efuse_value: maximum valid trimming data
264 * @first_point_trim: temp value of the first point trimming
265 * @second_point_trim: temp value of the second point trimming
266 * @default_temp_offset: default temperature offset in case of no trimming
267 * @test_mux; information if SoC supports test MUX
268 * @cal_type: calibration type for temperature
269 * @cal_mode: calibration mode for temperature
270 * @freq_clip_table: Table representing frequency reduction percentage.
271 * @freq_tab_count: Count of the above table as frequency reduction may
272 * applicable to only some of the trigger levels.
273 * @registers: Pointer to structure containing all the TMU controller registers
274 * and bitfields shifts and masks.
275 * @features: a bitfield value indicating the features supported in SOC like
276 * emulation, multi instance etc
278 * This structure is required for configuration of exynos_tmu driver.
280 struct exynos_tmu_platform_data {
282 u8 threshold_falling;
283 u8 trigger_levels[MAX_TRIP_COUNT];
284 enum trigger_type trigger_type[MAX_TRIP_COUNT];
285 bool trigger_enable[MAX_TRIP_COUNT];
286 u8 max_trigger_level;
288 u8 reference_voltage;
289 u8 noise_cancel_mode;
295 u8 second_point_trim;
296 u8 default_temp_offset;
299 enum calibration_type cal_type;
300 enum calibration_mode cal_mode;
302 struct freq_clip_table freq_tab[4];
303 unsigned int freq_tab_count;
304 const struct exynos_tmu_registers *registers;
305 unsigned int features;
309 * struct exynos_tmu_init_data
310 * @tmu_count: number of TMU instances.
311 * @tmu_data: platform data of all TMU instances.
312 * This structure is required to store data for multi-instance exynos tmu
315 struct exynos_tmu_init_data {
317 struct exynos_tmu_platform_data tmu_data[];
320 #endif /* _EXYNOS_TMU_H */