2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
4 * Copyright (C) 2014 Samsung Electronics
5 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
6 * Lukasz Majewski <l.majewski@samsung.com>
8 * Copyright (C) 2011 Samsung Electronics
9 * Donggeun Kim <dg77.kim@samsung.com>
10 * Amit Daniel Kachhap <amit.kachhap@linaro.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/clk.h>
30 #include <linux/interrupt.h>
31 #include <linux/module.h>
33 #include <linux/of_address.h>
34 #include <linux/of_irq.h>
35 #include <linux/platform_device.h>
36 #include <linux/regulator/consumer.h>
38 #include "exynos_tmu.h"
39 #include "../thermal_core.h"
41 /* Exynos generic registers */
42 #define EXYNOS_TMU_REG_TRIMINFO 0x0
43 #define EXYNOS_TMU_REG_CONTROL 0x20
44 #define EXYNOS_TMU_REG_STATUS 0x28
45 #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
46 #define EXYNOS_TMU_REG_INTEN 0x70
47 #define EXYNOS_TMU_REG_INTSTAT 0x74
48 #define EXYNOS_TMU_REG_INTCLEAR 0x78
50 #define EXYNOS_TMU_TEMP_MASK 0xff
51 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
52 #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f
53 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf
54 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8
55 #define EXYNOS_TMU_CORE_EN_SHIFT 0
57 /* Exynos3250 specific registers */
58 #define EXYNOS_TMU_TRIMINFO_CON1 0x10
60 /* Exynos4210 specific registers */
61 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
62 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
64 /* Exynos5250, Exynos4412, Exynos3250 specific registers */
65 #define EXYNOS_TMU_TRIMINFO_CON2 0x14
66 #define EXYNOS_THD_TEMP_RISE 0x50
67 #define EXYNOS_THD_TEMP_FALL 0x54
68 #define EXYNOS_EMUL_CON 0x80
70 #define EXYNOS_TRIMINFO_RELOAD_ENABLE 1
71 #define EXYNOS_TRIMINFO_25_SHIFT 0
72 #define EXYNOS_TRIMINFO_85_SHIFT 8
73 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13
74 #define EXYNOS_TMU_TRIP_MODE_MASK 0x7
75 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
77 #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0
78 #define EXYNOS_TMU_INTEN_RISE1_SHIFT 4
79 #define EXYNOS_TMU_INTEN_RISE2_SHIFT 8
80 #define EXYNOS_TMU_INTEN_RISE3_SHIFT 12
81 #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16
83 #define EXYNOS_EMUL_TIME 0x57F0
84 #define EXYNOS_EMUL_TIME_MASK 0xffff
85 #define EXYNOS_EMUL_TIME_SHIFT 16
86 #define EXYNOS_EMUL_DATA_SHIFT 8
87 #define EXYNOS_EMUL_DATA_MASK 0xFF
88 #define EXYNOS_EMUL_ENABLE 0x1
90 /* Exynos5260 specific */
91 #define EXYNOS5260_TMU_REG_INTEN 0xC0
92 #define EXYNOS5260_TMU_REG_INTSTAT 0xC4
93 #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8
94 #define EXYNOS5260_EMUL_CON 0x100
96 /* Exynos4412 specific */
97 #define EXYNOS4412_MUX_ADDR_VALUE 6
98 #define EXYNOS4412_MUX_ADDR_SHIFT 20
100 /*exynos5440 specific registers*/
101 #define EXYNOS5440_TMU_S0_7_TRIM 0x000
102 #define EXYNOS5440_TMU_S0_7_CTRL 0x020
103 #define EXYNOS5440_TMU_S0_7_DEBUG 0x040
104 #define EXYNOS5440_TMU_S0_7_TEMP 0x0f0
105 #define EXYNOS5440_TMU_S0_7_TH0 0x110
106 #define EXYNOS5440_TMU_S0_7_TH1 0x130
107 #define EXYNOS5440_TMU_S0_7_TH2 0x150
108 #define EXYNOS5440_TMU_S0_7_IRQEN 0x210
109 #define EXYNOS5440_TMU_S0_7_IRQ 0x230
110 /* exynos5440 common registers */
111 #define EXYNOS5440_TMU_IRQ_STATUS 0x000
112 #define EXYNOS5440_TMU_PMIN 0x004
114 #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0
115 #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1
116 #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2
117 #define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3
118 #define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4
119 #define EXYNOS5440_TMU_TH_RISE4_SHIFT 24
120 #define EXYNOS5440_EFUSE_SWAP_OFFSET 8
122 /* Exynos7 specific registers */
123 #define EXYNOS7_THD_TEMP_RISE7_6 0x50
124 #define EXYNOS7_THD_TEMP_FALL7_6 0x60
125 #define EXYNOS7_TMU_REG_INTEN 0x110
126 #define EXYNOS7_TMU_REG_INTPEND 0x118
127 #define EXYNOS7_TMU_REG_EMUL_CON 0x160
129 #define EXYNOS7_TMU_TEMP_MASK 0x1ff
130 #define EXYNOS7_PD_DET_EN_SHIFT 23
131 #define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0
132 #define EXYNOS7_TMU_INTEN_RISE1_SHIFT 1
133 #define EXYNOS7_TMU_INTEN_RISE2_SHIFT 2
134 #define EXYNOS7_TMU_INTEN_RISE3_SHIFT 3
135 #define EXYNOS7_TMU_INTEN_RISE4_SHIFT 4
136 #define EXYNOS7_TMU_INTEN_RISE5_SHIFT 5
137 #define EXYNOS7_TMU_INTEN_RISE6_SHIFT 6
138 #define EXYNOS7_TMU_INTEN_RISE7_SHIFT 7
139 #define EXYNOS7_EMUL_DATA_SHIFT 7
140 #define EXYNOS7_EMUL_DATA_MASK 0x1ff
142 #define MCELSIUS 1000
144 * struct exynos_tmu_data : A structure to hold the private data of the TMU
146 * @id: identifier of the one instance of the TMU controller.
147 * @pdata: pointer to the tmu platform/configuration data
148 * @base: base address of the single instance of the TMU controller.
149 * @base_second: base address of the common registers of the TMU controller.
150 * @irq: irq number of the TMU controller.
151 * @soc: id of the SOC type.
152 * @irq_work: pointer to the irq work structure.
153 * @lock: lock to implement synchronization.
154 * @clk: pointer to the clock structure.
155 * @clk_sec: pointer to the clock structure for accessing the base_second.
156 * @sclk: pointer to the clock structure for accessing the tmu special clk.
157 * @temp_error1: fused value of the first point trim.
158 * @temp_error2: fused value of the second point trim.
159 * @regulator: pointer to the TMU regulator structure.
160 * @reg_conf: pointer to structure to register with core thermal.
161 * @tmu_initialize: SoC specific TMU initialization method
162 * @tmu_control: SoC specific TMU control method
163 * @tmu_read: SoC specific TMU temperature read method
164 * @tmu_set_emulation: SoC specific TMU emulation setting method
165 * @tmu_clear_irqs: SoC specific TMU interrupts clearing method
167 struct exynos_tmu_data {
169 struct exynos_tmu_platform_data *pdata;
171 void __iomem *base_second;
174 struct work_struct irq_work;
176 struct clk *clk, *clk_sec, *sclk;
177 u16 temp_error1, temp_error2;
178 struct regulator *regulator;
179 struct thermal_zone_device *tzd;
181 int (*tmu_initialize)(struct platform_device *pdev);
182 void (*tmu_control)(struct platform_device *pdev, bool on);
183 int (*tmu_read)(struct exynos_tmu_data *data);
184 void (*tmu_set_emulation)(struct exynos_tmu_data *data,
186 void (*tmu_clear_irqs)(struct exynos_tmu_data *data);
189 static void exynos_report_trigger(struct exynos_tmu_data *p)
191 char data[10], *envp[] = { data, NULL };
192 struct thermal_zone_device *tz = p->tzd;
197 pr_err("No thermal zone device defined\n");
201 thermal_zone_device_update(tz);
203 mutex_lock(&tz->lock);
204 /* Find the level for which trip happened */
205 for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
206 tz->ops->get_trip_temp(tz, i, &temp);
207 if (tz->last_temperature < temp)
211 snprintf(data, sizeof(data), "%u", i);
212 kobject_uevent_env(&tz->device.kobj, KOBJ_CHANGE, envp);
213 mutex_unlock(&tz->lock);
217 * TMU treats temperature as a mapped temperature code.
218 * The temperature is converted differently depending on the calibration type.
220 static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
222 struct exynos_tmu_platform_data *pdata = data->pdata;
225 switch (pdata->cal_type) {
226 case TYPE_TWO_POINT_TRIMMING:
227 temp_code = (temp - pdata->first_point_trim) *
228 (data->temp_error2 - data->temp_error1) /
229 (pdata->second_point_trim - pdata->first_point_trim) +
232 case TYPE_ONE_POINT_TRIMMING:
233 temp_code = temp + data->temp_error1 - pdata->first_point_trim;
236 temp_code = temp + pdata->default_temp_offset;
244 * Calculate a temperature value from a temperature code.
245 * The unit of the temperature is degree Celsius.
247 static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code)
249 struct exynos_tmu_platform_data *pdata = data->pdata;
252 switch (pdata->cal_type) {
253 case TYPE_TWO_POINT_TRIMMING:
254 temp = (temp_code - data->temp_error1) *
255 (pdata->second_point_trim - pdata->first_point_trim) /
256 (data->temp_error2 - data->temp_error1) +
257 pdata->first_point_trim;
259 case TYPE_ONE_POINT_TRIMMING:
260 temp = temp_code - data->temp_error1 + pdata->first_point_trim;
263 temp = temp_code - pdata->default_temp_offset;
270 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
272 struct exynos_tmu_platform_data *pdata = data->pdata;
274 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
275 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
276 EXYNOS_TMU_TEMP_MASK);
278 if (!data->temp_error1 ||
279 (pdata->min_efuse_value > data->temp_error1) ||
280 (data->temp_error1 > pdata->max_efuse_value))
281 data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
283 if (!data->temp_error2)
285 (pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
286 EXYNOS_TMU_TEMP_MASK;
289 static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling)
291 struct thermal_zone_device *tz = data->tzd;
292 const struct thermal_trip * const trips =
293 of_thermal_get_trip_points(tz);
298 pr_err("%s: Cannot get trip points from of-thermal.c!\n",
303 for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
304 if (trips[i].type == THERMAL_TRIP_CRITICAL)
307 temp = trips[i].temperature / MCELSIUS;
309 temp -= (trips[i].hysteresis / MCELSIUS);
311 threshold &= ~(0xff << 8 * i);
313 threshold |= temp_to_code(data, temp) << 8 * i;
319 static int exynos_tmu_initialize(struct platform_device *pdev)
321 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
324 mutex_lock(&data->lock);
325 clk_enable(data->clk);
326 if (!IS_ERR(data->clk_sec))
327 clk_enable(data->clk_sec);
328 ret = data->tmu_initialize(pdev);
329 clk_disable(data->clk);
330 mutex_unlock(&data->lock);
331 if (!IS_ERR(data->clk_sec))
332 clk_disable(data->clk_sec);
337 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con)
339 struct exynos_tmu_platform_data *pdata = data->pdata;
341 if (data->soc == SOC_ARCH_EXYNOS4412 ||
342 data->soc == SOC_ARCH_EXYNOS3250)
343 con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT);
345 con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT);
346 con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
348 con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
349 con |= (pdata->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
351 if (pdata->noise_cancel_mode) {
352 con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT);
353 con |= (pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT);
359 static void exynos_tmu_control(struct platform_device *pdev, bool on)
361 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
363 mutex_lock(&data->lock);
364 clk_enable(data->clk);
365 data->tmu_control(pdev, on);
366 clk_disable(data->clk);
367 mutex_unlock(&data->lock);
370 static int exynos4210_tmu_initialize(struct platform_device *pdev)
372 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
373 struct thermal_zone_device *tz = data->tzd;
374 const struct thermal_trip * const trips =
375 of_thermal_get_trip_points(tz);
376 int ret = 0, threshold_code, i;
377 unsigned long reference, temp;
381 pr_err("%s: Cannot get trip points from of-thermal.c!\n",
387 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
393 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO));
395 /* Write temperature code for threshold */
396 reference = trips[0].temperature / MCELSIUS;
397 threshold_code = temp_to_code(data, reference);
398 if (threshold_code < 0) {
399 ret = threshold_code;
402 writeb(threshold_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
404 for (i = 0; i < of_thermal_get_ntrips(tz); i++) {
405 temp = trips[i].temperature / MCELSIUS;
406 writeb(temp - reference, data->base +
407 EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
410 data->tmu_clear_irqs(data);
415 static int exynos4412_tmu_initialize(struct platform_device *pdev)
417 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
418 const struct thermal_trip * const trips =
419 of_thermal_get_trip_points(data->tzd);
420 unsigned int status, trim_info, con, ctrl, rising_threshold;
421 int ret = 0, threshold_code, i;
422 unsigned long crit_temp = 0;
424 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
430 if (data->soc == SOC_ARCH_EXYNOS3250 ||
431 data->soc == SOC_ARCH_EXYNOS4412 ||
432 data->soc == SOC_ARCH_EXYNOS5250) {
433 if (data->soc == SOC_ARCH_EXYNOS3250) {
434 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1);
435 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
436 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1);
438 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2);
439 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
440 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2);
443 /* On exynos5420 the triminfo register is in the shared space */
444 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
445 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO);
447 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
449 sanitize_temp_error(data, trim_info);
451 /* Write temperature code for rising and falling threshold */
452 rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE);
453 rising_threshold = get_th_reg(data, rising_threshold, false);
454 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
455 writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL);
457 data->tmu_clear_irqs(data);
459 /* if last threshold limit is also present */
460 for (i = 0; i < of_thermal_get_ntrips(data->tzd); i++) {
461 if (trips[i].type == THERMAL_TRIP_CRITICAL) {
462 crit_temp = trips[i].temperature;
467 if (i == of_thermal_get_ntrips(data->tzd)) {
468 pr_err("%s: No CRITICAL trip point defined at of-thermal.c!\n",
474 threshold_code = temp_to_code(data, crit_temp / MCELSIUS);
475 /* 1-4 level to be assigned in th0 reg */
476 rising_threshold &= ~(0xff << 8 * i);
477 rising_threshold |= threshold_code << 8 * i;
478 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
479 con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
480 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
481 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
487 static int exynos5440_tmu_initialize(struct platform_device *pdev)
489 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
490 unsigned int trim_info = 0, con, rising_threshold;
491 int ret = 0, threshold_code;
492 unsigned long crit_temp = 0;
495 * For exynos5440 soc triminfo value is swapped between TMU0 and
496 * TMU2, so the below logic is needed.
500 trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET +
501 EXYNOS5440_TMU_S0_7_TRIM);
504 trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM);
507 trim_info = readl(data->base - EXYNOS5440_EFUSE_SWAP_OFFSET +
508 EXYNOS5440_TMU_S0_7_TRIM);
510 sanitize_temp_error(data, trim_info);
512 /* Write temperature code for rising and falling threshold */
513 rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0);
514 rising_threshold = get_th_reg(data, rising_threshold, false);
515 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0);
516 writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1);
518 data->tmu_clear_irqs(data);
520 /* if last threshold limit is also present */
521 if (!data->tzd->ops->get_crit_temp(data->tzd, &crit_temp)) {
522 threshold_code = temp_to_code(data, crit_temp / MCELSIUS);
523 /* 5th level to be assigned in th2 reg */
525 threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT;
526 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2);
527 con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL);
528 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
529 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
531 /* Clear the PMIN in the common TMU register */
533 writel(0, data->base_second + EXYNOS5440_TMU_PMIN);
537 static int exynos7_tmu_initialize(struct platform_device *pdev)
539 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
540 struct thermal_zone_device *tz = data->tzd;
541 struct exynos_tmu_platform_data *pdata = data->pdata;
542 unsigned int status, trim_info;
543 unsigned int rising_threshold = 0, falling_threshold = 0;
544 int ret = 0, threshold_code, i;
545 unsigned long temp, temp_hist;
546 unsigned int reg_off, bit_off;
548 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
554 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
556 data->temp_error1 = trim_info & EXYNOS7_TMU_TEMP_MASK;
557 if (!data->temp_error1 ||
558 (pdata->min_efuse_value > data->temp_error1) ||
559 (data->temp_error1 > pdata->max_efuse_value))
560 data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
562 /* Write temperature code for rising and falling threshold */
563 for (i = (of_thermal_get_ntrips(tz) - 1); i >= 0; i--) {
565 * On exynos7 there are 4 rising and 4 falling threshold
566 * registers (0x50-0x5c and 0x60-0x6c respectively). Each
567 * register holds the value of two threshold levels (at bit
568 * offsets 0 and 16). Based on the fact that there are atmost
569 * eight possible trigger levels, calculate the register and
570 * bit offsets where the threshold levels are to be written.
572 * e.g. EXYNOS7_THD_TEMP_RISE7_6 (0x50)
573 * [24:16] - Threshold level 7
574 * [8:0] - Threshold level 6
575 * e.g. EXYNOS7_THD_TEMP_RISE5_4 (0x54)
576 * [24:16] - Threshold level 5
577 * [8:0] - Threshold level 4
579 * and similarly for falling thresholds.
581 * Based on the above, calculate the register and bit offsets
582 * for rising/falling threshold levels and populate them.
584 reg_off = ((7 - i) / 2) * 4;
585 bit_off = ((8 - i) % 2);
587 tz->ops->get_trip_temp(tz, i, &temp);
590 tz->ops->get_trip_hyst(tz, i, &temp_hist);
591 temp_hist = temp - (temp_hist / MCELSIUS);
593 /* Set 9-bit temperature code for rising threshold levels */
594 threshold_code = temp_to_code(data, temp);
595 rising_threshold = readl(data->base +
596 EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
597 rising_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
598 rising_threshold |= threshold_code << (16 * bit_off);
599 writel(rising_threshold,
600 data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off);
602 /* Set 9-bit temperature code for falling threshold levels */
603 threshold_code = temp_to_code(data, temp_hist);
604 falling_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off));
605 falling_threshold |= threshold_code << (16 * bit_off);
606 writel(falling_threshold,
607 data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off);
610 data->tmu_clear_irqs(data);
615 static void exynos4210_tmu_control(struct platform_device *pdev, bool on)
617 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
618 struct thermal_zone_device *tz = data->tzd;
619 unsigned int con, interrupt_en;
621 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
624 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
626 (of_thermal_is_trip_valid(tz, 3)
627 << EXYNOS_TMU_INTEN_RISE3_SHIFT) |
628 (of_thermal_is_trip_valid(tz, 2)
629 << EXYNOS_TMU_INTEN_RISE2_SHIFT) |
630 (of_thermal_is_trip_valid(tz, 1)
631 << EXYNOS_TMU_INTEN_RISE1_SHIFT) |
632 (of_thermal_is_trip_valid(tz, 0)
633 << EXYNOS_TMU_INTEN_RISE0_SHIFT);
635 if (data->soc != SOC_ARCH_EXYNOS4210)
637 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
639 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
640 interrupt_en = 0; /* Disable all interrupts */
642 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
643 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
646 static void exynos5440_tmu_control(struct platform_device *pdev, bool on)
648 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
649 struct thermal_zone_device *tz = data->tzd;
650 unsigned int con, interrupt_en;
652 con = get_con_reg(data, readl(data->base + EXYNOS5440_TMU_S0_7_CTRL));
655 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
657 (of_thermal_is_trip_valid(tz, 3)
658 << EXYNOS5440_TMU_INTEN_RISE3_SHIFT) |
659 (of_thermal_is_trip_valid(tz, 2)
660 << EXYNOS5440_TMU_INTEN_RISE2_SHIFT) |
661 (of_thermal_is_trip_valid(tz, 1)
662 << EXYNOS5440_TMU_INTEN_RISE1_SHIFT) |
663 (of_thermal_is_trip_valid(tz, 0)
664 << EXYNOS5440_TMU_INTEN_RISE0_SHIFT);
666 interrupt_en << EXYNOS5440_TMU_INTEN_FALL0_SHIFT;
668 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
669 interrupt_en = 0; /* Disable all interrupts */
671 writel(interrupt_en, data->base + EXYNOS5440_TMU_S0_7_IRQEN);
672 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
675 static void exynos7_tmu_control(struct platform_device *pdev, bool on)
677 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
678 struct thermal_zone_device *tz = data->tzd;
679 unsigned int con, interrupt_en;
681 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
684 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
686 (of_thermal_is_trip_valid(tz, 7)
687 << EXYNOS7_TMU_INTEN_RISE7_SHIFT) |
688 (of_thermal_is_trip_valid(tz, 6)
689 << EXYNOS7_TMU_INTEN_RISE6_SHIFT) |
690 (of_thermal_is_trip_valid(tz, 5)
691 << EXYNOS7_TMU_INTEN_RISE5_SHIFT) |
692 (of_thermal_is_trip_valid(tz, 4)
693 << EXYNOS7_TMU_INTEN_RISE4_SHIFT) |
694 (of_thermal_is_trip_valid(tz, 3)
695 << EXYNOS7_TMU_INTEN_RISE3_SHIFT) |
696 (of_thermal_is_trip_valid(tz, 2)
697 << EXYNOS7_TMU_INTEN_RISE2_SHIFT) |
698 (of_thermal_is_trip_valid(tz, 1)
699 << EXYNOS7_TMU_INTEN_RISE1_SHIFT) |
700 (of_thermal_is_trip_valid(tz, 0)
701 << EXYNOS7_TMU_INTEN_RISE0_SHIFT);
704 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
706 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
707 interrupt_en = 0; /* Disable all interrupts */
709 con |= 1 << EXYNOS7_PD_DET_EN_SHIFT;
711 writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN);
712 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
715 static int exynos_get_temp(void *p, long *temp)
717 struct exynos_tmu_data *data = p;
719 if (!data || !data->tmu_read)
722 mutex_lock(&data->lock);
723 clk_enable(data->clk);
725 *temp = code_to_temp(data, data->tmu_read(data)) * MCELSIUS;
727 clk_disable(data->clk);
728 mutex_unlock(&data->lock);
733 #ifdef CONFIG_THERMAL_EMULATION
734 static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val,
740 if (data->soc != SOC_ARCH_EXYNOS5440) {
741 val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT);
742 val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT);
744 if (data->soc == SOC_ARCH_EXYNOS7) {
745 val &= ~(EXYNOS7_EMUL_DATA_MASK <<
746 EXYNOS7_EMUL_DATA_SHIFT);
747 val |= (temp_to_code(data, temp) <<
748 EXYNOS7_EMUL_DATA_SHIFT) |
751 val &= ~(EXYNOS_EMUL_DATA_MASK <<
752 EXYNOS_EMUL_DATA_SHIFT);
753 val |= (temp_to_code(data, temp) <<
754 EXYNOS_EMUL_DATA_SHIFT) |
758 val &= ~EXYNOS_EMUL_ENABLE;
764 static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data,
770 if (data->soc == SOC_ARCH_EXYNOS5260)
771 emul_con = EXYNOS5260_EMUL_CON;
772 else if (data->soc == SOC_ARCH_EXYNOS7)
773 emul_con = EXYNOS7_TMU_REG_EMUL_CON;
775 emul_con = EXYNOS_EMUL_CON;
777 val = readl(data->base + emul_con);
778 val = get_emul_con_reg(data, val, temp);
779 writel(val, data->base + emul_con);
782 static void exynos5440_tmu_set_emulation(struct exynos_tmu_data *data,
787 val = readl(data->base + EXYNOS5440_TMU_S0_7_DEBUG);
788 val = get_emul_con_reg(data, val, temp);
789 writel(val, data->base + EXYNOS5440_TMU_S0_7_DEBUG);
792 static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
794 struct exynos_tmu_data *data = drv_data;
797 if (data->soc == SOC_ARCH_EXYNOS4210)
800 if (temp && temp < MCELSIUS)
803 mutex_lock(&data->lock);
804 clk_enable(data->clk);
805 data->tmu_set_emulation(data, temp);
806 clk_disable(data->clk);
807 mutex_unlock(&data->lock);
813 #define exynos4412_tmu_set_emulation NULL
814 #define exynos5440_tmu_set_emulation NULL
815 static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
817 #endif /* CONFIG_THERMAL_EMULATION */
819 static int exynos4210_tmu_read(struct exynos_tmu_data *data)
821 int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
823 /* "temp_code" should range between 75 and 175 */
824 return (ret < 75 || ret > 175) ? -ENODATA : ret;
827 static int exynos4412_tmu_read(struct exynos_tmu_data *data)
829 return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
832 static int exynos5440_tmu_read(struct exynos_tmu_data *data)
834 return readb(data->base + EXYNOS5440_TMU_S0_7_TEMP);
837 static int exynos7_tmu_read(struct exynos_tmu_data *data)
839 return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) &
840 EXYNOS7_TMU_TEMP_MASK;
843 static void exynos_tmu_work(struct work_struct *work)
845 struct exynos_tmu_data *data = container_of(work,
846 struct exynos_tmu_data, irq_work);
847 unsigned int val_type;
849 if (!IS_ERR(data->clk_sec))
850 clk_enable(data->clk_sec);
851 /* Find which sensor generated this interrupt */
852 if (data->soc == SOC_ARCH_EXYNOS5440) {
853 val_type = readl(data->base_second + EXYNOS5440_TMU_IRQ_STATUS);
854 if (!((val_type >> data->id) & 0x1))
857 if (!IS_ERR(data->clk_sec))
858 clk_disable(data->clk_sec);
860 exynos_report_trigger(data);
861 mutex_lock(&data->lock);
862 clk_enable(data->clk);
864 /* TODO: take action based on particular interrupt */
865 data->tmu_clear_irqs(data);
867 clk_disable(data->clk);
868 mutex_unlock(&data->lock);
870 enable_irq(data->irq);
873 static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data)
875 unsigned int val_irq;
876 u32 tmu_intstat, tmu_intclear;
878 if (data->soc == SOC_ARCH_EXYNOS5260) {
879 tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT;
880 tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR;
881 } else if (data->soc == SOC_ARCH_EXYNOS7) {
882 tmu_intstat = EXYNOS7_TMU_REG_INTPEND;
883 tmu_intclear = EXYNOS7_TMU_REG_INTPEND;
885 tmu_intstat = EXYNOS_TMU_REG_INTSTAT;
886 tmu_intclear = EXYNOS_TMU_REG_INTCLEAR;
889 val_irq = readl(data->base + tmu_intstat);
891 * Clear the interrupts. Please note that the documentation for
892 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly
893 * states that INTCLEAR register has a different placing of bits
894 * responsible for FALL IRQs than INTSTAT register. Exynos5420
895 * and Exynos5440 documentation is correct (Exynos4210 doesn't
896 * support FALL IRQs at all).
898 writel(val_irq, data->base + tmu_intclear);
901 static void exynos5440_tmu_clear_irqs(struct exynos_tmu_data *data)
903 unsigned int val_irq;
905 val_irq = readl(data->base + EXYNOS5440_TMU_S0_7_IRQ);
906 /* clear the interrupts */
907 writel(val_irq, data->base + EXYNOS5440_TMU_S0_7_IRQ);
910 static irqreturn_t exynos_tmu_irq(int irq, void *id)
912 struct exynos_tmu_data *data = id;
914 disable_irq_nosync(irq);
915 schedule_work(&data->irq_work);
920 static const struct of_device_id exynos_tmu_match[] = {
922 .compatible = "samsung,exynos3250-tmu",
925 .compatible = "samsung,exynos4210-tmu",
928 .compatible = "samsung,exynos4412-tmu",
931 .compatible = "samsung,exynos5250-tmu",
934 .compatible = "samsung,exynos5260-tmu",
937 .compatible = "samsung,exynos5420-tmu",
940 .compatible = "samsung,exynos5420-tmu-ext-triminfo",
943 .compatible = "samsung,exynos5440-tmu",
946 .compatible = "samsung,exynos7-tmu",
950 MODULE_DEVICE_TABLE(of, exynos_tmu_match);
952 static int exynos_of_get_soc_type(struct device_node *np)
954 if (of_device_is_compatible(np, "samsung,exynos3250-tmu"))
955 return SOC_ARCH_EXYNOS3250;
956 else if (of_device_is_compatible(np, "samsung,exynos4210-tmu"))
957 return SOC_ARCH_EXYNOS4210;
958 else if (of_device_is_compatible(np, "samsung,exynos4412-tmu"))
959 return SOC_ARCH_EXYNOS4412;
960 else if (of_device_is_compatible(np, "samsung,exynos5250-tmu"))
961 return SOC_ARCH_EXYNOS5250;
962 else if (of_device_is_compatible(np, "samsung,exynos5260-tmu"))
963 return SOC_ARCH_EXYNOS5260;
964 else if (of_device_is_compatible(np, "samsung,exynos5420-tmu"))
965 return SOC_ARCH_EXYNOS5420;
966 else if (of_device_is_compatible(np,
967 "samsung,exynos5420-tmu-ext-triminfo"))
968 return SOC_ARCH_EXYNOS5420_TRIMINFO;
969 else if (of_device_is_compatible(np, "samsung,exynos5440-tmu"))
970 return SOC_ARCH_EXYNOS5440;
971 else if (of_device_is_compatible(np, "samsung,exynos7-tmu"))
972 return SOC_ARCH_EXYNOS7;
977 static int exynos_of_sensor_conf(struct device_node *np,
978 struct exynos_tmu_platform_data *pdata)
985 ret = of_property_read_u32(np, "samsung,tmu_gain", &value);
986 pdata->gain = (u8)value;
987 of_property_read_u32(np, "samsung,tmu_reference_voltage", &value);
988 pdata->reference_voltage = (u8)value;
989 of_property_read_u32(np, "samsung,tmu_noise_cancel_mode", &value);
990 pdata->noise_cancel_mode = (u8)value;
992 of_property_read_u32(np, "samsung,tmu_efuse_value",
993 &pdata->efuse_value);
994 of_property_read_u32(np, "samsung,tmu_min_efuse_value",
995 &pdata->min_efuse_value);
996 of_property_read_u32(np, "samsung,tmu_max_efuse_value",
997 &pdata->max_efuse_value);
999 of_property_read_u32(np, "samsung,tmu_first_point_trim", &value);
1000 pdata->first_point_trim = (u8)value;
1001 of_property_read_u32(np, "samsung,tmu_second_point_trim", &value);
1002 pdata->second_point_trim = (u8)value;
1003 of_property_read_u32(np, "samsung,tmu_default_temp_offset", &value);
1004 pdata->default_temp_offset = (u8)value;
1006 of_property_read_u32(np, "samsung,tmu_cal_type", &pdata->cal_type);
1007 of_property_read_u32(np, "samsung,tmu_cal_mode", &pdata->cal_mode);
1013 static int exynos_map_dt_data(struct platform_device *pdev)
1015 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
1016 struct exynos_tmu_platform_data *pdata;
1017 struct resource res;
1020 if (!data || !pdev->dev.of_node)
1024 * Try enabling the regulator if found
1025 * TODO: Add regulator as an SOC feature, so that regulator enable
1026 * is a compulsory call.
1028 data->regulator = devm_regulator_get(&pdev->dev, "vtmu");
1029 if (!IS_ERR(data->regulator)) {
1030 ret = regulator_enable(data->regulator);
1032 dev_err(&pdev->dev, "failed to enable vtmu\n");
1036 dev_info(&pdev->dev, "Regulator node (vtmu) not found\n");
1039 data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl");
1043 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1044 if (data->irq <= 0) {
1045 dev_err(&pdev->dev, "failed to get IRQ\n");
1049 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
1050 dev_err(&pdev->dev, "failed to get Resource 0\n");
1054 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
1056 dev_err(&pdev->dev, "Failed to ioremap memory\n");
1057 return -EADDRNOTAVAIL;
1060 pdata = devm_kzalloc(&pdev->dev,
1061 sizeof(struct exynos_tmu_platform_data),
1066 exynos_of_sensor_conf(pdev->dev.of_node, pdata);
1067 data->pdata = pdata;
1068 data->soc = exynos_of_get_soc_type(pdev->dev.of_node);
1070 switch (data->soc) {
1071 case SOC_ARCH_EXYNOS4210:
1072 data->tmu_initialize = exynos4210_tmu_initialize;
1073 data->tmu_control = exynos4210_tmu_control;
1074 data->tmu_read = exynos4210_tmu_read;
1075 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1077 case SOC_ARCH_EXYNOS3250:
1078 case SOC_ARCH_EXYNOS4412:
1079 case SOC_ARCH_EXYNOS5250:
1080 case SOC_ARCH_EXYNOS5260:
1081 case SOC_ARCH_EXYNOS5420:
1082 case SOC_ARCH_EXYNOS5420_TRIMINFO:
1083 data->tmu_initialize = exynos4412_tmu_initialize;
1084 data->tmu_control = exynos4210_tmu_control;
1085 data->tmu_read = exynos4412_tmu_read;
1086 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
1087 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1089 case SOC_ARCH_EXYNOS5440:
1090 data->tmu_initialize = exynos5440_tmu_initialize;
1091 data->tmu_control = exynos5440_tmu_control;
1092 data->tmu_read = exynos5440_tmu_read;
1093 data->tmu_set_emulation = exynos5440_tmu_set_emulation;
1094 data->tmu_clear_irqs = exynos5440_tmu_clear_irqs;
1096 case SOC_ARCH_EXYNOS7:
1097 data->tmu_initialize = exynos7_tmu_initialize;
1098 data->tmu_control = exynos7_tmu_control;
1099 data->tmu_read = exynos7_tmu_read;
1100 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
1101 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
1104 dev_err(&pdev->dev, "Platform not supported\n");
1109 * Check if the TMU shares some registers and then try to map the
1110 * memory of common registers.
1112 if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO &&
1113 data->soc != SOC_ARCH_EXYNOS5440)
1116 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
1117 dev_err(&pdev->dev, "failed to get Resource 1\n");
1121 data->base_second = devm_ioremap(&pdev->dev, res.start,
1122 resource_size(&res));
1123 if (!data->base_second) {
1124 dev_err(&pdev->dev, "Failed to ioremap memory\n");
1131 static struct thermal_zone_of_device_ops exynos_sensor_ops = {
1132 .get_temp = exynos_get_temp,
1133 .set_emul_temp = exynos_tmu_set_emulation,
1136 static int exynos_tmu_probe(struct platform_device *pdev)
1138 struct exynos_tmu_platform_data *pdata;
1139 struct exynos_tmu_data *data;
1142 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
1147 platform_set_drvdata(pdev, data);
1148 mutex_init(&data->lock);
1150 data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data,
1151 &exynos_sensor_ops);
1152 if (IS_ERR(data->tzd)) {
1153 pr_err("thermal: tz: %p ERROR\n", data->tzd);
1154 return PTR_ERR(data->tzd);
1156 ret = exynos_map_dt_data(pdev);
1160 pdata = data->pdata;
1162 INIT_WORK(&data->irq_work, exynos_tmu_work);
1164 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
1165 if (IS_ERR(data->clk)) {
1166 dev_err(&pdev->dev, "Failed to get clock\n");
1167 ret = PTR_ERR(data->clk);
1171 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
1172 if (IS_ERR(data->clk_sec)) {
1173 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
1174 dev_err(&pdev->dev, "Failed to get triminfo clock\n");
1175 ret = PTR_ERR(data->clk_sec);
1179 ret = clk_prepare(data->clk_sec);
1181 dev_err(&pdev->dev, "Failed to get clock\n");
1186 ret = clk_prepare(data->clk);
1188 dev_err(&pdev->dev, "Failed to get clock\n");
1192 if (data->soc == SOC_ARCH_EXYNOS7) {
1193 data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk");
1194 if (IS_ERR(data->sclk)) {
1195 dev_err(&pdev->dev, "Failed to get sclk\n");
1198 ret = clk_prepare_enable(data->sclk);
1200 dev_err(&pdev->dev, "Failed to enable sclk\n");
1206 ret = exynos_tmu_initialize(pdev);
1208 dev_err(&pdev->dev, "Failed to initialize TMU\n");
1212 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
1213 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data);
1215 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
1219 exynos_tmu_control(pdev, true);
1222 clk_disable_unprepare(data->sclk);
1224 clk_unprepare(data->clk);
1226 if (!IS_ERR(data->clk_sec))
1227 clk_unprepare(data->clk_sec);
1229 thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd);
1234 static int exynos_tmu_remove(struct platform_device *pdev)
1236 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
1237 struct thermal_zone_device *tzd = data->tzd;
1239 thermal_zone_of_sensor_unregister(&pdev->dev, tzd);
1240 exynos_tmu_control(pdev, false);
1242 clk_disable_unprepare(data->sclk);
1243 clk_unprepare(data->clk);
1244 if (!IS_ERR(data->clk_sec))
1245 clk_unprepare(data->clk_sec);
1247 if (!IS_ERR(data->regulator))
1248 regulator_disable(data->regulator);
1253 #ifdef CONFIG_PM_SLEEP
1254 static int exynos_tmu_suspend(struct device *dev)
1256 exynos_tmu_control(to_platform_device(dev), false);
1261 static int exynos_tmu_resume(struct device *dev)
1263 struct platform_device *pdev = to_platform_device(dev);
1265 exynos_tmu_initialize(pdev);
1266 exynos_tmu_control(pdev, true);
1271 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
1272 exynos_tmu_suspend, exynos_tmu_resume);
1273 #define EXYNOS_TMU_PM (&exynos_tmu_pm)
1275 #define EXYNOS_TMU_PM NULL
1278 static struct platform_driver exynos_tmu_driver = {
1280 .name = "exynos-tmu",
1281 .pm = EXYNOS_TMU_PM,
1282 .of_match_table = exynos_tmu_match,
1284 .probe = exynos_tmu_probe,
1285 .remove = exynos_tmu_remove,
1288 module_platform_driver(exynos_tmu_driver);
1290 MODULE_DESCRIPTION("EXYNOS TMU Driver");
1291 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
1292 MODULE_LICENSE("GPL");
1293 MODULE_ALIAS("platform:exynos-tmu");