2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
4 * Copyright (C) 2011 Samsung Electronics
5 * Donggeun Kim <dg77.kim@samsung.com>
6 * Amit Daniel Kachhap <amit.kachhap@linaro.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/clk.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/platform_device.h>
32 #include <linux/regulator/consumer.h>
34 #include "exynos_thermal_common.h"
35 #include "exynos_tmu.h"
37 /* Exynos generic registers */
38 #define EXYNOS_TMU_REG_TRIMINFO 0x0
39 #define EXYNOS_TMU_REG_CONTROL 0x20
40 #define EXYNOS_TMU_REG_STATUS 0x28
41 #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
42 #define EXYNOS_TMU_REG_INTEN 0x70
43 #define EXYNOS_TMU_REG_INTSTAT 0x74
44 #define EXYNOS_TMU_REG_INTCLEAR 0x78
46 #define EXYNOS_TMU_TEMP_MASK 0xff
47 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
48 #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f
49 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf
50 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8
51 #define EXYNOS_TMU_CORE_EN_SHIFT 0
53 /* Exynos3250 specific registers */
54 #define EXYNOS_TMU_TRIMINFO_CON1 0x10
56 /* Exynos4210 specific registers */
57 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
58 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
60 /* Exynos5250, Exynos4412, Exynos3250 specific registers */
61 #define EXYNOS_TMU_TRIMINFO_CON2 0x14
62 #define EXYNOS_THD_TEMP_RISE 0x50
63 #define EXYNOS_THD_TEMP_FALL 0x54
64 #define EXYNOS_EMUL_CON 0x80
66 #define EXYNOS_TRIMINFO_RELOAD_ENABLE 1
67 #define EXYNOS_TRIMINFO_25_SHIFT 0
68 #define EXYNOS_TRIMINFO_85_SHIFT 8
69 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13
70 #define EXYNOS_TMU_TRIP_MODE_MASK 0x7
71 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
73 #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0
74 #define EXYNOS_TMU_INTEN_RISE1_SHIFT 4
75 #define EXYNOS_TMU_INTEN_RISE2_SHIFT 8
76 #define EXYNOS_TMU_INTEN_RISE3_SHIFT 12
77 #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16
79 #define EXYNOS_EMUL_TIME 0x57F0
80 #define EXYNOS_EMUL_TIME_MASK 0xffff
81 #define EXYNOS_EMUL_TIME_SHIFT 16
82 #define EXYNOS_EMUL_DATA_SHIFT 8
83 #define EXYNOS_EMUL_DATA_MASK 0xFF
84 #define EXYNOS_EMUL_ENABLE 0x1
86 /* Exynos5260 specific */
87 #define EXYNOS5260_TMU_REG_INTEN 0xC0
88 #define EXYNOS5260_TMU_REG_INTSTAT 0xC4
89 #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8
90 #define EXYNOS5260_EMUL_CON 0x100
92 /* Exynos4412 specific */
93 #define EXYNOS4412_MUX_ADDR_VALUE 6
94 #define EXYNOS4412_MUX_ADDR_SHIFT 20
96 /*exynos5440 specific registers*/
97 #define EXYNOS5440_TMU_S0_7_TRIM 0x000
98 #define EXYNOS5440_TMU_S0_7_CTRL 0x020
99 #define EXYNOS5440_TMU_S0_7_DEBUG 0x040
100 #define EXYNOS5440_TMU_S0_7_TEMP 0x0f0
101 #define EXYNOS5440_TMU_S0_7_TH0 0x110
102 #define EXYNOS5440_TMU_S0_7_TH1 0x130
103 #define EXYNOS5440_TMU_S0_7_TH2 0x150
104 #define EXYNOS5440_TMU_S0_7_IRQEN 0x210
105 #define EXYNOS5440_TMU_S0_7_IRQ 0x230
106 /* exynos5440 common registers */
107 #define EXYNOS5440_TMU_IRQ_STATUS 0x000
108 #define EXYNOS5440_TMU_PMIN 0x004
110 #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0
111 #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1
112 #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2
113 #define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3
114 #define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4
115 #define EXYNOS5440_TMU_TH_RISE4_SHIFT 24
116 #define EXYNOS5440_EFUSE_SWAP_OFFSET 8
119 * struct exynos_tmu_data : A structure to hold the private data of the TMU
121 * @id: identifier of the one instance of the TMU controller.
122 * @pdata: pointer to the tmu platform/configuration data
123 * @base: base address of the single instance of the TMU controller.
124 * @base_second: base address of the common registers of the TMU controller.
125 * @irq: irq number of the TMU controller.
126 * @soc: id of the SOC type.
127 * @irq_work: pointer to the irq work structure.
128 * @lock: lock to implement synchronization.
129 * @clk: pointer to the clock structure.
130 * @clk_sec: pointer to the clock structure for accessing the base_second.
131 * @temp_error1: fused value of the first point trim.
132 * @temp_error2: fused value of the second point trim.
133 * @regulator: pointer to the TMU regulator structure.
134 * @reg_conf: pointer to structure to register with core thermal.
135 * @tmu_initialize: SoC specific TMU initialization method
136 * @tmu_control: SoC specific TMU control method
137 * @tmu_read: SoC specific TMU temperature read method
138 * @tmu_set_emulation: SoC specific TMU emulation setting method
139 * @tmu_clear_irqs: SoC specific TMU interrupts clearing method
141 struct exynos_tmu_data {
143 struct exynos_tmu_platform_data *pdata;
145 void __iomem *base_second;
148 struct work_struct irq_work;
150 struct clk *clk, *clk_sec;
151 u8 temp_error1, temp_error2;
152 struct regulator *regulator;
153 struct thermal_sensor_conf *reg_conf;
154 int (*tmu_initialize)(struct platform_device *pdev);
155 void (*tmu_control)(struct platform_device *pdev, bool on);
156 int (*tmu_read)(struct exynos_tmu_data *data);
157 void (*tmu_set_emulation)(struct exynos_tmu_data *data,
159 void (*tmu_clear_irqs)(struct exynos_tmu_data *data);
163 * TMU treats temperature as a mapped temperature code.
164 * The temperature is converted differently depending on the calibration type.
166 static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
168 struct exynos_tmu_platform_data *pdata = data->pdata;
171 switch (pdata->cal_type) {
172 case TYPE_TWO_POINT_TRIMMING:
173 temp_code = (temp - pdata->first_point_trim) *
174 (data->temp_error2 - data->temp_error1) /
175 (pdata->second_point_trim - pdata->first_point_trim) +
178 case TYPE_ONE_POINT_TRIMMING:
179 temp_code = temp + data->temp_error1 - pdata->first_point_trim;
182 temp_code = temp + pdata->default_temp_offset;
190 * Calculate a temperature value from a temperature code.
191 * The unit of the temperature is degree Celsius.
193 static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
195 struct exynos_tmu_platform_data *pdata = data->pdata;
198 switch (pdata->cal_type) {
199 case TYPE_TWO_POINT_TRIMMING:
200 temp = (temp_code - data->temp_error1) *
201 (pdata->second_point_trim - pdata->first_point_trim) /
202 (data->temp_error2 - data->temp_error1) +
203 pdata->first_point_trim;
205 case TYPE_ONE_POINT_TRIMMING:
206 temp = temp_code - data->temp_error1 + pdata->first_point_trim;
209 temp = temp_code - pdata->default_temp_offset;
216 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info)
218 struct exynos_tmu_platform_data *pdata = data->pdata;
220 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
221 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) &
222 EXYNOS_TMU_TEMP_MASK);
224 if (!data->temp_error1 ||
225 (pdata->min_efuse_value > data->temp_error1) ||
226 (data->temp_error1 > pdata->max_efuse_value))
227 data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK;
229 if (!data->temp_error2)
231 (pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) &
232 EXYNOS_TMU_TEMP_MASK;
235 static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling)
237 struct exynos_tmu_platform_data *pdata = data->pdata;
240 for (i = 0; i < pdata->non_hw_trigger_levels; i++) {
241 u8 temp = pdata->trigger_levels[i];
244 temp -= pdata->threshold_falling;
246 threshold &= ~(0xff << 8 * i);
248 threshold |= temp_to_code(data, temp) << 8 * i;
254 static int exynos_tmu_initialize(struct platform_device *pdev)
256 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
259 mutex_lock(&data->lock);
260 clk_enable(data->clk);
261 if (!IS_ERR(data->clk_sec))
262 clk_enable(data->clk_sec);
263 ret = data->tmu_initialize(pdev);
264 clk_disable(data->clk);
265 mutex_unlock(&data->lock);
266 if (!IS_ERR(data->clk_sec))
267 clk_disable(data->clk_sec);
272 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con)
274 struct exynos_tmu_platform_data *pdata = data->pdata;
276 if (data->soc == SOC_ARCH_EXYNOS4412 ||
277 data->soc == SOC_ARCH_EXYNOS3250)
278 con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT);
280 con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT);
281 con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT;
283 con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
284 con |= (pdata->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT);
286 if (pdata->noise_cancel_mode) {
287 con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT);
288 con |= (pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT);
294 static void exynos_tmu_control(struct platform_device *pdev, bool on)
296 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
298 mutex_lock(&data->lock);
299 clk_enable(data->clk);
300 data->tmu_control(pdev, on);
301 clk_disable(data->clk);
302 mutex_unlock(&data->lock);
305 static int exynos4210_tmu_initialize(struct platform_device *pdev)
307 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
308 struct exynos_tmu_platform_data *pdata = data->pdata;
310 int ret = 0, threshold_code, i;
312 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
318 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO));
320 /* Write temperature code for threshold */
321 threshold_code = temp_to_code(data, pdata->threshold);
322 writeb(threshold_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
324 for (i = 0; i < pdata->non_hw_trigger_levels; i++)
325 writeb(pdata->trigger_levels[i], data->base +
326 EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4);
328 data->tmu_clear_irqs(data);
333 static int exynos4412_tmu_initialize(struct platform_device *pdev)
335 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
336 struct exynos_tmu_platform_data *pdata = data->pdata;
337 unsigned int status, trim_info, con, ctrl, rising_threshold;
338 int ret = 0, threshold_code, i;
340 status = readb(data->base + EXYNOS_TMU_REG_STATUS);
346 if (data->soc == SOC_ARCH_EXYNOS3250 ||
347 data->soc == SOC_ARCH_EXYNOS4412 ||
348 data->soc == SOC_ARCH_EXYNOS5250) {
349 if (data->soc == SOC_ARCH_EXYNOS3250) {
350 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1);
351 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
352 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1);
354 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2);
355 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE;
356 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2);
359 /* On exynos5420 the triminfo register is in the shared space */
360 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
361 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO);
363 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
365 sanitize_temp_error(data, trim_info);
367 /* Write temperature code for rising and falling threshold */
368 rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE);
369 rising_threshold = get_th_reg(data, rising_threshold, false);
370 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
371 writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL);
373 data->tmu_clear_irqs(data);
375 /* if last threshold limit is also present */
376 i = pdata->max_trigger_level - 1;
377 if (pdata->trigger_levels[i] && pdata->trigger_type[i] == HW_TRIP) {
378 threshold_code = temp_to_code(data, pdata->trigger_levels[i]);
379 /* 1-4 level to be assigned in th0 reg */
380 rising_threshold &= ~(0xff << 8 * i);
381 rising_threshold |= threshold_code << 8 * i;
382 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE);
383 con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
384 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
385 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
391 static int exynos5440_tmu_initialize(struct platform_device *pdev)
393 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
394 struct exynos_tmu_platform_data *pdata = data->pdata;
395 unsigned int trim_info = 0, con, rising_threshold;
396 int ret = 0, threshold_code, i;
399 * For exynos5440 soc triminfo value is swapped between TMU0 and
400 * TMU2, so the below logic is needed.
404 trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET +
405 EXYNOS5440_TMU_S0_7_TRIM);
408 trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM);
411 trim_info = readl(data->base - EXYNOS5440_EFUSE_SWAP_OFFSET +
412 EXYNOS5440_TMU_S0_7_TRIM);
414 sanitize_temp_error(data, trim_info);
416 /* Write temperature code for rising and falling threshold */
417 rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0);
418 rising_threshold = get_th_reg(data, rising_threshold, false);
419 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0);
420 writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1);
422 data->tmu_clear_irqs(data);
424 /* if last threshold limit is also present */
425 i = pdata->max_trigger_level - 1;
426 if (pdata->trigger_levels[i] && pdata->trigger_type[i] == HW_TRIP) {
427 threshold_code = temp_to_code(data, pdata->trigger_levels[i]);
428 /* 5th level to be assigned in th2 reg */
430 threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT;
431 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2);
432 con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL);
433 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
434 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
436 /* Clear the PMIN in the common TMU register */
438 writel(0, data->base_second + EXYNOS5440_TMU_PMIN);
442 static void exynos4210_tmu_control(struct platform_device *pdev, bool on)
444 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
445 struct exynos_tmu_platform_data *pdata = data->pdata;
446 unsigned int con, interrupt_en;
448 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL));
451 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
453 pdata->trigger_enable[3] << EXYNOS_TMU_INTEN_RISE3_SHIFT |
454 pdata->trigger_enable[2] << EXYNOS_TMU_INTEN_RISE2_SHIFT |
455 pdata->trigger_enable[1] << EXYNOS_TMU_INTEN_RISE1_SHIFT |
456 pdata->trigger_enable[0] << EXYNOS_TMU_INTEN_RISE0_SHIFT;
457 if (data->soc != SOC_ARCH_EXYNOS4210)
459 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT;
461 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
462 interrupt_en = 0; /* Disable all interrupts */
464 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
465 writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
468 static void exynos5440_tmu_control(struct platform_device *pdev, bool on)
470 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
471 struct exynos_tmu_platform_data *pdata = data->pdata;
472 unsigned int con, interrupt_en;
474 con = get_con_reg(data, readl(data->base + EXYNOS5440_TMU_S0_7_CTRL));
477 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);
479 pdata->trigger_enable[3] << EXYNOS5440_TMU_INTEN_RISE3_SHIFT |
480 pdata->trigger_enable[2] << EXYNOS5440_TMU_INTEN_RISE2_SHIFT |
481 pdata->trigger_enable[1] << EXYNOS5440_TMU_INTEN_RISE1_SHIFT |
482 pdata->trigger_enable[0] << EXYNOS5440_TMU_INTEN_RISE0_SHIFT;
483 interrupt_en |= interrupt_en << EXYNOS5440_TMU_INTEN_FALL0_SHIFT;
485 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);
486 interrupt_en = 0; /* Disable all interrupts */
488 writel(interrupt_en, data->base + EXYNOS5440_TMU_S0_7_IRQEN);
489 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);
492 static int exynos_tmu_read(struct exynos_tmu_data *data)
496 mutex_lock(&data->lock);
497 clk_enable(data->clk);
498 ret = data->tmu_read(data);
500 ret = code_to_temp(data, ret);
501 clk_disable(data->clk);
502 mutex_unlock(&data->lock);
507 #ifdef CONFIG_THERMAL_EMULATION
508 static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val,
514 if (data->soc != SOC_ARCH_EXYNOS5440) {
515 val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT);
516 val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT);
518 val &= ~(EXYNOS_EMUL_DATA_MASK << EXYNOS_EMUL_DATA_SHIFT);
519 val |= (temp_to_code(data, temp) << EXYNOS_EMUL_DATA_SHIFT) |
522 val &= ~EXYNOS_EMUL_ENABLE;
528 static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data,
534 if (data->soc == SOC_ARCH_EXYNOS5260)
535 emul_con = EXYNOS5260_EMUL_CON;
537 emul_con = EXYNOS_EMUL_CON;
539 val = readl(data->base + emul_con);
540 val = get_emul_con_reg(data, val, temp);
541 writel(val, data->base + emul_con);
544 static void exynos5440_tmu_set_emulation(struct exynos_tmu_data *data,
549 val = readl(data->base + EXYNOS5440_TMU_S0_7_DEBUG);
550 val = get_emul_con_reg(data, val, temp);
551 writel(val, data->base + EXYNOS5440_TMU_S0_7_DEBUG);
554 static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
556 struct exynos_tmu_data *data = drv_data;
559 if (data->soc == SOC_ARCH_EXYNOS4210)
562 if (temp && temp < MCELSIUS)
565 mutex_lock(&data->lock);
566 clk_enable(data->clk);
567 data->tmu_set_emulation(data, temp);
568 clk_disable(data->clk);
569 mutex_unlock(&data->lock);
575 #define exynos4412_tmu_set_emulation NULL
576 #define exynos5440_tmu_set_emulation NULL
577 static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
579 #endif/*CONFIG_THERMAL_EMULATION*/
581 static int exynos4210_tmu_read(struct exynos_tmu_data *data)
583 int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
585 /* "temp_code" should range between 75 and 175 */
586 return (ret < 75 || ret > 175) ? -ENODATA : ret;
589 static int exynos4412_tmu_read(struct exynos_tmu_data *data)
591 return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
594 static int exynos5440_tmu_read(struct exynos_tmu_data *data)
596 return readb(data->base + EXYNOS5440_TMU_S0_7_TEMP);
599 static void exynos_tmu_work(struct work_struct *work)
601 struct exynos_tmu_data *data = container_of(work,
602 struct exynos_tmu_data, irq_work);
603 unsigned int val_type;
605 if (!IS_ERR(data->clk_sec))
606 clk_enable(data->clk_sec);
607 /* Find which sensor generated this interrupt */
608 if (data->soc == SOC_ARCH_EXYNOS5440) {
609 val_type = readl(data->base_second + EXYNOS5440_TMU_IRQ_STATUS);
610 if (!((val_type >> data->id) & 0x1))
613 if (!IS_ERR(data->clk_sec))
614 clk_disable(data->clk_sec);
616 exynos_report_trigger(data->reg_conf);
617 mutex_lock(&data->lock);
618 clk_enable(data->clk);
620 /* TODO: take action based on particular interrupt */
621 data->tmu_clear_irqs(data);
623 clk_disable(data->clk);
624 mutex_unlock(&data->lock);
626 enable_irq(data->irq);
629 static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data)
631 unsigned int val_irq;
632 u32 tmu_intstat, tmu_intclear;
634 if (data->soc == SOC_ARCH_EXYNOS5260) {
635 tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT;
636 tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR;
638 tmu_intstat = EXYNOS_TMU_REG_INTSTAT;
639 tmu_intclear = EXYNOS_TMU_REG_INTCLEAR;
642 val_irq = readl(data->base + tmu_intstat);
644 * Clear the interrupts. Please note that the documentation for
645 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly
646 * states that INTCLEAR register has a different placing of bits
647 * responsible for FALL IRQs than INTSTAT register. Exynos5420
648 * and Exynos5440 documentation is correct (Exynos4210 doesn't
649 * support FALL IRQs at all).
651 writel(val_irq, data->base + tmu_intclear);
654 static void exynos5440_tmu_clear_irqs(struct exynos_tmu_data *data)
656 unsigned int val_irq;
658 val_irq = readl(data->base + EXYNOS5440_TMU_S0_7_IRQ);
659 /* clear the interrupts */
660 writel(val_irq, data->base + EXYNOS5440_TMU_S0_7_IRQ);
663 static irqreturn_t exynos_tmu_irq(int irq, void *id)
665 struct exynos_tmu_data *data = id;
667 disable_irq_nosync(irq);
668 schedule_work(&data->irq_work);
673 static const struct of_device_id exynos_tmu_match[] = {
675 .compatible = "samsung,exynos3250-tmu",
676 .data = &exynos3250_default_tmu_data,
679 .compatible = "samsung,exynos4210-tmu",
680 .data = &exynos4210_default_tmu_data,
683 .compatible = "samsung,exynos4412-tmu",
684 .data = &exynos4412_default_tmu_data,
687 .compatible = "samsung,exynos5250-tmu",
688 .data = &exynos5250_default_tmu_data,
691 .compatible = "samsung,exynos5260-tmu",
692 .data = &exynos5260_default_tmu_data,
695 .compatible = "samsung,exynos5420-tmu",
696 .data = &exynos5420_default_tmu_data,
699 .compatible = "samsung,exynos5420-tmu-ext-triminfo",
700 .data = &exynos5420_default_tmu_data,
703 .compatible = "samsung,exynos5440-tmu",
704 .data = &exynos5440_default_tmu_data,
708 MODULE_DEVICE_TABLE(of, exynos_tmu_match);
710 static inline struct exynos_tmu_platform_data *exynos_get_driver_data(
711 struct platform_device *pdev, int id)
713 struct exynos_tmu_init_data *data_table;
714 struct exynos_tmu_platform_data *tmu_data;
715 const struct of_device_id *match;
717 match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
720 data_table = (struct exynos_tmu_init_data *) match->data;
721 if (!data_table || id >= data_table->tmu_count)
723 tmu_data = data_table->tmu_data;
724 return (struct exynos_tmu_platform_data *) (tmu_data + id);
727 static int exynos_map_dt_data(struct platform_device *pdev)
729 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
730 struct exynos_tmu_platform_data *pdata;
734 if (!data || !pdev->dev.of_node)
738 * Try enabling the regulator if found
739 * TODO: Add regulator as an SOC feature, so that regulator enable
740 * is a compulsory call.
742 data->regulator = devm_regulator_get(&pdev->dev, "vtmu");
743 if (!IS_ERR(data->regulator)) {
744 ret = regulator_enable(data->regulator);
746 dev_err(&pdev->dev, "failed to enable vtmu\n");
750 dev_info(&pdev->dev, "Regulator node (vtmu) not found\n");
753 data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl");
757 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
758 if (data->irq <= 0) {
759 dev_err(&pdev->dev, "failed to get IRQ\n");
763 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) {
764 dev_err(&pdev->dev, "failed to get Resource 0\n");
768 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res));
770 dev_err(&pdev->dev, "Failed to ioremap memory\n");
771 return -EADDRNOTAVAIL;
774 pdata = exynos_get_driver_data(pdev, data->id);
776 dev_err(&pdev->dev, "No platform init data supplied.\n");
781 data->soc = pdata->type;
784 case SOC_ARCH_EXYNOS4210:
785 data->tmu_initialize = exynos4210_tmu_initialize;
786 data->tmu_control = exynos4210_tmu_control;
787 data->tmu_read = exynos4210_tmu_read;
788 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
790 case SOC_ARCH_EXYNOS3250:
791 case SOC_ARCH_EXYNOS4412:
792 case SOC_ARCH_EXYNOS5250:
793 case SOC_ARCH_EXYNOS5260:
794 case SOC_ARCH_EXYNOS5420:
795 case SOC_ARCH_EXYNOS5420_TRIMINFO:
796 data->tmu_initialize = exynos4412_tmu_initialize;
797 data->tmu_control = exynos4210_tmu_control;
798 data->tmu_read = exynos4412_tmu_read;
799 data->tmu_set_emulation = exynos4412_tmu_set_emulation;
800 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs;
802 case SOC_ARCH_EXYNOS5440:
803 data->tmu_initialize = exynos5440_tmu_initialize;
804 data->tmu_control = exynos5440_tmu_control;
805 data->tmu_read = exynos5440_tmu_read;
806 data->tmu_set_emulation = exynos5440_tmu_set_emulation;
807 data->tmu_clear_irqs = exynos5440_tmu_clear_irqs;
810 dev_err(&pdev->dev, "Platform not supported\n");
815 * Check if the TMU shares some registers and then try to map the
816 * memory of common registers.
818 if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO &&
819 data->soc != SOC_ARCH_EXYNOS5440)
822 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
823 dev_err(&pdev->dev, "failed to get Resource 1\n");
827 data->base_second = devm_ioremap(&pdev->dev, res.start,
828 resource_size(&res));
829 if (!data->base_second) {
830 dev_err(&pdev->dev, "Failed to ioremap memory\n");
837 static int exynos_tmu_probe(struct platform_device *pdev)
839 struct exynos_tmu_data *data;
840 struct exynos_tmu_platform_data *pdata;
841 struct thermal_sensor_conf *sensor_conf;
844 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
849 platform_set_drvdata(pdev, data);
850 mutex_init(&data->lock);
852 ret = exynos_map_dt_data(pdev);
858 INIT_WORK(&data->irq_work, exynos_tmu_work);
860 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
861 if (IS_ERR(data->clk)) {
862 dev_err(&pdev->dev, "Failed to get clock\n");
863 return PTR_ERR(data->clk);
866 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
867 if (IS_ERR(data->clk_sec)) {
868 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
869 dev_err(&pdev->dev, "Failed to get triminfo clock\n");
870 return PTR_ERR(data->clk_sec);
873 ret = clk_prepare(data->clk_sec);
875 dev_err(&pdev->dev, "Failed to get clock\n");
880 ret = clk_prepare(data->clk);
882 dev_err(&pdev->dev, "Failed to get clock\n");
886 ret = exynos_tmu_initialize(pdev);
888 dev_err(&pdev->dev, "Failed to initialize TMU\n");
892 exynos_tmu_control(pdev, true);
894 /* Allocate a structure to register with the exynos core thermal */
895 sensor_conf = devm_kzalloc(&pdev->dev,
896 sizeof(struct thermal_sensor_conf), GFP_KERNEL);
901 sprintf(sensor_conf->name, "therm_zone%d", data->id);
902 sensor_conf->read_temperature = (int (*)(void *))exynos_tmu_read;
903 sensor_conf->write_emul_temp =
904 (int (*)(void *, unsigned long))exynos_tmu_set_emulation;
905 sensor_conf->driver_data = data;
906 sensor_conf->trip_data.trip_count = pdata->trigger_enable[0] +
907 pdata->trigger_enable[1] + pdata->trigger_enable[2]+
908 pdata->trigger_enable[3];
910 for (i = 0; i < sensor_conf->trip_data.trip_count; i++) {
911 sensor_conf->trip_data.trip_val[i] =
912 pdata->threshold + pdata->trigger_levels[i];
913 sensor_conf->trip_data.trip_type[i] =
914 pdata->trigger_type[i];
917 sensor_conf->trip_data.trigger_falling = pdata->threshold_falling;
919 sensor_conf->cooling_data.freq_clip_count = pdata->freq_tab_count;
920 for (i = 0; i < pdata->freq_tab_count; i++) {
921 sensor_conf->cooling_data.freq_data[i].freq_clip_max =
922 pdata->freq_tab[i].freq_clip_max;
923 sensor_conf->cooling_data.freq_data[i].temp_level =
924 pdata->freq_tab[i].temp_level;
926 sensor_conf->dev = &pdev->dev;
927 /* Register the sensor with thermal management interface */
928 ret = exynos_register_thermal(sensor_conf);
930 if (ret != -EPROBE_DEFER)
932 "Failed to register thermal interface: %d\n",
936 data->reg_conf = sensor_conf;
938 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
939 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data);
941 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
947 clk_unprepare(data->clk);
949 if (!IS_ERR(data->clk_sec))
950 clk_unprepare(data->clk_sec);
954 static int exynos_tmu_remove(struct platform_device *pdev)
956 struct exynos_tmu_data *data = platform_get_drvdata(pdev);
958 exynos_unregister_thermal(data->reg_conf);
960 exynos_tmu_control(pdev, false);
962 clk_unprepare(data->clk);
963 if (!IS_ERR(data->clk_sec))
964 clk_unprepare(data->clk_sec);
966 if (!IS_ERR(data->regulator))
967 regulator_disable(data->regulator);
972 #ifdef CONFIG_PM_SLEEP
973 static int exynos_tmu_suspend(struct device *dev)
975 exynos_tmu_control(to_platform_device(dev), false);
980 static int exynos_tmu_resume(struct device *dev)
982 struct platform_device *pdev = to_platform_device(dev);
984 exynos_tmu_initialize(pdev);
985 exynos_tmu_control(pdev, true);
990 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
991 exynos_tmu_suspend, exynos_tmu_resume);
992 #define EXYNOS_TMU_PM (&exynos_tmu_pm)
994 #define EXYNOS_TMU_PM NULL
997 static struct platform_driver exynos_tmu_driver = {
999 .name = "exynos-tmu",
1000 .pm = EXYNOS_TMU_PM,
1001 .of_match_table = exynos_tmu_match,
1003 .probe = exynos_tmu_probe,
1004 .remove = exynos_tmu_remove,
1007 module_platform_driver(exynos_tmu_driver);
1009 MODULE_DESCRIPTION("EXYNOS TMU Driver");
1010 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
1011 MODULE_LICENSE("GPL");
1012 MODULE_ALIAS("platform:exynos-tmu");