1 /* ////////////////////////////////////////////////////////////////////////// */
3 /* Copyright (c) Atmel Corporation. All rights reserved. */
5 /* Module Name: wilc_spi.c */
8 /* //////////////////////////////////////////////////////////////////////////// */
10 #include <linux/string.h>
11 #include "wilc_wlan_if.h"
12 #include "wilc_wlan.h"
16 int (*spi_tx)(u8 *, u32);
17 int (*spi_rx)(u8 *, u32);
18 int (*spi_trx)(u8 *, u8 *, u32);
19 int (*spi_max_speed)(void);
20 wilc_debug_func dPrint;
26 static wilc_spi_t g_spi;
28 static int spi_read(u32, u8 *, u32);
29 static int spi_write(u32, u8 *, u32);
31 /********************************************
35 ********************************************/
37 static const u8 crc7_syndrome_table[256] = {
38 0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
39 0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
40 0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
41 0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
42 0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
43 0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
44 0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
45 0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
46 0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
47 0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
48 0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
49 0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
50 0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
51 0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
52 0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
53 0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
54 0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
55 0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
56 0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
57 0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
58 0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
59 0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
60 0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
61 0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
62 0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
63 0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
64 0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
65 0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
66 0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
67 0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
68 0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
69 0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
72 static u8 crc7_byte(u8 crc, u8 data)
74 return crc7_syndrome_table[(crc << 1) ^ data];
77 static u8 crc7(u8 crc, const u8 *buffer, u32 len)
80 crc = crc7_byte(crc, *buffer++);
84 /********************************************
86 * Spi protocol Function
88 ********************************************/
90 #define CMD_DMA_WRITE 0xc1
91 #define CMD_DMA_READ 0xc2
92 #define CMD_INTERNAL_WRITE 0xc3
93 #define CMD_INTERNAL_READ 0xc4
94 #define CMD_TERMINATE 0xc5
95 #define CMD_REPEAT 0xc6
96 #define CMD_DMA_EXT_WRITE 0xc7
97 #define CMD_DMA_EXT_READ 0xc8
98 #define CMD_SINGLE_WRITE 0xc9
99 #define CMD_SINGLE_READ 0xca
100 #define CMD_RESET 0xcf
107 #define DATA_PKT_SZ_256 256
108 #define DATA_PKT_SZ_512 512
109 #define DATA_PKT_SZ_1K 1024
110 #define DATA_PKT_SZ_4K (4 * 1024)
111 #define DATA_PKT_SZ_8K (8 * 1024)
112 #define DATA_PKT_SZ DATA_PKT_SZ_8K
114 static int spi_cmd(u8 cmd, u32 adr, u32 data, u32 sz, u8 clockless)
122 case CMD_SINGLE_READ: /* single word (4 bytes) read */
123 bc[1] = (u8)(adr >> 16);
124 bc[2] = (u8)(adr >> 8);
129 case CMD_INTERNAL_READ: /* internal register read */
130 bc[1] = (u8)(adr >> 8);
138 case CMD_TERMINATE: /* termination */
145 case CMD_REPEAT: /* repeat */
152 case CMD_RESET: /* reset */
159 case CMD_DMA_WRITE: /* dma write */
160 case CMD_DMA_READ: /* dma read */
161 bc[1] = (u8)(adr >> 16);
162 bc[2] = (u8)(adr >> 8);
164 bc[4] = (u8)(sz >> 8);
169 case CMD_DMA_EXT_WRITE: /* dma extended write */
170 case CMD_DMA_EXT_READ: /* dma extended read */
171 bc[1] = (u8)(adr >> 16);
172 bc[2] = (u8)(adr >> 8);
174 bc[4] = (u8)(sz >> 16);
175 bc[5] = (u8)(sz >> 8);
180 case CMD_INTERNAL_WRITE: /* internal register write */
181 bc[1] = (u8)(adr >> 8);
185 bc[3] = (u8)(data >> 24);
186 bc[4] = (u8)(data >> 16);
187 bc[5] = (u8)(data >> 8);
192 case CMD_SINGLE_WRITE: /* single word write */
193 bc[1] = (u8)(adr >> 16);
194 bc[2] = (u8)(adr >> 8);
196 bc[4] = (u8)(data >> 24);
197 bc[5] = (u8)(data >> 16);
198 bc[6] = (u8)(data >> 8);
210 bc[len - 1] = (crc7(0x7f, (const u8 *)&bc[0], len - 1)) << 1;
214 if (!g_spi.spi_tx(bc, len)) {
215 PRINT_ER("[wilc spi]: Failed cmd write, bus error...\n");
223 static int spi_cmd_rsp(u8 cmd)
229 * Command/Control response
231 if ((cmd == CMD_RESET) ||
232 (cmd == CMD_TERMINATE) ||
233 (cmd == CMD_REPEAT)) {
234 if (!g_spi.spi_rx(&rsp, 1)) {
240 if (!g_spi.spi_rx(&rsp, 1)) {
241 PRINT_ER("[wilc spi]: Failed cmd response read, bus error...\n");
247 PRINT_ER("[wilc spi]: Failed cmd response, cmd (%02x), resp (%02x)\n", cmd, rsp);
255 if (!g_spi.spi_rx(&rsp, 1)) {
256 PRINT_ER("[wilc spi]: Failed cmd state read, bus error...\n");
262 PRINT_ER("[wilc spi]: Failed cmd state response state (%02x)\n", rsp);
271 static int spi_cmd_complete(u8 cmd, u32 adr, u8 *b, u32 sz, u8 clockless)
282 case CMD_SINGLE_READ: /* single word (4 bytes) read */
283 wb[1] = (u8)(adr >> 16);
284 wb[2] = (u8)(adr >> 8);
289 case CMD_INTERNAL_READ: /* internal register read */
290 wb[1] = (u8)(adr >> 8);
298 case CMD_TERMINATE: /* termination */
305 case CMD_REPEAT: /* repeat */
312 case CMD_RESET: /* reset */
319 case CMD_DMA_WRITE: /* dma write */
320 case CMD_DMA_READ: /* dma read */
321 wb[1] = (u8)(adr >> 16);
322 wb[2] = (u8)(adr >> 8);
324 wb[4] = (u8)(sz >> 8);
329 case CMD_DMA_EXT_WRITE: /* dma extended write */
330 case CMD_DMA_EXT_READ: /* dma extended read */
331 wb[1] = (u8)(adr >> 16);
332 wb[2] = (u8)(adr >> 8);
334 wb[4] = (u8)(sz >> 16);
335 wb[5] = (u8)(sz >> 8);
340 case CMD_INTERNAL_WRITE: /* internal register write */
341 wb[1] = (u8)(adr >> 8);
352 case CMD_SINGLE_WRITE: /* single word write */
353 wb[1] = (u8)(adr >> 16);
354 wb[2] = (u8)(adr >> 8);
368 if (result != N_OK) {
373 wb[len - 1] = (crc7(0x7f, (const u8 *)&wb[0], len - 1)) << 1;
377 #define NUM_SKIP_BYTES (1)
378 #define NUM_RSP_BYTES (2)
379 #define NUM_DATA_HDR_BYTES (1)
380 #define NUM_DATA_BYTES (4)
381 #define NUM_CRC_BYTES (2)
382 #define NUM_DUMMY_BYTES (3)
383 if ((cmd == CMD_RESET) ||
384 (cmd == CMD_TERMINATE) ||
385 (cmd == CMD_REPEAT)) {
386 len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
387 } else if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
388 if (!g_spi.crc_off) {
389 len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
390 + NUM_CRC_BYTES + NUM_DUMMY_BYTES);
392 len2 = len + (NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
396 len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
398 #undef NUM_DUMMY_BYTES
400 if (len2 > ARRAY_SIZE(wb)) {
401 PRINT_ER("[wilc spi]: spi buffer size too small (%d) (%zu)\n",
402 len2, ARRAY_SIZE(wb));
406 /* zero spi write buffers. */
407 for (wix = len; wix < len2; wix++) {
412 if (!g_spi.spi_trx(wb, rb, len2)) {
413 PRINT_ER("[wilc spi]: Failed cmd write, bus error...\n");
419 * Command/Control response
421 if ((cmd == CMD_RESET) ||
422 (cmd == CMD_TERMINATE) ||
423 (cmd == CMD_REPEAT)) {
424 rix++; /* skip 1 byte */
429 /* if(rsp == cmd) break; */
430 /* } while(&rptr[1] <= &rb[len2]); */
433 PRINT_ER("[wilc spi]: Failed cmd response, cmd (%02x)"
434 ", resp (%02x)\n", cmd, rsp);
444 PRINT_ER("[wilc spi]: Failed cmd state response "
445 "state (%02x)\n", rsp);
450 if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)
451 || (cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
453 /* u16 crc1, crc2; */
456 * Data Respnose header
460 /* ensure there is room in buffer later to read data and crc */
467 if (((rsp >> 4) & 0xf) == 0xf)
472 PRINT_ER("[wilc spi]: Error, data read "
473 "response (%02x)\n", rsp);
478 if ((cmd == CMD_INTERNAL_READ) || (cmd == CMD_SINGLE_READ)) {
482 if ((rix + 3) < len2) {
488 PRINT_ER("[wilc spi]: buffer overrun when reading data.\n");
493 if (!g_spi.crc_off) {
497 if ((rix + 1) < len2) {
501 PRINT_ER("[wilc spi]: buffer overrun when reading crc.\n");
506 } else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
509 /* some data may be read in response to dummy bytes. */
510 for (ix = 0; (rix < len2) && (ix < sz); ) {
519 if (sz <= (DATA_PKT_SZ - ix))
522 nbytes = DATA_PKT_SZ - ix;
527 if (!g_spi.spi_rx(&b[ix], nbytes)) {
528 PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
536 if (!g_spi.crc_off) {
537 if (!g_spi.spi_rx(crc, 2)) {
538 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
549 /* if any data in left unread, then read the rest using normal DMA code.*/
553 if (sz <= DATA_PKT_SZ)
556 nbytes = DATA_PKT_SZ;
559 * read data response only on the next DMA cycles not
560 * the first DMA since data response header is already
561 * handled above for the first DMA.
564 * Data Respnose header
568 if (!g_spi.spi_rx(&rsp, 1)) {
569 PRINT_ER("[wilc spi]: Failed data response read, bus error...\n");
573 if (((rsp >> 4) & 0xf) == 0xf)
577 if (result == N_FAIL)
584 if (!g_spi.spi_rx(&b[ix], nbytes)) {
585 PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
593 if (!g_spi.crc_off) {
594 if (!g_spi.spi_rx(crc, 2)) {
595 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
610 static int spi_data_read(u8 *b, u32 sz)
612 int retry, ix, nbytes;
622 if (sz <= DATA_PKT_SZ)
625 nbytes = DATA_PKT_SZ;
628 * Data Respnose header
632 if (!g_spi.spi_rx(&rsp, 1)) {
633 PRINT_ER("[wilc spi]: Failed data response read, bus error...\n");
637 if (((rsp >> 4) & 0xf) == 0xf)
641 if (result == N_FAIL)
645 PRINT_ER("[wilc spi]: Failed data response read...(%02x)\n", rsp);
653 if (!g_spi.spi_rx(&b[ix], nbytes)) {
654 PRINT_ER("[wilc spi]: Failed data block read, bus error...\n");
662 if (!g_spi.crc_off) {
663 if (!g_spi.spi_rx(crc, 2)) {
664 PRINT_ER("[wilc spi]: Failed data block crc read, bus error...\n");
678 static int spi_data_write(u8 *b, u32 sz)
682 u8 cmd, order, crc[2] = {0};
690 if (sz <= DATA_PKT_SZ)
693 nbytes = DATA_PKT_SZ;
700 if (sz <= DATA_PKT_SZ)
706 if (sz <= DATA_PKT_SZ)
712 if (!g_spi.spi_tx(&cmd, 1)) {
713 PRINT_ER("[wilc spi]: Failed data block cmd write, bus error...\n");
721 if (!g_spi.spi_tx(&b[ix], nbytes)) {
722 PRINT_ER("[wilc spi]: Failed data block write, bus error...\n");
730 if (!g_spi.crc_off) {
731 if (!g_spi.spi_tx(crc, 2)) {
732 PRINT_ER("[wilc spi]: Failed data block crc write, bus error...\n");
739 * No need to wait for response
749 /********************************************
751 * Spi Internal Read/Write Function
753 ********************************************/
755 static int spi_internal_write(u32 adr, u32 dat)
760 dat = BYTE_SWAP(dat);
762 result = spi_cmd_complete(CMD_INTERNAL_WRITE, adr, (u8 *)&dat, 4, 0);
763 if (result != N_OK) {
764 PRINT_ER("[wilc spi]: Failed internal write cmd...\n");
770 static int spi_internal_read(u32 adr, u32 *data)
774 result = spi_cmd_complete(CMD_INTERNAL_READ, adr, (u8 *)data, 4, 0);
775 if (result != N_OK) {
776 PRINT_ER("[wilc spi]: Failed internal read cmd...\n");
781 *data = BYTE_SWAP(*data);
787 /********************************************
791 ********************************************/
793 static int spi_write_reg(u32 addr, u32 data)
796 u8 cmd = CMD_SINGLE_WRITE;
800 data = BYTE_SWAP(data);
803 /* Clockless register*/
804 cmd = CMD_INTERNAL_WRITE;
808 result = spi_cmd_complete(cmd, addr, (u8 *)&data, 4, clockless);
809 if (result != N_OK) {
810 PRINT_ER("[wilc spi]: Failed cmd, write reg (%08x)...\n", addr);
816 static int spi_write(u32 addr, u8 *buf, u32 size)
819 u8 cmd = CMD_DMA_EXT_WRITE;
822 * has to be greated than 4
827 result = spi_cmd_complete(cmd, addr, NULL, size, 0);
828 if (result != N_OK) {
829 PRINT_ER("[wilc spi]: Failed cmd, write block (%08x)...\n", addr);
836 result = spi_data_write(buf, size);
837 if (result != N_OK) {
838 PRINT_ER("[wilc spi]: Failed block data write...\n");
844 static int spi_read_reg(u32 addr, u32 *data)
847 u8 cmd = CMD_SINGLE_READ;
851 /* PRINT_ER("***** read addr %d\n\n", addr); */
852 /* Clockless register*/
853 cmd = CMD_INTERNAL_READ;
857 result = spi_cmd_complete(cmd, addr, (u8 *)data, 4, clockless);
858 if (result != N_OK) {
859 PRINT_ER("[wilc spi]: Failed cmd, read reg (%08x)...\n", addr);
864 *data = BYTE_SWAP(*data);
870 static int spi_read(u32 addr, u8 *buf, u32 size)
872 u8 cmd = CMD_DMA_EXT_READ;
878 result = spi_cmd_complete(cmd, addr, buf, size, 0);
879 if (result != N_OK) {
880 PRINT_ER("[wilc spi]: Failed cmd, read block (%08x)...\n", addr);
887 /********************************************
891 ********************************************/
893 static int spi_clear_int(void)
897 if (!spi_read_reg(WILC_HOST_RX_CTRL_0, ®)) {
898 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_HOST_RX_CTRL_0);
902 spi_write_reg(WILC_HOST_RX_CTRL_0, reg);
906 static int spi_deinit(void *pv)
914 static int spi_sync(void)
920 * interrupt pin mux select
922 ret = spi_read_reg(WILC_PIN_MUX_0, ®);
924 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0);
928 ret = spi_write_reg(WILC_PIN_MUX_0, reg);
930 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0);
937 ret = spi_read_reg(WILC_INTR_ENABLE, ®);
939 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR_ENABLE);
943 ret = spi_write_reg(WILC_INTR_ENABLE, reg);
945 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR_ENABLE);
952 static int spi_init(wilc_wlan_inp_t *inp, wilc_debug_func func)
961 if (!spi_read_reg(0x1000, &chipid)) {
962 PRINT_ER("[wilc spi]: Fail cmd read chip id...\n");
968 memset(&g_spi, 0, sizeof(wilc_spi_t));
971 g_spi.os_context = inp->os_context.os_private;
972 if (inp->io_func.io_init) {
973 if (!inp->io_func.io_init(g_spi.os_context)) {
974 PRINT_ER("[wilc spi]: Failed io init bus...\n");
980 g_spi.spi_tx = inp->io_func.u.spi.spi_tx;
981 g_spi.spi_rx = inp->io_func.u.spi.spi_rx;
982 g_spi.spi_trx = inp->io_func.u.spi.spi_trx;
983 g_spi.spi_max_speed = inp->io_func.u.spi.spi_max_speed;
990 /* TODO: We can remove the CRC trials if there is a definite way to reset */
991 /* the SPI to it's initial value. */
992 if (!spi_internal_read(WILC_SPI_PROTOCOL_OFFSET, ®)) {
993 /* Read failed. Try with CRC off. This might happen when module
994 * is removed but chip isn't reset*/
996 PRINT_ER("[wilc spi]: Failed internal read protocol with CRC on, retyring with CRC off...\n");
997 if (!spi_internal_read(WILC_SPI_PROTOCOL_OFFSET, ®)) {
998 /* Reaad failed with both CRC on and off, something went bad */
999 PRINT_ER("[wilc spi]: Failed internal read protocol...\n");
1003 if (g_spi.crc_off == 0) {
1004 reg &= ~0xc; /* disable crc checking */
1007 if (!spi_internal_write(WILC_SPI_PROTOCOL_OFFSET, reg)) {
1008 PRINT_ER("[wilc spi %d]: Failed internal write protocol reg...\n", __LINE__);
1016 * make sure can read back chip id correctly
1018 if (!spi_read_reg(0x1000, &chipid)) {
1019 PRINT_ER("[wilc spi]: Fail cmd read chip id...\n");
1022 /* PRINT_ER("[wilc spi]: chipid (%08x)\n", chipid); */
1024 g_spi.has_thrpt_enh = 1;
1031 static void spi_max_bus_speed(void)
1033 g_spi.spi_max_speed();
1036 static void spi_default_bus_speed(void)
1040 static int spi_read_size(u32 *size)
1044 if (g_spi.has_thrpt_enh) {
1045 ret = spi_internal_read(0xe840 - WILC_SPI_REG_BASE, size);
1046 *size = *size & IRQ_DMA_WD_CNT_MASK;
1051 ret = spi_read_reg(WILC_VMM_TO_HOST_SIZE, &byte_cnt);
1053 PRINT_ER("[wilc spi]: Failed read WILC_VMM_TO_HOST_SIZE ...\n");
1056 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
1068 static int spi_read_int(u32 *int_status)
1072 if (g_spi.has_thrpt_enh) {
1073 ret = spi_internal_read(0xe840 - WILC_SPI_REG_BASE, int_status);
1078 ret = spi_read_reg(WILC_VMM_TO_HOST_SIZE, &byte_cnt);
1080 PRINT_ER("[wilc spi]: Failed read WILC_VMM_TO_HOST_SIZE ...\n");
1083 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
1094 spi_read_reg(0x1a90, &irq_flags);
1095 tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
1097 if (g_spi.nint > 5) {
1098 spi_read_reg(0x1a94, &irq_flags);
1099 tmp |= (((irq_flags >> 0) & 0x7) << (IRG_FLAGS_OFFSET + 5));
1105 unkmown_mask = ~((1ul << g_spi.nint) - 1);
1107 if ((tmp >> IRG_FLAGS_OFFSET) & unkmown_mask) {
1108 PRINT_ER("[wilc spi]: Unexpected interrupt (2): j=%d, tmp=%x, mask=%x\n", j, tmp, unkmown_mask);
1113 } while (happended);
1124 static int spi_clear_int_ext(u32 val)
1128 if (g_spi.has_thrpt_enh) {
1129 ret = spi_internal_write(0xe844 - WILC_SPI_REG_BASE, val);
1133 flags = val & (BIT(MAX_NUM_INT) - 1);
1138 for (i = 0; i < g_spi.nint; i++) {
1139 /* No matter what you write 1 or 0, it will clear interrupt. */
1141 ret = spi_write_reg(0x10c8 + i * 4, 1);
1147 PRINT_ER("[wilc spi]: Failed spi_write_reg, set reg %x ...\n", 0x10c8 + i * 4);
1150 for (i = g_spi.nint; i < MAX_NUM_INT; i++) {
1152 PRINT_ER("[wilc spi]: Unexpected interrupt cleared %d...\n", i);
1161 /* select VMM table 0 */
1162 if ((val & SEL_VMM_TBL0) == SEL_VMM_TBL0)
1164 /* select VMM table 1 */
1165 if ((val & SEL_VMM_TBL1) == SEL_VMM_TBL1)
1168 ret = spi_write_reg(WILC_VMM_TBL_CTL, tbl_ctl);
1170 PRINT_ER("[wilc spi]: fail write reg vmm_tbl_ctl...\n");
1174 if ((val & EN_VMM) == EN_VMM) {
1176 * enable vmm transfer.
1178 ret = spi_write_reg(WILC_VMM_CORE_CTL, 1);
1180 PRINT_ER("[wilc spi]: fail write reg vmm_core_ctl...\n");
1190 static int spi_sync_ext(int nint /* how mant interrupts to enable. */)
1195 if (nint > MAX_NUM_INT) {
1196 PRINT_ER("[wilc spi]: Too many interupts (%d)...\n", nint);
1203 * interrupt pin mux select
1205 ret = spi_read_reg(WILC_PIN_MUX_0, ®);
1207 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_PIN_MUX_0);
1211 ret = spi_write_reg(WILC_PIN_MUX_0, reg);
1213 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_PIN_MUX_0);
1220 ret = spi_read_reg(WILC_INTR_ENABLE, ®);
1222 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR_ENABLE);
1226 for (i = 0; (i < 5) && (nint > 0); i++, nint--) {
1227 reg |= (BIT((27 + i)));
1229 ret = spi_write_reg(WILC_INTR_ENABLE, reg);
1231 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR_ENABLE);
1235 ret = spi_read_reg(WILC_INTR2_ENABLE, ®);
1237 PRINT_ER("[wilc spi]: Failed read reg (%08x)...\n", WILC_INTR2_ENABLE);
1241 for (i = 0; (i < 3) && (nint > 0); i++, nint--) {
1245 ret = spi_read_reg(WILC_INTR2_ENABLE, ®);
1247 PRINT_ER("[wilc spi]: Failed write reg (%08x)...\n", WILC_INTR2_ENABLE);
1254 /********************************************
1256 * Global spi HIF function table
1258 ********************************************/
1259 wilc_hif_func_t hif_spi = {
1275 spi_default_bus_speed,