2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
22 * Purpose: Implement functions to access baseband
29 * BBuGetFrameTime - Calculate data frame transmitting time
30 * BBvCaculateParameter - Caculate PhyLength, PhyService and Phy Signal parameter for baseband Tx
31 * BBbReadEmbedded - Embedded read baseband register via MAC
32 * BBbWriteEmbedded - Embedded write baseband register via MAC
33 * BBbVT3253Init - VIA VT3253 baseband chip init code
36 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
37 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
38 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and BBvCalculateParameter().
39 * cancel the setting of MAC_REG_SOFTPWRCTL on BBbVT3253Init().
41 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
42 * Modified BBvLoopbackOn & BBvLoopbackOff().
53 /*--------------------- Static Classes ----------------------------*/
55 /*--------------------- Static Variables --------------------------*/
57 /*--------------------- Static Functions --------------------------*/
59 /*--------------------- Export Variables --------------------------*/
61 /*--------------------- Static Definitions -------------------------*/
63 /*--------------------- Static Classes ----------------------------*/
65 /*--------------------- Static Variables --------------------------*/
67 #define CB_VT3253_INIT_FOR_RFMD 446
68 static unsigned char byVT3253InitTab_RFMD[CB_VT3253_INIT_FOR_RFMD][2] = {
517 #define CB_VT3253B0_INIT_FOR_RFMD 256
518 static unsigned char byVT3253B0_RFMD[CB_VT3253B0_INIT_FOR_RFMD][2] = {
777 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
779 static unsigned char byVT3253B0_AGC4_RFMD2959[CB_VT3253B0_AGC_FOR_RFMD2959][2] = {
977 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
979 static unsigned char byVT3253B0_AIROHA2230[CB_VT3253B0_INIT_FOR_AIROHA2230][2] = {
1088 {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */
1238 #define CB_VT3253B0_INIT_FOR_UW2451 256
1240 static unsigned char byVT3253B0_UW2451[CB_VT3253B0_INIT_FOR_UW2451][2] = {
1349 {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */
1499 #define CB_VT3253B0_AGC 193
1501 static unsigned char byVT3253B0_AGC[CB_VT3253B0_AGC][2] = {
1697 static const unsigned short awcFrameTime[MAX_RATE] = {
1698 10, 20, 55, 110, 24, 36, 48, 72, 96, 144, 192, 216
1701 /*--------------------- Static Functions --------------------------*/
1705 s_ulGetRatio(struct vnt_private *priv);
1710 struct vnt_private *priv
1716 struct vnt_private *priv
1719 if (priv->dwRxAntennaSel == 0) {
1720 priv->dwRxAntennaSel = 1;
1721 if (priv->bTxRxAntInv == true)
1722 BBvSetRxAntennaMode(priv, ANT_A);
1724 BBvSetRxAntennaMode(priv, ANT_B);
1726 priv->dwRxAntennaSel = 0;
1727 if (priv->bTxRxAntInv == true)
1728 BBvSetRxAntennaMode(priv, ANT_B);
1730 BBvSetRxAntennaMode(priv, ANT_A);
1732 if (priv->dwTxAntennaSel == 0) {
1733 priv->dwTxAntennaSel = 1;
1734 BBvSetTxAntennaMode(priv, ANT_B);
1736 priv->dwTxAntennaSel = 0;
1737 BBvSetTxAntennaMode(priv, ANT_A);
1741 /*--------------------- Export Variables --------------------------*/
1743 * Description: Calculate data frame transmitting time
1747 * byPreambleType - Preamble Type
1748 * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1749 * cbFrameLength - Baseband Type
1753 * Return Value: FrameTime
1758 unsigned char byPreambleType,
1759 unsigned char byPktType,
1760 unsigned int cbFrameLength,
1761 unsigned short wRate
1764 unsigned int uFrameTime;
1765 unsigned int uPreamble;
1767 unsigned int uRateIdx = (unsigned int) wRate;
1768 unsigned int uRate = 0;
1770 if (uRateIdx > RATE_54M) {
1775 uRate = (unsigned int)awcFrameTime[uRateIdx];
1777 if (uRateIdx <= 3) { /* CCK mode */
1778 if (byPreambleType == 1) /* Short */
1783 uFrameTime = (cbFrameLength * 80) / uRate; /* ????? */
1784 uTmp = (uFrameTime * uRate) / 80;
1785 if (cbFrameLength != uTmp)
1788 return uPreamble + uFrameTime;
1790 uFrameTime = (cbFrameLength * 8 + 22) / uRate; /* ???????? */
1791 uTmp = ((uFrameTime * uRate) - 22) / 8;
1792 if (cbFrameLength != uTmp)
1795 uFrameTime = uFrameTime * 4; /* ??????? */
1796 if (byPktType != PK_TYPE_11A)
1797 uFrameTime += 6; /* ?????? */
1799 return 20 + uFrameTime; /* ?????? */
1803 * Description: Calculate Length, Service, and Signal fields of Phy for Tx
1807 * priv - Device Structure
1808 * frame_length - Tx Frame Length
1811 * struct vnt_phy_field *phy
1812 * - pointer to Phy Length field
1813 * - pointer to Phy Service field
1814 * - pointer to Phy Signal field
1816 * Return Value: none
1819 void vnt_get_phy_field(struct vnt_private *priv, u32 frame_length,
1820 u16 tx_rate, u8 pkt_type, struct vnt_phy_field *phy)
1826 u8 preamble_type = priv->byPreambleType;
1828 bit_count = frame_length * 8;
1839 count = bit_count / 2;
1841 if (preamble_type == 1)
1848 count = (bit_count * 10) / 55;
1849 tmp = (count * 55) / 10;
1851 if (tmp != bit_count)
1854 if (preamble_type == 1)
1861 count = bit_count / 11;
1864 if (tmp != bit_count) {
1867 if ((bit_count - tmp) <= 3)
1871 if (preamble_type == 1)
1878 if (pkt_type == PK_TYPE_11A)
1885 if (pkt_type == PK_TYPE_11A)
1892 if (pkt_type == PK_TYPE_11A)
1899 if (pkt_type == PK_TYPE_11A)
1906 if (pkt_type == PK_TYPE_11A)
1913 if (pkt_type == PK_TYPE_11A)
1920 if (pkt_type == PK_TYPE_11A)
1927 if (pkt_type == PK_TYPE_11A)
1933 if (pkt_type == PK_TYPE_11A)
1940 if (pkt_type == PK_TYPE_11B) {
1941 phy->service = 0x00;
1943 phy->service |= 0x80;
1944 phy->len = cpu_to_le16((u16)count);
1946 phy->service = 0x00;
1947 phy->len = cpu_to_le16((u16)frame_length);
1952 * Description: Read a byte from BASEBAND, by embedded programming
1956 * dwIoBase - I/O base address
1957 * byBBAddr - address of register in Baseband
1959 * pbyData - data read
1961 * Return Value: true if succeeded; false if failed.
1964 bool BBbReadEmbedded(void __iomem *dwIoBase, unsigned char byBBAddr, unsigned char *pbyData)
1967 unsigned char byValue;
1970 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
1973 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGR);
1974 /* W_MAX_TIMEOUT is the timeout period */
1975 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
1976 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
1977 if (byValue & BBREGCTL_DONE)
1982 VNSvInPortB(dwIoBase + MAC_REG_BBREGDATA, pbyData);
1984 if (ww == W_MAX_TIMEOUT) {
1986 pr_debug(" DBG_PORT80(0x30)\n");
1993 * Description: Write a Byte to BASEBAND, by embedded programming
1997 * dwIoBase - I/O base address
1998 * byBBAddr - address of register in Baseband
1999 * byData - data to write
2003 * Return Value: true if succeeded; false if failed.
2006 bool BBbWriteEmbedded(void __iomem *dwIoBase, unsigned char byBBAddr, unsigned char byData)
2009 unsigned char byValue;
2012 VNSvOutPortB(dwIoBase + MAC_REG_BBREGADR, byBBAddr);
2014 VNSvOutPortB(dwIoBase + MAC_REG_BBREGDATA, byData);
2016 /* turn on BBREGCTL_REGW */
2017 MACvRegBitsOn(dwIoBase, MAC_REG_BBREGCTL, BBREGCTL_REGW);
2018 /* W_MAX_TIMEOUT is the timeout period */
2019 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
2020 VNSvInPortB(dwIoBase + MAC_REG_BBREGCTL, &byValue);
2021 if (byValue & BBREGCTL_DONE)
2025 if (ww == W_MAX_TIMEOUT) {
2027 pr_debug(" DBG_PORT80(0x31)\n");
2034 * Description: VIA VT3253 Baseband chip init function
2038 * dwIoBase - I/O base address
2039 * byRevId - Revision ID
2040 * byRFType - RF type
2044 * Return Value: true if succeeded; false if failed.
2048 bool BBbVT3253Init(struct vnt_private *priv)
2050 bool bResult = true;
2052 void __iomem *dwIoBase = priv->PortOffset;
2053 unsigned char byRFType = priv->byRFType;
2054 unsigned char byLocalID = priv->byLocalID;
2056 if (byRFType == RF_RFMD2959) {
2057 if (byLocalID <= REV_ID_VT3253_A1) {
2058 for (ii = 0; ii < CB_VT3253_INIT_FOR_RFMD; ii++)
2059 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253InitTab_RFMD[ii][0], byVT3253InitTab_RFMD[ii][1]);
2062 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_RFMD; ii++)
2063 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_RFMD[ii][0], byVT3253B0_RFMD[ii][1]);
2065 for (ii = 0; ii < CB_VT3253B0_AGC_FOR_RFMD2959; ii++)
2066 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC4_RFMD2959[ii][0], byVT3253B0_AGC4_RFMD2959[ii][1]);
2068 VNSvOutPortD(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2069 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT(0));
2071 priv->abyBBVGA[0] = 0x18;
2072 priv->abyBBVGA[1] = 0x0A;
2073 priv->abyBBVGA[2] = 0x0;
2074 priv->abyBBVGA[3] = 0x0;
2075 priv->ldBmThreshold[0] = -70;
2076 priv->ldBmThreshold[1] = -50;
2077 priv->ldBmThreshold[2] = 0;
2078 priv->ldBmThreshold[3] = 0;
2079 } else if ((byRFType == RF_AIROHA) || (byRFType == RF_AL2230S)) {
2080 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2081 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2083 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2084 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2086 priv->abyBBVGA[0] = 0x1C;
2087 priv->abyBBVGA[1] = 0x10;
2088 priv->abyBBVGA[2] = 0x0;
2089 priv->abyBBVGA[3] = 0x0;
2090 priv->ldBmThreshold[0] = -70;
2091 priv->ldBmThreshold[1] = -48;
2092 priv->ldBmThreshold[2] = 0;
2093 priv->ldBmThreshold[3] = 0;
2094 } else if (byRFType == RF_UW2451) {
2095 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
2096 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_UW2451[ii][0], byVT3253B0_UW2451[ii][1]);
2098 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2099 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2101 VNSvOutPortB(dwIoBase + MAC_REG_ITRTMSET, 0x23);
2102 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT(0));
2104 priv->abyBBVGA[0] = 0x14;
2105 priv->abyBBVGA[1] = 0x0A;
2106 priv->abyBBVGA[2] = 0x0;
2107 priv->abyBBVGA[3] = 0x0;
2108 priv->ldBmThreshold[0] = -60;
2109 priv->ldBmThreshold[1] = -50;
2110 priv->ldBmThreshold[2] = 0;
2111 priv->ldBmThreshold[3] = 0;
2112 } else if (byRFType == RF_UW2452) {
2113 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_UW2451; ii++)
2114 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_UW2451[ii][0], byVT3253B0_UW2451[ii][1]);
2116 /* Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted) */
2117 /*bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);*/
2118 /* Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted) */
2119 /*bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);*/
2120 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2121 bResult &= BBbWriteEmbedded(dwIoBase, 0xd7, 0x06);
2123 /* {{RobertYu:20050125, request by Jack */
2124 bResult &= BBbWriteEmbedded(dwIoBase, 0x90, 0x20);
2125 bResult &= BBbWriteEmbedded(dwIoBase, 0x97, 0xeb);
2128 /* {{RobertYu:20050221, request by Jack */
2129 bResult &= BBbWriteEmbedded(dwIoBase, 0xa6, 0x00);
2130 bResult &= BBbWriteEmbedded(dwIoBase, 0xa8, 0x30);
2132 bResult &= BBbWriteEmbedded(dwIoBase, 0xb0, 0x58);
2134 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2135 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2137 priv->abyBBVGA[0] = 0x14;
2138 priv->abyBBVGA[1] = 0x0A;
2139 priv->abyBBVGA[2] = 0x0;
2140 priv->abyBBVGA[3] = 0x0;
2141 priv->ldBmThreshold[0] = -60;
2142 priv->ldBmThreshold[1] = -50;
2143 priv->ldBmThreshold[2] = 0;
2144 priv->ldBmThreshold[3] = 0;
2147 } else if (byRFType == RF_VT3226) {
2148 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2149 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2151 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2152 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2154 priv->abyBBVGA[0] = 0x1C;
2155 priv->abyBBVGA[1] = 0x10;
2156 priv->abyBBVGA[2] = 0x0;
2157 priv->abyBBVGA[3] = 0x0;
2158 priv->ldBmThreshold[0] = -70;
2159 priv->ldBmThreshold[1] = -48;
2160 priv->ldBmThreshold[2] = 0;
2161 priv->ldBmThreshold[3] = 0;
2162 /* Fix VT3226 DFC system timing issue */
2163 MACvSetRFLE_LatchBase(dwIoBase);
2164 /* {{ RobertYu: 20050104 */
2165 } else if (byRFType == RF_AIROHA7230) {
2166 for (ii = 0; ii < CB_VT3253B0_INIT_FOR_AIROHA2230; ii++)
2167 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AIROHA2230[ii][0], byVT3253B0_AIROHA2230[ii][1]);
2170 /* {{ RobertYu:20050223, request by JerryChung */
2171 /* Init ANT B select,TX Config CR09 = 0x61->0x45, 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted) */
2172 /*bResult &= BBbWriteEmbedded(dwIoBase,0x09,0x41);*/
2173 /* Init ANT B select,RX Config CR10 = 0x28->0x2A, 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted) */
2174 /*bResult &= BBbWriteEmbedded(dwIoBase,0x0a,0x28);*/
2175 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2176 bResult &= BBbWriteEmbedded(dwIoBase, 0xd7, 0x06);
2179 for (ii = 0; ii < CB_VT3253B0_AGC; ii++)
2180 bResult &= BBbWriteEmbedded(dwIoBase, byVT3253B0_AGC[ii][0], byVT3253B0_AGC[ii][1]);
2182 priv->abyBBVGA[0] = 0x1C;
2183 priv->abyBBVGA[1] = 0x10;
2184 priv->abyBBVGA[2] = 0x0;
2185 priv->abyBBVGA[3] = 0x0;
2186 priv->ldBmThreshold[0] = -70;
2187 priv->ldBmThreshold[1] = -48;
2188 priv->ldBmThreshold[2] = 0;
2189 priv->ldBmThreshold[3] = 0;
2192 /* No VGA Table now */
2193 priv->bUpdateBBVGA = false;
2194 priv->abyBBVGA[0] = 0x1C;
2197 if (byLocalID > REV_ID_VT3253_A1) {
2198 BBbWriteEmbedded(dwIoBase, 0x04, 0x7F);
2199 BBbWriteEmbedded(dwIoBase, 0x0D, 0x01);
2206 * Description: Set ShortSlotTime mode
2210 * priv - Device Structure
2214 * Return Value: none
2218 BBvSetShortSlotTime(struct vnt_private *priv)
2220 unsigned char byBBRxConf = 0;
2221 unsigned char byBBVGA = 0;
2223 BBbReadEmbedded(priv->PortOffset, 0x0A, &byBBRxConf); /* CR10 */
2225 if (priv->bShortSlotTime)
2226 byBBRxConf &= 0xDF; /* 1101 1111 */
2228 byBBRxConf |= 0x20; /* 0010 0000 */
2230 /* patch for 3253B0 Baseband with Cardbus module */
2231 BBbReadEmbedded(priv->PortOffset, 0xE7, &byBBVGA);
2232 if (byBBVGA == priv->abyBBVGA[0])
2233 byBBRxConf |= 0x20; /* 0010 0000 */
2235 BBbWriteEmbedded(priv->PortOffset, 0x0A, byBBRxConf); /* CR10 */
2238 void BBvSetVGAGainOffset(struct vnt_private *priv, unsigned char byData)
2240 unsigned char byBBRxConf = 0;
2242 BBbWriteEmbedded(priv->PortOffset, 0xE7, byData);
2244 BBbReadEmbedded(priv->PortOffset, 0x0A, &byBBRxConf); /* CR10 */
2245 /* patch for 3253B0 Baseband with Cardbus module */
2246 if (byData == priv->abyBBVGA[0])
2247 byBBRxConf |= 0x20; /* 0010 0000 */
2248 else if (priv->bShortSlotTime)
2249 byBBRxConf &= 0xDF; /* 1101 1111 */
2251 byBBRxConf |= 0x20; /* 0010 0000 */
2252 priv->byBBVGACurrent = byData;
2253 BBbWriteEmbedded(priv->PortOffset, 0x0A, byBBRxConf); /* CR10 */
2257 * Description: Baseband SoftwareReset
2261 * dwIoBase - I/O base address
2265 * Return Value: none
2269 BBvSoftwareReset(struct vnt_private *priv)
2271 void __iomem *dwIoBase = priv->PortOffset;
2273 BBbWriteEmbedded(dwIoBase, 0x50, 0x40);
2274 BBbWriteEmbedded(dwIoBase, 0x50, 0);
2275 BBbWriteEmbedded(dwIoBase, 0x9C, 0x01);
2276 BBbWriteEmbedded(dwIoBase, 0x9C, 0);
2280 * Description: Baseband Power Save Mode ON
2284 * dwIoBase - I/O base address
2288 * Return Value: none
2292 BBvPowerSaveModeON(void __iomem *dwIoBase)
2294 unsigned char byOrgData;
2296 BBbReadEmbedded(dwIoBase, 0x0D, &byOrgData);
2297 byOrgData |= BIT(0);
2298 BBbWriteEmbedded(dwIoBase, 0x0D, byOrgData);
2302 * Description: Baseband Power Save Mode OFF
2306 * dwIoBase - I/O base address
2310 * Return Value: none
2314 BBvPowerSaveModeOFF(void __iomem *dwIoBase)
2316 unsigned char byOrgData;
2318 BBbReadEmbedded(dwIoBase, 0x0D, &byOrgData);
2319 byOrgData &= ~(BIT(0));
2320 BBbWriteEmbedded(dwIoBase, 0x0D, byOrgData);
2324 * Description: Set Tx Antenna mode
2328 * priv - Device Structure
2329 * byAntennaMode - Antenna Mode
2333 * Return Value: none
2338 BBvSetTxAntennaMode(struct vnt_private *priv, unsigned char byAntennaMode)
2340 void __iomem *dwIoBase = priv->PortOffset;
2341 unsigned char byBBTxConf;
2343 BBbReadEmbedded(dwIoBase, 0x09, &byBBTxConf); /* CR09 */
2344 if (byAntennaMode == ANT_DIVERSITY) {
2345 /* bit 1 is diversity */
2347 } else if (byAntennaMode == ANT_A) {
2348 /* bit 2 is ANTSEL */
2349 byBBTxConf &= 0xF9; /* 1111 1001 */
2350 } else if (byAntennaMode == ANT_B) {
2351 byBBTxConf &= 0xFD; /* 1111 1101 */
2354 BBbWriteEmbedded(dwIoBase, 0x09, byBBTxConf); /* CR09 */
2358 * Description: Set Rx Antenna mode
2362 * priv - Device Structure
2363 * byAntennaMode - Antenna Mode
2367 * Return Value: none
2372 BBvSetRxAntennaMode(struct vnt_private *priv, unsigned char byAntennaMode)
2374 void __iomem *dwIoBase = priv->PortOffset;
2375 unsigned char byBBRxConf;
2377 BBbReadEmbedded(dwIoBase, 0x0A, &byBBRxConf); /* CR10 */
2378 if (byAntennaMode == ANT_DIVERSITY) {
2381 } else if (byAntennaMode == ANT_A) {
2382 byBBRxConf &= 0xFC; /* 1111 1100 */
2383 } else if (byAntennaMode == ANT_B) {
2384 byBBRxConf &= 0xFE; /* 1111 1110 */
2387 BBbWriteEmbedded(dwIoBase, 0x0A, byBBRxConf); /* CR10 */
2391 * Description: BBvSetDeepSleep
2395 * priv - Device Structure
2399 * Return Value: none
2403 BBvSetDeepSleep(struct vnt_private *priv, unsigned char byLocalID)
2405 void __iomem *dwIoBase = priv->PortOffset;
2407 BBbWriteEmbedded(dwIoBase, 0x0C, 0x17); /* CR12 */
2408 BBbWriteEmbedded(dwIoBase, 0x0D, 0xB9); /* CR13 */
2412 BBvExitDeepSleep(struct vnt_private *priv, unsigned char byLocalID)
2414 void __iomem *dwIoBase = priv->PortOffset;
2416 BBbWriteEmbedded(dwIoBase, 0x0C, 0x00); /* CR12 */
2417 BBbWriteEmbedded(dwIoBase, 0x0D, 0x01); /* CR13 */
2422 s_ulGetRatio(struct vnt_private *priv)
2424 unsigned long ulRatio = 0;
2425 unsigned long ulMaxPacket;
2426 unsigned long ulPacketNum;
2428 /* This is a thousand-ratio */
2429 ulMaxPacket = priv->uNumSQ3[RATE_54M];
2430 if (priv->uNumSQ3[RATE_54M] != 0) {
2431 ulPacketNum = priv->uNumSQ3[RATE_54M];
2432 ulRatio = (ulPacketNum * 1000 / priv->uDiversityCnt);
2433 ulRatio += TOP_RATE_54M;
2435 if (priv->uNumSQ3[RATE_48M] > ulMaxPacket) {
2436 ulPacketNum = priv->uNumSQ3[RATE_54M] + priv->uNumSQ3[RATE_48M];
2437 ulRatio = (ulPacketNum * 1000 / priv->uDiversityCnt);
2438 ulRatio += TOP_RATE_48M;
2439 ulMaxPacket = priv->uNumSQ3[RATE_48M];
2441 if (priv->uNumSQ3[RATE_36M] > ulMaxPacket) {
2442 ulPacketNum = priv->uNumSQ3[RATE_54M] + priv->uNumSQ3[RATE_48M] +
2443 priv->uNumSQ3[RATE_36M];
2444 ulRatio = (ulPacketNum * 1000 / priv->uDiversityCnt);
2445 ulRatio += TOP_RATE_36M;
2446 ulMaxPacket = priv->uNumSQ3[RATE_36M];
2448 if (priv->uNumSQ3[RATE_24M] > ulMaxPacket) {
2449 ulPacketNum = priv->uNumSQ3[RATE_54M] + priv->uNumSQ3[RATE_48M] +
2450 priv->uNumSQ3[RATE_36M] + priv->uNumSQ3[RATE_24M];
2451 ulRatio = (ulPacketNum * 1000 / priv->uDiversityCnt);
2452 ulRatio += TOP_RATE_24M;
2453 ulMaxPacket = priv->uNumSQ3[RATE_24M];
2455 if (priv->uNumSQ3[RATE_18M] > ulMaxPacket) {
2456 ulPacketNum = priv->uNumSQ3[RATE_54M] + priv->uNumSQ3[RATE_48M] +
2457 priv->uNumSQ3[RATE_36M] + priv->uNumSQ3[RATE_24M] +
2458 priv->uNumSQ3[RATE_18M];
2459 ulRatio = (ulPacketNum * 1000 / priv->uDiversityCnt);
2460 ulRatio += TOP_RATE_18M;
2461 ulMaxPacket = priv->uNumSQ3[RATE_18M];
2463 if (priv->uNumSQ3[RATE_12M] > ulMaxPacket) {
2464 ulPacketNum = priv->uNumSQ3[RATE_54M] + priv->uNumSQ3[RATE_48M] +
2465 priv->uNumSQ3[RATE_36M] + priv->uNumSQ3[RATE_24M] +
2466 priv->uNumSQ3[RATE_18M] + priv->uNumSQ3[RATE_12M];
2467 ulRatio = (ulPacketNum * 1000 / priv->uDiversityCnt);
2468 ulRatio += TOP_RATE_12M;
2469 ulMaxPacket = priv->uNumSQ3[RATE_12M];
2471 if (priv->uNumSQ3[RATE_11M] > ulMaxPacket) {
2472 ulPacketNum = priv->uDiversityCnt - priv->uNumSQ3[RATE_1M] -
2473 priv->uNumSQ3[RATE_2M] - priv->uNumSQ3[RATE_5M] -
2474 priv->uNumSQ3[RATE_6M] - priv->uNumSQ3[RATE_9M];
2475 ulRatio = (ulPacketNum * 1000 / priv->uDiversityCnt);
2476 ulRatio += TOP_RATE_11M;
2477 ulMaxPacket = priv->uNumSQ3[RATE_11M];
2479 if (priv->uNumSQ3[RATE_9M] > ulMaxPacket) {
2480 ulPacketNum = priv->uDiversityCnt - priv->uNumSQ3[RATE_1M] -
2481 priv->uNumSQ3[RATE_2M] - priv->uNumSQ3[RATE_5M] -
2482 priv->uNumSQ3[RATE_6M];
2483 ulRatio = (ulPacketNum * 1000 / priv->uDiversityCnt);
2484 ulRatio += TOP_RATE_9M;
2485 ulMaxPacket = priv->uNumSQ3[RATE_9M];
2487 if (priv->uNumSQ3[RATE_6M] > ulMaxPacket) {
2488 ulPacketNum = priv->uDiversityCnt - priv->uNumSQ3[RATE_1M] -
2489 priv->uNumSQ3[RATE_2M] - priv->uNumSQ3[RATE_5M];
2490 ulRatio = (ulPacketNum * 1000 / priv->uDiversityCnt);
2491 ulRatio += TOP_RATE_6M;
2492 ulMaxPacket = priv->uNumSQ3[RATE_6M];
2494 if (priv->uNumSQ3[RATE_5M] > ulMaxPacket) {
2495 ulPacketNum = priv->uDiversityCnt - priv->uNumSQ3[RATE_1M] -
2496 priv->uNumSQ3[RATE_2M];
2497 ulRatio = (ulPacketNum * 1000 / priv->uDiversityCnt);
2498 ulRatio += TOP_RATE_55M;
2499 ulMaxPacket = priv->uNumSQ3[RATE_5M];
2501 if (priv->uNumSQ3[RATE_2M] > ulMaxPacket) {
2502 ulPacketNum = priv->uDiversityCnt - priv->uNumSQ3[RATE_1M];
2503 ulRatio = (ulPacketNum * 1000 / priv->uDiversityCnt);
2504 ulRatio += TOP_RATE_2M;
2505 ulMaxPacket = priv->uNumSQ3[RATE_2M];
2507 if (priv->uNumSQ3[RATE_1M] > ulMaxPacket) {
2508 ulPacketNum = priv->uDiversityCnt;
2509 ulRatio = (ulPacketNum * 1000 / priv->uDiversityCnt);
2510 ulRatio += TOP_RATE_1M;
2517 BBvClearAntDivSQ3Value(struct vnt_private *priv)
2521 priv->uDiversityCnt = 0;
2522 for (ii = 0; ii < MAX_RATE; ii++)
2523 priv->uNumSQ3[ii] = 0;
2527 * Description: Antenna Diversity
2531 * priv - Device Structure
2532 * byRSR - RSR from received packet
2533 * bySQ3 - SQ3 value from received packet
2537 * Return Value: none
2541 void BBvAntennaDiversity(struct vnt_private *priv,
2542 unsigned char byRxRate, unsigned char bySQ3)
2544 if ((byRxRate >= MAX_RATE) || (priv->wAntDiversityMaxRate >= MAX_RATE))
2547 priv->uDiversityCnt++;
2549 priv->uNumSQ3[byRxRate]++;
2551 if (priv->byAntennaState == 0) {
2552 if (priv->uDiversityCnt > priv->ulDiversityNValue) {
2553 pr_debug("ulDiversityNValue=[%d],54M-[%d]\n",
2554 (int)priv->ulDiversityNValue,
2555 (int)priv->uNumSQ3[(int)priv->wAntDiversityMaxRate]);
2557 if (priv->uNumSQ3[priv->wAntDiversityMaxRate] < priv->uDiversityCnt/2) {
2558 priv->ulRatio_State0 = s_ulGetRatio(priv);
2559 pr_debug("SQ3_State0, rate = [%08x]\n",
2560 (int)priv->ulRatio_State0);
2562 if (priv->byTMax == 0)
2564 pr_debug("1.[%08x], uNumSQ3[%d]=%d, %d\n",
2565 (int)priv->ulRatio_State0,
2566 (int)priv->wAntDiversityMaxRate,
2567 (int)priv->uNumSQ3[(int)priv->wAntDiversityMaxRate],
2568 (int)priv->uDiversityCnt);
2570 s_vChangeAntenna(priv);
2571 priv->byAntennaState = 1;
2572 del_timer(&priv->TimerSQ3Tmax3);
2573 del_timer(&priv->TimerSQ3Tmax2);
2574 priv->TimerSQ3Tmax1.expires = RUN_AT(priv->byTMax * HZ);
2575 add_timer(&priv->TimerSQ3Tmax1);
2578 priv->TimerSQ3Tmax3.expires = RUN_AT(priv->byTMax3 * HZ);
2579 add_timer(&priv->TimerSQ3Tmax3);
2581 BBvClearAntDivSQ3Value(priv);
2584 } else { /* byAntennaState == 1 */
2586 if (priv->uDiversityCnt > priv->ulDiversityMValue) {
2587 del_timer(&priv->TimerSQ3Tmax1);
2589 priv->ulRatio_State1 = s_ulGetRatio(priv);
2590 pr_debug("RX:SQ3_State1, rate0 = %08x,rate1 = %08x\n",
2591 (int)priv->ulRatio_State0,
2592 (int)priv->ulRatio_State1);
2594 if (priv->ulRatio_State1 < priv->ulRatio_State0) {
2595 pr_debug("2.[%08x][%08x], uNumSQ3[%d]=%d, %d\n",
2596 (int)priv->ulRatio_State0,
2597 (int)priv->ulRatio_State1,
2598 (int)priv->wAntDiversityMaxRate,
2599 (int)priv->uNumSQ3[(int)priv->wAntDiversityMaxRate],
2600 (int)priv->uDiversityCnt);
2602 s_vChangeAntenna(priv);
2603 priv->TimerSQ3Tmax3.expires = RUN_AT(priv->byTMax3 * HZ);
2604 priv->TimerSQ3Tmax2.expires = RUN_AT(priv->byTMax2 * HZ);
2605 add_timer(&priv->TimerSQ3Tmax3);
2606 add_timer(&priv->TimerSQ3Tmax2);
2608 priv->byAntennaState = 0;
2609 BBvClearAntDivSQ3Value(priv);
2611 } /* byAntennaState */
2617 * Timer for SQ3 antenna diversity
2624 * Return Value: none
2633 struct vnt_private *priv = (struct vnt_private *)data;
2634 unsigned long flags;
2636 pr_debug("TimerSQ3CallBack...\n");
2638 spin_lock_irqsave(&priv->lock, flags);
2640 pr_debug("3.[%08x][%08x], %d\n",
2641 (int)priv->ulRatio_State0, (int)priv->ulRatio_State1,
2642 (int)priv->uDiversityCnt);
2644 s_vChangeAntenna(priv);
2645 priv->byAntennaState = 0;
2646 BBvClearAntDivSQ3Value(priv);
2648 priv->TimerSQ3Tmax3.expires = RUN_AT(priv->byTMax3 * HZ);
2649 priv->TimerSQ3Tmax2.expires = RUN_AT(priv->byTMax2 * HZ);
2650 add_timer(&priv->TimerSQ3Tmax3);
2651 add_timer(&priv->TimerSQ3Tmax2);
2653 spin_unlock_irqrestore(&priv->lock, flags);
2659 * Timer for SQ3 antenna diversity
2664 * hDeviceContext - Pointer to the adapter
2670 * Return Value: none
2675 TimerState1CallBack(
2679 struct vnt_private *priv = (struct vnt_private *)data;
2680 unsigned long flags;
2682 pr_debug("TimerState1CallBack...\n");
2684 spin_lock_irqsave(&priv->lock, flags);
2686 if (priv->uDiversityCnt < priv->ulDiversityMValue/100) {
2687 s_vChangeAntenna(priv);
2688 priv->TimerSQ3Tmax3.expires = RUN_AT(priv->byTMax3 * HZ);
2689 priv->TimerSQ3Tmax2.expires = RUN_AT(priv->byTMax2 * HZ);
2690 add_timer(&priv->TimerSQ3Tmax3);
2691 add_timer(&priv->TimerSQ3Tmax2);
2693 priv->ulRatio_State1 = s_ulGetRatio(priv);
2694 pr_debug("SQ3_State1, rate0 = %08x,rate1 = %08x\n",
2695 (int)priv->ulRatio_State0,
2696 (int)priv->ulRatio_State1);
2698 if (priv->ulRatio_State1 < priv->ulRatio_State0) {
2699 pr_debug("2.[%08x][%08x], uNumSQ3[%d]=%d, %d\n",
2700 (int)priv->ulRatio_State0,
2701 (int)priv->ulRatio_State1,
2702 (int)priv->wAntDiversityMaxRate,
2703 (int)priv->uNumSQ3[(int)priv->wAntDiversityMaxRate],
2704 (int)priv->uDiversityCnt);
2706 s_vChangeAntenna(priv);
2708 priv->TimerSQ3Tmax3.expires = RUN_AT(priv->byTMax3 * HZ);
2709 priv->TimerSQ3Tmax2.expires = RUN_AT(priv->byTMax2 * HZ);
2710 add_timer(&priv->TimerSQ3Tmax3);
2711 add_timer(&priv->TimerSQ3Tmax2);
2714 priv->byAntennaState = 0;
2715 BBvClearAntDivSQ3Value(priv);
2717 spin_unlock_irqrestore(&priv->lock, flags);