4 * DSP-BIOS Bridge driver support functions for TI OMAP processors.
6 * Processor Manager Driver for TI OMAP3430 EVM.
8 * Copyright (C) 2005-2006 Texas Instruments, Inc.
10 * This package is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
21 #include <linux/types.h>
22 /* ----------------------------------- Host OS */
23 #include <dspbridge/host_os.h>
25 #include <linux/mmzone.h>
27 /* ----------------------------------- DSP/BIOS Bridge */
28 #include <dspbridge/dbdefs.h>
30 /* ----------------------------------- OS Adaptation Layer */
31 #include <dspbridge/drv.h>
32 #include <dspbridge/sync.h>
34 /* ------------------------------------ Hardware Abstraction Layer */
38 /* ----------------------------------- Link Driver */
39 #include <dspbridge/dspdefs.h>
40 #include <dspbridge/dspchnl.h>
41 #include <dspbridge/dspdeh.h>
42 #include <dspbridge/dspio.h>
43 #include <dspbridge/dspmsg.h>
44 #include <dspbridge/pwr.h>
45 #include <dspbridge/io_sm.h>
47 /* ----------------------------------- Platform Manager */
48 #include <dspbridge/dev.h>
49 #include <dspbridge/dspapi.h>
50 #include <dspbridge/dmm.h>
51 #include <dspbridge/wdt.h>
53 /* ----------------------------------- Local */
55 #include "_tiomap_pwr.h"
56 #include "tiomap_io.h"
58 /* Offset in shared mem to write to in order to synchronize start with DSP */
59 #define SHMSYNCOFFSET 4 /* GPP byte offset */
61 #define BUFFERSIZE 1024
63 #define TIHELEN_ACKTIMEOUT 10000
65 #define MMU_SECTION_ADDR_MASK 0xFFF00000
66 #define MMU_SSECTION_ADDR_MASK 0xFF000000
67 #define MMU_LARGE_PAGE_MASK 0xFFFF0000
68 #define MMU_SMALL_PAGE_MASK 0xFFFFF000
69 #define OMAP3_IVA2_BOOTADDR_MASK 0xFFFFFC00
70 #define PAGES_II_LVL_TABLE 512
71 #define PHYS_TO_PAGE(phys) pfn_to_page((phys) >> PAGE_SHIFT)
74 * This is a totally ugly layer violation, but needed until
75 * omap_ctrl_set_dsp_boot*() are provided.
77 #define OMAP3_IVA2_BOOTMOD_IDLE 1
78 #define OMAP2_CONTROL_GENERAL 0x270
79 #define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
80 #define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
82 /* Forward Declarations: */
83 static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt);
84 static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
86 u32 dsp_addr, u32 ul_num_bytes,
88 static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
90 static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
92 static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt);
93 static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
95 u32 dsp_addr, u32 ul_num_bytes,
97 static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
99 static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
100 u32 dsp_dest_addr, u32 dsp_src_addr,
101 u32 ul_num_bytes, u32 mem_type);
102 static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
103 u8 *host_buff, u32 dsp_addr,
104 u32 ul_num_bytes, u32 mem_type);
105 static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt,
106 u32 ul_mpu_addr, u32 virt_addr,
107 u32 ul_num_bytes, u32 ul_map_attr,
108 struct page **mapped_pages);
109 static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt,
110 u32 virt_addr, u32 ul_num_bytes);
111 static int bridge_dev_create(struct bridge_dev_context
113 struct dev_object *hdev_obj,
114 struct cfg_hostres *config_param);
115 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
116 u32 dw_cmd, void *pargs);
117 static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt);
118 static u32 user_va2_pa(struct mm_struct *mm, u32 address);
119 static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa,
121 struct hw_mmu_map_attrs_t *map_attrs);
122 static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
123 u32 size, struct hw_mmu_map_attrs_t *attrs);
124 static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
125 u32 ul_mpu_addr, u32 virt_addr,
127 struct hw_mmu_map_attrs_t *hw_attrs);
129 bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr);
131 /* ----------------------------------- Globals */
133 /* Attributes of L2 page tables for DSP MMU */
135 u32 num_entries; /* Number of valid PTEs in the L2 PT */
138 /* Attributes used to manage the DSP MMU page tables */
139 struct pg_table_attrs {
140 spinlock_t pg_lock; /* Critical section object handle */
142 u32 l1_base_pa; /* Physical address of the L1 PT */
143 u32 l1_base_va; /* Virtual address of the L1 PT */
144 u32 l1_size; /* Size of the L1 PT */
146 /* Physical address of Allocated mem for L1 table. May not be aligned */
148 /* Virtual address of Allocated mem for L1 table. May not be aligned */
150 /* Size of consistent memory allocated for L1 table.
151 * May not be aligned */
153 u32 l2_base_pa; /* Physical address of the L2 PT */
154 u32 l2_base_va; /* Virtual address of the L2 PT */
155 u32 l2_size; /* Size of the L2 PT */
157 /* Physical address of Allocated mem for L2 table. May not be aligned */
159 /* Virtual address of Allocated mem for L2 table. May not be aligned */
161 /* Size of consistent memory allocated for L2 table.
162 * May not be aligned */
164 u32 l2_num_pages; /* Number of allocated L2 PT */
165 /* Array [l2_num_pages] of L2 PT info structs */
166 struct page_info *pg_info;
170 * This Bridge driver's function interface table.
172 static struct bridge_drv_interface drv_interface_fxns = {
173 /* Bridge API ver. for which this bridge driver is built. */
174 BRD_API_MAJOR_VERSION,
175 BRD_API_MINOR_VERSION,
185 bridge_brd_set_state,
187 bridge_brd_mem_write,
189 bridge_brd_mem_un_map,
190 /* The following CHNL functions are provided by chnl_io.lib: */
195 bridge_chnl_add_io_req,
197 bridge_chnl_cancel_io,
198 bridge_chnl_flush_io,
199 bridge_chnl_get_info,
200 bridge_chnl_get_mgr_info,
202 bridge_chnl_register_notify,
203 /* The following IO functions are provided by chnl_io.lib: */
207 bridge_io_get_proc_load,
208 /* The following msg_ctrl functions are provided by chnl_io.lib: */
210 bridge_msg_create_queue,
212 bridge_msg_delete_queue,
215 bridge_msg_register_notify,
216 bridge_msg_set_queue_id,
219 static struct notifier_block dsp_mbox_notifier = {
220 .notifier_call = io_mbox_msg,
223 static inline void flush_all(struct bridge_dev_context *dev_context)
225 if (dev_context->brd_state == BRD_DSP_HIBERNATION ||
226 dev_context->brd_state == BRD_HIBERNATION)
227 wake_dsp(dev_context, NULL);
229 hw_mmu_tlb_flush_all(dev_context->dsp_mmu_base);
232 static void bad_page_dump(u32 pa, struct page *pg)
234 pr_emerg("DSPBRIDGE: MAP function: COUNT 0 FOR PA 0x%x\n", pa);
235 pr_emerg("Bad page state in process '%s'\n"
236 "page:%p flags:0x%0*lx mapping:%p mapcount:%d count:%d\n"
238 current->comm, pg, (int)(2 * sizeof(unsigned long)),
239 (unsigned long)pg->flags, pg->mapping,
240 page_mapcount(pg), page_count(pg));
245 * ======== bridge_drv_entry ========
247 * Bridge Driver entry point.
249 void bridge_drv_entry(struct bridge_drv_interface **drv_intf,
250 const char *driver_file_name)
252 if (strcmp(driver_file_name, "UMA") == 0)
253 *drv_intf = &drv_interface_fxns;
255 dev_dbg(bridge, "%s Unknown Bridge file name", __func__);
260 * ======== bridge_brd_monitor ========
262 * This bridge_brd_monitor puts DSP into a Loadable state.
263 * i.e Application can load and start the device.
266 * Device in 'OFF' state.
268 static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt)
270 struct bridge_dev_context *dev_context = dev_ctxt;
272 struct omap_dsp_platform_data *pdata =
273 omap_dspbridge_dev->dev.platform_data;
275 temp = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
276 OMAP_POWERSTATEST_MASK;
277 if (!(temp & 0x02)) {
278 /* IVA2 is not in ON state */
279 /* Read and set PM_PWSTCTRL_IVA2 to ON */
280 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
281 PWRDM_POWER_ON, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
282 /* Set the SW supervised state transition */
283 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP,
284 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
286 /* Wait until the state has moved to ON */
287 while ((*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
288 OMAP_INTRANSITION_MASK)
290 /* Disable Automatic transition */
291 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_DISABLE_AUTO,
292 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
294 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
295 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
296 dsp_clk_enable(DSP_CLK_IVA2);
298 /* set the device state to IDLE */
299 dev_context->brd_state = BRD_IDLE;
305 * ======== bridge_brd_read ========
307 * Reads buffers for DSP memory.
309 static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
310 u8 *host_buff, u32 dsp_addr,
311 u32 ul_num_bytes, u32 mem_type)
314 struct bridge_dev_context *dev_context = dev_ctxt;
316 u32 dsp_base_addr = dev_ctxt->dsp_base_addr;
318 if (dsp_addr < dev_context->dsp_start_add) {
322 /* change here to account for the 3 bands of the DSP internal memory */
323 if ((dsp_addr - dev_context->dsp_start_add) <
324 dev_context->internal_size) {
325 offset = dsp_addr - dev_context->dsp_start_add;
327 status = read_ext_dsp_data(dev_context, host_buff, dsp_addr,
328 ul_num_bytes, mem_type);
331 /* copy the data from DSP memory, */
332 memcpy(host_buff, (void *)(dsp_base_addr + offset), ul_num_bytes);
337 * ======== bridge_brd_set_state ========
339 * This routine updates the Board status.
341 static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
345 struct bridge_dev_context *dev_context = dev_ctxt;
347 dev_context->brd_state = brd_state;
352 * ======== bridge_brd_start ========
354 * Initializes DSP MMU and Starts DSP.
357 * a) DSP domain is 'ACTIVE'.
358 * b) DSP_RST1 is asserted.
359 * b) DSP_RST2 is released.
361 static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
365 struct bridge_dev_context *dev_context = dev_ctxt;
366 u32 dw_sync_addr = 0;
367 u32 ul_shm_base; /* Gpp Phys SM base addr(byte) */
368 u32 ul_shm_base_virt; /* Dsp Virt SM base addr */
369 u32 ul_tlb_base_virt; /* Base of MMU TLB entry */
370 /* Offset of shm_base_virt from tlb_base_virt */
371 u32 ul_shm_offset_virt;
373 s32 itmp_entry_ndx = 0; /* DSP-MMU TLB entry base address */
374 struct cfg_hostres *resources = NULL;
378 u32 ul_bios_gp_timer;
380 struct io_mgr *hio_mgr;
381 u32 ul_load_monitor_timer;
383 struct omap_dsp_platform_data *pdata =
384 omap_dspbridge_dev->dev.platform_data;
386 /* The device context contains all the mmu setup info from when the
387 * last dsp base image was loaded. The first entry is always
389 /* Get SHM_BEG - convert to byte address */
390 (void)dev_get_symbol(dev_context->dev_obj, SHMBASENAME,
392 ul_shm_base_virt *= DSPWORDSIZE;
393 /* DSP Virtual address */
394 ul_tlb_base_virt = dev_context->atlb_entry[0].dsp_va;
396 ul_shm_base_virt - (ul_tlb_base_virt * DSPWORDSIZE);
397 /* Kernel logical address */
398 ul_shm_base = dev_context->atlb_entry[0].gpp_va + ul_shm_offset_virt;
400 /* 2nd wd is used as sync field */
401 dw_sync_addr = ul_shm_base + SHMSYNCOFFSET;
402 /* Write a signature into the shm base + offset; this will
403 * get cleared when the DSP program starts. */
404 if ((ul_shm_base_virt == 0) || (ul_shm_base == 0)) {
405 pr_err("%s: Illegal SM base\n", __func__);
408 __raw_writel(0xffffffff, dw_sync_addr);
411 resources = dev_context->resources;
415 /* Assert RST1 i.e only the RST only for DSP megacell */
418 * XXX: ioremapping MUST be removed once ctrl
419 * function is made available.
421 void __iomem *ctrl = ioremap(OMAP343X_CTRL_BASE, SZ_4K);
425 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
426 OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD,
428 /* Mask address with 1K for compatibility */
429 __raw_writel(dsp_addr & OMAP3_IVA2_BOOTADDR_MASK,
430 ctrl + OMAP343X_CONTROL_IVA2_BOOTADDR);
432 * Set bootmode to self loop if dsp_debug flag is true
434 __raw_writel((dsp_debug) ? OMAP3_IVA2_BOOTMOD_IDLE : 0,
435 ctrl + OMAP343X_CONTROL_IVA2_BOOTMOD);
441 /* Reset and Unreset the RST2, so that BOOTADDR is copied to
442 * IVA2 SYSC register */
443 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK,
444 OMAP3430_RST2_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
446 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
447 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
450 /* Disbale the DSP MMU */
451 hw_mmu_disable(resources->dmmu_base);
453 hw_mmu_twl_disable(resources->dmmu_base);
455 /* Only make TLB entry if both addresses are non-zero */
456 for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB;
458 struct bridge_ioctl_extproc *e = &dev_context->atlb_entry[entry_ndx];
459 struct hw_mmu_map_attrs_t map_attrs = {
460 .endianism = e->endianism,
461 .element_size = e->elem_size,
462 .mixed_size = e->mixed_mode,
465 if (!e->gpp_pa || !e->dsp_va)
469 "MMU %d, pa: 0x%x, va: 0x%x, size: 0x%x",
475 hw_mmu_tlb_add(dev_context->dsp_mmu_base,
486 /* Lock the above TLB entries and get the BIOS and load monitor timer
489 hw_mmu_num_locked_set(resources->dmmu_base, itmp_entry_ndx);
490 hw_mmu_victim_num_set(resources->dmmu_base, itmp_entry_ndx);
491 hw_mmu_ttb_set(resources->dmmu_base,
492 dev_context->pt_attrs->l1_base_pa);
493 hw_mmu_twl_enable(resources->dmmu_base);
494 /* Enable the SmartIdle and AutoIdle bit for MMU_SYSCONFIG */
496 temp = __raw_readl((resources->dmmu_base) + 0x10);
497 temp = (temp & 0xFFFFFFEF) | 0x11;
498 __raw_writel(temp, (resources->dmmu_base) + 0x10);
500 /* Let the DSP MMU run */
501 hw_mmu_enable(resources->dmmu_base);
503 /* Enable the BIOS clock */
504 (void)dev_get_symbol(dev_context->dev_obj,
505 BRIDGEINIT_BIOSGPTIMER, &ul_bios_gp_timer);
506 (void)dev_get_symbol(dev_context->dev_obj,
507 BRIDGEINIT_LOADMON_GPTIMER,
508 &ul_load_monitor_timer);
512 if (ul_load_monitor_timer != 0xFFFF) {
513 clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
514 ul_load_monitor_timer;
515 dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
517 dev_dbg(bridge, "Not able to get the symbol for Load "
523 if (ul_bios_gp_timer != 0xFFFF) {
524 clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
526 dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
529 "Not able to get the symbol for BIOS Timer\n");
534 /* Set the DSP clock rate */
535 (void)dev_get_symbol(dev_context->dev_obj,
536 "_BRIDGEINIT_DSP_FREQ", &ul_dsp_clk_addr);
537 /*Set Autoidle Mode for IVA2 PLL */
538 (*pdata->dsp_cm_write)(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
539 OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL);
541 if ((unsigned int *)ul_dsp_clk_addr != NULL) {
542 /* Get the clock rate */
543 ul_dsp_clk_rate = dsp_clk_get_iva2_rate();
544 dev_dbg(bridge, "%s: DSP clock rate (KHZ): 0x%x \n",
545 __func__, ul_dsp_clk_rate);
546 (void)bridge_brd_write(dev_context,
547 (u8 *) &ul_dsp_clk_rate,
548 ul_dsp_clk_addr, sizeof(u32), 0);
551 * Enable Mailbox events and also drain any pending
554 dev_context->mbox = omap_mbox_get("dsp", &dsp_mbox_notifier);
555 if (IS_ERR(dev_context->mbox)) {
556 dev_context->mbox = NULL;
557 pr_err("%s: Failed to get dsp mailbox handle\n",
564 /*PM_IVA2GRPSEL_PER = 0xC0;*/
565 temp = readl(resources->per_pm_base + 0xA8);
566 temp = (temp & 0xFFFFFF30) | 0xC0;
567 writel(temp, resources->per_pm_base + 0xA8);
569 /*PM_MPUGRPSEL_PER &= 0xFFFFFF3F; */
570 temp = readl(resources->per_pm_base + 0xA4);
571 temp = (temp & 0xFFFFFF3F);
572 writel(temp, resources->per_pm_base + 0xA4);
573 /*CM_SLEEPDEP_PER |= 0x04; */
574 temp = readl(resources->per_base + 0x44);
575 temp = (temp & 0xFFFFFFFB) | 0x04;
576 writel(temp, resources->per_base + 0x44);
578 /*CM_CLKSTCTRL_IVA2 = 0x00000003 -To Allow automatic transitions */
579 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_ENABLE_AUTO,
580 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
583 dev_dbg(bridge, "%s Unreset\n", __func__);
584 /* Enable DSP MMU Interrupts */
585 hw_mmu_event_enable(resources->dmmu_base,
586 HW_MMU_ALL_INTERRUPTS);
587 /* release the RST1, DSP starts executing now .. */
588 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK, 0,
589 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
591 dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", dw_sync_addr);
592 dev_dbg(bridge, "DSP c_int00 Address = 0x%x\n", dsp_addr);
594 while (__raw_readw(dw_sync_addr))
597 /* Wait for DSP to clear word in shared memory */
598 /* Read the Location */
599 if (!wait_for_start(dev_context, dw_sync_addr))
602 dev_get_symbol(dev_context->dev_obj, "_WDT_enable", &wdt_en);
605 dsp_wdt_sm_set((void *)ul_shm_base);
606 dsp_wdt_enable(true);
609 status = dev_get_io_mgr(dev_context->dev_obj, &hio_mgr);
611 io_sh_msetting(hio_mgr, SHM_OPPINFO, NULL);
612 /* Write the synchronization bit to indicate the
613 * completion of OPP table update to DSP
615 __raw_writel(0XCAFECAFE, dw_sync_addr);
617 /* update board state */
618 dev_context->brd_state = BRD_RUNNING;
619 /* (void)chnlsm_enable_interrupt(dev_context); */
621 dev_context->brd_state = BRD_UNKNOWN;
628 * ======== bridge_brd_stop ========
630 * Puts DSP in self loop.
635 static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt)
638 struct bridge_dev_context *dev_context = dev_ctxt;
639 struct pg_table_attrs *pt_attrs;
641 struct omap_dsp_platform_data *pdata =
642 omap_dspbridge_dev->dev.platform_data;
644 if (dev_context->brd_state == BRD_STOPPED)
647 /* as per TRM, it is advised to first drive the IVA2 to 'Standby' mode,
648 * before turning off the clocks.. This is to ensure that there are no
649 * pending L3 or other transactons from IVA2 */
650 dsp_pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
651 OMAP_POWERSTATEST_MASK;
652 if (dsp_pwr_state != PWRDM_POWER_OFF) {
653 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
654 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
655 sm_interrupt_dsp(dev_context, MBX_PM_DSPIDLE);
658 /* IVA2 is not in OFF state */
659 /* Set PM_PWSTCTRL_IVA2 to OFF */
660 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
661 PWRDM_POWER_OFF, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
662 /* Set the SW supervised state transition for Sleep */
663 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_SLEEP,
664 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
667 /* Release the Ext Base virtual Address as the next DSP Program
668 * may have a different load address */
669 if (dev_context->dsp_ext_base_addr)
670 dev_context->dsp_ext_base_addr = 0;
672 dev_context->brd_state = BRD_STOPPED; /* update board state */
674 dsp_wdt_enable(false);
676 /* This is a good place to clear the MMU page tables as well */
677 if (dev_context->pt_attrs) {
678 pt_attrs = dev_context->pt_attrs;
679 memset((u8 *) pt_attrs->l1_base_va, 0x00, pt_attrs->l1_size);
680 memset((u8 *) pt_attrs->l2_base_va, 0x00, pt_attrs->l2_size);
681 memset((u8 *) pt_attrs->pg_info, 0x00,
682 (pt_attrs->l2_num_pages * sizeof(struct page_info)));
684 /* Disable the mailbox interrupts */
685 if (dev_context->mbox) {
686 omap_mbox_disable_irq(dev_context->mbox, IRQ_RX);
687 omap_mbox_put(dev_context->mbox, &dsp_mbox_notifier);
688 dev_context->mbox = NULL;
690 /* Reset IVA2 clocks*/
691 (*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK |
692 OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
694 dsp_clock_disable_all(dev_context->dsp_per_clks);
695 dsp_clk_disable(DSP_CLK_IVA2);
701 * ======== bridge_brd_status ========
702 * Returns the board status.
704 static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
707 struct bridge_dev_context *dev_context = dev_ctxt;
708 *board_state = dev_context->brd_state;
713 * ======== bridge_brd_write ========
714 * Copies the buffers to DSP internal or external memory.
716 static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
717 u8 *host_buff, u32 dsp_addr,
718 u32 ul_num_bytes, u32 mem_type)
721 struct bridge_dev_context *dev_context = dev_ctxt;
723 if (dsp_addr < dev_context->dsp_start_add) {
727 if ((dsp_addr - dev_context->dsp_start_add) <
728 dev_context->internal_size) {
729 status = write_dsp_data(dev_ctxt, host_buff, dsp_addr,
730 ul_num_bytes, mem_type);
732 status = write_ext_dsp_data(dev_context, host_buff, dsp_addr,
733 ul_num_bytes, mem_type, false);
740 * ======== bridge_dev_create ========
741 * Creates a driver object. Puts DSP in self loop.
743 static int bridge_dev_create(struct bridge_dev_context
745 struct dev_object *hdev_obj,
746 struct cfg_hostres *config_param)
749 struct bridge_dev_context *dev_context = NULL;
751 struct cfg_hostres *resources = config_param;
752 struct pg_table_attrs *pt_attrs;
756 struct drv_data *drv_datap = dev_get_drvdata(bridge);
758 /* Allocate and initialize a data structure to contain the bridge driver
759 * state, which becomes the context for later calls into this driver */
760 dev_context = kzalloc(sizeof(struct bridge_dev_context), GFP_KERNEL);
766 dev_context->dsp_start_add = (u32) OMAP_GEM_BASE;
767 dev_context->self_loop = (u32) NULL;
768 dev_context->dsp_per_clks = 0;
769 dev_context->internal_size = OMAP_DSP_SIZE;
770 /* Clear dev context MMU table entries.
771 * These get set on bridge_io_on_loaded() call after program loaded. */
772 for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB; entry_ndx++) {
773 dev_context->atlb_entry[entry_ndx].gpp_pa =
774 dev_context->atlb_entry[entry_ndx].dsp_va = 0;
776 dev_context->dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *)
783 if (!dev_context->dsp_base_addr)
786 pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL);
787 if (pt_attrs != NULL) {
788 pt_attrs->l1_size = SZ_16K; /* 4096 entries of 32 bits */
789 align_size = pt_attrs->l1_size;
790 /* Align sizes are expected to be power of 2 */
791 /* we like to get aligned on L1 table size */
792 pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l1_size,
793 align_size, &pg_tbl_pa);
795 /* Check if the PA is aligned for us */
796 if ((pg_tbl_pa) & (align_size - 1)) {
797 /* PA not aligned to page table size ,
798 * try with more allocation and align */
799 mem_free_phys_mem((void *)pg_tbl_va, pg_tbl_pa,
801 /* we like to get aligned on L1 table size */
803 (u32) mem_alloc_phys_mem((pt_attrs->l1_size) * 2,
804 align_size, &pg_tbl_pa);
805 /* We should be able to get aligned table now */
806 pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
807 pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
808 pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size * 2;
809 /* Align the PA to the next 'align' boundary */
810 pt_attrs->l1_base_pa =
812 (align_size - 1)) & (~(align_size - 1));
813 pt_attrs->l1_base_va =
814 pg_tbl_va + (pt_attrs->l1_base_pa - pg_tbl_pa);
816 /* We got aligned PA, cool */
817 pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
818 pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
819 pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size;
820 pt_attrs->l1_base_pa = pg_tbl_pa;
821 pt_attrs->l1_base_va = pg_tbl_va;
823 if (pt_attrs->l1_base_va)
824 memset((u8 *) pt_attrs->l1_base_va, 0x00,
827 /* number of L2 page tables = DMM pool used + SHMMEM +EXTMEM +
829 pt_attrs->l2_num_pages = ((DMMPOOLSIZE >> 20) + 6);
830 pt_attrs->l2_size = HW_MMU_COARSE_PAGE_SIZE *
831 pt_attrs->l2_num_pages;
832 align_size = 4; /* Make it u32 aligned */
833 /* we like to get aligned on L1 table size */
834 pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l2_size,
835 align_size, &pg_tbl_pa);
836 pt_attrs->l2_tbl_alloc_pa = pg_tbl_pa;
837 pt_attrs->l2_tbl_alloc_va = pg_tbl_va;
838 pt_attrs->l2_tbl_alloc_sz = pt_attrs->l2_size;
839 pt_attrs->l2_base_pa = pg_tbl_pa;
840 pt_attrs->l2_base_va = pg_tbl_va;
842 if (pt_attrs->l2_base_va)
843 memset((u8 *) pt_attrs->l2_base_va, 0x00,
846 pt_attrs->pg_info = kzalloc(pt_attrs->l2_num_pages *
847 sizeof(struct page_info), GFP_KERNEL);
849 "L1 pa %x, va %x, size %x\n L2 pa %x, va "
850 "%x, size %x\n", pt_attrs->l1_base_pa,
851 pt_attrs->l1_base_va, pt_attrs->l1_size,
852 pt_attrs->l2_base_pa, pt_attrs->l2_base_va,
854 dev_dbg(bridge, "pt_attrs %p L2 NumPages %x pg_info %p\n",
855 pt_attrs, pt_attrs->l2_num_pages, pt_attrs->pg_info);
857 if ((pt_attrs != NULL) && (pt_attrs->l1_base_va != 0) &&
858 (pt_attrs->l2_base_va != 0) && (pt_attrs->pg_info != NULL))
859 dev_context->pt_attrs = pt_attrs;
864 spin_lock_init(&pt_attrs->pg_lock);
865 dev_context->tc_word_swap_on = drv_datap->tc_wordswapon;
867 /* Set the Clock Divisor for the DSP module */
869 /* MMU address is obtained from the host
870 * resources struct */
871 dev_context->dsp_mmu_base = resources->dmmu_base;
874 dev_context->dev_obj = hdev_obj;
875 /* Store current board state. */
876 dev_context->brd_state = BRD_UNKNOWN;
877 dev_context->resources = resources;
878 dsp_clk_enable(DSP_CLK_IVA2);
879 bridge_brd_stop(dev_context);
880 /* Return ptr to our device state to the DSP API for storage */
881 *dev_cntxt = dev_context;
883 if (pt_attrs != NULL) {
884 kfree(pt_attrs->pg_info);
886 if (pt_attrs->l2_tbl_alloc_va) {
887 mem_free_phys_mem((void *)
888 pt_attrs->l2_tbl_alloc_va,
889 pt_attrs->l2_tbl_alloc_pa,
890 pt_attrs->l2_tbl_alloc_sz);
892 if (pt_attrs->l1_tbl_alloc_va) {
893 mem_free_phys_mem((void *)
894 pt_attrs->l1_tbl_alloc_va,
895 pt_attrs->l1_tbl_alloc_pa,
896 pt_attrs->l1_tbl_alloc_sz);
907 * ======== bridge_dev_ctrl ========
908 * Receives device specific commands.
910 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
911 u32 dw_cmd, void *pargs)
914 struct bridge_ioctl_extproc *pa_ext_proc =
915 (struct bridge_ioctl_extproc *)pargs;
919 case BRDIOCTL_CHNLREAD:
921 case BRDIOCTL_CHNLWRITE:
923 case BRDIOCTL_SETMMUCONFIG:
924 /* store away dsp-mmu setup values for later use */
925 for (ndx = 0; ndx < BRDIOCTL_NUMOFMMUTLB; ndx++, pa_ext_proc++)
926 dev_context->atlb_entry[ndx] = *pa_ext_proc;
928 case BRDIOCTL_DEEPSLEEP:
929 case BRDIOCTL_EMERGENCYSLEEP:
930 /* Currently only DSP Idle is supported Need to update for
932 status = sleep_dsp(dev_context, PWR_DEEPSLEEP, pargs);
934 case BRDIOCTL_WAKEUP:
935 status = wake_dsp(dev_context, pargs);
937 case BRDIOCTL_CLK_CTRL:
939 /* Looking For Baseport Fix for Clocks */
940 status = dsp_peripheral_clk_ctrl(dev_context, pargs);
942 case BRDIOCTL_PWR_HIBERNATE:
943 status = handle_hibernation_from_dsp(dev_context);
945 case BRDIOCTL_PRESCALE_NOTIFY:
946 status = pre_scale_dsp(dev_context, pargs);
948 case BRDIOCTL_POSTSCALE_NOTIFY:
949 status = post_scale_dsp(dev_context, pargs);
951 case BRDIOCTL_CONSTRAINT_REQUEST:
952 status = handle_constraints_set(dev_context, pargs);
962 * ======== bridge_dev_destroy ========
963 * Destroys the driver object.
965 static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt)
967 struct pg_table_attrs *pt_attrs;
969 struct bridge_dev_context *dev_context = (struct bridge_dev_context *)
971 struct cfg_hostres *host_res;
973 struct drv_data *drv_datap = dev_get_drvdata(bridge);
975 /* It should never happen */
979 /* first put the device to stop state */
980 bridge_brd_stop(dev_context);
981 if (dev_context->pt_attrs) {
982 pt_attrs = dev_context->pt_attrs;
983 kfree(pt_attrs->pg_info);
985 if (pt_attrs->l2_tbl_alloc_va) {
986 mem_free_phys_mem((void *)pt_attrs->l2_tbl_alloc_va,
987 pt_attrs->l2_tbl_alloc_pa,
988 pt_attrs->l2_tbl_alloc_sz);
990 if (pt_attrs->l1_tbl_alloc_va) {
991 mem_free_phys_mem((void *)pt_attrs->l1_tbl_alloc_va,
992 pt_attrs->l1_tbl_alloc_pa,
993 pt_attrs->l1_tbl_alloc_sz);
999 if (dev_context->resources) {
1000 host_res = dev_context->resources;
1001 shm_size = drv_datap->shm_size;
1002 if (shm_size >= 0x10000) {
1003 if ((host_res->mem_base[1]) &&
1004 (host_res->mem_phys[1])) {
1005 mem_free_phys_mem((void *)
1012 dev_dbg(bridge, "%s: Error getting shm size "
1013 "from registry: %x. Not calling "
1014 "mem_free_phys_mem\n", __func__,
1017 host_res->mem_base[1] = 0;
1018 host_res->mem_phys[1] = 0;
1020 if (host_res->mem_base[0])
1021 iounmap((void *)host_res->mem_base[0]);
1022 if (host_res->mem_base[2])
1023 iounmap((void *)host_res->mem_base[2]);
1024 if (host_res->mem_base[3])
1025 iounmap((void *)host_res->mem_base[3]);
1026 if (host_res->mem_base[4])
1027 iounmap((void *)host_res->mem_base[4]);
1028 if (host_res->dmmu_base)
1029 iounmap(host_res->dmmu_base);
1030 if (host_res->per_base)
1031 iounmap(host_res->per_base);
1032 if (host_res->per_pm_base)
1033 iounmap((void *)host_res->per_pm_base);
1034 if (host_res->core_pm_base)
1035 iounmap((void *)host_res->core_pm_base);
1037 host_res->mem_base[0] = (u32) NULL;
1038 host_res->mem_base[2] = (u32) NULL;
1039 host_res->mem_base[3] = (u32) NULL;
1040 host_res->mem_base[4] = (u32) NULL;
1041 host_res->dmmu_base = NULL;
1046 /* Free the driver's device context: */
1047 kfree(drv_datap->base_img);
1048 kfree((void *)dev_ctxt);
1052 static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
1053 u32 dsp_dest_addr, u32 dsp_src_addr,
1054 u32 ul_num_bytes, u32 mem_type)
1057 u32 src_addr = dsp_src_addr;
1058 u32 dest_addr = dsp_dest_addr;
1060 u32 total_bytes = ul_num_bytes;
1061 u8 host_buf[BUFFERSIZE];
1062 struct bridge_dev_context *dev_context = dev_ctxt;
1063 while (total_bytes > 0 && !status) {
1065 total_bytes > BUFFERSIZE ? BUFFERSIZE : total_bytes;
1066 /* Read from External memory */
1067 status = read_ext_dsp_data(dev_ctxt, host_buf, src_addr,
1068 copy_bytes, mem_type);
1070 if (dest_addr < (dev_context->dsp_start_add +
1071 dev_context->internal_size)) {
1072 /* Write to Internal memory */
1073 status = write_dsp_data(dev_ctxt, host_buf,
1074 dest_addr, copy_bytes,
1077 /* Write to External memory */
1079 write_ext_dsp_data(dev_ctxt, host_buf,
1080 dest_addr, copy_bytes,
1084 total_bytes -= copy_bytes;
1085 src_addr += copy_bytes;
1086 dest_addr += copy_bytes;
1091 /* Mem Write does not halt the DSP to write unlike bridge_brd_write */
1092 static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
1093 u8 *host_buff, u32 dsp_addr,
1094 u32 ul_num_bytes, u32 mem_type)
1097 struct bridge_dev_context *dev_context = dev_ctxt;
1098 u32 ul_remain_bytes = 0;
1100 ul_remain_bytes = ul_num_bytes;
1101 while (ul_remain_bytes > 0 && !status) {
1103 ul_remain_bytes > BUFFERSIZE ? BUFFERSIZE : ul_remain_bytes;
1104 if (dsp_addr < (dev_context->dsp_start_add +
1105 dev_context->internal_size)) {
1107 write_dsp_data(dev_ctxt, host_buff, dsp_addr,
1108 ul_bytes, mem_type);
1110 status = write_ext_dsp_data(dev_ctxt, host_buff,
1114 ul_remain_bytes -= ul_bytes;
1115 dsp_addr += ul_bytes;
1116 host_buff = host_buff + ul_bytes;
1122 * ======== bridge_brd_mem_map ========
1123 * This function maps MPU buffer to the DSP address space. It performs
1124 * linear to physical address translation if required. It translates each
1125 * page since linear addresses can be physically non-contiguous
1126 * All address & size arguments are assumed to be page aligned (in proc.c)
1128 * TODO: Disable MMU while updating the page tables (but that'll stall DSP)
1130 static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt,
1131 u32 ul_mpu_addr, u32 virt_addr,
1132 u32 ul_num_bytes, u32 ul_map_attr,
1133 struct page **mapped_pages)
1137 struct bridge_dev_context *dev_context = dev_ctxt;
1138 struct hw_mmu_map_attrs_t hw_attrs;
1139 struct vm_area_struct *vma;
1140 struct mm_struct *mm = current->mm;
1142 u32 num_usr_pgs = 0;
1143 struct page *mapped_page, *pg;
1146 struct task_struct *curr_task = current;
1151 "%s hDevCtxt %p, pa %x, va %x, size %x, ul_map_attr %x\n",
1152 __func__, dev_ctxt, ul_mpu_addr, virt_addr, ul_num_bytes,
1154 if (ul_num_bytes == 0)
1157 if (ul_map_attr & DSP_MAP_DIR_MASK) {
1158 attrs = ul_map_attr;
1160 /* Assign default attributes */
1161 attrs = ul_map_attr | (DSP_MAPVIRTUALADDR | DSP_MAPELEMSIZE16);
1163 /* Take mapping properties */
1164 if (attrs & DSP_MAPBIGENDIAN)
1165 hw_attrs.endianism = HW_BIG_ENDIAN;
1167 hw_attrs.endianism = HW_LITTLE_ENDIAN;
1169 hw_attrs.mixed_size = (enum hw_mmu_mixed_size_t)
1170 ((attrs & DSP_MAPMIXEDELEMSIZE) >> 2);
1171 /* Ignore element_size if mixed_size is enabled */
1172 if (hw_attrs.mixed_size == 0) {
1173 if (attrs & DSP_MAPELEMSIZE8) {
1175 hw_attrs.element_size = HW_ELEM_SIZE8BIT;
1176 } else if (attrs & DSP_MAPELEMSIZE16) {
1177 /* Size is 16 bit */
1178 hw_attrs.element_size = HW_ELEM_SIZE16BIT;
1179 } else if (attrs & DSP_MAPELEMSIZE32) {
1180 /* Size is 32 bit */
1181 hw_attrs.element_size = HW_ELEM_SIZE32BIT;
1182 } else if (attrs & DSP_MAPELEMSIZE64) {
1183 /* Size is 64 bit */
1184 hw_attrs.element_size = HW_ELEM_SIZE64BIT;
1187 * Mixedsize isn't enabled, so size can't be
1193 if (attrs & DSP_MAPDONOTLOCK)
1194 hw_attrs.donotlockmpupage = 1;
1196 hw_attrs.donotlockmpupage = 0;
1198 if (attrs & DSP_MAPVMALLOCADDR) {
1199 return mem_map_vmalloc(dev_ctxt, ul_mpu_addr, virt_addr,
1200 ul_num_bytes, &hw_attrs);
1203 * Do OS-specific user-va to pa translation.
1204 * Combine physically contiguous regions to reduce TLBs.
1205 * Pass the translated pa to pte_update.
1207 if ((attrs & DSP_MAPPHYSICALADDR)) {
1208 status = pte_update(dev_context, ul_mpu_addr, virt_addr,
1209 ul_num_bytes, &hw_attrs);
1214 * Important Note: ul_mpu_addr is mapped from user application process
1215 * to current process - it must lie completely within the current
1216 * virtual memory address space in order to be of use to us here!
1218 down_read(&mm->mmap_sem);
1219 vma = find_vma(mm, ul_mpu_addr);
1222 "VMAfor UserBuf: ul_mpu_addr=%x, ul_num_bytes=%x, "
1223 "vm_start=%lx, vm_end=%lx, vm_flags=%lx\n", ul_mpu_addr,
1224 ul_num_bytes, vma->vm_start, vma->vm_end,
1228 * It is observed that under some circumstances, the user buffer is
1229 * spread across several VMAs. So loop through and check if the entire
1230 * user buffer is covered
1232 while ((vma) && (ul_mpu_addr + ul_num_bytes > vma->vm_end)) {
1233 /* jump to the next VMA region */
1234 vma = find_vma(mm, vma->vm_end + 1);
1236 "VMA for UserBuf ul_mpu_addr=%x ul_num_bytes=%x, "
1237 "vm_start=%lx, vm_end=%lx, vm_flags=%lx\n", ul_mpu_addr,
1238 ul_num_bytes, vma->vm_start, vma->vm_end,
1242 pr_err("%s: Failed to get VMA region for 0x%x (%d)\n",
1243 __func__, ul_mpu_addr, ul_num_bytes);
1245 up_read(&mm->mmap_sem);
1249 if (vma->vm_flags & VM_IO) {
1250 num_usr_pgs = ul_num_bytes / PG_SIZE4K;
1251 mpu_addr = ul_mpu_addr;
1253 /* Get the physical addresses for user buffer */
1254 for (pg_i = 0; pg_i < num_usr_pgs; pg_i++) {
1255 pa = user_va2_pa(mm, mpu_addr);
1258 pr_err("DSPBRIDGE: VM_IO mapping physical"
1259 "address is invalid\n");
1262 if (pfn_valid(__phys_to_pfn(pa))) {
1263 pg = PHYS_TO_PAGE(pa);
1265 if (page_count(pg) < 1) {
1266 pr_err("Bad page in VM_IO buffer\n");
1267 bad_page_dump(pa, pg);
1270 status = pte_set(dev_context->pt_attrs, pa,
1271 va, HW_PAGE_SIZE4KB, &hw_attrs);
1275 va += HW_PAGE_SIZE4KB;
1276 mpu_addr += HW_PAGE_SIZE4KB;
1277 pa += HW_PAGE_SIZE4KB;
1280 num_usr_pgs = ul_num_bytes / PG_SIZE4K;
1281 if (vma->vm_flags & (VM_WRITE | VM_MAYWRITE))
1284 for (pg_i = 0; pg_i < num_usr_pgs; pg_i++) {
1285 pg_num = get_user_pages(curr_task, mm, ul_mpu_addr, 1,
1286 write, 1, &mapped_page, NULL);
1288 if (page_count(mapped_page) < 1) {
1289 pr_err("Bad page count after doing"
1292 bad_page_dump(page_to_phys(mapped_page),
1295 status = pte_set(dev_context->pt_attrs,
1296 page_to_phys(mapped_page), va,
1297 HW_PAGE_SIZE4KB, &hw_attrs);
1302 mapped_pages[pg_i] = mapped_page;
1304 va += HW_PAGE_SIZE4KB;
1305 ul_mpu_addr += HW_PAGE_SIZE4KB;
1307 pr_err("DSPBRIDGE: get_user_pages FAILED,"
1309 "vma->vm_flags = 0x%lx,"
1310 "get_user_pages Err"
1311 "Value = %d, Buffer"
1312 "size=0x%x\n", ul_mpu_addr,
1313 vma->vm_flags, pg_num, ul_num_bytes);
1319 up_read(&mm->mmap_sem);
1323 * Roll out the mapped pages incase it failed in middle of
1327 bridge_brd_mem_un_map(dev_context, virt_addr,
1328 (pg_i * PG_SIZE4K));
1333 * In any case, flush the TLB
1334 * This is called from here instead from pte_update to avoid unnecessary
1335 * repetition while mapping non-contiguous physical regions of a virtual
1338 flush_all(dev_context);
1339 dev_dbg(bridge, "%s status %x\n", __func__, status);
1344 * ======== bridge_brd_mem_un_map ========
1345 * Invalidate the PTEs for the DSP VA block to be unmapped.
1347 * PTEs of a mapped memory block are contiguous in any page table
1348 * So, instead of looking up the PTE address for every 4K block,
1349 * we clear consecutive PTEs until we unmap all the bytes
1351 static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt,
1352 u32 virt_addr, u32 ul_num_bytes)
1362 u32 pte_addr_l2 = 0;
1366 struct page *pg = NULL;
1368 struct bridge_dev_context *dev_context = dev_ctxt;
1369 struct pg_table_attrs *pt = dev_context->pt_attrs;
1372 u32 numof4k_pages = 0;
1374 va_curr = virt_addr;
1375 rem_bytes = ul_num_bytes;
1377 l1_base_va = pt->l1_base_va;
1378 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va_curr);
1379 dev_dbg(bridge, "%s dev_ctxt %p, va %x, NumBytes %x l1_base_va %x, "
1380 "pte_addr_l1 %x\n", __func__, dev_ctxt, virt_addr,
1381 ul_num_bytes, l1_base_va, pte_addr_l1);
1383 while (rem_bytes && !status) {
1384 u32 va_curr_orig = va_curr;
1385 /* Find whether the L1 PTE points to a valid L2 PT */
1386 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va_curr);
1387 pte_val = *(u32 *) pte_addr_l1;
1388 pte_size = hw_mmu_pte_size_l1(pte_val);
1390 if (pte_size != HW_MMU_COARSE_PAGE_SIZE)
1391 goto skip_coarse_page;
1394 * Get the L2 PA from the L1 PTE, and find
1395 * corresponding L2 VA
1397 l2_base_pa = hw_mmu_pte_coarse_l1(pte_val);
1398 l2_base_va = l2_base_pa - pt->l2_base_pa + pt->l2_base_va;
1400 (l2_base_pa - pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE;
1402 * Find the L2 PTE address from which we will start
1403 * clearing, the number of PTEs to be cleared on this
1404 * page, and the size of VA space that needs to be
1405 * cleared on this L2 page
1407 pte_addr_l2 = hw_mmu_pte_addr_l2(l2_base_va, va_curr);
1408 pte_count = pte_addr_l2 & (HW_MMU_COARSE_PAGE_SIZE - 1);
1409 pte_count = (HW_MMU_COARSE_PAGE_SIZE - pte_count) / sizeof(u32);
1410 if (rem_bytes < (pte_count * PG_SIZE4K))
1411 pte_count = rem_bytes / PG_SIZE4K;
1412 rem_bytes_l2 = pte_count * PG_SIZE4K;
1415 * Unmap the VA space on this L2 PT. A quicker way
1416 * would be to clear pte_count entries starting from
1417 * pte_addr_l2. However, below code checks that we don't
1418 * clear invalid entries or less than 64KB for a 64KB
1419 * entry. Similar checking is done for L1 PTEs too
1422 while (rem_bytes_l2 && !status) {
1423 pte_val = *(u32 *) pte_addr_l2;
1424 pte_size = hw_mmu_pte_size_l2(pte_val);
1425 /* va_curr aligned to pte_size? */
1426 if (pte_size == 0 || rem_bytes_l2 < pte_size ||
1427 va_curr & (pte_size - 1)) {
1432 /* Collect Physical addresses from VA */
1433 paddr = (pte_val & ~(pte_size - 1));
1434 if (pte_size == HW_PAGE_SIZE64KB)
1439 while (temp++ < numof4k_pages) {
1440 if (!pfn_valid(__phys_to_pfn(paddr))) {
1441 paddr += HW_PAGE_SIZE4KB;
1444 pg = PHYS_TO_PAGE(paddr);
1445 if (page_count(pg) < 1) {
1446 pr_info("DSPBRIDGE: UNMAP function: "
1447 "COUNT 0 FOR PA 0x%x, size = "
1448 "0x%x\n", paddr, ul_num_bytes);
1449 bad_page_dump(paddr, pg);
1452 page_cache_release(pg);
1454 paddr += HW_PAGE_SIZE4KB;
1456 if (hw_mmu_pte_clear(pte_addr_l2, va_curr, pte_size)) {
1462 rem_bytes_l2 -= pte_size;
1463 va_curr += pte_size;
1464 pte_addr_l2 += (pte_size >> 12) * sizeof(u32);
1466 spin_lock(&pt->pg_lock);
1467 if (rem_bytes_l2 == 0) {
1468 pt->pg_info[l2_page_num].num_entries -= pte_count;
1469 if (pt->pg_info[l2_page_num].num_entries == 0) {
1471 * Clear the L1 PTE pointing to the L2 PT
1473 if (!hw_mmu_pte_clear(l1_base_va, va_curr_orig,
1474 HW_MMU_COARSE_PAGE_SIZE))
1478 spin_unlock(&pt->pg_lock);
1482 rem_bytes -= pte_count * PG_SIZE4K;
1486 spin_unlock(&pt->pg_lock);
1489 /* va_curr aligned to pte_size? */
1490 /* pte_size = 1 MB or 16 MB */
1491 if (pte_size == 0 || rem_bytes < pte_size ||
1492 va_curr & (pte_size - 1)) {
1497 if (pte_size == HW_PAGE_SIZE1MB)
1498 numof4k_pages = 256;
1500 numof4k_pages = 4096;
1502 /* Collect Physical addresses from VA */
1503 paddr = (pte_val & ~(pte_size - 1));
1504 while (temp++ < numof4k_pages) {
1505 if (pfn_valid(__phys_to_pfn(paddr))) {
1506 pg = PHYS_TO_PAGE(paddr);
1507 if (page_count(pg) < 1) {
1508 pr_info("DSPBRIDGE: UNMAP function: "
1509 "COUNT 0 FOR PA 0x%x, size = "
1510 "0x%x\n", paddr, ul_num_bytes);
1511 bad_page_dump(paddr, pg);
1514 page_cache_release(pg);
1517 paddr += HW_PAGE_SIZE4KB;
1519 if (!hw_mmu_pte_clear(l1_base_va, va_curr, pte_size)) {
1521 rem_bytes -= pte_size;
1522 va_curr += pte_size;
1529 * It is better to flush the TLB here, so that any stale old entries
1533 flush_all(dev_context);
1535 "%s: va_curr %x, pte_addr_l1 %x pte_addr_l2 %x rem_bytes %x,"
1536 " rem_bytes_l2 %x status %x\n", __func__, va_curr, pte_addr_l1,
1537 pte_addr_l2, rem_bytes, rem_bytes_l2, status);
1542 * ======== user_va2_pa ========
1544 * This function walks through the page tables to convert a userland
1545 * virtual address to physical address
1547 static u32 user_va2_pa(struct mm_struct *mm, u32 address)
1553 pgd = pgd_offset(mm, address);
1554 if (!(pgd_none(*pgd) || pgd_bad(*pgd))) {
1555 pmd = pmd_offset(pgd, address);
1556 if (!(pmd_none(*pmd) || pmd_bad(*pmd))) {
1557 ptep = pte_offset_map(pmd, address);
1560 if (pte_present(pte))
1561 return pte & PAGE_MASK;
1570 * ======== pte_update ========
1571 * This function calculates the optimum page-aligned addresses and sizes
1572 * Caller must pass page-aligned values
1574 static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa,
1576 struct hw_mmu_map_attrs_t *map_attrs)
1582 u32 num_bytes = size;
1583 struct bridge_dev_context *dev_context = dev_ctxt;
1585 u32 page_size[] = { HW_PAGE_SIZE16MB, HW_PAGE_SIZE1MB,
1586 HW_PAGE_SIZE64KB, HW_PAGE_SIZE4KB
1589 while (num_bytes && !status) {
1590 /* To find the max. page size with which both PA & VA are
1592 all_bits = pa_curr | va_curr;
1594 for (i = 0; i < 4; i++) {
1595 if ((num_bytes >= page_size[i]) && ((all_bits &
1599 pte_set(dev_context->pt_attrs, pa_curr,
1600 va_curr, page_size[i], map_attrs);
1601 pa_curr += page_size[i];
1602 va_curr += page_size[i];
1603 num_bytes -= page_size[i];
1604 /* Don't try smaller sizes. Hopefully we have
1605 * reached an address aligned to a bigger page
1616 * ======== pte_set ========
1617 * This function calculates PTE address (MPU virtual) to be updated
1618 * It also manages the L2 page tables
1620 static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
1621 u32 size, struct hw_mmu_map_attrs_t *attrs)
1627 /* Base address of the PT that will be updated */
1630 /* Compiler warns that the next three variables might be used
1631 * uninitialized in this function. Doesn't seem so. Working around,
1635 u32 l2_page_num = 0;
1638 l1_base_va = pt->l1_base_va;
1639 pg_tbl_va = l1_base_va;
1640 if ((size == HW_PAGE_SIZE64KB) || (size == HW_PAGE_SIZE4KB)) {
1641 /* Find whether the L1 PTE points to a valid L2 PT */
1642 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va);
1643 if (pte_addr_l1 <= (pt->l1_base_va + pt->l1_size)) {
1644 pte_val = *(u32 *) pte_addr_l1;
1645 pte_size = hw_mmu_pte_size_l1(pte_val);
1649 spin_lock(&pt->pg_lock);
1650 if (pte_size == HW_MMU_COARSE_PAGE_SIZE) {
1651 /* Get the L2 PA from the L1 PTE, and find
1652 * corresponding L2 VA */
1653 l2_base_pa = hw_mmu_pte_coarse_l1(pte_val);
1655 l2_base_pa - pt->l2_base_pa + pt->l2_base_va;
1658 pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE;
1659 } else if (pte_size == 0) {
1660 /* L1 PTE is invalid. Allocate a L2 PT and
1661 * point the L1 PTE to it */
1662 /* Find a free L2 PT. */
1663 for (i = 0; (i < pt->l2_num_pages) &&
1664 (pt->pg_info[i].num_entries != 0); i++)
1666 if (i < pt->l2_num_pages) {
1668 l2_base_pa = pt->l2_base_pa + (l2_page_num *
1669 HW_MMU_COARSE_PAGE_SIZE);
1670 l2_base_va = pt->l2_base_va + (l2_page_num *
1671 HW_MMU_COARSE_PAGE_SIZE);
1672 /* Endianness attributes are ignored for
1673 * HW_MMU_COARSE_PAGE_SIZE */
1675 hw_mmu_pte_set(l1_base_va, l2_base_pa, va,
1676 HW_MMU_COARSE_PAGE_SIZE,
1682 /* Found valid L1 PTE of another size.
1683 * Should not overwrite it. */
1687 pg_tbl_va = l2_base_va;
1688 if (size == HW_PAGE_SIZE64KB)
1689 pt->pg_info[l2_page_num].num_entries += 16;
1691 pt->pg_info[l2_page_num].num_entries++;
1692 dev_dbg(bridge, "PTE: L2 BaseVa %x, BasePa %x, PageNum "
1693 "%x, num_entries %x\n", l2_base_va,
1694 l2_base_pa, l2_page_num,
1695 pt->pg_info[l2_page_num].num_entries);
1697 spin_unlock(&pt->pg_lock);
1700 dev_dbg(bridge, "PTE: pg_tbl_va %x, pa %x, va %x, size %x\n",
1701 pg_tbl_va, pa, va, size);
1702 dev_dbg(bridge, "PTE: endianism %x, element_size %x, "
1703 "mixed_size %x\n", attrs->endianism,
1704 attrs->element_size, attrs->mixed_size);
1705 status = hw_mmu_pte_set(pg_tbl_va, pa, va, size, attrs);
1711 /* Memory map kernel VA -- memory allocated with vmalloc */
1712 static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
1713 u32 ul_mpu_addr, u32 virt_addr,
1715 struct hw_mmu_map_attrs_t *hw_attrs)
1718 struct page *page[1];
1730 * Do Kernel va to pa translation.
1731 * Combine physically contiguous regions to reduce TLBs.
1732 * Pass the translated pa to pte_update.
1734 num_pages = ul_num_bytes / PAGE_SIZE; /* PAGE_SIZE = OS page size */
1736 va_curr = ul_mpu_addr;
1737 page[0] = vmalloc_to_page((void *)va_curr);
1738 pa_next = page_to_phys(page[0]);
1739 while (!status && (i < num_pages)) {
1741 * Reuse pa_next from the previous iteraion to avoid
1742 * an extra va2pa call
1745 size_curr = PAGE_SIZE;
1747 * If the next page is physically contiguous,
1748 * map it with the current one by increasing
1749 * the size of the region to be mapped
1751 while (++i < num_pages) {
1753 vmalloc_to_page((void *)(va_curr + size_curr));
1754 pa_next = page_to_phys(page[0]);
1756 if (pa_next == (pa_curr + size_curr))
1757 size_curr += PAGE_SIZE;
1767 num_of4k_pages = size_curr / HW_PAGE_SIZE4KB;
1768 while (temp++ < num_of4k_pages) {
1769 get_page(PHYS_TO_PAGE(pa));
1770 pa += HW_PAGE_SIZE4KB;
1772 status = pte_update(dev_context, pa_curr, virt_addr +
1773 (va_curr - ul_mpu_addr), size_curr,
1775 va_curr += size_curr;
1778 * In any case, flush the TLB
1779 * This is called from here instead from pte_update to avoid unnecessary
1780 * repetition while mapping non-contiguous physical regions of a virtual
1783 flush_all(dev_context);
1784 dev_dbg(bridge, "%s status %x\n", __func__, status);
1789 * ======== wait_for_start ========
1790 * Wait for the singal from DSP that it has started, or time out.
1792 bool wait_for_start(struct bridge_dev_context *dev_context, u32 dw_sync_addr)
1794 u16 timeout = TIHELEN_ACKTIMEOUT;
1796 /* Wait for response from board */
1797 while (__raw_readw(dw_sync_addr) && --timeout)
1800 /* If timed out: return false */
1802 pr_err("%s: Timed out waiting DSP to Start\n", __func__);