1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
30 #define SD_MAX_RETRY_COUNT 3
32 static u16 REG_SD_CFG1;
33 static u16 REG_SD_CFG2;
34 static u16 REG_SD_CFG3;
35 static u16 REG_SD_STAT1;
36 static u16 REG_SD_STAT2;
37 static u16 REG_SD_BUS_STAT;
38 static u16 REG_SD_PAD_CTL;
39 static u16 REG_SD_SAMPLE_POINT_CTL;
40 static u16 REG_SD_PUSH_POINT_CTL;
41 static u16 REG_SD_CMD0;
42 static u16 REG_SD_CMD1;
43 static u16 REG_SD_CMD2;
44 static u16 REG_SD_CMD3;
45 static u16 REG_SD_CMD4;
46 static u16 REG_SD_CMD5;
47 static u16 REG_SD_BYTE_CNT_L;
48 static u16 REG_SD_BYTE_CNT_H;
49 static u16 REG_SD_BLOCK_CNT_L;
50 static u16 REG_SD_BLOCK_CNT_H;
51 static u16 REG_SD_TRANSFER;
52 static u16 REG_SD_VPCLK0_CTL;
53 static u16 REG_SD_VPCLK1_CTL;
54 static u16 REG_SD_DCMPS0_CTL;
55 static u16 REG_SD_DCMPS1_CTL;
57 static inline void sd_set_err_code(struct rtsx_chip *chip, u8 err_code)
59 struct sd_info *sd_card = &(chip->sd_card);
61 sd_card->err_code |= err_code;
64 static inline void sd_clr_err_code(struct rtsx_chip *chip)
66 struct sd_info *sd_card = &(chip->sd_card);
68 sd_card->err_code = 0;
71 static inline int sd_check_err_code(struct rtsx_chip *chip, u8 err_code)
73 struct sd_info *sd_card = &(chip->sd_card);
75 return sd_card->err_code & err_code;
78 static void sd_init_reg_addr(struct rtsx_chip *chip)
83 REG_SD_STAT1 = 0xFD30;
87 REG_SD_SAMPLE_POINT_CTL = 0;
88 REG_SD_PUSH_POINT_CTL = 0;
95 REG_SD_BYTE_CNT_L = 0xFD39;
96 REG_SD_BYTE_CNT_H = 0xFD3A;
97 REG_SD_BLOCK_CNT_L = 0xFD3B;
98 REG_SD_BLOCK_CNT_H = 0xFD3C;
99 REG_SD_TRANSFER = 0xFD32;
100 REG_SD_VPCLK0_CTL = 0;
101 REG_SD_VPCLK1_CTL = 0;
102 REG_SD_DCMPS0_CTL = 0;
103 REG_SD_DCMPS1_CTL = 0;
106 static int sd_check_data0_status(struct rtsx_chip *chip)
111 retval = rtsx_read_register(chip, REG_SD_STAT1, &stat);
117 if (!(stat & SD_DAT0_STATUS)) {
118 sd_set_err_code(chip, SD_BUSY);
123 return STATUS_SUCCESS;
126 static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
127 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len)
129 struct sd_info *sd_card = &(chip->sd_card);
137 sd_clr_err_code(chip);
139 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg);
141 if (rsp_type == SD_RSP_TYPE_R1b)
148 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
149 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
150 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
151 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
152 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
154 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
155 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
156 0x01, PINGPONG_BUFFER);
157 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
158 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
159 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
160 SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END | SD_STAT_IDLE);
162 if (rsp_type == SD_RSP_TYPE_R2) {
163 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
165 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
168 } else if (rsp_type != SD_RSP_TYPE_R0) {
169 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
171 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
176 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
178 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
182 rtsx_read_register(chip, REG_SD_STAT1, &val);
183 dev_dbg(rtsx_dev(chip), "SD_STAT1: 0x%x\n", val);
185 rtsx_read_register(chip, REG_SD_CFG3, &val);
186 dev_dbg(rtsx_dev(chip), "SD_CFG3: 0x%x\n", val);
188 if (retval == -ETIMEDOUT) {
189 if (rsp_type & SD_WAIT_BUSY_END) {
190 retval = sd_check_data0_status(chip);
191 if (retval != STATUS_SUCCESS) {
192 rtsx_clear_sd_error(chip);
197 sd_set_err_code(chip, SD_TO_ERR);
199 retval = STATUS_TIMEDOUT;
201 retval = STATUS_FAIL;
203 rtsx_clear_sd_error(chip);
209 if (rsp_type == SD_RSP_TYPE_R0)
210 return STATUS_SUCCESS;
212 ptr = rtsx_get_cmd_data(chip) + 1;
214 if ((ptr[0] & 0xC0) != 0) {
215 sd_set_err_code(chip, SD_STS_ERR);
220 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
221 if (ptr[stat_idx] & SD_CRC7_ERR) {
222 if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
223 sd_set_err_code(chip, SD_CRC_ERR);
227 if (rty_cnt < SD_MAX_RETRY_COUNT) {
232 sd_set_err_code(chip, SD_CRC_ERR);
239 if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) {
240 if ((cmd_idx != SEND_RELATIVE_ADDR) &&
241 (cmd_idx != SEND_IF_COND)) {
242 if (cmd_idx != STOP_TRANSMISSION) {
248 #ifdef SUPPORT_SD_LOCK
253 dev_dbg(rtsx_dev(chip), "ptr[1]: 0x%02x\n",
259 dev_dbg(rtsx_dev(chip), "ptr[2]: 0x%02x\n",
265 dev_dbg(rtsx_dev(chip), "ptr[3]: 0x%02x\n",
271 sd_card->sd_data_buf_ready = 1;
273 sd_card->sd_data_buf_ready = 0;
278 memcpy(rsp, ptr, rsp_len);
280 return STATUS_SUCCESS;
283 static int sd_read_data(struct rtsx_chip *chip,
284 u8 trans_mode, u8 *cmd, int cmd_len, u16 byte_cnt,
285 u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len,
288 struct sd_info *sd_card = &(chip->sd_card);
292 sd_clr_err_code(chip);
305 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40);
306 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++)
307 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0 + i,
310 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
312 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
313 (u8)(byte_cnt >> 8));
314 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
316 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
319 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
321 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
322 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END|
323 SD_CHECK_CRC7 | SD_RSP_LEN_6);
324 if (trans_mode != SD_TM_AUTO_TUNING)
325 rtsx_add_cmd(chip, WRITE_REG_CMD,
326 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
328 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
329 trans_mode | SD_TRANSFER_START);
330 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
333 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
335 if (retval == -ETIMEDOUT) {
336 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
337 SD_RSP_TYPE_R1, NULL, 0);
344 if (buf && buf_len) {
345 retval = rtsx_read_ppbuf(chip, buf, buf_len);
346 if (retval != STATUS_SUCCESS) {
352 return STATUS_SUCCESS;
355 static int sd_write_data(struct rtsx_chip *chip, u8 trans_mode,
356 u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt, u8 bus_width,
357 u8 *buf, int buf_len, int timeout)
359 struct sd_info *sd_card = &(chip->sd_card);
363 sd_clr_err_code(chip);
369 /* This function can't write data more than one page */
374 if (buf && buf_len) {
375 retval = rtsx_write_ppbuf(chip, buf, buf_len);
376 if (retval != STATUS_SUCCESS) {
385 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40);
386 for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
387 rtsx_add_cmd(chip, WRITE_REG_CMD,
388 REG_SD_CMD0 + i, 0xFF, cmd[i]);
391 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
393 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
394 (u8)(byte_cnt >> 8));
395 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
397 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
400 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
402 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
403 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
404 SD_CHECK_CRC7 | SD_RSP_LEN_6);
406 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
407 trans_mode | SD_TRANSFER_START);
408 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
411 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
413 if (retval == -ETIMEDOUT) {
414 sd_send_cmd_get_rsp(chip, SEND_STATUS,
415 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
422 return STATUS_SUCCESS;
425 static int sd_check_csd(struct rtsx_chip *chip, char check_wp)
427 struct sd_info *sd_card = &(chip->sd_card);
430 u8 csd_ver, trans_speed;
433 for (i = 0; i < 6; i++) {
434 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
435 sd_set_err_code(chip, SD_NO_CARD);
440 retval = sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr,
441 SD_RSP_TYPE_R2, rsp, 16);
442 if (retval == STATUS_SUCCESS)
451 memcpy(sd_card->raw_csd, rsp + 1, 15);
453 dev_dbg(rtsx_dev(chip), "CSD Response:\n");
454 dev_dbg(rtsx_dev(chip), "%*ph\n", 16, sd_card->raw_csd);
456 csd_ver = (rsp[1] & 0xc0) >> 6;
457 dev_dbg(rtsx_dev(chip), "csd_ver = %d\n", csd_ver);
459 trans_speed = rsp[4];
460 if ((trans_speed & 0x07) == 0x02) {
461 if ((trans_speed & 0xf8) >= 0x30) {
463 sd_card->sd_clock = 47;
465 sd_card->sd_clock = CLK_50;
467 } else if ((trans_speed & 0xf8) == 0x28) {
469 sd_card->sd_clock = 39;
471 sd_card->sd_clock = CLK_40;
473 } else if ((trans_speed & 0xf8) == 0x20) {
475 sd_card->sd_clock = 29;
477 sd_card->sd_clock = CLK_30;
479 } else if ((trans_speed & 0xf8) >= 0x10) {
481 sd_card->sd_clock = 23;
483 sd_card->sd_clock = CLK_20;
485 } else if ((trans_speed & 0x08) >= 0x08) {
487 sd_card->sd_clock = 19;
489 sd_card->sd_clock = CLK_20;
499 if (CHK_MMC_SECTOR_MODE(sd_card)) {
500 sd_card->capacity = 0;
502 if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) {
503 u8 blk_size, c_size_mult;
506 blk_size = rsp[6] & 0x0F;
507 c_size = ((u16)(rsp[7] & 0x03) << 10)
509 + ((u16)(rsp[9] & 0xC0) >> 6);
510 c_size_mult = (u8)((rsp[10] & 0x03) << 1);
511 c_size_mult += (rsp[11] & 0x80) >> 7;
512 sd_card->capacity = (((u32)(c_size + 1)) *
513 (1 << (c_size_mult + 2)))
516 u32 total_sector = 0;
518 total_sector = (((u32)rsp[8] & 0x3f) << 16) |
519 ((u32)rsp[9] << 8) | (u32)rsp[10];
520 sd_card->capacity = (total_sector + 1) << 10;
526 chip->card_wp |= SD_CARD;
528 dev_dbg(rtsx_dev(chip), "CSD WP Status: 0x%x\n", rsp[15]);
531 return STATUS_SUCCESS;
534 static int sd_set_sample_push_timing(struct rtsx_chip *chip)
537 struct sd_info *sd_card = &(chip->sd_card);
540 if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY)
543 if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
544 if (chip->asic_code) {
545 if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) {
557 } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) ==
558 SD_SAMPLE_POINT_DELAY) {
565 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x1C, val);
571 return STATUS_SUCCESS;
574 static void sd_choose_proper_clock(struct rtsx_chip *chip)
576 struct sd_info *sd_card = &(chip->sd_card);
578 if (CHK_SD_SDR104(sd_card)) {
580 sd_card->sd_clock = chip->asic_sd_sdr104_clk;
582 sd_card->sd_clock = chip->fpga_sd_sdr104_clk;
584 } else if (CHK_SD_DDR50(sd_card)) {
586 sd_card->sd_clock = chip->asic_sd_ddr50_clk;
588 sd_card->sd_clock = chip->fpga_sd_ddr50_clk;
590 } else if (CHK_SD_SDR50(sd_card)) {
592 sd_card->sd_clock = chip->asic_sd_sdr50_clk;
594 sd_card->sd_clock = chip->fpga_sd_sdr50_clk;
596 } else if (CHK_SD_HS(sd_card)) {
598 sd_card->sd_clock = chip->asic_sd_hs_clk;
600 sd_card->sd_clock = chip->fpga_sd_hs_clk;
602 } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
604 sd_card->sd_clock = chip->asic_mmc_52m_clk;
606 sd_card->sd_clock = chip->fpga_mmc_52m_clk;
608 } else if (CHK_MMC_26M(sd_card)) {
610 sd_card->sd_clock = 48;
612 sd_card->sd_clock = CLK_50;
616 static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div)
619 u8 mask = 0, val = 0;
622 if (clk_div == SD_CLK_DIVIDE_0)
624 else if (clk_div == SD_CLK_DIVIDE_128)
626 else if (clk_div == SD_CLK_DIVIDE_256)
629 retval = rtsx_write_register(chip, REG_SD_CFG1, mask, val);
635 return STATUS_SUCCESS;
638 static int sd_set_init_para(struct rtsx_chip *chip)
640 struct sd_info *sd_card = &(chip->sd_card);
643 retval = sd_set_sample_push_timing(chip);
644 if (retval != STATUS_SUCCESS) {
649 sd_choose_proper_clock(chip);
651 retval = switch_clock(chip, sd_card->sd_clock);
652 if (retval != STATUS_SUCCESS) {
657 return STATUS_SUCCESS;
660 int sd_select_card(struct rtsx_chip *chip, int select)
662 struct sd_info *sd_card = &(chip->sd_card);
664 u8 cmd_idx, cmd_type;
668 cmd_idx = SELECT_CARD;
669 cmd_type = SD_RSP_TYPE_R1;
670 addr = sd_card->sd_addr;
672 cmd_idx = DESELECT_CARD;
673 cmd_type = SD_RSP_TYPE_R0;
677 retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0);
678 if (retval != STATUS_SUCCESS) {
683 return STATUS_SUCCESS;
686 #ifdef SUPPORT_SD_LOCK
687 static int sd_update_lock_status(struct rtsx_chip *chip)
689 struct sd_info *sd_card = &(chip->sd_card);
693 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
694 SD_RSP_TYPE_R1, rsp, 5);
695 if (retval != STATUS_SUCCESS) {
701 sd_card->sd_lock_status |= SD_LOCKED;
703 sd_card->sd_lock_status &= ~SD_LOCKED;
705 dev_dbg(rtsx_dev(chip), "sd_card->sd_lock_status = 0x%x\n",
706 sd_card->sd_lock_status);
713 return STATUS_SUCCESS;
717 static int sd_wait_state_data_ready(struct rtsx_chip *chip, u8 state,
718 u8 data_ready, int polling_cnt)
720 struct sd_info *sd_card = &(chip->sd_card);
724 for (i = 0; i < polling_cnt; i++) {
725 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
726 sd_card->sd_addr, SD_RSP_TYPE_R1, rsp,
728 if (retval != STATUS_SUCCESS) {
733 if (((rsp[3] & 0x1E) == state) &&
734 ((rsp[3] & 0x01) == data_ready))
735 return STATUS_SUCCESS;
742 static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage)
746 if (voltage == SD_IO_3V3) {
747 if (chip->asic_code) {
748 retval = rtsx_write_phy_register(chip, 0x08,
751 if (retval != STATUS_SUCCESS) {
756 retval = rtsx_write_register(chip, SD_PAD_CTL,
763 } else if (voltage == SD_IO_1V8) {
764 if (chip->asic_code) {
765 retval = rtsx_write_phy_register(chip, 0x08,
768 if (retval != STATUS_SUCCESS) {
773 retval = rtsx_write_register(chip, SD_PAD_CTL,
786 return STATUS_SUCCESS;
789 static int sd_voltage_switch(struct rtsx_chip *chip)
794 retval = rtsx_write_register(chip, SD_BUS_STAT,
795 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP,
802 retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1,
804 if (retval != STATUS_SUCCESS) {
809 udelay(chip->sd_voltage_switch_delay);
811 retval = rtsx_read_register(chip, SD_BUS_STAT, &stat);
816 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
817 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
822 retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF,
828 retval = sd_change_bank_voltage(chip, SD_IO_1V8);
829 if (retval != STATUS_SUCCESS) {
836 retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF,
844 retval = rtsx_read_register(chip, SD_BUS_STAT, &stat);
849 if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
850 SD_DAT1_STATUS | SD_DAT0_STATUS)) !=
851 (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
852 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
853 dev_dbg(rtsx_dev(chip), "SD_BUS_STAT: 0x%x\n", stat);
854 rtsx_write_register(chip, SD_BUS_STAT,
855 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
856 rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0);
861 retval = rtsx_write_register(chip, SD_BUS_STAT,
862 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
868 return STATUS_SUCCESS;
871 static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir)
875 if (tune_dir == TUNE_RX) {
876 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF,
882 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_RX);
888 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF,
894 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_TX);
901 return STATUS_SUCCESS;
904 static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
906 struct sd_info *sd_card = &(chip->sd_card);
907 u16 SD_VP_CTL, SD_DCMPS_CTL;
912 dev_dbg(rtsx_dev(chip), "sd_change_phase (sample_point = %d, tune_dir = %d)\n",
913 sample_point, tune_dir);
915 if (tune_dir == TUNE_RX) {
916 SD_VP_CTL = SD_VPRX_CTL;
917 SD_DCMPS_CTL = SD_DCMPS_RX_CTL;
918 if (CHK_SD_DDR50(sd_card))
921 SD_VP_CTL = SD_VPTX_CTL;
922 SD_DCMPS_CTL = SD_DCMPS_TX_CTL;
925 if (chip->asic_code) {
926 retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK,
932 retval = rtsx_write_register(chip, SD_VP_CTL, 0x1F,
938 retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
944 retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
945 PHASE_NOT_RESET, PHASE_NOT_RESET);
950 retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK, 0);
956 rtsx_read_register(chip, SD_VP_CTL, &val);
957 dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val);
958 rtsx_read_register(chip, SD_DCMPS_CTL, &val);
959 dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val);
962 retval = rtsx_write_register(chip, SD_VP_CTL,
970 retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF,
971 PHASE_CHANGE | PHASE_NOT_RESET | sample_point);
977 retval = rtsx_write_register(chip, CLK_CTL,
978 CHANGE_CLK, CHANGE_CLK);
984 retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF,
985 PHASE_NOT_RESET | sample_point);
994 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE,
996 rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL,
997 DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE);
998 retval = rtsx_send_cmd(chip, SD_CARD, 100);
999 if (retval != STATUS_SUCCESS) {
1004 val = *rtsx_get_cmd_data(chip);
1005 if (val & DCMPS_ERROR) {
1010 if ((val & DCMPS_CURRENT_PHASE) != sample_point) {
1015 retval = rtsx_write_register(chip, SD_DCMPS_CTL,
1022 retval = rtsx_write_register(chip, SD_VP_CTL,
1029 retval = rtsx_write_register(chip, CLK_CTL,
1040 retval = rtsx_write_register(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
1046 return STATUS_SUCCESS;
1049 rtsx_read_register(chip, SD_VP_CTL, &val);
1050 dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val);
1051 rtsx_read_register(chip, SD_DCMPS_CTL, &val);
1052 dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val);
1054 rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
1055 rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0);
1057 sd_reset_dcm(chip, tune_dir);
1061 static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width)
1063 struct sd_info *sd_card = &(chip->sd_card);
1067 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
1068 SD_RSP_TYPE_R1, NULL, 0);
1069 if (retval != STATUS_SUCCESS) {
1074 cmd[0] = 0x40 | SEND_SCR;
1080 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width,
1082 if (retval != STATUS_SUCCESS) {
1083 rtsx_clear_sd_error(chip);
1088 memcpy(sd_card->raw_scr, buf, 8);
1090 if ((buf[0] & 0x0F) == 0) {
1095 return STATUS_SUCCESS;
1098 static int sd_query_switch_result(struct rtsx_chip *chip, u8 func_group,
1099 u8 func_to_switch, u8 *buf, int buf_len)
1101 u8 support_mask = 0, query_switch = 0, switch_busy = 0;
1102 int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0;
1104 if (func_group == SD_FUNC_GROUP_1) {
1105 support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET;
1106 query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET;
1107 check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET;
1109 switch (func_to_switch) {
1111 support_mask = HS_SUPPORT_MASK;
1112 query_switch = HS_QUERY_SWITCH_OK;
1113 switch_busy = HS_SWITCH_BUSY;
1117 support_mask = SDR50_SUPPORT_MASK;
1118 query_switch = SDR50_QUERY_SWITCH_OK;
1119 switch_busy = SDR50_SWITCH_BUSY;
1122 case SDR104_SUPPORT:
1123 support_mask = SDR104_SUPPORT_MASK;
1124 query_switch = SDR104_QUERY_SWITCH_OK;
1125 switch_busy = SDR104_SWITCH_BUSY;
1129 support_mask = DDR50_SUPPORT_MASK;
1130 query_switch = DDR50_QUERY_SWITCH_OK;
1131 switch_busy = DDR50_SWITCH_BUSY;
1138 } else if (func_group == SD_FUNC_GROUP_3) {
1139 support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET;
1140 query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET;
1141 check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET;
1143 switch (func_to_switch) {
1144 case DRIVING_TYPE_A:
1145 support_mask = DRIVING_TYPE_A_MASK;
1146 query_switch = TYPE_A_QUERY_SWITCH_OK;
1147 switch_busy = TYPE_A_SWITCH_BUSY;
1150 case DRIVING_TYPE_C:
1151 support_mask = DRIVING_TYPE_C_MASK;
1152 query_switch = TYPE_C_QUERY_SWITCH_OK;
1153 switch_busy = TYPE_C_SWITCH_BUSY;
1156 case DRIVING_TYPE_D:
1157 support_mask = DRIVING_TYPE_D_MASK;
1158 query_switch = TYPE_D_QUERY_SWITCH_OK;
1159 switch_busy = TYPE_D_SWITCH_BUSY;
1166 } else if (func_group == SD_FUNC_GROUP_4) {
1167 support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET;
1168 query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET;
1169 check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET;
1171 switch (func_to_switch) {
1172 case CURRENT_LIMIT_400:
1173 support_mask = CURRENT_LIMIT_400_MASK;
1174 query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK;
1175 switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY;
1178 case CURRENT_LIMIT_600:
1179 support_mask = CURRENT_LIMIT_600_MASK;
1180 query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK;
1181 switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY;
1184 case CURRENT_LIMIT_800:
1185 support_mask = CURRENT_LIMIT_800_MASK;
1186 query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK;
1187 switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY;
1199 if (func_group == SD_FUNC_GROUP_1) {
1200 if (!(buf[support_offset] & support_mask) ||
1201 ((buf[query_switch_offset] & 0x0F) != query_switch)) {
1207 /* Check 'Busy Status' */
1208 if ((buf[DATA_STRUCTURE_VER_OFFSET] == 0x01) &&
1209 ((buf[check_busy_offset] & switch_busy) == switch_busy)) {
1214 return STATUS_SUCCESS;
1217 static int sd_check_switch_mode(struct rtsx_chip *chip, u8 mode,
1218 u8 func_group, u8 func_to_switch, u8 bus_width)
1220 struct sd_info *sd_card = &(chip->sd_card);
1224 dev_dbg(rtsx_dev(chip), "sd_check_switch_mode (mode = %d, func_group = %d, func_to_switch = %d)\n",
1225 mode, func_group, func_to_switch);
1227 cmd[0] = 0x40 | SWITCH;
1230 if (func_group == SD_FUNC_GROUP_1) {
1233 cmd[4] = 0xF0 + func_to_switch;
1234 } else if (func_group == SD_FUNC_GROUP_3) {
1236 cmd[3] = 0xF0 + func_to_switch;
1238 } else if (func_group == SD_FUNC_GROUP_4) {
1240 cmd[3] = 0x0F + (func_to_switch << 4);
1243 cmd[1] = SD_CHECK_MODE;
1249 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width,
1251 if (retval != STATUS_SUCCESS) {
1252 rtsx_clear_sd_error(chip);
1257 dev_dbg(rtsx_dev(chip), "%*ph\n", 64, buf);
1259 if (func_group == NO_ARGUMENT) {
1260 sd_card->func_group1_mask = buf[0x0D];
1261 sd_card->func_group2_mask = buf[0x0B];
1262 sd_card->func_group3_mask = buf[0x09];
1263 sd_card->func_group4_mask = buf[0x07];
1265 dev_dbg(rtsx_dev(chip), "func_group1_mask = 0x%02x\n",
1267 dev_dbg(rtsx_dev(chip), "func_group2_mask = 0x%02x\n",
1269 dev_dbg(rtsx_dev(chip), "func_group3_mask = 0x%02x\n",
1271 dev_dbg(rtsx_dev(chip), "func_group4_mask = 0x%02x\n",
1274 /* Maximum current consumption, check whether current is
1275 * acceptable; bit[511:496] = 0x0000 means some error happened.
1277 u16 cc = ((u16)buf[0] << 8) | buf[1];
1279 dev_dbg(rtsx_dev(chip), "Maximum current consumption: %dmA\n",
1281 if ((cc == 0) || (cc > 800)) {
1286 retval = sd_query_switch_result(chip, func_group,
1287 func_to_switch, buf, 64);
1288 if (retval != STATUS_SUCCESS) {
1293 if ((cc > 400) || (func_to_switch > CURRENT_LIMIT_400)) {
1294 retval = rtsx_write_register(chip, OCPPARA2,
1296 chip->sd_800mA_ocp_thd);
1301 retval = rtsx_write_register(chip, CARD_PWR_CTL,
1311 return STATUS_SUCCESS;
1314 static u8 downgrade_switch_mode(u8 func_group, u8 func_to_switch)
1316 if (func_group == SD_FUNC_GROUP_1) {
1317 if (func_to_switch > HS_SUPPORT)
1320 } else if (func_group == SD_FUNC_GROUP_4) {
1321 if (func_to_switch > CURRENT_LIMIT_200)
1325 return func_to_switch;
1328 static int sd_check_switch(struct rtsx_chip *chip,
1329 u8 func_group, u8 func_to_switch, u8 bus_width)
1333 bool switch_good = false;
1335 for (i = 0; i < 3; i++) {
1336 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1337 sd_set_err_code(chip, SD_NO_CARD);
1342 retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group,
1343 func_to_switch, bus_width);
1344 if (retval == STATUS_SUCCESS) {
1347 retval = sd_check_switch_mode(chip, SD_SWITCH_MODE,
1348 func_group, func_to_switch, bus_width);
1349 if (retval == STATUS_SUCCESS) {
1354 retval = rtsx_read_register(chip, SD_STAT1, &stat);
1359 if (stat & SD_CRC16_ERR) {
1360 dev_dbg(rtsx_dev(chip), "SD CRC16 error when switching mode\n");
1366 func_to_switch = downgrade_switch_mode(func_group,
1377 return STATUS_SUCCESS;
1380 static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width)
1382 struct sd_info *sd_card = &(chip->sd_card);
1385 u8 func_to_switch = 0;
1387 /* Get supported functions */
1388 retval = sd_check_switch_mode(chip, SD_CHECK_MODE,
1389 NO_ARGUMENT, NO_ARGUMENT, bus_width);
1390 if (retval != STATUS_SUCCESS) {
1395 sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail);
1397 /* Function Group 1: Access Mode */
1398 for (i = 0; i < 4; i++) {
1399 switch ((u8)(chip->sd_speed_prior >> (i*8))) {
1400 case SDR104_SUPPORT:
1401 if ((sd_card->func_group1_mask & SDR104_SUPPORT_MASK)
1402 && chip->sdr104_en) {
1403 func_to_switch = SDR104_SUPPORT;
1408 if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK)
1409 && chip->ddr50_en) {
1410 func_to_switch = DDR50_SUPPORT;
1415 if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK)
1416 && chip->sdr50_en) {
1417 func_to_switch = SDR50_SUPPORT;
1422 if (sd_card->func_group1_mask & HS_SUPPORT_MASK)
1423 func_to_switch = HS_SUPPORT;
1436 dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_1: func_to_switch = 0x%02x",
1439 #ifdef SUPPORT_SD_LOCK
1440 if ((sd_card->sd_lock_status & SD_SDR_RST)
1441 && (DDR50_SUPPORT == func_to_switch)
1442 && (sd_card->func_group1_mask & SDR50_SUPPORT_MASK)) {
1443 func_to_switch = SDR50_SUPPORT;
1444 dev_dbg(rtsx_dev(chip), "Using SDR50 instead of DDR50 for SD Lock\n");
1448 if (func_to_switch) {
1449 retval = sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch,
1451 if (retval != STATUS_SUCCESS) {
1452 if (func_to_switch == SDR104_SUPPORT) {
1453 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK;
1454 } else if (func_to_switch == DDR50_SUPPORT) {
1455 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
1457 } else if (func_to_switch == SDR50_SUPPORT) {
1458 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
1459 DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
1465 if (func_to_switch == SDR104_SUPPORT)
1466 SET_SD_SDR104(sd_card);
1467 else if (func_to_switch == DDR50_SUPPORT)
1468 SET_SD_DDR50(sd_card);
1469 else if (func_to_switch == SDR50_SUPPORT)
1470 SET_SD_SDR50(sd_card);
1475 if (CHK_SD_DDR50(sd_card)) {
1476 retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06,
1482 retval = sd_set_sample_push_timing(chip);
1483 if (retval != STATUS_SUCCESS) {
1489 if (!func_to_switch || (func_to_switch == HS_SUPPORT)) {
1490 /* Do not try to switch current limit if the card doesn't
1491 * support UHS mode or we don't want it to support UHS mode
1493 return STATUS_SUCCESS;
1496 /* Function Group 4: Current Limit */
1497 func_to_switch = 0xFF;
1499 for (i = 0; i < 4; i++) {
1500 switch ((u8)(chip->sd_current_prior >> (i*8))) {
1501 case CURRENT_LIMIT_800:
1502 if (sd_card->func_group4_mask & CURRENT_LIMIT_800_MASK)
1503 func_to_switch = CURRENT_LIMIT_800;
1507 case CURRENT_LIMIT_600:
1508 if (sd_card->func_group4_mask & CURRENT_LIMIT_600_MASK)
1509 func_to_switch = CURRENT_LIMIT_600;
1513 case CURRENT_LIMIT_400:
1514 if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK)
1515 func_to_switch = CURRENT_LIMIT_400;
1519 case CURRENT_LIMIT_200:
1520 if (sd_card->func_group4_mask & CURRENT_LIMIT_200_MASK)
1521 func_to_switch = CURRENT_LIMIT_200;
1529 if (func_to_switch != 0xFF)
1533 dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_4: func_to_switch = 0x%02x",
1536 if (func_to_switch <= CURRENT_LIMIT_800) {
1537 retval = sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch,
1539 if (retval != STATUS_SUCCESS) {
1540 if (sd_check_err_code(chip, SD_NO_CARD)) {
1545 dev_dbg(rtsx_dev(chip), "Switch current limit finished! (%d)\n",
1549 if (CHK_SD_DDR50(sd_card)) {
1550 retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06, 0);
1557 return STATUS_SUCCESS;
1560 static int sd_wait_data_idle(struct rtsx_chip *chip)
1562 int retval = STATUS_TIMEDOUT;
1566 for (i = 0; i < 100; i++) {
1567 retval = rtsx_read_register(chip, SD_DATA_STATE, &val);
1572 if (val & SD_DATA_IDLE) {
1573 retval = STATUS_SUCCESS;
1578 dev_dbg(rtsx_dev(chip), "SD_DATA_STATE: 0x%02x\n", val);
1583 static int sd_sdr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1588 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1589 if (retval != STATUS_SUCCESS) {
1594 cmd[0] = 0x40 | SEND_TUNING_PATTERN;
1600 retval = sd_read_data(chip, SD_TM_AUTO_TUNING,
1601 cmd, 5, 0x40, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1602 if (retval != STATUS_SUCCESS) {
1603 (void)sd_wait_data_idle(chip);
1605 rtsx_clear_sd_error(chip);
1610 return STATUS_SUCCESS;
1613 static int sd_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1615 struct sd_info *sd_card = &(chip->sd_card);
1619 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1620 if (retval != STATUS_SUCCESS) {
1625 dev_dbg(rtsx_dev(chip), "sd ddr tuning rx\n");
1627 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
1628 SD_RSP_TYPE_R1, NULL, 0);
1629 if (retval != STATUS_SUCCESS) {
1634 cmd[0] = 0x40 | SD_STATUS;
1640 retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1641 cmd, 5, 64, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1642 if (retval != STATUS_SUCCESS) {
1643 (void)sd_wait_data_idle(chip);
1645 rtsx_clear_sd_error(chip);
1650 return STATUS_SUCCESS;
1653 static int mmc_ddr_tunning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1655 struct sd_info *sd_card = &(chip->sd_card);
1657 u8 cmd[5], bus_width;
1659 if (CHK_MMC_8BIT(sd_card))
1660 bus_width = SD_BUS_WIDTH_8;
1661 else if (CHK_MMC_4BIT(sd_card))
1662 bus_width = SD_BUS_WIDTH_4;
1664 bus_width = SD_BUS_WIDTH_1;
1666 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1667 if (retval != STATUS_SUCCESS) {
1672 dev_dbg(rtsx_dev(chip), "mmc ddr tuning rx\n");
1674 cmd[0] = 0x40 | SEND_EXT_CSD;
1680 retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1681 cmd, 5, 0x200, 1, bus_width, NULL, 0, 100);
1682 if (retval != STATUS_SUCCESS) {
1683 (void)sd_wait_data_idle(chip);
1685 rtsx_clear_sd_error(chip);
1690 return STATUS_SUCCESS;
1693 static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1695 struct sd_info *sd_card = &(chip->sd_card);
1698 retval = sd_change_phase(chip, sample_point, TUNE_TX);
1699 if (retval != STATUS_SUCCESS) {
1704 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1705 SD_RSP_80CLK_TIMEOUT_EN);
1711 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1712 SD_RSP_TYPE_R1, NULL, 0);
1713 if (retval != STATUS_SUCCESS) {
1714 if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1715 rtsx_write_register(chip, SD_CFG3,
1716 SD_RSP_80CLK_TIMEOUT_EN, 0);
1722 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1729 return STATUS_SUCCESS;
1732 static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1734 struct sd_info *sd_card = &(chip->sd_card);
1736 u8 cmd[5], bus_width;
1738 retval = sd_change_phase(chip, sample_point, TUNE_TX);
1739 if (retval != STATUS_SUCCESS) {
1744 if (CHK_SD(sd_card)) {
1745 bus_width = SD_BUS_WIDTH_4;
1747 if (CHK_MMC_8BIT(sd_card))
1748 bus_width = SD_BUS_WIDTH_8;
1749 else if (CHK_MMC_4BIT(sd_card))
1750 bus_width = SD_BUS_WIDTH_4;
1752 bus_width = SD_BUS_WIDTH_1;
1755 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
1756 if (retval != STATUS_SUCCESS) {
1761 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1762 SD_RSP_80CLK_TIMEOUT_EN);
1768 cmd[0] = 0x40 | PROGRAM_CSD;
1774 retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2,
1775 cmd, 5, 16, 1, bus_width, sd_card->raw_csd, 16, 100);
1776 if (retval != STATUS_SUCCESS) {
1777 rtsx_clear_sd_error(chip);
1778 rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1783 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1790 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1,
1793 return STATUS_SUCCESS;
1796 static u8 sd_search_final_phase(struct rtsx_chip *chip, u32 phase_map,
1799 struct sd_info *sd_card = &(chip->sd_card);
1800 struct timing_phase_path path[MAX_PHASE + 1];
1801 int i, j, cont_path_cnt;
1803 int max_len, final_path_idx;
1804 u8 final_phase = 0xFF;
1806 if (phase_map == 0xFFFFFFFF) {
1807 if (tune_dir == TUNE_RX)
1808 final_phase = (u8)chip->sd_default_rx_phase;
1810 final_phase = (u8)chip->sd_default_tx_phase;
1818 for (i = 0; i < MAX_PHASE + 1; i++) {
1819 if (phase_map & (1 << i)) {
1822 j = cont_path_cnt++;
1830 if (cont_path_cnt) {
1831 int idx = cont_path_cnt - 1;
1833 path[idx].len = path[idx].end -
1834 path[idx].start + 1;
1835 path[idx].mid = path[idx].start +
1841 if (cont_path_cnt == 0) {
1842 dev_dbg(rtsx_dev(chip), "No continuous phase path\n");
1845 int idx = cont_path_cnt - 1;
1847 path[idx].len = path[idx].end - path[idx].start + 1;
1848 path[idx].mid = path[idx].start + path[idx].len / 2;
1851 if ((path[0].start == 0) &&
1852 (path[cont_path_cnt - 1].end == MAX_PHASE)) {
1853 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
1854 path[0].len += path[cont_path_cnt - 1].len;
1855 path[0].mid = path[0].start + path[0].len / 2;
1856 if (path[0].mid < 0)
1857 path[0].mid += MAX_PHASE + 1;
1865 for (i = 0; i < cont_path_cnt; i++) {
1866 if (path[i].len > max_len) {
1867 max_len = path[i].len;
1868 final_phase = (u8)path[i].mid;
1872 dev_dbg(rtsx_dev(chip), "path[%d].start = %d\n",
1874 dev_dbg(rtsx_dev(chip), "path[%d].end = %d\n", i, path[i].end);
1875 dev_dbg(rtsx_dev(chip), "path[%d].len = %d\n", i, path[i].len);
1876 dev_dbg(rtsx_dev(chip), "path[%d].mid = %d\n", i, path[i].mid);
1877 dev_dbg(rtsx_dev(chip), "\n");
1880 if (tune_dir == TUNE_TX) {
1881 if (CHK_SD_SDR104(sd_card)) {
1883 int temp_mid = (max_len - 16) / 2;
1884 int temp_final_phase =
1885 path[final_path_idx].end -
1886 (max_len - (6 + temp_mid));
1888 if (temp_final_phase < 0)
1889 final_phase = (u8)(temp_final_phase +
1892 final_phase = (u8)temp_final_phase;
1894 } else if (CHK_SD_SDR50(sd_card)) {
1896 int temp_mid = (max_len - 13) / 2;
1897 int temp_final_phase =
1898 path[final_path_idx].end -
1899 (max_len - (3 + temp_mid));
1901 if (temp_final_phase < 0)
1902 final_phase = (u8)(temp_final_phase +
1905 final_phase = (u8)temp_final_phase;
1911 dev_dbg(rtsx_dev(chip), "Final chosen phase: %d\n", final_phase);
1915 static int sd_tuning_rx(struct rtsx_chip *chip)
1917 struct sd_info *sd_card = &(chip->sd_card);
1920 u32 raw_phase_map[3], phase_map;
1922 int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1924 if (CHK_SD(sd_card)) {
1925 if (CHK_SD_DDR50(sd_card))
1926 tuning_cmd = sd_ddr_tuning_rx_cmd;
1928 tuning_cmd = sd_sdr_tuning_rx_cmd;
1931 if (CHK_MMC_DDR52(sd_card))
1932 tuning_cmd = mmc_ddr_tunning_rx_cmd;
1939 for (i = 0; i < 3; i++) {
1940 raw_phase_map[i] = 0;
1941 for (j = MAX_PHASE; j >= 0; j--) {
1942 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1943 sd_set_err_code(chip, SD_NO_CARD);
1948 retval = tuning_cmd(chip, (u8)j);
1949 if (retval == STATUS_SUCCESS)
1950 raw_phase_map[i] |= 1 << j;
1954 phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1955 for (i = 0; i < 3; i++)
1956 dev_dbg(rtsx_dev(chip), "RX raw_phase_map[%d] = 0x%08x\n",
1957 i, raw_phase_map[i]);
1959 dev_dbg(rtsx_dev(chip), "RX phase_map = 0x%08x\n", phase_map);
1961 final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX);
1962 if (final_phase == 0xFF) {
1967 retval = sd_change_phase(chip, final_phase, TUNE_RX);
1968 if (retval != STATUS_SUCCESS) {
1973 return STATUS_SUCCESS;
1976 static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip)
1978 struct sd_info *sd_card = &(chip->sd_card);
1984 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1985 SD_RSP_80CLK_TIMEOUT_EN);
1992 for (i = MAX_PHASE; i >= 0; i--) {
1993 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1994 sd_set_err_code(chip, SD_NO_CARD);
1995 rtsx_write_register(chip, SD_CFG3,
1996 SD_RSP_80CLK_TIMEOUT_EN, 0);
2001 retval = sd_change_phase(chip, (u8)i, TUNE_TX);
2002 if (retval != STATUS_SUCCESS)
2005 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
2006 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL,
2008 if ((retval == STATUS_SUCCESS) ||
2009 !sd_check_err_code(chip, SD_RSP_TIMEOUT))
2010 phase_map |= 1 << i;
2013 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
2020 dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase_map = 0x%08x\n",
2023 final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
2024 if (final_phase == 0xFF) {
2029 retval = sd_change_phase(chip, final_phase, TUNE_TX);
2030 if (retval != STATUS_SUCCESS) {
2035 dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase: %d\n",
2038 return STATUS_SUCCESS;
2041 static int sd_tuning_tx(struct rtsx_chip *chip)
2043 struct sd_info *sd_card = &(chip->sd_card);
2046 u32 raw_phase_map[3], phase_map;
2048 int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
2050 if (CHK_SD(sd_card)) {
2051 if (CHK_SD_DDR50(sd_card))
2052 tuning_cmd = sd_ddr_tuning_tx_cmd;
2054 tuning_cmd = sd_sdr_tuning_tx_cmd;
2057 if (CHK_MMC_DDR52(sd_card))
2058 tuning_cmd = sd_ddr_tuning_tx_cmd;
2065 for (i = 0; i < 3; i++) {
2066 raw_phase_map[i] = 0;
2067 for (j = MAX_PHASE; j >= 0; j--) {
2068 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2069 sd_set_err_code(chip, SD_NO_CARD);
2070 rtsx_write_register(chip, SD_CFG3,
2071 SD_RSP_80CLK_TIMEOUT_EN, 0);
2076 retval = tuning_cmd(chip, (u8)j);
2077 if (retval == STATUS_SUCCESS)
2078 raw_phase_map[i] |= 1 << j;
2082 phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
2083 for (i = 0; i < 3; i++)
2084 dev_dbg(rtsx_dev(chip), "TX raw_phase_map[%d] = 0x%08x\n",
2085 i, raw_phase_map[i]);
2087 dev_dbg(rtsx_dev(chip), "TX phase_map = 0x%08x\n", phase_map);
2089 final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
2090 if (final_phase == 0xFF) {
2095 retval = sd_change_phase(chip, final_phase, TUNE_TX);
2096 if (retval != STATUS_SUCCESS) {
2101 return STATUS_SUCCESS;
2104 static int sd_sdr_tuning(struct rtsx_chip *chip)
2108 retval = sd_tuning_tx(chip);
2109 if (retval != STATUS_SUCCESS) {
2114 retval = sd_tuning_rx(chip);
2115 if (retval != STATUS_SUCCESS) {
2120 return STATUS_SUCCESS;
2123 static int sd_ddr_tuning(struct rtsx_chip *chip)
2127 if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
2128 retval = sd_ddr_pre_tuning_tx(chip);
2129 if (retval != STATUS_SUCCESS) {
2134 retval = sd_change_phase(chip, (u8)chip->sd_ddr_tx_phase,
2136 if (retval != STATUS_SUCCESS) {
2142 retval = sd_tuning_rx(chip);
2143 if (retval != STATUS_SUCCESS) {
2148 if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
2149 retval = sd_tuning_tx(chip);
2150 if (retval != STATUS_SUCCESS) {
2156 return STATUS_SUCCESS;
2159 static int mmc_ddr_tuning(struct rtsx_chip *chip)
2163 if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
2164 retval = sd_ddr_pre_tuning_tx(chip);
2165 if (retval != STATUS_SUCCESS) {
2170 retval = sd_change_phase(chip, (u8)chip->mmc_ddr_tx_phase,
2172 if (retval != STATUS_SUCCESS) {
2178 retval = sd_tuning_rx(chip);
2179 if (retval != STATUS_SUCCESS) {
2184 if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
2185 retval = sd_tuning_tx(chip);
2186 if (retval != STATUS_SUCCESS) {
2192 return STATUS_SUCCESS;
2195 int sd_switch_clock(struct rtsx_chip *chip)
2197 struct sd_info *sd_card = &(chip->sd_card);
2201 retval = select_card(chip, SD_CARD);
2202 if (retval != STATUS_SUCCESS) {
2207 retval = switch_clock(chip, sd_card->sd_clock);
2208 if (retval != STATUS_SUCCESS) {
2214 if (CHK_SD(sd_card)) {
2215 if (CHK_SD_DDR50(sd_card))
2216 retval = sd_ddr_tuning(chip);
2218 retval = sd_sdr_tuning(chip);
2220 if (CHK_MMC_DDR52(sd_card))
2221 retval = mmc_ddr_tuning(chip);
2224 if (retval != STATUS_SUCCESS) {
2230 return STATUS_SUCCESS;
2233 static int sd_prepare_reset(struct rtsx_chip *chip)
2235 struct sd_info *sd_card = &(chip->sd_card);
2238 if (chip->asic_code)
2239 sd_card->sd_clock = 29;
2241 sd_card->sd_clock = CLK_30;
2243 sd_card->sd_type = 0;
2244 sd_card->seq_mode = 0;
2245 sd_card->sd_data_buf_ready = 0;
2246 sd_card->capacity = 0;
2248 #ifdef SUPPORT_SD_LOCK
2249 sd_card->sd_lock_status = 0;
2250 sd_card->sd_erase_status = 0;
2253 chip->capacity[chip->card2lun[SD_CARD]] = 0;
2256 retval = sd_set_init_para(chip);
2257 if (retval != STATUS_SUCCESS) {
2262 retval = rtsx_write_register(chip, REG_SD_CFG1, 0xFF, 0x40);
2268 retval = rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR,
2269 SD_STOP | SD_CLR_ERR);
2275 retval = select_card(chip, SD_CARD);
2276 if (retval != STATUS_SUCCESS) {
2281 return STATUS_SUCCESS;
2284 static int sd_pull_ctl_disable(struct rtsx_chip *chip)
2288 if (CHECK_PID(chip, 0x5208)) {
2289 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF,
2290 XD_D3_PD | SD_D7_PD | SD_CLK_PD | SD_D5_PD);
2295 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF,
2296 SD_D6_PD | SD_D0_PD | SD_D1_PD | XD_D5_PD);
2301 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF,
2302 SD_D4_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
2307 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF,
2308 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
2313 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF,
2314 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
2319 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF,
2320 MS_D5_PD | MS_D4_PD);
2325 } else if (CHECK_PID(chip, 0x5288)) {
2326 if (CHECK_BARO_PKG(chip, QFN)) {
2327 retval = rtsx_write_register(chip, CARD_PULL_CTL1,
2333 retval = rtsx_write_register(chip, CARD_PULL_CTL2,
2339 retval = rtsx_write_register(chip, CARD_PULL_CTL3,
2345 retval = rtsx_write_register(chip, CARD_PULL_CTL4,
2354 return STATUS_SUCCESS;
2357 int sd_pull_ctl_enable(struct rtsx_chip *chip)
2361 rtsx_init_cmd(chip);
2363 if (CHECK_PID(chip, 0x5208)) {
2364 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
2365 XD_D3_PD | SD_DAT7_PU | SD_CLK_NP | SD_D5_PU);
2366 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
2367 SD_D6_PU | SD_D0_PU | SD_D1_PU | XD_D5_PD);
2368 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
2369 SD_D4_PU | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
2370 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
2371 XD_RDY_PD | SD_D3_PU | SD_D2_PU | XD_ALE_PD);
2372 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
2373 MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
2374 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
2375 MS_D5_PD | MS_D4_PD);
2376 } else if (CHECK_PID(chip, 0x5288)) {
2377 if (CHECK_BARO_PKG(chip, QFN)) {
2378 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
2380 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
2382 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
2384 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
2389 retval = rtsx_send_cmd(chip, SD_CARD, 100);
2395 return STATUS_SUCCESS;
2398 static int sd_init_power(struct rtsx_chip *chip)
2402 retval = sd_power_off_card3v3(chip);
2403 if (retval != STATUS_SUCCESS) {
2408 if (!chip->ft2_fast_mode)
2411 retval = enable_card_clock(chip, SD_CARD);
2412 if (retval != STATUS_SUCCESS) {
2417 if (chip->asic_code) {
2418 retval = sd_pull_ctl_enable(chip);
2419 if (retval != STATUS_SUCCESS) {
2424 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
2425 FPGA_SD_PULL_CTL_BIT | 0x20, 0);
2432 if (!chip->ft2_fast_mode) {
2433 retval = card_power_on(chip, SD_CARD);
2434 if (retval != STATUS_SUCCESS) {
2442 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
2443 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
2451 retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN,
2458 return STATUS_SUCCESS;
2461 static int sd_dummy_clock(struct rtsx_chip *chip)
2465 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0x01);
2471 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0);
2477 return STATUS_SUCCESS;
2480 static int sd_read_lba0(struct rtsx_chip *chip)
2482 struct sd_info *sd_card = &(chip->sd_card);
2484 u8 cmd[5], bus_width;
2486 cmd[0] = 0x40 | READ_SINGLE_BLOCK;
2492 if (CHK_SD(sd_card)) {
2493 bus_width = SD_BUS_WIDTH_4;
2495 if (CHK_MMC_8BIT(sd_card))
2496 bus_width = SD_BUS_WIDTH_8;
2497 else if (CHK_MMC_4BIT(sd_card))
2498 bus_width = SD_BUS_WIDTH_4;
2500 bus_width = SD_BUS_WIDTH_1;
2503 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd,
2504 5, 512, 1, bus_width, NULL, 0, 100);
2505 if (retval != STATUS_SUCCESS) {
2506 rtsx_clear_sd_error(chip);
2511 return STATUS_SUCCESS;
2514 static int sd_check_wp_state(struct rtsx_chip *chip)
2516 struct sd_info *sd_card = &(chip->sd_card);
2522 retval = sd_send_cmd_get_rsp(chip, APP_CMD,
2523 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2524 if (retval != STATUS_SUCCESS) {
2529 cmd[0] = 0x40 | SD_STATUS;
2535 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1,
2536 SD_BUS_WIDTH_4, buf, 64, 250);
2537 if (retval != STATUS_SUCCESS) {
2538 rtsx_clear_sd_error(chip);
2540 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2541 SD_RSP_TYPE_R1, NULL, 0);
2546 dev_dbg(rtsx_dev(chip), "ACMD13:\n");
2547 dev_dbg(rtsx_dev(chip), "%*ph\n", 64, buf);
2549 sd_card_type = ((u16)buf[2] << 8) | buf[3];
2550 dev_dbg(rtsx_dev(chip), "sd_card_type = 0x%04x\n", sd_card_type);
2551 if ((sd_card_type == 0x0001) || (sd_card_type == 0x0002)) {
2552 /* ROM card or OTP */
2553 chip->card_wp |= SD_CARD;
2556 /* Check SD Machanical Write-Protect Switch */
2557 val = rtsx_readl(chip, RTSX_BIPR);
2558 if (val & SD_WRITE_PROTECT)
2559 chip->card_wp |= SD_CARD;
2561 return STATUS_SUCCESS;
2564 static int reset_sd(struct rtsx_chip *chip)
2566 struct sd_info *sd_card = &(chip->sd_card);
2567 bool hi_cap_flow = false;
2568 int retval, i = 0, j = 0, k = 0;
2569 bool sd_dont_switch = false;
2570 bool support_1v8 = false;
2571 bool try_sdio = true;
2573 u8 switch_bus_width;
2575 bool sd20_mode = false;
2584 hi_cap_flow = false;
2586 #ifdef SUPPORT_SD_LOCK
2587 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2588 goto SD_UNLOCK_ENTRY;
2591 retval = sd_prepare_reset(chip);
2592 if (retval != STATUS_SUCCESS) {
2597 retval = sd_dummy_clock(chip);
2598 if (retval != STATUS_SUCCESS) {
2603 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && try_sdio) {
2606 for (; rty_cnt < chip->sdio_retry_cnt; rty_cnt++) {
2607 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2608 sd_set_err_code(chip, SD_NO_CARD);
2613 retval = sd_send_cmd_get_rsp(chip, IO_SEND_OP_COND, 0,
2614 SD_RSP_TYPE_R4, rsp, 5);
2615 if (retval == STATUS_SUCCESS) {
2616 int func_num = (rsp[1] >> 4) & 0x07;
2619 dev_dbg(rtsx_dev(chip), "SD_IO card (Function number: %d)!\n",
2629 sd_init_power(chip);
2631 sd_dummy_clock(chip);
2634 dev_dbg(rtsx_dev(chip), "Normal card!\n");
2637 /* Start Initialization Process of SD Card */
2639 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0,
2641 if (retval != STATUS_SUCCESS) {
2648 retval = sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA,
2649 SD_RSP_TYPE_R7, rsp, 5);
2650 if (retval == STATUS_SUCCESS) {
2651 if ((rsp[4] == 0xAA) && ((rsp[3] & 0x0f) == 0x01)) {
2653 voltage = SUPPORT_VOLTAGE | 0x40000000;
2658 voltage = SUPPORT_VOLTAGE;
2660 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0,
2661 SD_RSP_TYPE_R0, NULL, 0);
2662 if (retval != STATUS_SUCCESS) {
2671 retval = sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1,
2673 if (retval != STATUS_SUCCESS) {
2674 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2675 sd_set_err_code(chip, SD_NO_CARD);
2689 retval = sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage,
2690 SD_RSP_TYPE_R3, rsp, 5);
2691 if (retval != STATUS_SUCCESS) {
2703 } while (!(rsp[1] & 0x80) && (i < 255));
2712 SET_SD_HCXC(sd_card);
2714 CLR_SD_HCXC(sd_card);
2716 support_1v8 = false;
2718 CLR_SD_HCXC(sd_card);
2719 support_1v8 = false;
2721 dev_dbg(rtsx_dev(chip), "support_1v8 = %d\n", support_1v8);
2724 retval = sd_voltage_switch(chip);
2725 if (retval != STATUS_SUCCESS) {
2731 retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2,
2733 if (retval != STATUS_SUCCESS) {
2738 for (i = 0; i < 3; i++) {
2739 retval = sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0,
2740 SD_RSP_TYPE_R6, rsp, 5);
2741 if (retval != STATUS_SUCCESS) {
2746 sd_card->sd_addr = (u32)rsp[1] << 24;
2747 sd_card->sd_addr += (u32)rsp[2] << 16;
2749 if (sd_card->sd_addr)
2753 retval = sd_check_csd(chip, 1);
2754 if (retval != STATUS_SUCCESS) {
2759 retval = sd_select_card(chip, 1);
2760 if (retval != STATUS_SUCCESS) {
2765 #ifdef SUPPORT_SD_LOCK
2767 retval = sd_update_lock_status(chip);
2768 if (retval != STATUS_SUCCESS) {
2773 if (sd_card->sd_lock_status & SD_LOCKED) {
2774 sd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST);
2775 return STATUS_SUCCESS;
2776 } else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) {
2777 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
2781 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2782 SD_RSP_TYPE_R1, NULL, 0);
2783 if (retval != STATUS_SUCCESS) {
2788 retval = sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0,
2789 SD_RSP_TYPE_R1, NULL, 0);
2790 if (retval != STATUS_SUCCESS) {
2796 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2797 SD_RSP_TYPE_R1, NULL, 0);
2798 if (retval != STATUS_SUCCESS) {
2803 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2,
2804 SD_RSP_TYPE_R1, NULL, 0);
2805 if (retval != STATUS_SUCCESS) {
2810 switch_bus_width = SD_BUS_WIDTH_4;
2812 switch_bus_width = SD_BUS_WIDTH_1;
2815 retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1,
2817 if (retval != STATUS_SUCCESS) {
2822 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2823 if (retval != STATUS_SUCCESS) {
2828 if (!(sd_card->raw_csd[4] & 0x40))
2829 sd_dont_switch = true;
2831 if (!sd_dont_switch) {
2833 /* Set sd_switch_fail here, because we needn't
2834 * switch to UHS mode
2836 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
2837 DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
2840 /* Check the card whether follow SD1.1 spec or higher */
2841 retval = sd_check_spec(chip, switch_bus_width);
2842 if (retval == STATUS_SUCCESS) {
2843 retval = sd_switch_function(chip, switch_bus_width);
2844 if (retval != STATUS_SUCCESS) {
2845 sd_init_power(chip);
2846 sd_dont_switch = true;
2853 sd_init_power(chip);
2854 sd_dont_switch = true;
2863 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2864 SD_RSP_TYPE_R1, NULL, 0);
2865 if (retval != STATUS_SUCCESS) {
2870 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2,
2871 SD_RSP_TYPE_R1, NULL, 0);
2872 if (retval != STATUS_SUCCESS) {
2878 #ifdef SUPPORT_SD_LOCK
2879 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2882 if (!sd20_mode && CHK_SD30_SPEED(sd_card)) {
2885 retval = rtsx_write_register(chip, SD30_DRIVE_SEL, 0x07,
2886 chip->sd30_drive_sel_1v8);
2892 retval = sd_set_init_para(chip);
2893 if (retval != STATUS_SUCCESS) {
2898 if (CHK_SD_DDR50(sd_card))
2899 retval = sd_ddr_tuning(chip);
2901 retval = sd_sdr_tuning(chip);
2903 if (retval != STATUS_SUCCESS) {
2908 retval = sd_init_power(chip);
2909 if (retval != STATUS_SUCCESS) {
2920 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2921 SD_RSP_TYPE_R1, NULL, 0);
2923 if (CHK_SD_DDR50(sd_card)) {
2924 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
2925 if (retval != STATUS_SUCCESS)
2930 retval = sd_read_lba0(chip);
2931 if (retval != STATUS_SUCCESS) {
2936 retval = sd_init_power(chip);
2937 if (retval != STATUS_SUCCESS) {
2950 retval = sd_check_wp_state(chip);
2951 if (retval != STATUS_SUCCESS) {
2956 chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2958 #ifdef SUPPORT_SD_LOCK
2959 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
2960 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF,
2966 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF,
2975 return STATUS_SUCCESS;
2979 static int mmc_test_switch_bus(struct rtsx_chip *chip, u8 width)
2981 struct sd_info *sd_card = &(chip->sd_card);
2983 u8 buf[8] = {0}, bus_width, *ptr;
2987 retval = sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL,
2989 if (retval != STATUS_SUCCESS) {
2994 if (width == MMC_8BIT_BUS) {
2999 bus_width = SD_BUS_WIDTH_8;
3004 bus_width = SD_BUS_WIDTH_4;
3007 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0x02);
3008 if (retval != STATUS_SUCCESS) {
3013 retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3,
3014 NULL, 0, byte_cnt, 1, bus_width, buf, len, 100);
3015 if (retval != STATUS_SUCCESS) {
3016 rtsx_clear_sd_error(chip);
3017 rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
3022 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
3023 if (retval != STATUS_SUCCESS) {
3028 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", BUSTEST_R);
3030 rtsx_init_cmd(chip);
3032 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | BUSTEST_R);
3034 if (width == MMC_8BIT_BUS)
3035 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L,
3038 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L,
3041 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
3042 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
3044 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
3045 SD_CALCULATE_CRC7 | SD_NO_CHECK_CRC16 | SD_NO_WAIT_BUSY_END|
3046 SD_CHECK_CRC7 | SD_RSP_LEN_6);
3047 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
3049 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3050 SD_TM_NORMAL_READ | SD_TRANSFER_START);
3051 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
3054 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0);
3055 if (width == MMC_8BIT_BUS)
3056 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0);
3058 retval = rtsx_send_cmd(chip, SD_CARD, 100);
3060 rtsx_clear_sd_error(chip);
3065 ptr = rtsx_get_cmd_data(chip) + 1;
3067 if (width == MMC_8BIT_BUS) {
3068 dev_dbg(rtsx_dev(chip), "BUSTEST_R [8bits]: 0x%02x 0x%02x\n",
3070 if ((ptr[0] == 0xAA) && (ptr[1] == 0x55)) {
3074 if (CHK_MMC_DDR52(sd_card))
3079 retval = sd_send_cmd_get_rsp(chip, SWITCH, arg,
3080 SD_RSP_TYPE_R1b, rsp, 5);
3081 if ((retval == STATUS_SUCCESS) &&
3082 !(rsp[4] & MMC_SWITCH_ERR))
3083 return SWITCH_SUCCESS;
3086 dev_dbg(rtsx_dev(chip), "BUSTEST_R [4bits]: 0x%02x\n", ptr[0]);
3087 if (ptr[0] == 0xA5) {
3091 if (CHK_MMC_DDR52(sd_card))
3096 retval = sd_send_cmd_get_rsp(chip, SWITCH, arg,
3097 SD_RSP_TYPE_R1b, rsp, 5);
3098 if ((retval == STATUS_SUCCESS) &&
3099 !(rsp[4] & MMC_SWITCH_ERR))
3100 return SWITCH_SUCCESS;
3109 static int mmc_switch_timing_bus(struct rtsx_chip *chip, bool switch_ddr)
3111 struct sd_info *sd_card = &(chip->sd_card);
3113 u8 *ptr, card_type, card_type_mask = 0;
3115 CLR_MMC_HS(sd_card);
3117 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", SEND_EXT_CSD);
3119 rtsx_init_cmd(chip);
3121 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
3122 0x40 | SEND_EXT_CSD);
3123 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 0);
3124 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 0);
3125 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 0);
3126 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 0);
3128 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0);
3129 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 2);
3130 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
3131 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
3133 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
3134 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END|
3135 SD_CHECK_CRC7 | SD_RSP_LEN_6);
3136 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
3138 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3139 SD_TM_NORMAL_READ | SD_TRANSFER_START);
3140 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
3143 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0);
3144 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0);
3145 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0);
3146 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0);
3147 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0);
3149 retval = rtsx_send_cmd(chip, SD_CARD, 1000);
3151 if (retval == -ETIMEDOUT) {
3152 rtsx_clear_sd_error(chip);
3153 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3154 SD_RSP_TYPE_R1, NULL, 0);
3160 ptr = rtsx_get_cmd_data(chip);
3161 if (ptr[0] & SD_TRANSFER_ERR) {
3162 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3163 SD_RSP_TYPE_R1, NULL, 0);
3168 if (CHK_MMC_SECTOR_MODE(sd_card)) {
3169 sd_card->capacity = ((u32)ptr[5] << 24) | ((u32)ptr[4] << 16) |
3170 ((u32)ptr[3] << 8) | ((u32)ptr[2]);
3173 card_type_mask = 0x03;
3174 card_type = ptr[1] & card_type_mask;
3178 if (card_type & 0x04) {
3180 SET_MMC_DDR52(sd_card);
3182 SET_MMC_52M(sd_card);
3183 } else if (card_type & 0x02) {
3184 SET_MMC_52M(sd_card);
3186 SET_MMC_26M(sd_card);
3189 retval = sd_send_cmd_get_rsp(chip, SWITCH,
3190 0x03B90100, SD_RSP_TYPE_R1b, rsp, 5);
3191 if ((retval != STATUS_SUCCESS) || (rsp[4] & MMC_SWITCH_ERR))
3192 CLR_MMC_HS(sd_card);
3195 sd_choose_proper_clock(chip);
3196 retval = switch_clock(chip, sd_card->sd_clock);
3197 if (retval != STATUS_SUCCESS) {
3202 /* Test Bus Procedure */
3203 retval = mmc_test_switch_bus(chip, MMC_8BIT_BUS);
3204 if (retval == SWITCH_SUCCESS) {
3205 SET_MMC_8BIT(sd_card);
3206 chip->card_bus_width[chip->card2lun[SD_CARD]] = 8;
3207 #ifdef SUPPORT_SD_LOCK
3208 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
3210 } else if (retval == SWITCH_FAIL) {
3211 retval = mmc_test_switch_bus(chip, MMC_4BIT_BUS);
3212 if (retval == SWITCH_SUCCESS) {
3213 SET_MMC_4BIT(sd_card);
3214 chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
3215 #ifdef SUPPORT_SD_LOCK
3216 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
3218 } else if (retval == SWITCH_FAIL) {
3219 CLR_MMC_8BIT(sd_card);
3220 CLR_MMC_4BIT(sd_card);
3230 return STATUS_SUCCESS;
3234 static int reset_mmc(struct rtsx_chip *chip)
3236 struct sd_info *sd_card = &(chip->sd_card);
3237 int retval, i = 0, j = 0, k = 0;
3238 bool switch_ddr = true;
3243 #ifdef SUPPORT_SD_LOCK
3244 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
3245 goto MMC_UNLOCK_ENTRY;
3249 retval = sd_prepare_reset(chip);
3250 if (retval != STATUS_SUCCESS) {
3258 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0,
3260 if (retval != STATUS_SUCCESS) {
3266 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3267 sd_set_err_code(chip, SD_NO_CARD);
3272 retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND,
3273 (SUPPORT_VOLTAGE | 0x40000000),
3274 SD_RSP_TYPE_R3, rsp, 5);
3275 if (retval != STATUS_SUCCESS) {
3276 if (sd_check_err_code(chip, SD_BUSY) ||
3277 sd_check_err_code(chip, SD_TO_ERR)) {
3280 sd_clr_err_code(chip);
3289 sd_clr_err_code(chip);
3300 } while (!(rsp[1] & 0x80) && (i < 255));
3307 if ((rsp[1] & 0x60) == 0x40)
3308 SET_MMC_SECTOR_MODE(sd_card);
3310 CLR_MMC_SECTOR_MODE(sd_card);
3312 retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2,
3314 if (retval != STATUS_SUCCESS) {
3319 sd_card->sd_addr = 0x00100000;
3320 retval = sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr,
3321 SD_RSP_TYPE_R6, rsp, 5);
3322 if (retval != STATUS_SUCCESS) {
3327 retval = sd_check_csd(chip, 1);
3328 if (retval != STATUS_SUCCESS) {
3333 spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2;
3335 retval = sd_select_card(chip, 1);
3336 if (retval != STATUS_SUCCESS) {
3341 retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1,
3343 if (retval != STATUS_SUCCESS) {
3348 #ifdef SUPPORT_SD_LOCK
3350 retval = sd_update_lock_status(chip);
3351 if (retval != STATUS_SUCCESS) {
3357 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3358 if (retval != STATUS_SUCCESS) {
3363 chip->card_bus_width[chip->card2lun[SD_CARD]] = 1;
3365 if (!sd_card->mmc_dont_switch_bus) {
3366 if (spec_ver == 4) {
3368 retval = mmc_switch_timing_bus(chip, switch_ddr);
3369 if (retval != STATUS_SUCCESS) {
3370 retval = sd_init_power(chip);
3371 if (retval != STATUS_SUCCESS) {
3375 sd_card->mmc_dont_switch_bus = 1;
3381 if (CHK_MMC_SECTOR_MODE(sd_card) && (sd_card->capacity == 0)) {
3386 if (switch_ddr && CHK_MMC_DDR52(sd_card)) {
3387 retval = sd_set_init_para(chip);
3388 if (retval != STATUS_SUCCESS) {
3393 retval = mmc_ddr_tuning(chip);
3394 if (retval != STATUS_SUCCESS) {
3395 retval = sd_init_power(chip);
3396 if (retval != STATUS_SUCCESS) {
3406 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3407 if (retval == STATUS_SUCCESS) {
3408 retval = sd_read_lba0(chip);
3409 if (retval != STATUS_SUCCESS) {
3410 retval = sd_init_power(chip);
3411 if (retval != STATUS_SUCCESS) {
3424 #ifdef SUPPORT_SD_LOCK
3425 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
3426 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF,
3432 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF,
3441 temp = rtsx_readl(chip, RTSX_BIPR);
3442 if (temp & SD_WRITE_PROTECT)
3443 chip->card_wp |= SD_CARD;
3445 return STATUS_SUCCESS;
3448 int reset_sd_card(struct rtsx_chip *chip)
3450 struct sd_info *sd_card = &(chip->sd_card);
3453 sd_init_reg_addr(chip);
3455 memset(sd_card, 0, sizeof(struct sd_info));
3456 chip->capacity[chip->card2lun[SD_CARD]] = 0;
3458 retval = enable_card_clock(chip, SD_CARD);
3459 if (retval != STATUS_SUCCESS) {
3464 if (chip->ignore_sd && CHK_SDIO_EXIST(chip) &&
3465 !CHK_SDIO_IGNORED(chip)) {
3466 if (chip->asic_code) {
3467 retval = sd_pull_ctl_enable(chip);
3468 if (retval != STATUS_SUCCESS) {
3473 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
3474 FPGA_SD_PULL_CTL_BIT | 0x20, 0);
3475 if (retval != STATUS_SUCCESS) {
3480 retval = card_share_mode(chip, SD_CARD);
3481 if (retval != STATUS_SUCCESS) {
3491 retval = sd_init_power(chip);
3492 if (retval != STATUS_SUCCESS) {
3497 if (chip->sd_ctl & RESET_MMC_FIRST) {
3498 retval = reset_mmc(chip);
3499 if (retval != STATUS_SUCCESS) {
3500 if (sd_check_err_code(chip, SD_NO_CARD)) {
3505 retval = reset_sd(chip);
3506 if (retval != STATUS_SUCCESS) {
3512 retval = reset_sd(chip);
3513 if (retval != STATUS_SUCCESS) {
3514 if (sd_check_err_code(chip, SD_NO_CARD)) {
3523 retval = reset_mmc(chip);
3524 if (retval != STATUS_SUCCESS) {
3531 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3532 if (retval != STATUS_SUCCESS) {
3537 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3542 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3548 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3550 retval = sd_set_init_para(chip);
3551 if (retval != STATUS_SUCCESS) {
3556 dev_dbg(rtsx_dev(chip), "sd_card->sd_type = 0x%x\n", sd_card->sd_type);
3558 return STATUS_SUCCESS;
3561 static int reset_mmc_only(struct rtsx_chip *chip)
3563 struct sd_info *sd_card = &(chip->sd_card);
3566 sd_card->sd_type = 0;
3567 sd_card->seq_mode = 0;
3568 sd_card->sd_data_buf_ready = 0;
3569 sd_card->capacity = 0;
3570 sd_card->sd_switch_fail = 0;
3572 #ifdef SUPPORT_SD_LOCK
3573 sd_card->sd_lock_status = 0;
3574 sd_card->sd_erase_status = 0;
3577 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0;
3579 retval = enable_card_clock(chip, SD_CARD);
3580 if (retval != STATUS_SUCCESS) {
3585 retval = sd_init_power(chip);
3586 if (retval != STATUS_SUCCESS) {
3591 retval = reset_mmc(chip);
3592 if (retval != STATUS_SUCCESS) {
3597 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3598 if (retval != STATUS_SUCCESS) {
3603 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3608 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3614 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3616 retval = sd_set_init_para(chip);
3617 if (retval != STATUS_SUCCESS) {
3622 dev_dbg(rtsx_dev(chip), "In reset_mmc_only, sd_card->sd_type = 0x%x\n",
3625 return STATUS_SUCCESS;
3628 #define WAIT_DATA_READY_RTY_CNT 255
3630 static int wait_data_buf_ready(struct rtsx_chip *chip)
3632 struct sd_info *sd_card = &(chip->sd_card);
3635 for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) {
3636 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3637 sd_set_err_code(chip, SD_NO_CARD);
3642 sd_card->sd_data_buf_ready = 0;
3644 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
3645 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3646 if (retval != STATUS_SUCCESS) {
3651 if (sd_card->sd_data_buf_ready) {
3652 return sd_send_cmd_get_rsp(chip, SEND_STATUS,
3653 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3657 sd_set_err_code(chip, SD_TO_ERR);
3663 void sd_stop_seq_mode(struct rtsx_chip *chip)
3665 struct sd_info *sd_card = &(chip->sd_card);
3668 if (sd_card->seq_mode) {
3669 retval = sd_switch_clock(chip);
3670 if (retval != STATUS_SUCCESS)
3673 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3674 SD_RSP_TYPE_R1b, NULL, 0);
3675 if (retval != STATUS_SUCCESS)
3676 sd_set_err_code(chip, SD_STS_ERR);
3678 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3679 if (retval != STATUS_SUCCESS)
3680 sd_set_err_code(chip, SD_STS_ERR);
3682 sd_card->seq_mode = 0;
3684 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3688 static inline int sd_auto_tune_clock(struct rtsx_chip *chip)
3690 struct sd_info *sd_card = &(chip->sd_card);
3693 if (chip->asic_code) {
3694 if (sd_card->sd_clock > 30)
3695 sd_card->sd_clock -= 20;
3697 switch (sd_card->sd_clock) {
3699 sd_card->sd_clock = CLK_150;
3703 sd_card->sd_clock = CLK_120;
3707 sd_card->sd_clock = CLK_100;
3711 sd_card->sd_clock = CLK_80;
3715 sd_card->sd_clock = CLK_60;
3719 sd_card->sd_clock = CLK_50;
3727 retval = sd_switch_clock(chip);
3728 if (retval != STATUS_SUCCESS) {
3733 return STATUS_SUCCESS;
3736 int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector,
3739 struct sd_info *sd_card = &(chip->sd_card);
3744 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3745 dev_dbg(rtsx_dev(chip), "sd_rw: Read %d %s from 0x%x\n",
3746 sector_cnt, (sector_cnt > 1) ? "sectors" : "sector",
3749 dev_dbg(rtsx_dev(chip), "sd_rw: Write %d %s to 0x%x\n",
3750 sector_cnt, (sector_cnt > 1) ? "sectors" : "sector",
3754 sd_card->cleanup_counter = 0;
3756 if (!(chip->card_ready & SD_CARD)) {
3757 sd_card->seq_mode = 0;
3759 retval = reset_sd_card(chip);
3760 if (retval == STATUS_SUCCESS) {
3761 chip->card_ready |= SD_CARD;
3762 chip->card_fail &= ~SD_CARD;
3764 chip->card_ready &= ~SD_CARD;
3765 chip->card_fail |= SD_CARD;
3766 chip->capacity[chip->card2lun[SD_CARD]] = 0;
3767 chip->rw_need_retry = 1;
3773 if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card))
3774 data_addr = start_sector << 9;
3776 data_addr = start_sector;
3778 sd_clr_err_code(chip);
3780 retval = sd_switch_clock(chip);
3781 if (retval != STATUS_SUCCESS) {
3782 sd_set_err_code(chip, SD_IO_ERR);
3787 if (sd_card->seq_mode &&
3788 ((sd_card->pre_dir != srb->sc_data_direction) ||
3789 ((sd_card->pre_sec_addr + sd_card->pre_sec_cnt) !=
3791 if ((sd_card->pre_sec_cnt < 0x80)
3792 && (sd_card->pre_dir == DMA_FROM_DEVICE)
3793 && !CHK_SD30_SPEED(sd_card)
3794 && !CHK_SD_HS(sd_card)
3795 && !CHK_MMC_HS(sd_card)) {
3796 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3797 SD_RSP_TYPE_R1, NULL, 0);
3800 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
3801 0, SD_RSP_TYPE_R1b, NULL, 0);
3802 if (retval != STATUS_SUCCESS) {
3803 chip->rw_need_retry = 1;
3804 sd_set_err_code(chip, SD_STS_ERR);
3809 sd_card->seq_mode = 0;
3811 retval = rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3812 if (retval != STATUS_SUCCESS) {
3813 sd_set_err_code(chip, SD_IO_ERR);
3818 if ((sd_card->pre_sec_cnt < 0x80)
3819 && !CHK_SD30_SPEED(sd_card)
3820 && !CHK_SD_HS(sd_card)
3821 && !CHK_MMC_HS(sd_card)) {
3822 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3823 SD_RSP_TYPE_R1, NULL, 0);
3827 rtsx_init_cmd(chip);
3829 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
3830 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
3831 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
3833 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
3834 (u8)(sector_cnt >> 8));
3836 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
3838 if (CHK_MMC_8BIT(sd_card))
3839 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3840 0x03, SD_BUS_WIDTH_8);
3841 else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card))
3842 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3843 0x03, SD_BUS_WIDTH_4);
3845 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3846 0x03, SD_BUS_WIDTH_1);
3848 if (sd_card->seq_mode) {
3849 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16|
3850 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 |
3852 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3854 trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512,
3857 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3858 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3859 SD_TM_AUTO_READ_3 | SD_TRANSFER_START);
3861 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3862 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3865 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3866 SD_TRANSFER_END, SD_TRANSFER_END);
3868 rtsx_send_cmd_no_wait(chip);
3870 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3871 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n",
3872 READ_MULTIPLE_BLOCK);
3873 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
3874 0x40 | READ_MULTIPLE_BLOCK);
3875 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF,
3876 (u8)(data_addr >> 24));
3877 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF,
3878 (u8)(data_addr >> 16));
3879 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF,
3880 (u8)(data_addr >> 8));
3881 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF,
3884 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3885 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 |
3887 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
3890 trans_dma_enable(srb->sc_data_direction, chip,
3891 sector_cnt * 512, DMA_512);
3893 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3894 SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
3895 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3896 SD_TRANSFER_END, SD_TRANSFER_END);
3898 rtsx_send_cmd_no_wait(chip);
3900 retval = rtsx_send_cmd(chip, SD_CARD, 50);
3902 rtsx_clear_sd_error(chip);
3904 chip->rw_need_retry = 1;
3905 sd_set_err_code(chip, SD_TO_ERR);
3910 retval = wait_data_buf_ready(chip);
3911 if (retval != STATUS_SUCCESS) {
3912 chip->rw_need_retry = 1;
3913 sd_set_err_code(chip, SD_TO_ERR);
3918 retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK,
3919 data_addr, SD_RSP_TYPE_R1, NULL, 0);
3920 if (retval != STATUS_SUCCESS) {
3921 chip->rw_need_retry = 1;
3926 rtsx_init_cmd(chip);
3928 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3929 SD_NO_WAIT_BUSY_END |
3930 SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
3931 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
3934 trans_dma_enable(srb->sc_data_direction, chip,
3935 sector_cnt * 512, DMA_512);
3937 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3938 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3939 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3940 SD_TRANSFER_END, SD_TRANSFER_END);
3942 rtsx_send_cmd_no_wait(chip);
3945 sd_card->seq_mode = 1;
3948 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
3949 scsi_bufflen(srb), scsi_sg_count(srb),
3950 srb->sc_data_direction, chip->sd_timeout);
3955 sd_card->seq_mode = 0;
3957 if (retval == -ETIMEDOUT)
3958 err = STATUS_TIMEDOUT;
3962 rtsx_read_register(chip, REG_SD_STAT1, &stat);
3963 rtsx_clear_sd_error(chip);
3964 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3965 chip->rw_need_retry = 0;
3966 dev_dbg(rtsx_dev(chip), "No card exist, exit sd_rw\n");
3971 chip->rw_need_retry = 1;
3973 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3974 SD_RSP_TYPE_R1b, NULL, 0);
3975 if (retval != STATUS_SUCCESS) {
3976 sd_set_err_code(chip, SD_STS_ERR);
3981 if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) {
3982 dev_dbg(rtsx_dev(chip), "SD CRC error, tune clock!\n");
3983 sd_set_err_code(chip, SD_CRC_ERR);
3988 if (err == STATUS_TIMEDOUT) {
3989 sd_set_err_code(chip, SD_TO_ERR);
3998 sd_card->pre_sec_addr = start_sector;
3999 sd_card->pre_sec_cnt = sector_cnt;
4000 sd_card->pre_dir = srb->sc_data_direction;
4002 return STATUS_SUCCESS;
4005 sd_card->seq_mode = 0;
4007 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
4008 chip->rw_need_retry = 0;
4009 dev_dbg(rtsx_dev(chip), "No card exist, exit sd_rw\n");
4014 if (sd_check_err_code(chip, SD_CRC_ERR)) {
4015 if (CHK_MMC_4BIT(sd_card) || CHK_MMC_8BIT(sd_card)) {
4016 sd_card->mmc_dont_switch_bus = 1;
4017 reset_mmc_only(chip);
4018 sd_card->mmc_dont_switch_bus = 0;
4020 sd_card->need_retune = 1;
4021 sd_auto_tune_clock(chip);
4023 } else if (sd_check_err_code(chip, SD_TO_ERR | SD_STS_ERR)) {
4024 retval = reset_sd_card(chip);
4025 if (retval != STATUS_SUCCESS) {
4026 chip->card_ready &= ~SD_CARD;
4027 chip->card_fail |= SD_CARD;
4028 chip->capacity[chip->card2lun[SD_CARD]] = 0;
4037 int soft_reset_sd_card(struct rtsx_chip *chip)
4039 return reset_sd(chip);
4042 int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
4043 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len, bool special_check)
4052 dev_dbg(rtsx_dev(chip), "EXT SD/MMC CMD %d\n", cmd_idx);
4054 if (rsp_type == SD_RSP_TYPE_R1b)
4059 rtsx_init_cmd(chip);
4061 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
4062 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
4063 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
4064 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
4065 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
4067 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
4068 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
4069 0x01, PINGPONG_BUFFER);
4070 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
4071 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
4072 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
4075 if (rsp_type == SD_RSP_TYPE_R2) {
4076 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
4078 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
4081 } else if (rsp_type != SD_RSP_TYPE_R0) {
4082 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
4084 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
4088 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0, 0);
4090 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
4092 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
4094 if (retval == -ETIMEDOUT) {
4095 rtsx_clear_sd_error(chip);
4097 if (rsp_type & SD_WAIT_BUSY_END) {
4098 retval = sd_check_data0_status(chip);
4099 if (retval != STATUS_SUCCESS) {
4104 sd_set_err_code(chip, SD_TO_ERR);
4111 if (rsp_type == SD_RSP_TYPE_R0)
4112 return STATUS_SUCCESS;
4114 ptr = rtsx_get_cmd_data(chip) + 1;
4116 if ((ptr[0] & 0xC0) != 0) {
4117 sd_set_err_code(chip, SD_STS_ERR);
4122 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
4123 if (ptr[stat_idx] & SD_CRC7_ERR) {
4124 if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
4125 sd_set_err_code(chip, SD_CRC_ERR);
4129 if (rty_cnt < SD_MAX_RETRY_COUNT) {
4134 sd_set_err_code(chip, SD_CRC_ERR);
4141 if ((cmd_idx == SELECT_CARD) || (cmd_idx == APP_CMD) ||
4142 (cmd_idx == SEND_STATUS) || (cmd_idx == STOP_TRANSMISSION)) {
4143 if ((cmd_idx != STOP_TRANSMISSION) && !special_check) {
4144 if (ptr[1] & 0x80) {
4149 #ifdef SUPPORT_SD_LOCK
4150 if (ptr[1] & 0x7D) {
4152 if (ptr[1] & 0x7F) {
4157 if (ptr[2] & 0xF8) {
4162 if (cmd_idx == SELECT_CARD) {
4163 if (rsp_type == SD_RSP_TYPE_R2) {
4164 if ((ptr[3] & 0x1E) != 0x04) {
4169 } else if (rsp_type == SD_RSP_TYPE_R0) {
4170 if ((ptr[3] & 0x1E) != 0x03) {
4179 memcpy(rsp, ptr, rsp_len);
4181 return STATUS_SUCCESS;
4184 int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type)
4186 int retval, rsp_len;
4189 if (rsp_type == SD_RSP_TYPE_R0)
4190 return STATUS_SUCCESS;
4192 rtsx_init_cmd(chip);
4194 if (rsp_type == SD_RSP_TYPE_R2) {
4195 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
4197 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
4200 } else if (rsp_type != SD_RSP_TYPE_R0) {
4201 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
4203 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
4207 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0xFF, 0);
4209 retval = rtsx_send_cmd(chip, SD_CARD, 100);
4210 if (retval != STATUS_SUCCESS) {
4216 int min_len = (rsp_len < len) ? rsp_len : len;
4218 memcpy(rsp, rtsx_get_cmd_data(chip), min_len);
4220 dev_dbg(rtsx_dev(chip), "min_len = %d\n", min_len);
4221 dev_dbg(rtsx_dev(chip), "Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n",
4222 rsp[0], rsp[1], rsp[2], rsp[3]);
4225 return STATUS_SUCCESS;
4228 int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4230 struct sd_info *sd_card = &(chip->sd_card);
4231 unsigned int lun = SCSI_LUN(srb);
4254 sd_card->pre_cmd_err = 0;
4256 if (!(CHK_BIT(chip->lun_mc, lun))) {
4257 SET_BIT(chip->lun_mc, lun);
4258 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4260 return TRANSPORT_FAILED;
4263 if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) ||
4264 (0x20 != srb->cmnd[4]) || (0x43 != srb->cmnd[5]) ||
4265 (0x61 != srb->cmnd[6]) || (0x72 != srb->cmnd[7]) ||
4266 (0x64 != srb->cmnd[8])) {
4267 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4269 return TRANSPORT_FAILED;
4272 switch (srb->cmnd[1] & 0x0F) {
4274 sd_card->sd_pass_thru_en = 0;
4278 sd_card->sd_pass_thru_en = 1;
4282 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4284 return TRANSPORT_FAILED;
4287 buf[5] = (1 == CHK_SD(sd_card)) ? 0x01 : 0x02;
4288 if (chip->card_wp & SD_CARD)
4291 buf[6] = (u8)(sd_card->sd_addr >> 16);
4292 buf[7] = (u8)(sd_card->sd_addr >> 24);
4294 buf[15] = chip->max_lun;
4296 len = min_t(int, 18, scsi_bufflen(srb));
4297 rtsx_stor_set_xfer_buf(buf, len, srb);
4299 return TRANSPORT_GOOD;
4302 static inline int get_rsp_type(struct scsi_cmnd *srb, u8 *rsp_type,
4305 if (!rsp_type || !rsp_len)
4308 switch (srb->cmnd[10]) {
4310 *rsp_type = SD_RSP_TYPE_R0;
4315 *rsp_type = SD_RSP_TYPE_R1;
4320 *rsp_type = SD_RSP_TYPE_R1b;
4325 *rsp_type = SD_RSP_TYPE_R2;
4330 *rsp_type = SD_RSP_TYPE_R3;
4338 return STATUS_SUCCESS;
4341 int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4343 struct sd_info *sd_card = &(chip->sd_card);
4344 unsigned int lun = SCSI_LUN(srb);
4345 int retval, rsp_len;
4346 u8 cmd_idx, rsp_type;
4347 bool standby = false, acmd = false;
4350 if (!sd_card->sd_pass_thru_en) {
4351 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4353 return TRANSPORT_FAILED;
4356 retval = sd_switch_clock(chip);
4357 if (retval != STATUS_SUCCESS) {
4359 return TRANSPORT_FAILED;
4362 if (sd_card->pre_cmd_err) {
4363 sd_card->pre_cmd_err = 0;
4364 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4366 return TRANSPORT_FAILED;
4369 cmd_idx = srb->cmnd[2] & 0x3F;
4370 if (srb->cmnd[1] & 0x02)
4373 if (srb->cmnd[1] & 0x01)
4376 arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
4377 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
4379 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4380 if (retval != STATUS_SUCCESS) {
4381 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4383 return TRANSPORT_FAILED;
4385 sd_card->last_rsp_type = rsp_type;
4387 retval = sd_switch_clock(chip);
4388 if (retval != STATUS_SUCCESS) {
4390 return TRANSPORT_FAILED;
4393 #ifdef SUPPORT_SD_LOCK
4394 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4395 if (CHK_MMC_8BIT(sd_card)) {
4396 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4398 if (retval != STATUS_SUCCESS) {
4400 return TRANSPORT_FAILED;
4403 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4404 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4406 if (retval != STATUS_SUCCESS) {
4408 return TRANSPORT_FAILED;
4413 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4414 if (retval != STATUS_SUCCESS) {
4416 return TRANSPORT_FAILED;
4421 retval = sd_select_card(chip, 0);
4422 if (retval != STATUS_SUCCESS) {
4424 goto SD_Execute_Cmd_Failed;
4429 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
4431 SD_RSP_TYPE_R1, NULL, 0, false);
4432 if (retval != STATUS_SUCCESS) {
4434 goto SD_Execute_Cmd_Failed;
4438 retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
4439 sd_card->rsp, rsp_len, false);
4440 if (retval != STATUS_SUCCESS) {
4442 goto SD_Execute_Cmd_Failed;
4446 retval = sd_select_card(chip, 1);
4447 if (retval != STATUS_SUCCESS) {
4449 goto SD_Execute_Cmd_Failed;
4453 #ifdef SUPPORT_SD_LOCK
4454 retval = sd_update_lock_status(chip);
4455 if (retval != STATUS_SUCCESS) {
4457 goto SD_Execute_Cmd_Failed;
4461 scsi_set_resid(srb, 0);
4462 return TRANSPORT_GOOD;
4464 SD_Execute_Cmd_Failed:
4465 sd_card->pre_cmd_err = 1;
4466 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4467 release_sd_card(chip);
4468 do_reset_sd_card(chip);
4469 if (!(chip->card_ready & SD_CARD))
4470 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4473 return TRANSPORT_FAILED;
4476 int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4478 struct sd_info *sd_card = &(chip->sd_card);
4479 unsigned int lun = SCSI_LUN(srb);
4480 int retval, rsp_len, i;
4481 bool read_err = false, cmd13_checkbit = false;
4482 u8 cmd_idx, rsp_type, bus_width;
4483 bool standby = false, send_cmd12 = false, acmd = false;
4486 if (!sd_card->sd_pass_thru_en) {
4487 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4489 return TRANSPORT_FAILED;
4492 if (sd_card->pre_cmd_err) {
4493 sd_card->pre_cmd_err = 0;
4494 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4496 return TRANSPORT_FAILED;
4499 retval = sd_switch_clock(chip);
4500 if (retval != STATUS_SUCCESS) {
4502 return TRANSPORT_FAILED;
4505 cmd_idx = srb->cmnd[2] & 0x3F;
4506 if (srb->cmnd[1] & 0x04)
4509 if (srb->cmnd[1] & 0x02)
4512 if (srb->cmnd[1] & 0x01)
4515 data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8]
4516 << 8) | srb->cmnd[9];
4518 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4519 if (retval != STATUS_SUCCESS) {
4520 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4522 return TRANSPORT_FAILED;
4524 sd_card->last_rsp_type = rsp_type;
4526 retval = sd_switch_clock(chip);
4527 if (retval != STATUS_SUCCESS) {
4529 return TRANSPORT_FAILED;
4532 #ifdef SUPPORT_SD_LOCK
4533 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4534 if (CHK_MMC_8BIT(sd_card))
4535 bus_width = SD_BUS_WIDTH_8;
4536 else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card))
4537 bus_width = SD_BUS_WIDTH_4;
4539 bus_width = SD_BUS_WIDTH_1;
4541 bus_width = SD_BUS_WIDTH_4;
4543 dev_dbg(rtsx_dev(chip), "bus_width = %d\n", bus_width);
4545 bus_width = SD_BUS_WIDTH_4;
4548 if (data_len < 512) {
4549 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4550 SD_RSP_TYPE_R1, NULL, 0, false);
4551 if (retval != STATUS_SUCCESS) {
4553 goto SD_Execute_Read_Cmd_Failed;
4558 retval = sd_select_card(chip, 0);
4559 if (retval != STATUS_SUCCESS) {
4561 goto SD_Execute_Read_Cmd_Failed;
4566 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
4568 SD_RSP_TYPE_R1, NULL, 0, false);
4569 if (retval != STATUS_SUCCESS) {
4571 goto SD_Execute_Read_Cmd_Failed;
4575 if (data_len <= 512) {
4578 u16 byte_cnt, blk_cnt;
4581 byte_cnt = ((u16)(srb->cmnd[8] & 0x03) << 8) | srb->cmnd[9];
4584 cmd[0] = 0x40 | cmd_idx;
4585 cmd[1] = srb->cmnd[3];
4586 cmd[2] = srb->cmnd[4];
4587 cmd[3] = srb->cmnd[5];
4588 cmd[4] = srb->cmnd[6];
4590 buf = kmalloc(data_len, GFP_KERNEL);
4593 return TRANSPORT_ERROR;
4596 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, byte_cnt,
4597 blk_cnt, bus_width, buf, data_len, 2000);
4598 if (retval != STATUS_SUCCESS) {
4601 rtsx_clear_sd_error(chip);
4603 goto SD_Execute_Read_Cmd_Failed;
4606 min_len = min(data_len, scsi_bufflen(srb));
4607 rtsx_stor_set_xfer_buf(buf, min_len, srb);
4610 } else if (!(data_len & 0x1FF)) {
4611 rtsx_init_cmd(chip);
4613 trans_dma_enable(DMA_FROM_DEVICE, chip, data_len, DMA_512);
4615 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4617 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4619 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4620 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4621 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4622 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4624 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
4626 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF,
4628 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF,
4630 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF,
4632 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF,
4635 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
4636 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
4638 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
4639 0xFF, SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
4640 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4641 SD_TRANSFER_END, SD_TRANSFER_END);
4643 rtsx_send_cmd_no_wait(chip);
4645 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
4646 scsi_bufflen(srb), scsi_sg_count(srb),
4647 DMA_FROM_DEVICE, 10000);
4650 rtsx_clear_sd_error(chip);
4652 goto SD_Execute_Read_Cmd_Failed;
4657 goto SD_Execute_Read_Cmd_Failed;
4660 retval = ext_sd_get_rsp(chip, rsp_len, sd_card->rsp, rsp_type);
4661 if (retval != STATUS_SUCCESS) {
4663 goto SD_Execute_Read_Cmd_Failed;
4667 retval = sd_select_card(chip, 1);
4668 if (retval != STATUS_SUCCESS) {
4670 goto SD_Execute_Read_Cmd_Failed;
4675 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
4676 0, SD_RSP_TYPE_R1b, NULL, 0, false);
4677 if (retval != STATUS_SUCCESS) {
4679 goto SD_Execute_Read_Cmd_Failed;
4683 if (data_len < 512) {
4684 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4685 SD_RSP_TYPE_R1, NULL, 0, false);
4686 if (retval != STATUS_SUCCESS) {
4688 goto SD_Execute_Read_Cmd_Failed;
4691 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4692 if (retval != STATUS_SUCCESS) {
4694 goto SD_Execute_Read_Cmd_Failed;
4697 retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4698 if (retval != STATUS_SUCCESS) {
4700 goto SD_Execute_Read_Cmd_Failed;
4704 if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04))
4705 cmd13_checkbit = true;
4707 for (i = 0; i < 3; i++) {
4708 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS,
4710 SD_RSP_TYPE_R1, NULL, 0,
4712 if (retval == STATUS_SUCCESS)
4715 if (retval != STATUS_SUCCESS) {
4717 goto SD_Execute_Read_Cmd_Failed;
4720 scsi_set_resid(srb, 0);
4721 return TRANSPORT_GOOD;
4723 SD_Execute_Read_Cmd_Failed:
4724 sd_card->pre_cmd_err = 1;
4725 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4727 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4729 release_sd_card(chip);
4730 do_reset_sd_card(chip);
4731 if (!(chip->card_ready & SD_CARD))
4732 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4735 return TRANSPORT_FAILED;
4738 int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4740 struct sd_info *sd_card = &(chip->sd_card);
4741 unsigned int lun = SCSI_LUN(srb);
4742 int retval, rsp_len, i;
4743 bool write_err = false, cmd13_checkbit = false;
4744 u8 cmd_idx, rsp_type;
4745 bool standby = false, send_cmd12 = false, acmd = false;
4747 #ifdef SUPPORT_SD_LOCK
4748 int lock_cmd_fail = 0;
4749 u8 sd_lock_state = 0;
4750 u8 lock_cmd_type = 0;
4753 if (!sd_card->sd_pass_thru_en) {
4754 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4756 return TRANSPORT_FAILED;
4759 if (sd_card->pre_cmd_err) {
4760 sd_card->pre_cmd_err = 0;
4761 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4763 return TRANSPORT_FAILED;
4766 retval = sd_switch_clock(chip);
4767 if (retval != STATUS_SUCCESS) {
4769 return TRANSPORT_FAILED;
4772 cmd_idx = srb->cmnd[2] & 0x3F;
4773 if (srb->cmnd[1] & 0x04)
4776 if (srb->cmnd[1] & 0x02)
4779 if (srb->cmnd[1] & 0x01)
4782 data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8]
4783 << 8) | srb->cmnd[9];
4784 arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
4785 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
4787 #ifdef SUPPORT_SD_LOCK
4788 if (cmd_idx == LOCK_UNLOCK) {
4789 sd_lock_state = sd_card->sd_lock_status;
4790 sd_lock_state &= SD_LOCKED;
4794 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4795 if (retval != STATUS_SUCCESS) {
4796 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4798 return TRANSPORT_FAILED;
4800 sd_card->last_rsp_type = rsp_type;
4802 retval = sd_switch_clock(chip);
4803 if (retval != STATUS_SUCCESS) {
4805 return TRANSPORT_FAILED;
4808 #ifdef SUPPORT_SD_LOCK
4809 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4810 if (CHK_MMC_8BIT(sd_card)) {
4811 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4813 if (retval != STATUS_SUCCESS) {
4815 return TRANSPORT_FAILED;
4818 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4819 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4821 if (retval != STATUS_SUCCESS) {
4823 return TRANSPORT_FAILED;
4828 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4829 if (retval != STATUS_SUCCESS) {
4831 return TRANSPORT_FAILED;
4835 if (data_len < 512) {
4836 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4837 SD_RSP_TYPE_R1, NULL, 0, false);
4838 if (retval != STATUS_SUCCESS) {
4840 goto SD_Execute_Write_Cmd_Failed;
4845 retval = sd_select_card(chip, 0);
4846 if (retval != STATUS_SUCCESS) {
4848 goto SD_Execute_Write_Cmd_Failed;
4853 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
4855 SD_RSP_TYPE_R1, NULL, 0, false);
4856 if (retval != STATUS_SUCCESS) {
4858 goto SD_Execute_Write_Cmd_Failed;
4862 retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
4863 sd_card->rsp, rsp_len, false);
4864 if (retval != STATUS_SUCCESS) {
4866 goto SD_Execute_Write_Cmd_Failed;
4869 if (data_len <= 512) {
4873 buf = kmalloc(data_len, GFP_KERNEL);
4876 return TRANSPORT_ERROR;
4879 rtsx_stor_get_xfer_buf(buf, data_len, srb);
4881 #ifdef SUPPORT_SD_LOCK
4882 if (cmd_idx == LOCK_UNLOCK)
4883 lock_cmd_type = buf[0] & 0x0F;
4886 if (data_len > 256) {
4887 rtsx_init_cmd(chip);
4888 for (i = 0; i < 256; i++) {
4889 rtsx_add_cmd(chip, WRITE_REG_CMD,
4890 PPBUF_BASE2 + i, 0xFF, buf[i]);
4892 retval = rtsx_send_cmd(chip, 0, 250);
4893 if (retval != STATUS_SUCCESS) {
4896 goto SD_Execute_Write_Cmd_Failed;
4899 rtsx_init_cmd(chip);
4900 for (i = 256; i < data_len; i++) {
4901 rtsx_add_cmd(chip, WRITE_REG_CMD,
4902 PPBUF_BASE2 + i, 0xFF, buf[i]);
4904 retval = rtsx_send_cmd(chip, 0, 250);
4905 if (retval != STATUS_SUCCESS) {
4908 goto SD_Execute_Write_Cmd_Failed;
4911 rtsx_init_cmd(chip);
4912 for (i = 0; i < data_len; i++) {
4913 rtsx_add_cmd(chip, WRITE_REG_CMD,
4914 PPBUF_BASE2 + i, 0xFF, buf[i]);
4916 retval = rtsx_send_cmd(chip, 0, 250);
4917 if (retval != STATUS_SUCCESS) {
4920 goto SD_Execute_Write_Cmd_Failed;
4926 rtsx_init_cmd(chip);
4928 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4929 srb->cmnd[8] & 0x03);
4930 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4932 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
4934 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
4936 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
4939 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4940 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4941 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4942 SD_TRANSFER_END, SD_TRANSFER_END);
4944 retval = rtsx_send_cmd(chip, SD_CARD, 250);
4945 } else if (!(data_len & 0x1FF)) {
4946 rtsx_init_cmd(chip);
4948 trans_dma_enable(DMA_TO_DEVICE, chip, data_len, DMA_512);
4950 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4952 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4954 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4955 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4956 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4957 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4959 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4960 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4961 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4962 SD_TRANSFER_END, SD_TRANSFER_END);
4964 rtsx_send_cmd_no_wait(chip);
4966 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
4967 scsi_bufflen(srb), scsi_sg_count(srb),
4968 DMA_TO_DEVICE, 10000);
4972 goto SD_Execute_Write_Cmd_Failed;
4977 rtsx_clear_sd_error(chip);
4979 goto SD_Execute_Write_Cmd_Failed;
4982 #ifdef SUPPORT_SD_LOCK
4983 if (cmd_idx == LOCK_UNLOCK) {
4984 if (lock_cmd_type == SD_ERASE) {
4985 sd_card->sd_erase_status = SD_UNDER_ERASING;
4986 scsi_set_resid(srb, 0);
4987 return TRANSPORT_GOOD;
4990 rtsx_init_cmd(chip);
4991 rtsx_add_cmd(chip, CHECK_REG_CMD, 0xFD30, 0x02, 0x02);
4993 rtsx_send_cmd(chip, SD_CARD, 250);
4995 retval = sd_update_lock_status(chip);
4996 if (retval != STATUS_SUCCESS) {
4997 dev_dbg(rtsx_dev(chip), "Lock command fail!\n");
5001 #endif /* SUPPORT_SD_LOCK */
5004 retval = sd_select_card(chip, 1);
5005 if (retval != STATUS_SUCCESS) {
5007 goto SD_Execute_Write_Cmd_Failed;
5012 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
5013 0, SD_RSP_TYPE_R1b, NULL, 0, false);
5014 if (retval != STATUS_SUCCESS) {
5016 goto SD_Execute_Write_Cmd_Failed;
5020 if (data_len < 512) {
5021 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
5022 SD_RSP_TYPE_R1, NULL, 0, false);
5023 if (retval != STATUS_SUCCESS) {
5025 goto SD_Execute_Write_Cmd_Failed;
5028 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
5029 if (retval != STATUS_SUCCESS) {
5031 goto SD_Execute_Write_Cmd_Failed;
5034 rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
5035 if (retval != STATUS_SUCCESS) {
5037 goto SD_Execute_Write_Cmd_Failed;
5041 if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04))
5042 cmd13_checkbit = true;
5044 for (i = 0; i < 3; i++) {
5045 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS,
5047 SD_RSP_TYPE_R1, NULL, 0,
5049 if (retval == STATUS_SUCCESS)
5052 if (retval != STATUS_SUCCESS) {
5054 goto SD_Execute_Write_Cmd_Failed;
5057 #ifdef SUPPORT_SD_LOCK
5058 if (cmd_idx == LOCK_UNLOCK) {
5059 if (!lock_cmd_fail) {
5060 dev_dbg(rtsx_dev(chip), "lock_cmd_type = 0x%x\n",
5062 if (lock_cmd_type & SD_CLR_PWD)
5063 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
5065 if (lock_cmd_type & SD_SET_PWD)
5066 sd_card->sd_lock_status |= SD_PWD_EXIST;
5069 dev_dbg(rtsx_dev(chip), "sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n",
5070 sd_lock_state, sd_card->sd_lock_status);
5071 if (sd_lock_state ^ (sd_card->sd_lock_status & SD_LOCKED)) {
5072 sd_card->sd_lock_notify = 1;
5073 if (sd_lock_state) {
5074 if (sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) {
5075 sd_card->sd_lock_status |= (
5076 SD_UNLOCK_POW_ON | SD_SDR_RST);
5077 if (CHK_SD(sd_card)) {
5078 retval = reset_sd(chip);
5079 if (retval != STATUS_SUCCESS) {
5080 sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
5082 goto SD_Execute_Write_Cmd_Failed;
5086 sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
5092 if (lock_cmd_fail) {
5093 scsi_set_resid(srb, 0);
5094 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
5096 return TRANSPORT_FAILED;
5098 #endif /* SUPPORT_SD_LOCK */
5100 scsi_set_resid(srb, 0);
5101 return TRANSPORT_GOOD;
5103 SD_Execute_Write_Cmd_Failed:
5104 sd_card->pre_cmd_err = 1;
5105 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
5107 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
5109 release_sd_card(chip);
5110 do_reset_sd_card(chip);
5111 if (!(chip->card_ready & SD_CARD))
5112 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
5115 return TRANSPORT_FAILED;
5118 int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
5120 struct sd_info *sd_card = &(chip->sd_card);
5121 unsigned int lun = SCSI_LUN(srb);
5125 if (!sd_card->sd_pass_thru_en) {
5126 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
5128 return TRANSPORT_FAILED;
5131 if (sd_card->pre_cmd_err) {
5132 sd_card->pre_cmd_err = 0;
5133 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
5135 return TRANSPORT_FAILED;
5138 data_len = ((u16)srb->cmnd[7] << 8) | srb->cmnd[8];
5140 if (sd_card->last_rsp_type == SD_RSP_TYPE_R0) {
5141 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
5143 return TRANSPORT_FAILED;
5144 } else if (sd_card->last_rsp_type == SD_RSP_TYPE_R2) {
5145 count = (data_len < 17) ? data_len : 17;
5147 count = (data_len < 6) ? data_len : 6;
5149 rtsx_stor_set_xfer_buf(sd_card->rsp, count, srb);
5151 dev_dbg(rtsx_dev(chip), "Response length: %d\n", data_len);
5152 dev_dbg(rtsx_dev(chip), "Response: 0x%x 0x%x 0x%x 0x%x\n",
5153 sd_card->rsp[0], sd_card->rsp[1],
5154 sd_card->rsp[2], sd_card->rsp[3]);
5156 scsi_set_resid(srb, 0);
5157 return TRANSPORT_GOOD;
5160 int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip)
5162 struct sd_info *sd_card = &(chip->sd_card);
5163 unsigned int lun = SCSI_LUN(srb);
5166 if (!sd_card->sd_pass_thru_en) {
5167 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
5169 return TRANSPORT_FAILED;
5172 if (sd_card->pre_cmd_err) {
5173 sd_card->pre_cmd_err = 0;
5174 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
5176 return TRANSPORT_FAILED;
5179 if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) ||
5180 (0x20 != srb->cmnd[4]) || (0x43 != srb->cmnd[5]) ||
5181 (0x61 != srb->cmnd[6]) || (0x72 != srb->cmnd[7]) ||
5182 (0x64 != srb->cmnd[8])) {
5183 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
5185 return TRANSPORT_FAILED;
5188 switch (srb->cmnd[1] & 0x0F) {
5190 #ifdef SUPPORT_SD_LOCK
5191 if (0x64 == srb->cmnd[9])
5192 sd_card->sd_lock_status |= SD_SDR_RST;
5194 retval = reset_sd_card(chip);
5195 if (retval != STATUS_SUCCESS) {
5196 #ifdef SUPPORT_SD_LOCK
5197 sd_card->sd_lock_status &= ~SD_SDR_RST;
5199 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
5200 sd_card->pre_cmd_err = 1;
5202 return TRANSPORT_FAILED;
5204 #ifdef SUPPORT_SD_LOCK
5205 sd_card->sd_lock_status &= ~SD_SDR_RST;
5210 retval = soft_reset_sd_card(chip);
5211 if (retval != STATUS_SUCCESS) {
5212 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
5213 sd_card->pre_cmd_err = 1;
5215 return TRANSPORT_FAILED;
5220 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
5222 return TRANSPORT_FAILED;
5225 scsi_set_resid(srb, 0);
5226 return TRANSPORT_GOOD;
5230 void sd_cleanup_work(struct rtsx_chip *chip)
5232 struct sd_info *sd_card = &(chip->sd_card);
5234 if (sd_card->seq_mode) {
5235 dev_dbg(rtsx_dev(chip), "SD: stop transmission\n");
5236 sd_stop_seq_mode(chip);
5237 sd_card->cleanup_counter = 0;
5241 int sd_power_off_card3v3(struct rtsx_chip *chip)
5245 retval = disable_card_clock(chip, SD_CARD);
5246 if (retval != STATUS_SUCCESS) {
5251 retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
5257 if (!chip->ft2_fast_mode) {
5258 retval = card_power_off(chip, SD_CARD);
5259 if (retval != STATUS_SUCCESS) {
5267 if (chip->asic_code) {
5268 retval = sd_pull_ctl_disable(chip);
5269 if (retval != STATUS_SUCCESS) {
5274 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
5275 FPGA_SD_PULL_CTL_BIT | 0x20,
5276 FPGA_SD_PULL_CTL_BIT);
5283 return STATUS_SUCCESS;
5286 int release_sd_card(struct rtsx_chip *chip)
5288 struct sd_info *sd_card = &(chip->sd_card);
5291 chip->card_ready &= ~SD_CARD;
5292 chip->card_fail &= ~SD_CARD;
5293 chip->card_wp &= ~SD_CARD;
5298 #ifdef SUPPORT_SD_LOCK
5299 sd_card->sd_lock_status = 0;
5300 sd_card->sd_erase_status = 0;
5303 memset(sd_card->raw_csd, 0, 16);
5304 memset(sd_card->raw_scr, 0, 8);
5306 retval = sd_power_off_card3v3(chip);
5307 if (retval != STATUS_SUCCESS) {
5312 return STATUS_SUCCESS;