1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
29 /***********************************************************************
30 * Scatter-gather transfer buffer access routines
31 ***********************************************************************/
33 /* Copy a buffer of length buflen to/from the srb's transfer buffer.
34 * (Note: for scatter-gather transfers (srb->use_sg > 0), srb->request_buffer
35 * points to a list of s-g entries and we ignore srb->request_bufflen.
36 * For non-scatter-gather transfers, srb->request_buffer points to the
37 * transfer buffer itself and srb->request_bufflen is the buffer's length.)
38 * Update the *index and *offset variables so that the next copy will
39 * pick up from where this one left off. */
41 unsigned int rtsx_stor_access_xfer_buf(unsigned char *buffer,
42 unsigned int buflen, struct scsi_cmnd *srb, unsigned int *index,
43 unsigned int *offset, enum xfer_buf_dir dir)
47 /* If not using scatter-gather, just transfer the data directly.
48 * Make certain it will fit in the available buffer space. */
49 if (scsi_sg_count(srb) == 0) {
50 if (*offset >= scsi_bufflen(srb))
52 cnt = min(buflen, scsi_bufflen(srb) - *offset);
53 if (dir == TO_XFER_BUF)
54 memcpy((unsigned char *) scsi_sglist(srb) + *offset,
57 memcpy(buffer, (unsigned char *) scsi_sglist(srb) +
61 /* Using scatter-gather. We have to go through the list one entry
62 * at a time. Each s-g entry contains some number of pages, and
63 * each page has to be kmap()'ed separately. If the page is already
64 * in kernel-addressable memory then kmap() will return its address.
65 * If the page is not directly accessible -- such as a user buffer
66 * located in high memory -- then kmap() will map it to a temporary
67 * position in the kernel's virtual address space. */
69 struct scatterlist *sg =
70 (struct scatterlist *) scsi_sglist(srb)
73 /* This loop handles a single s-g list entry, which may
74 * include multiple pages. Find the initial page structure
75 * and the starting offset within the page, and update
76 * the *offset and *index values for the next loop. */
78 while (cnt < buflen && *index < scsi_sg_count(srb)) {
79 struct page *page = sg_page(sg) +
80 ((sg->offset + *offset) >> PAGE_SHIFT);
82 (sg->offset + *offset) & (PAGE_SIZE-1);
83 unsigned int sglen = sg->length - *offset;
85 if (sglen > buflen - cnt) {
87 /* Transfer ends within this s-g entry */
92 /* Transfer continues to next s-g entry */
98 /* Transfer the data for all the pages in this
99 * s-g entry. For each page: call kmap(), do the
100 * transfer, and call kunmap() immediately after. */
102 unsigned int plen = min(sglen, (unsigned int)
104 unsigned char *ptr = kmap(page);
106 if (dir == TO_XFER_BUF)
107 memcpy(ptr + poff, buffer + cnt, plen);
109 memcpy(buffer + cnt, ptr + poff, plen);
112 /* Start at the beginning of the next page */
121 /* Return the amount actually transferred */
125 /* Store the contents of buffer into srb's transfer buffer and set the
127 void rtsx_stor_set_xfer_buf(unsigned char *buffer,
128 unsigned int buflen, struct scsi_cmnd *srb)
130 unsigned int index = 0, offset = 0;
132 rtsx_stor_access_xfer_buf(buffer, buflen, srb, &index, &offset,
134 if (buflen < scsi_bufflen(srb))
135 scsi_set_resid(srb, scsi_bufflen(srb) - buflen);
138 void rtsx_stor_get_xfer_buf(unsigned char *buffer,
139 unsigned int buflen, struct scsi_cmnd *srb)
141 unsigned int index = 0, offset = 0;
143 rtsx_stor_access_xfer_buf(buffer, buflen, srb, &index, &offset,
145 if (buflen < scsi_bufflen(srb))
146 scsi_set_resid(srb, scsi_bufflen(srb) - buflen);
150 /***********************************************************************
152 ***********************************************************************/
154 /* Invoke the transport and basic error-handling/recovery methods
156 * This is used to send the message to the device and receive the response.
158 void rtsx_invoke_transport(struct scsi_cmnd *srb, struct rtsx_chip *chip)
162 result = rtsx_scsi_handler(srb, chip);
164 /* if the command gets aborted by the higher layers, we need to
165 * short-circuit all other processing
167 if (rtsx_chk_stat(chip, RTSX_STAT_ABORT)) {
168 dev_dbg(rtsx_dev(chip), "-- command was aborted\n");
169 srb->result = DID_ABORT << 16;
173 /* if there is a transport error, reset and don't auto-sense */
174 if (result == TRANSPORT_ERROR) {
175 dev_dbg(rtsx_dev(chip), "-- transport indicates error, resetting\n");
176 srb->result = DID_ERROR << 16;
180 srb->result = SAM_STAT_GOOD;
183 * If we have a failure, we're going to do a REQUEST_SENSE
184 * automatically. Note that we differentiate between a command
185 * "failure" and an "error" in the transport mechanism.
187 if (result == TRANSPORT_FAILED) {
188 /* set the result so the higher layers expect this data */
189 srb->result = SAM_STAT_CHECK_CONDITION;
190 memcpy(srb->sense_buffer,
191 (unsigned char *)&(chip->sense_buffer[SCSI_LUN(srb)]),
192 sizeof(struct sense_data_t));
197 /* Error and abort processing: try to resynchronize with the device
198 * by issuing a port reset. If that fails, try a class-specific
204 void rtsx_add_cmd(struct rtsx_chip *chip,
205 u8 cmd_type, u16 reg_addr, u8 mask, u8 data)
207 u32 *cb = (u32 *)(chip->host_cmds_ptr);
210 val |= (u32)(cmd_type & 0x03) << 30;
211 val |= (u32)(reg_addr & 0x3FFF) << 16;
212 val |= (u32)mask << 8;
215 spin_lock_irq(&chip->rtsx->reg_lock);
216 if (chip->ci < (HOST_CMDS_BUF_LEN / 4))
217 cb[(chip->ci)++] = cpu_to_le32(val);
219 spin_unlock_irq(&chip->rtsx->reg_lock);
222 void rtsx_send_cmd_no_wait(struct rtsx_chip *chip)
226 rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
228 val |= (u32)(chip->ci * 4) & 0x00FFFFFF;
229 /* Hardware Auto Response */
231 rtsx_writel(chip, RTSX_HCBCTLR, val);
234 int rtsx_send_cmd(struct rtsx_chip *chip, u8 card, int timeout)
236 struct rtsx_dev *rtsx = chip->rtsx;
237 struct completion trans_done;
243 rtsx->check_card_cd = SD_EXIST;
244 else if (card == MS_CARD)
245 rtsx->check_card_cd = MS_EXIST;
246 else if (card == XD_CARD)
247 rtsx->check_card_cd = XD_EXIST;
249 rtsx->check_card_cd = 0;
251 spin_lock_irq(&rtsx->reg_lock);
253 /* set up data structures for the wakeup system */
254 rtsx->done = &trans_done;
255 rtsx->trans_result = TRANS_NOT_READY;
256 init_completion(&trans_done);
257 rtsx->trans_state = STATE_TRANS_CMD;
259 rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
261 val |= (u32)(chip->ci * 4) & 0x00FFFFFF;
262 /* Hardware Auto Response */
264 rtsx_writel(chip, RTSX_HCBCTLR, val);
266 spin_unlock_irq(&rtsx->reg_lock);
268 /* Wait for TRANS_OK_INT */
269 timeleft = wait_for_completion_interruptible_timeout(
270 &trans_done, msecs_to_jiffies(timeout));
272 dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n",
276 goto finish_send_cmd;
279 spin_lock_irq(&rtsx->reg_lock);
280 if (rtsx->trans_result == TRANS_RESULT_FAIL)
282 else if (rtsx->trans_result == TRANS_RESULT_OK)
285 spin_unlock_irq(&rtsx->reg_lock);
289 rtsx->trans_state = STATE_TRANS_NONE;
292 rtsx_stop_cmd(chip, card);
297 static inline void rtsx_add_sg_tbl(
298 struct rtsx_chip *chip, u32 addr, u32 len, u8 option)
300 u64 *sgb = (u64 *)(chip->host_sg_tbl_ptr);
308 temp_opt = option & (~SG_END);
313 val = ((u64)addr << 32) | ((u64)temp_len << 12) | temp_opt;
315 if (chip->sgi < (HOST_SG_TBL_BUF_LEN / 8))
316 sgb[(chip->sgi)++] = cpu_to_le64(val);
323 static int rtsx_transfer_sglist_adma_partial(struct rtsx_chip *chip, u8 card,
324 struct scatterlist *sg, int num_sg, unsigned int *index,
325 unsigned int *offset, int size,
326 enum dma_data_direction dma_dir, int timeout)
328 struct rtsx_dev *rtsx = chip->rtsx;
329 struct completion trans_done;
331 int sg_cnt, i, resid;
334 struct scatterlist *sg_ptr;
337 if ((sg == NULL) || (num_sg <= 0) || !offset || !index)
340 if (dma_dir == DMA_TO_DEVICE)
341 dir = HOST_TO_DEVICE;
342 else if (dma_dir == DMA_FROM_DEVICE)
343 dir = DEVICE_TO_HOST;
348 rtsx->check_card_cd = SD_EXIST;
349 else if (card == MS_CARD)
350 rtsx->check_card_cd = MS_EXIST;
351 else if (card == XD_CARD)
352 rtsx->check_card_cd = XD_EXIST;
354 rtsx->check_card_cd = 0;
356 spin_lock_irq(&rtsx->reg_lock);
358 /* set up data structures for the wakeup system */
359 rtsx->done = &trans_done;
361 rtsx->trans_state = STATE_TRANS_SG;
362 rtsx->trans_result = TRANS_NOT_READY;
364 spin_unlock_irq(&rtsx->reg_lock);
366 sg_cnt = dma_map_sg(&(rtsx->pci->dev), sg, num_sg, dma_dir);
371 /* Usually the next entry will be @sg@ + 1, but if this sg element
372 * is part of a chained scatterlist, it could jump to the start of
373 * a new scatterlist array. So here we use sg_next to move to
376 for (i = 0; i < *index; i++)
377 sg_ptr = sg_next(sg_ptr);
378 for (i = *index; i < sg_cnt; i++) {
383 addr = sg_dma_address(sg_ptr);
384 len = sg_dma_len(sg_ptr);
386 dev_dbg(rtsx_dev(chip), "DMA addr: 0x%x, Len: 0x%x\n",
387 (unsigned int)addr, len);
388 dev_dbg(rtsx_dev(chip), "*index = %d, *offset = %d\n",
393 if ((len - *offset) > resid) {
398 resid -= (len - *offset);
403 if ((i == (sg_cnt - 1)) || !resid)
404 option = SG_VALID | SG_END | SG_TRANS_DATA;
406 option = SG_VALID | SG_TRANS_DATA;
408 rtsx_add_sg_tbl(chip, (u32)addr, (u32)len, option);
413 sg_ptr = sg_next(sg_ptr);
416 dev_dbg(rtsx_dev(chip), "SG table count = %d\n", chip->sgi);
418 val |= (u32)(dir & 0x01) << 29;
421 spin_lock_irq(&rtsx->reg_lock);
423 init_completion(&trans_done);
425 rtsx_writel(chip, RTSX_HDBAR, chip->host_sg_tbl_addr);
426 rtsx_writel(chip, RTSX_HDBCTLR, val);
428 spin_unlock_irq(&rtsx->reg_lock);
430 timeleft = wait_for_completion_interruptible_timeout(
431 &trans_done, msecs_to_jiffies(timeout));
433 dev_dbg(rtsx_dev(chip), "Timeout (%s %d)\n",
435 dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n",
441 spin_lock_irq(&rtsx->reg_lock);
442 if (rtsx->trans_result == TRANS_RESULT_FAIL) {
444 spin_unlock_irq(&rtsx->reg_lock);
447 spin_unlock_irq(&rtsx->reg_lock);
449 /* Wait for TRANS_OK_INT */
450 spin_lock_irq(&rtsx->reg_lock);
451 if (rtsx->trans_result == TRANS_NOT_READY) {
452 init_completion(&trans_done);
453 spin_unlock_irq(&rtsx->reg_lock);
454 timeleft = wait_for_completion_interruptible_timeout(
455 &trans_done, msecs_to_jiffies(timeout));
457 dev_dbg(rtsx_dev(chip), "Timeout (%s %d)\n",
459 dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n",
465 spin_unlock_irq(&rtsx->reg_lock);
468 spin_lock_irq(&rtsx->reg_lock);
469 if (rtsx->trans_result == TRANS_RESULT_FAIL)
471 else if (rtsx->trans_result == TRANS_RESULT_OK)
474 spin_unlock_irq(&rtsx->reg_lock);
478 rtsx->trans_state = STATE_TRANS_NONE;
479 dma_unmap_sg(&(rtsx->pci->dev), sg, num_sg, dma_dir);
482 rtsx_stop_cmd(chip, card);
487 static int rtsx_transfer_sglist_adma(struct rtsx_chip *chip, u8 card,
488 struct scatterlist *sg, int num_sg,
489 enum dma_data_direction dma_dir, int timeout)
491 struct rtsx_dev *rtsx = chip->rtsx;
492 struct completion trans_done;
497 struct scatterlist *sg_ptr;
499 if ((sg == NULL) || (num_sg <= 0))
502 if (dma_dir == DMA_TO_DEVICE)
503 dir = HOST_TO_DEVICE;
504 else if (dma_dir == DMA_FROM_DEVICE)
505 dir = DEVICE_TO_HOST;
510 rtsx->check_card_cd = SD_EXIST;
511 else if (card == MS_CARD)
512 rtsx->check_card_cd = MS_EXIST;
513 else if (card == XD_CARD)
514 rtsx->check_card_cd = XD_EXIST;
516 rtsx->check_card_cd = 0;
518 spin_lock_irq(&rtsx->reg_lock);
520 /* set up data structures for the wakeup system */
521 rtsx->done = &trans_done;
523 rtsx->trans_state = STATE_TRANS_SG;
524 rtsx->trans_result = TRANS_NOT_READY;
526 spin_unlock_irq(&rtsx->reg_lock);
528 buf_cnt = dma_map_sg(&(rtsx->pci->dev), sg, num_sg, dma_dir);
532 for (i = 0; i <= buf_cnt / (HOST_SG_TBL_BUF_LEN / 8); i++) {
536 if (i == buf_cnt / (HOST_SG_TBL_BUF_LEN / 8))
537 sg_cnt = buf_cnt % (HOST_SG_TBL_BUF_LEN / 8);
539 sg_cnt = HOST_SG_TBL_BUF_LEN / 8;
542 for (j = 0; j < sg_cnt; j++) {
543 dma_addr_t addr = sg_dma_address(sg_ptr);
544 unsigned int len = sg_dma_len(sg_ptr);
547 dev_dbg(rtsx_dev(chip), "DMA addr: 0x%x, Len: 0x%x\n",
548 (unsigned int)addr, len);
550 if (j == (sg_cnt - 1))
551 option = SG_VALID | SG_END | SG_TRANS_DATA;
553 option = SG_VALID | SG_TRANS_DATA;
555 rtsx_add_sg_tbl(chip, (u32)addr, (u32)len, option);
557 sg_ptr = sg_next(sg_ptr);
560 dev_dbg(rtsx_dev(chip), "SG table count = %d\n", chip->sgi);
562 val |= (u32)(dir & 0x01) << 29;
565 spin_lock_irq(&rtsx->reg_lock);
567 init_completion(&trans_done);
569 rtsx_writel(chip, RTSX_HDBAR, chip->host_sg_tbl_addr);
570 rtsx_writel(chip, RTSX_HDBCTLR, val);
572 spin_unlock_irq(&rtsx->reg_lock);
574 timeleft = wait_for_completion_interruptible_timeout(
575 &trans_done, msecs_to_jiffies(timeout));
577 dev_dbg(rtsx_dev(chip), "Timeout (%s %d)\n",
579 dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n",
585 spin_lock_irq(&rtsx->reg_lock);
586 if (rtsx->trans_result == TRANS_RESULT_FAIL) {
588 spin_unlock_irq(&rtsx->reg_lock);
591 spin_unlock_irq(&rtsx->reg_lock);
596 /* Wait for TRANS_OK_INT */
597 spin_lock_irq(&rtsx->reg_lock);
598 if (rtsx->trans_result == TRANS_NOT_READY) {
599 init_completion(&trans_done);
600 spin_unlock_irq(&rtsx->reg_lock);
601 timeleft = wait_for_completion_interruptible_timeout(
602 &trans_done, msecs_to_jiffies(timeout));
604 dev_dbg(rtsx_dev(chip), "Timeout (%s %d)\n",
606 dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n",
612 spin_unlock_irq(&rtsx->reg_lock);
615 spin_lock_irq(&rtsx->reg_lock);
616 if (rtsx->trans_result == TRANS_RESULT_FAIL)
618 else if (rtsx->trans_result == TRANS_RESULT_OK)
621 spin_unlock_irq(&rtsx->reg_lock);
625 rtsx->trans_state = STATE_TRANS_NONE;
626 dma_unmap_sg(&(rtsx->pci->dev), sg, num_sg, dma_dir);
629 rtsx_stop_cmd(chip, card);
634 static int rtsx_transfer_buf(struct rtsx_chip *chip, u8 card, void *buf,
635 size_t len, enum dma_data_direction dma_dir, int timeout)
637 struct rtsx_dev *rtsx = chip->rtsx;
638 struct completion trans_done;
645 if ((buf == NULL) || (len <= 0))
648 if (dma_dir == DMA_TO_DEVICE)
649 dir = HOST_TO_DEVICE;
650 else if (dma_dir == DMA_FROM_DEVICE)
651 dir = DEVICE_TO_HOST;
655 addr = dma_map_single(&(rtsx->pci->dev), buf, len, dma_dir);
660 rtsx->check_card_cd = SD_EXIST;
661 else if (card == MS_CARD)
662 rtsx->check_card_cd = MS_EXIST;
663 else if (card == XD_CARD)
664 rtsx->check_card_cd = XD_EXIST;
666 rtsx->check_card_cd = 0;
668 val |= (u32)(dir & 0x01) << 29;
669 val |= (u32)(len & 0x00FFFFFF);
671 spin_lock_irq(&rtsx->reg_lock);
673 /* set up data structures for the wakeup system */
674 rtsx->done = &trans_done;
676 init_completion(&trans_done);
678 rtsx->trans_state = STATE_TRANS_BUF;
679 rtsx->trans_result = TRANS_NOT_READY;
681 rtsx_writel(chip, RTSX_HDBAR, addr);
682 rtsx_writel(chip, RTSX_HDBCTLR, val);
684 spin_unlock_irq(&rtsx->reg_lock);
686 /* Wait for TRANS_OK_INT */
687 timeleft = wait_for_completion_interruptible_timeout(
688 &trans_done, msecs_to_jiffies(timeout));
690 dev_dbg(rtsx_dev(chip), "Timeout (%s %d)\n",
692 dev_dbg(rtsx_dev(chip), "chip->int_reg = 0x%x\n",
698 spin_lock_irq(&rtsx->reg_lock);
699 if (rtsx->trans_result == TRANS_RESULT_FAIL)
701 else if (rtsx->trans_result == TRANS_RESULT_OK)
704 spin_unlock_irq(&rtsx->reg_lock);
708 rtsx->trans_state = STATE_TRANS_NONE;
709 dma_unmap_single(&(rtsx->pci->dev), addr, len, dma_dir);
712 rtsx_stop_cmd(chip, card);
717 int rtsx_transfer_data_partial(struct rtsx_chip *chip, u8 card,
718 void *buf, size_t len, int use_sg, unsigned int *index,
719 unsigned int *offset, enum dma_data_direction dma_dir,
724 /* don't transfer data during abort processing */
725 if (rtsx_chk_stat(chip, RTSX_STAT_ABORT))
729 err = rtsx_transfer_sglist_adma_partial(chip, card,
730 (struct scatterlist *)buf, use_sg,
731 index, offset, (int)len, dma_dir, timeout);
733 err = rtsx_transfer_buf(chip, card,
734 buf, len, dma_dir, timeout);
736 if (RTSX_TST_DELINK(chip)) {
737 RTSX_CLR_DELINK(chip);
738 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
739 rtsx_reinit_cards(chip, 1);
746 int rtsx_transfer_data(struct rtsx_chip *chip, u8 card, void *buf, size_t len,
747 int use_sg, enum dma_data_direction dma_dir, int timeout)
751 dev_dbg(rtsx_dev(chip), "use_sg = %d\n", use_sg);
753 /* don't transfer data during abort processing */
754 if (rtsx_chk_stat(chip, RTSX_STAT_ABORT))
758 err = rtsx_transfer_sglist_adma(chip, card,
759 (struct scatterlist *)buf,
760 use_sg, dma_dir, timeout);
762 err = rtsx_transfer_buf(chip, card, buf, len, dma_dir, timeout);
766 if (RTSX_TST_DELINK(chip)) {
767 RTSX_CLR_DELINK(chip);
768 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
769 rtsx_reinit_cards(chip, 1);