1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 ******************************************************************************/
17 #ifndef __HALDMOUTSRC_H__
18 #define __HALDMOUTSRC_H__
24 /* 2011/09/22 MH Define all team supprt ability. */
28 /* 2011/09/22 MH Define for all teams. Please Define the constan in your precomp header. */
30 /* define DM_ODM_SUPPORT_AP 0 */
31 /* define DM_ODM_SUPPORT_ADSL 0 */
32 /* define DM_ODM_SUPPORT_CE 0 */
33 /* define DM_ODM_SUPPORT_MP 1 */
38 #define TRAFFIC_HIGH 1
42 /* 3 Tx Power Tracking */
43 /* 3============================================================ */
44 #define DPK_DELTA_MAPPING_NUM 13
45 #define index_mapping_HP_NUM 15
50 /* 3============================================================ */
52 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */
53 #define MODE_40M 0 /* 0:20M, 1:40M */
55 #define PSD_CHMIN 20 /* Minimum channel number for BT AFH */
56 #define SIR_STEP_SIZE 3
57 #define Smooth_Size_1 5
59 #define Smooth_Size_2 10
61 #define Smooth_Size_3 20
63 #define Smooth_Step_Size 5
64 #define Adaptive_SIR 1
66 #define PSD_SCAN_INTERVAL 700 /* ms */
68 /* 8723A High Power IGI Setting */
69 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
70 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
71 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a
74 #define DM_DIG_FA_TH0_LPS 4 /* 4 in lps */
75 #define DM_DIG_FA_TH1_LPS 15 /* 15 lps */
76 #define DM_DIG_FA_TH2_LPS 30 /* 30 lps */
77 #define RSSI_OFFSET_DIG 0x05;
80 #define ANTTESTALL 0x00 /* Ant A or B will be Testing */
81 #define ANTTESTA 0x01 /* Ant A will be Testing */
82 #define ANTTESTB 0x02 /* Ant B will be testing */
86 /* structure and define */
91 u8 Dig_Ext_Port_Stage;
99 u8 CurSTAConnectState;
100 u8 PreSTAConnectState;
101 u8 CurMultiSTAConnectState;
108 s8 BackoffVal_range_max;
109 s8 BackoffVal_range_min;
110 u8 rx_gain_range_max;
111 u8 rx_gain_range_min;
123 u8 DIG_Dynamic_MIN_0;
124 u8 DIG_Dynamic_MIN_1;
125 bool bMediaConnect_0;
126 bool bMediaConnect_1;
132 struct dynamic_pwr_sav {
142 u32 Reg874,RegC70,Reg85C,RegA74;
145 struct false_alarm_stats {
147 u32 Cnt_Rate_Illegal;
154 u32 Cnt_SB_Search_fail;
158 u32 Cnt_BW_USC; /* Gary */
159 u32 Cnt_BW_LSC; /* Gary */
173 u8 PSD_bitmap_RXHP[80];
178 bool First_time_enter;
183 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */
184 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
186 /* This indicates two different the steps. */
187 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
188 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
189 /* with original RSSI to determine if it is necessary to switch antenna. */
190 #define SWAW_STEP_PEAK 0
191 #define SWAW_STEP_DETERMINE 1
195 #define TRAFFIC_LOW 0
196 #define TRAFFIC_HIGH 1
205 u8 bTriggerAntennaSwitch;
209 /* Before link Antenna Switch check */
210 u8 SWAS_NoLink_State;
211 u32 SWAS_NoLink_BK_Reg860;
212 bool ANTA_ON; /* To indicate Ant A is or not */
213 bool ANTB_ON; /* To indicate Ant B is on or not */
230 bool bCurrentTurboEDCA;
232 u32 prv_traffic_idx; /* edca turbo */
235 struct odm_rate_adapt {
236 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */
237 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */
238 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */
239 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
240 u32 LastRATR; /* RATR Register Content */
243 #define IQK_MAC_REG_NUM 4
244 #define IQK_ADDA_REG_NUM 16
245 #define IQK_BB_REG_NUM_MAX 10
246 #define IQK_BB_REG_NUM 9
247 #define HP_THERMAL_NUM 8
249 #define AVG_THERMAL_NUM 8
250 #define IQK_Matrix_REG_NUM 8
251 #define IQK_Matrix_Settings_NUM 1+24+21
253 #define DM_Type_ByFW 0
254 #define DM_Type_ByDriver 1
256 /* Declare for common info */
258 struct odm_phy_dbg_info {
259 /* ODM Write,debug info */
260 s8 RxSNRdB[RF_PATH_MAX];
262 u64 NumQryPhyStatusCCK;
263 u64 NumQryPhyStatusOFDM;
265 s32 RxEVM[RF_PATH_MAX];
269 struct odm_packet_info {
272 bool bPacketMatchBSSID;
280 ODM_DIG = 0x00000001,
281 ODM_HIGH_POWER = 0x00000002,
282 ODM_CCK_CCA_TH = 0x00000004,
283 ODM_FA_STATISTICS = 0x00000008,
284 ODM_RAMASK = 0x00000010,
285 ODM_RSSI_MONITOR = 0x00000020,
286 ODM_SW_ANTDIV = 0x00000040,
287 ODM_HW_ANTDIV = 0x00000080,
288 ODM_BB_PWRSV = 0x00000100,
289 ODM_2TPATHDIV = 0x00000200,
290 ODM_1TPATHDIV = 0x00000400,
291 ODM_PSD2AFH = 0x00000800
295 /* 2011/10/20 MH Define Common info enum for all team. */
302 ODM_CMNINFO_PLATFORM = 0,
303 ODM_CMNINFO_ABILITY, /* enum odm_ability */
304 ODM_CMNINFO_INTERFACE, /* enum odm_interface_def */
305 ODM_CMNINFO_MP_TEST_CHIP,
306 ODM_CMNINFO_IC_TYPE, /* enum odm_ic_type_def */
307 ODM_CMNINFO_CUT_VER, /* enum odm_cut_version */
308 ODM_CMNINFO_FAB_VER, /* enum odm_fab_version */
309 ODM_CMNINFO_RF_TYPE, /* enum rf_path_def or enum odm_rf_type? */
310 ODM_CMNINFO_BOARD_TYPE, /* enum odm_board_type */
311 ODM_CMNINFO_EXT_LNA, /* true */
313 ODM_CMNINFO_EXT_TRSW,
314 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */
315 ODM_CMNINFO_BINHCT_TEST,
316 ODM_CMNINFO_BWIFI_TEST,
317 ODM_CMNINFO_SMART_CONCURRENT,
323 ODM_CMNINFO_MAC_PHY_MODE, /* enum odm_mac_phy_mode */
326 ODM_CMNINFO_WM_MODE, /* enum odm_wireless_mode */
327 ODM_CMNINFO_BAND, /* enum odm_band_type */
328 ODM_CMNINFO_SEC_CHNL_OFFSET, /* enum odm_sec_chnl_offset */
329 ODM_CMNINFO_SEC_MODE, /* enum odm_security */
330 ODM_CMNINFO_BW, /* enum odm_band_width */
333 ODM_CMNINFO_DMSP_GET_VALUE,
334 ODM_CMNINFO_BUDDY_ADAPTOR,
335 ODM_CMNINFO_DMSP_IS_MASTER,
337 ODM_CMNINFO_POWER_SAVING,
338 ODM_CMNINFO_ONE_PATH_CCA, /* enum odm_cca_path */
339 ODM_CMNINFO_DRV_STOP,
342 ODM_CMNINFO_ANT_TEST,
343 ODM_CMNINFO_NET_CLOSED,
346 ODM_CMNINFO_WIFI_DIRECT,
347 ODM_CMNINFO_WIFI_DISPLAY,
349 ODM_CMNINFO_RSSI_MIN,
350 ODM_CMNINFO_DBG_COMP, /* u64 */
351 ODM_CMNINFO_DBG_LEVEL, /* u32 */
352 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */
353 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */
354 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */
355 ODM_CMNINFO_BT_DISABLED,
356 ODM_CMNINFO_BT_OPERATION,
358 ODM_CMNINFO_BT_BUSY, /* Check Bt is using or not */
359 ODM_CMNINFO_BT_DISABLE_EDCA,
362 /* Dynamic ptr array hook itms. */
364 ODM_CMNINFO_STA_STATUS,
365 ODM_CMNINFO_PHY_STATUS,
366 ODM_CMNINFO_MAC_STATUS,
371 /* Define ODM support ability. ODM_CMNINFO_ABILITY */
373 /* BB ODM section BIT 0-15 */
375 ODM_BB_RA_MASK = BIT(1),
376 ODM_BB_DYNAMIC_TXPWR = BIT(2),
377 ODM_BB_FA_CNT = BIT(3),
378 ODM_BB_RSSI_MONITOR = BIT(4),
379 ODM_BB_CCK_PD = BIT(5),
380 ODM_BB_ANT_DIV = BIT(6),
381 ODM_BB_PWR_SAVE = BIT(7),
382 ODM_BB_PWR_TRAIN = BIT(8),
383 ODM_BB_RATE_ADAPTIVE = BIT(9),
384 ODM_BB_PATH_DIV = BIT(10),
385 ODM_BB_PSD = BIT(11),
386 ODM_BB_RXHP = BIT(12),
388 /* MAC DM section BIT 16-23 */
389 ODM_MAC_EDCA_TURBO = BIT(16),
390 ODM_MAC_EARLY_MODE = BIT(17),
392 /* RF ODM section BIT 24-31 */
393 ODM_RF_TX_PWR_TRACK = BIT(24),
394 ODM_RF_RX_GAIN_TRACK = BIT(25),
395 ODM_RF_CALIBRATION = BIT(26),
399 /* ODM_CMNINFO_INTERFACE */
400 enum odm_interface_def {
407 /* ODM_CMNINFO_IC_TYPE */
408 enum odm_ic_type_def {
409 ODM_RTL8192S = BIT(0),
410 ODM_RTL8192C = BIT(1),
411 ODM_RTL8192D = BIT(2),
412 ODM_RTL8723A = BIT(3),
413 ODM_RTL8188E = BIT(4),
414 ODM_RTL8812 = BIT(5),
415 ODM_RTL8821 = BIT(6),
418 #define ODM_IC_11N_SERIES \
419 (ODM_RTL8192S|ODM_RTL8192C|ODM_RTL8192D|ODM_RTL8723A|ODM_RTL8188E)
420 #define ODM_IC_11AC_SERIES (ODM_RTL8812)
422 /* ODM_CMNINFO_CUT_VER */
423 enum odm_cut_version {
433 /* ODM_CMNINFO_FAB_VER */
434 enum odm_fab_version {
439 /* ODM_CMNINFO_RF_TYPE */
440 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
442 ODM_RF_TX_A = BIT(0),
443 ODM_RF_TX_B = BIT(1),
444 ODM_RF_TX_C = BIT(2),
445 ODM_RF_TX_D = BIT(3),
446 ODM_RF_RX_A = BIT(4),
447 ODM_RF_RX_B = BIT(5),
448 ODM_RF_RX_C = BIT(6),
449 ODM_RF_RX_D = BIT(7),
464 /* ODM Dynamic common info value definition */
466 enum odm_mac_phy_mode {
473 enum odm_bt_coexist {
480 /* ODM_CMNINFO_OP_MODE */
481 enum odm_operation_mode {
482 ODM_NO_LINK = BIT(0),
485 ODM_POWERSAVE = BIT(3),
486 ODM_AP_MODE = BIT(4),
487 ODM_CLIENT_MODE = BIT(5),
489 ODM_WIFI_DIRECT = BIT(7),
490 ODM_WIFI_DISPLAY = BIT(8),
493 /* ODM_CMNINFO_WM_MODE */
494 enum odm_wireless_mode {
499 ODM_WM_N24G = BIT(3),
501 ODM_WM_AUTO = BIT(5),
505 /* ODM_CMNINFO_BAND */
507 ODM_BAND_2_4G = BIT(0),
508 ODM_BAND_5G = BIT(1),
512 /* ODM_CMNINFO_SEC_CHNL_OFFSET */
513 enum odm_sec_chnl_offset {
520 enum odm_band_width {
528 /* ODM_CMNINFO_CHNL */
530 /* ODM_CMNINFO_BOARD_TYPE */
531 enum odm_board_type {
532 ODM_BOARD_NORMAL = 0,
533 ODM_BOARD_HIGHPWR = 1,
534 ODM_BOARD_MINICARD = 2,
540 /* ODM_CMNINFO_ONE_PATH_CCA */
547 struct iqk_matrix_regs_set {
549 s32 Value[1][IQK_Matrix_REG_NUM];
552 struct odm_rf_cal_t {
553 /* for tx power tracking */
555 u32 RegA24; /* for TempCCK */
561 /* u8 bTXPowerTracking; */
563 bool bTXPowerTrackingInit;
564 bool bTXPowerTracking;
565 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
567 u8 InternalPA5G[2]; /* pathA / pathB */
569 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
574 u8 ThermalValue_AVG[AVG_THERMAL_NUM];
575 u8 ThermalValue_AVG_index;
576 u8 ThermalValue_RxGain;
577 u8 ThermalValue_Crystal;
578 u8 ThermalValue_DPKstore;
579 u8 ThermalValue_DPKtrack;
580 bool TxPowerTrackingInProgress;
583 bool bReloadtxpowerindex;
585 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
592 u8 ThermalValue_HP[HP_THERMAL_NUM];
593 u8 ThermalValue_HP_index;
594 struct iqk_matrix_regs_set IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
609 bool bIQKInitialized;
611 bool bAntennaDetected;
612 u32 ADDA_backup[IQK_ADDA_REG_NUM];
613 u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
614 u32 IQK_BB_backup_recover[9];
615 u32 IQK_BB_backup[IQK_BB_REG_NUM];
618 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
620 u8 bAPKThermalMeterIgnore;
626 /* ODM Dynamic common info value definition */
637 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
638 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
639 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
640 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
641 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
642 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
643 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
649 FAT_NORMAL_STATE = 0,
650 FAT_TRAINING_STATE = 1,
655 CG_TRX_HW_ANTDIV = 0x01,
656 CGCS_RX_HW_ANTDIV = 0x02,
657 FIXED_HW_ANTDIV = 0x03,
658 CG_TRX_SMART_ANTDIV = 0x04,
659 CGCS_RX_SW_ANTDIV = 0x05,
662 /* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */
665 /* Add for different team use temporarily */
667 struct rtw_adapter *Adapter; /* For CE/NIC team */
672 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
674 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */
676 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
678 /* 1 COMMON INFORMATION */
681 /* HOOK BEFORE REG INIT----------- */
682 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ¡K¡K = 1/2/3/¡K */
684 /* ODM PCIE/USB/SDIO/GSPI = 0/1/2/3 */
686 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */
688 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
690 /* Fab Version TSMC/UMC = 0/1 */
692 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */
694 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */
696 /* with external LNA NO/Yes = 0/1 */
698 /* with external PA NO/Yes = 0/1 */
700 /* with external TRSW NO/Yes = 0/1 */
702 u8 PatchID; /* Customer ID */
706 bool bDualMacSmartConcurrent;
707 u32 BK_SupportAbility;
709 /* HOOK BEFORE REG INIT----------- */
714 /* POINTER REFERENCE----------- */
718 struct rtw_adapter *PADAPTER_temp;
720 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
722 /* TX Unicast byte count */
723 u64 *pNumTxBytesUnicast;
724 /* RX Unicast byte count */
725 u64 *pNumRxBytesUnicast;
726 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
727 u8 *pWirelessMode; /* enum odm_wireless_mode */
728 /* Frequence band 2.4G/5G = 0/1 */
730 /* Secondary channel offset don't_care/below/above = 0/1/2 */
732 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
734 /* BW info 20M/40M/80M = 0/1/2 */
736 /* Central channel location Ch1/Ch2/.... */
737 u8 *pChannel; /* central channel number */
738 /* Common info for 92D DMSP */
740 bool *pbGetValueFromOtherMac;
741 struct rtw_adapter **pBuddyAdapter;
742 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
743 /* Common info for Status */
744 bool *pbScanInProcess;
746 /* CCA Path 2-path/path-A/path-B = 0/1/2; using enum odm_cca_path. */
748 /* pMgntInfo->AntennaTest */
751 /* POINTER REFERENCE----------- */
753 /* CALL BY VALUE------------- */
758 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */
761 /* Common info for BTDM */
762 bool bBtDisabled; /* BT is disabled */
763 bool bBtHsOperation; /* BT HS mode is under progress */
764 u8 btHsDigVal; /* use BT rssi to decide the DIG value */
765 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */
766 bool bBtBusy; /* BT is busy. */
767 /* CALL BY VALUE------------- */
769 /* 2 Define STA info. */
771 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */
772 struct sta_info * pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
775 /* 2012/02/14 MH Add to share 88E ra with other SW team. */
776 /* We need to colelct all support abilit to a proper area. */
780 /* Define ........... */
782 /* Latest packet phy info (ODM write) */
783 struct odm_phy_dbg_info PhyDbgInfo;
784 /* PHY_INFO_88E PhyInfo; */
786 /* Latest packet phy info (ODM write) */
787 /* MAC_INFO_88E MacInfo; */
789 /* Different Team independt structure?? */
792 /* TX_RTP_CMN TX_retrpo; */
793 /* TX_RTP_88E TX_retrpo; */
794 /* TX_RTP_8195 TX_retrpo; */
799 struct odm_fat_t DM_FatTable;
800 struct dig_t DM_DigTable;
801 struct dynamic_pwr_sav DM_PSTable;
802 struct pri_cca DM_PriCCA;
803 struct rx_hp DM_RXHP_Table;
804 struct false_alarm_stats FalseAlmCnt;
805 struct false_alarm_stats FlaseAlmCntBuddyAdapter;
806 struct sw_ant_sw DM_SWAT_Table;
809 struct edca_turbo DM_EDCA_Table;
811 /* Copy from SD4 structure */
813 /* ================================================== */
817 bool *pbDriverStopped;
818 bool *pbDriverIsGoingToPnpSetPowerSleep;
819 bool *pinit_adpt_in_progress;
822 bool bUserAssignLevel;
823 u8 RSSI_BT; /* come from BT */
825 bool bDMInitialGainEnable;
827 /* for rate adaptive, in fact, 88c/92c fw will handle this */
830 struct odm_rate_adapt RateAdaptive;
833 struct odm_rf_cal_t RFCalibrateInfo;
836 /* TX power tracking */
839 u8 BbSwingIdxOfdmCurrent;
840 u8 BbSwingIdxOfdmBase;
841 bool BbSwingFlagOfdm;
843 u8 BbSwingIdxCckCurrent;
844 u8 BbSwingIdxCckBase;
847 /* ODM system resource. */
849 }; /* DM_Dynamic_Mechanism_Structure */
851 enum odm_rf_content {
852 odm_radioa_txt = 0x1000,
853 odm_radiob_txt = 0x1001,
854 odm_radioc_txt = 0x1002,
855 odm_radiod_txt = 0x1003
864 RT_STATUS_INVALID_CONTEXT,
865 RT_STATUS_INVALID_PARAMETER,
866 RT_STATUS_NOT_SUPPORT,
867 RT_STATUS_OS_API_FAILED,
870 /* include "odm_function.h" */
872 /* 3=========================================================== */
874 /* 3=========================================================== */
877 DIG_TYPE_THRESH_HIGH = 0,
878 DIG_TYPE_THRESH_LOW = 1,
879 DIG_TYPE_BACKOFF = 2,
880 DIG_TYPE_RX_GAIN_MIN = 3,
881 DIG_TYPE_RX_GAIN_MAX = 4,
883 DIG_TYPE_DISABLE = 6,
887 #define DM_DIG_THRESH_HIGH 40
888 #define DM_DIG_THRESH_LOW 35
890 #define DM_SCAN_RSSI_TH 0x14 /* scan return issue for LC */
893 #define DM_FALSEALARM_THRESH_LOW 400
894 #define DM_FALSEALARM_THRESH_HIGH 1000
896 #define DM_DIG_MAX_NIC 0x4e
897 #define DM_DIG_MIN_NIC 0x1e
899 #define DM_DIG_MAX_AP 0x32
900 #define DM_DIG_MIN_AP 0x20
902 #define DM_DIG_MAX_NIC_HP 0x46
903 #define DM_DIG_MIN_NIC_HP 0x2e
905 #define DM_DIG_MAX_AP_HP 0x42
906 #define DM_DIG_MIN_AP_HP 0x30
908 /* vivi 92c&92d has different definition, 20110504 */
909 /* this is for 92c */
910 #define DM_DIG_FA_TH0 0x200
911 #define DM_DIG_FA_TH1 0x300
912 #define DM_DIG_FA_TH2 0x400
913 /* this is for 92d */
914 #define DM_DIG_FA_TH0_92D 0x100
915 #define DM_DIG_FA_TH1_92D 0x400
916 #define DM_DIG_FA_TH2_92D 0x600
918 #define DM_DIG_BACKOFF_MAX 12
919 #define DM_DIG_BACKOFF_MIN -4
920 #define DM_DIG_BACKOFF_DEFAULT 10
922 /* 3=========================================================== */
923 /* 3 AGC RX High Power Mode */
924 /* 3=========================================================== */
925 #define LNA_Low_Gain_1 0x64
926 #define LNA_Low_Gain_2 0x5A
927 #define LNA_Low_Gain_3 0x58
929 #define FA_RXHP_TH1 5000
930 #define FA_RXHP_TH2 1500
931 #define FA_RXHP_TH3 800
932 #define FA_RXHP_TH4 600
933 #define FA_RXHP_TH5 500
935 /* 3=========================================================== */
937 /* 3=========================================================== */
939 /* 3=========================================================== */
940 /* 3 Dynamic Tx Power */
941 /* 3=========================================================== */
942 /* Dynamic Tx Power Control Threshold */
943 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
944 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
945 #define TX_POWER_NEAR_FIELD_THRESH_AP 0x3F
947 #define TxHighPwrLevel_Normal 0
948 #define TxHighPwrLevel_Level1 1
949 #define TxHighPwrLevel_Level2 2
950 #define TxHighPwrLevel_BT1 3
951 #define TxHighPwrLevel_BT2 4
952 #define TxHighPwrLevel_15 5
953 #define TxHighPwrLevel_35 6
954 #define TxHighPwrLevel_50 7
955 #define TxHighPwrLevel_70 8
956 #define TxHighPwrLevel_100 9
958 /* 3=========================================================== */
959 /* 3 Rate Adaptive */
960 /* 3=========================================================== */
961 #define DM_RATR_STA_INIT 0
962 #define DM_RATR_STA_HIGH 1
963 #define DM_RATR_STA_MIDDLE 2
964 #define DM_RATR_STA_LOW 3
966 /* 3=========================================================== */
967 /* 3 BB Power Save */
968 /* 3=========================================================== */
983 /* 3=========================================================== */
984 /* 3 Antenna Diversity */
985 /* 3=========================================================== */
992 /* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */
993 #define MAX_ANTENNA_DETECTION_CNT 10
996 /* Extern Global Variables. */
998 #define OFDM_TABLE_SIZE_92C 37
999 #define OFDM_TABLE_SIZE_92D 43
1000 #define CCK_TABLE_SIZE 33
1002 extern u32 OFDMSwingTable23A[OFDM_TABLE_SIZE_92D];
1003 extern u8 CCKSwingTable_Ch1_Ch1323A[CCK_TABLE_SIZE][8];
1004 extern u8 CCKSwingTable_Ch1423A [CCK_TABLE_SIZE][8];
1009 /* check Sta pointer valid or not */
1011 #define IS_STA_VALID(pSta) (pSta)
1012 /* 20100514 Joseph: Add definition for antenna switching test after link. */
1013 /* This indicates two different the steps. */
1014 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
1015 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
1016 /* with original RSSI to determine if it is necessary to switch antenna. */
1017 #define SWAW_STEP_PEAK 0
1018 #define SWAW_STEP_DETERMINE 1
1020 void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm, u8 CurrentIGI);
1021 void ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t *pDM_Odm, u8 CurCCK_CCAThres);
1023 void ODM_SetAntenna(struct dm_odm_t *pDM_Odm, u8 Antenna);
1026 #define dm_RF_Saving ODM_RF_Saving23a
1027 void ODM_RF_Saving23a(struct dm_odm_t *pDM_Odm, u8 bForceInNormal);
1029 #define SwAntDivRestAfterLink ODM_SwAntDivRestAfterLink
1030 void ODM_SwAntDivRestAfterLink(struct dm_odm_t *pDM_Odm);
1032 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck23a
1033 void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm);
1035 bool ODM_RAStateCheck23a(struct dm_odm_t *pDM_Odm, s32 RSSI, bool bForceUpdate,
1039 #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi
1040 void ODM_SwAntDivChkPerPktRssi(struct dm_odm_t *pDM_Odm, u8 StationID,
1041 struct phy_info *pPhyInfo);
1043 u32 ConvertTo_dB23a(u32 Value);
1045 u32 GetPSDData(struct dm_odm_t *pDM_Odm, unsigned int point, u8 initial_gain_psd);
1047 void odm_DIG23abyRSSI_LPS(struct dm_odm_t *pDM_Odm);
1049 u32 ODM_Get_Rate_Bitmap23a(struct dm_odm_t *pDM_Odm, u32 macid, u32 ra_mask, u8 rssi_level);
1052 void ODM23a_DMInit(struct dm_odm_t *pDM_Odm);
1054 void ODM_DMWatchdog23a(struct dm_odm_t *pDM_Odm); /* For common use in the future */
1056 void ODM_CmnInfoInit23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, u32 Value);
1058 void ODM23a_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, void *pValue);
1060 void ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo, u16 Index, void *pValue);
1062 void ODM_CmnInfoUpdate23a(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value);
1064 void ODM_ResetIQKResult(struct dm_odm_t *pDM_Odm);
1066 void ODM_AntselStatistics_88C(struct dm_odm_t *pDM_Odm, u8 MacId, u32 PWDBAll, bool isCCKrate);
1068 void ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t *pDM_Odm);
1070 bool ODM_SingleDualAntennaDetection(struct dm_odm_t *pDM_Odm, u8 mode);
1072 void odm_dtc(struct dm_odm_t *pDM_Odm);