Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[firefly-linux-kernel-4.4.55.git] / drivers / staging / rtl8192e / rtl8192e / r8192E_dev.c
1 /******************************************************************************
2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3  *
4  * Based on the r8180 driver, which is:
5  * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of version 2 of the GNU General Public License as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program; if not, write to the Free Software Foundation, Inc.,
17  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18  *
19  * The full GNU General Public License is included in this distribution in the
20  * file called LICENSE.
21  *
22  * Contact Information:
23  * wlanfae <wlanfae@realtek.com>
24 ******************************************************************************/
25 #include "rtl_core.h"
26 #include "r8192E_phy.h"
27 #include "r8192E_phyreg.h"
28 #include "r8190P_rtl8256.h"
29 #include "r8192E_cmdpkt.h"
30 #include "rtl_dm.h"
31 #include "rtl_wx.h"
32
33 static int WDCAPARA_ADD[] = {EDCAPARA_BE, EDCAPARA_BK, EDCAPARA_VI,
34                              EDCAPARA_VO};
35
36 void rtl8192e_start_beacon(struct net_device *dev)
37 {
38         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
39         struct rtllib_network *net = &priv->rtllib->current_network;
40         u16 BcnTimeCfg = 0;
41         u16 BcnCW = 6;
42         u16 BcnIFS = 0xf;
43
44         DMESG("Enabling beacon TX");
45         rtl8192_irq_disable(dev);
46
47         write_nic_word(dev, ATIMWND, 2);
48
49         write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
50         write_nic_word(dev, BCN_DRV_EARLY_INT, 10);
51         write_nic_word(dev, BCN_DMATIME, 256);
52
53         write_nic_byte(dev, BCN_ERR_THRESH, 100);
54
55         BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
56         BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
57         write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
58         rtl8192_irq_enable(dev);
59 }
60
61 static void rtl8192e_update_msr(struct net_device *dev)
62 {
63         struct r8192_priv *priv = rtllib_priv(dev);
64         u8 msr;
65         enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
66
67         msr  = read_nic_byte(dev, MSR);
68         msr &= ~MSR_LINK_MASK;
69
70         switch (priv->rtllib->iw_mode) {
71         case IW_MODE_INFRA:
72                 if (priv->rtllib->state == RTLLIB_LINKED)
73                         msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
74                 else
75                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
76                 LedAction = LED_CTL_LINK;
77                 break;
78         case IW_MODE_ADHOC:
79                 if (priv->rtllib->state == RTLLIB_LINKED)
80                         msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
81                 else
82                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
83                 break;
84         case IW_MODE_MASTER:
85                 if (priv->rtllib->state == RTLLIB_LINKED)
86                         msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
87                 else
88                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
89                 break;
90         default:
91                 break;
92         }
93
94         write_nic_byte(dev, MSR, msr);
95         if (priv->rtllib->LedControlHandler)
96                 priv->rtllib->LedControlHandler(dev, LedAction);
97 }
98
99 void rtl8192e_SetHwReg(struct net_device *dev, u8 variable, u8 *val)
100 {
101         struct r8192_priv *priv = rtllib_priv(dev);
102
103         switch (variable) {
104         case HW_VAR_BSSID:
105                 write_nic_dword(dev, BSSIDR, ((u32 *)(val))[0]);
106                 write_nic_word(dev, BSSIDR+2, ((u16 *)(val+2))[0]);
107                 break;
108
109         case HW_VAR_MEDIA_STATUS:
110         {
111                 enum rt_op_mode OpMode = *((enum rt_op_mode *)(val));
112                 enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
113                 u8              btMsr = read_nic_byte(dev, MSR);
114
115                 btMsr &= 0xfc;
116
117                 switch (OpMode) {
118                 case RT_OP_MODE_INFRASTRUCTURE:
119                         btMsr |= MSR_INFRA;
120                         LedAction = LED_CTL_LINK;
121                         break;
122
123                 case RT_OP_MODE_IBSS:
124                         btMsr |= MSR_ADHOC;
125                         break;
126
127                 case RT_OP_MODE_AP:
128                         btMsr |= MSR_AP;
129                         LedAction = LED_CTL_LINK;
130                         break;
131
132                 default:
133                         btMsr |= MSR_NOLINK;
134                         break;
135                 }
136
137                 write_nic_byte(dev, MSR, btMsr);
138
139         }
140         break;
141
142         case HW_VAR_CECHK_BSSID:
143         {
144                 u32     RegRCR, Type;
145
146                 Type = ((u8 *)(val))[0];
147                 RegRCR = read_nic_dword(dev, RCR);
148                 priv->ReceiveConfig = RegRCR;
149
150                 if (Type == true)
151                         RegRCR |= (RCR_CBSSID);
152                 else if (Type == false)
153                         RegRCR &= (~RCR_CBSSID);
154
155                 write_nic_dword(dev, RCR, RegRCR);
156                 priv->ReceiveConfig = RegRCR;
157
158         }
159         break;
160
161         case HW_VAR_SLOT_TIME:
162
163                 priv->slot_time = val[0];
164                 write_nic_byte(dev, SLOT_TIME, val[0]);
165
166                 break;
167
168         case HW_VAR_ACK_PREAMBLE:
169         {
170                 u32 regTmp;
171
172                 priv->short_preamble = (bool)(*(u8 *)val);
173                 regTmp = priv->basic_rate;
174                 if (priv->short_preamble)
175                         regTmp |= BRSR_AckShortPmb;
176                 write_nic_dword(dev, RRSR, regTmp);
177                 break;
178         }
179
180         case HW_VAR_CPU_RST:
181                 write_nic_dword(dev, CPU_GEN, ((u32 *)(val))[0]);
182                 break;
183
184         case HW_VAR_AC_PARAM:
185         {
186                 u8      pAcParam = *((u8 *)val);
187                 u32     eACI = pAcParam;
188                 u8              u1bAIFS;
189                 u32             u4bAcParam;
190                 u8 mode = priv->rtllib->mode;
191                 struct rtllib_qos_parameters *qop =
192                          &priv->rtllib->current_network.qos_data.parameters;
193
194                 u1bAIFS = qop->aifs[pAcParam] *
195                           ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime;
196
197                 dm_init_edca_turbo(dev);
198
199                 u4bAcParam = (le16_to_cpu(qop->tx_op_limit[pAcParam]) <<
200                               AC_PARAM_TXOP_LIMIT_OFFSET) |
201                                 ((le16_to_cpu(qop->cw_max[pAcParam])) <<
202                                  AC_PARAM_ECW_MAX_OFFSET) |
203                                 ((le16_to_cpu(qop->cw_min[pAcParam])) <<
204                                  AC_PARAM_ECW_MIN_OFFSET) |
205                                 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET);
206
207                 RT_TRACE(COMP_DBG, "%s():HW_VAR_AC_PARAM eACI:%x:%x\n",
208                          __func__, eACI, u4bAcParam);
209                 switch (eACI) {
210                 case AC1_BK:
211                         write_nic_dword(dev, EDCAPARA_BK, u4bAcParam);
212                         break;
213
214                 case AC0_BE:
215                         write_nic_dword(dev, EDCAPARA_BE, u4bAcParam);
216                         break;
217
218                 case AC2_VI:
219                         write_nic_dword(dev, EDCAPARA_VI, u4bAcParam);
220                         break;
221
222                 case AC3_VO:
223                         write_nic_dword(dev, EDCAPARA_VO, u4bAcParam);
224                         break;
225
226                 default:
227                         netdev_info(dev, "SetHwReg8185(): invalid ACI: %d !\n",
228                                     eACI);
229                         break;
230                 }
231                 priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL,
232                                               (u8 *)(&pAcParam));
233                 break;
234         }
235
236         case HW_VAR_ACM_CTRL:
237         {
238                 struct rtllib_qos_parameters *qos_parameters =
239                          &priv->rtllib->current_network.qos_data.parameters;
240                 u8 pAcParam = *((u8 *)val);
241                 u32 eACI = pAcParam;
242                 union aci_aifsn *pAciAifsn = (union aci_aifsn *) &
243                                               (qos_parameters->aifs[0]);
244                 u8 acm = pAciAifsn->f.acm;
245                 u8 AcmCtrl = read_nic_byte(dev, AcmHwCtrl);
246
247                 RT_TRACE(COMP_DBG, "===========>%s():HW_VAR_ACM_CTRL:%x\n",
248                          __func__, eACI);
249                 AcmCtrl = AcmCtrl | ((priv->AcmMethod == 2) ? 0x0 : 0x1);
250
251                 if (acm) {
252                         switch (eACI) {
253                         case AC0_BE:
254                                 AcmCtrl |= AcmHw_BeqEn;
255                                 break;
256
257                         case AC2_VI:
258                                 AcmCtrl |= AcmHw_ViqEn;
259                                 break;
260
261                         case AC3_VO:
262                                 AcmCtrl |= AcmHw_VoqEn;
263                                 break;
264
265                         default:
266                                 RT_TRACE(COMP_QOS,
267                                          "SetHwReg8185(): [HW_VAR_ACM_CTRL] acm set failed: eACI is %d\n",
268                                          eACI);
269                                 break;
270                         }
271                 } else {
272                         switch (eACI) {
273                         case AC0_BE:
274                                 AcmCtrl &= (~AcmHw_BeqEn);
275                                 break;
276
277                         case AC2_VI:
278                                 AcmCtrl &= (~AcmHw_ViqEn);
279                                 break;
280
281                         case AC3_VO:
282                                 AcmCtrl &= (~AcmHw_BeqEn);
283                                 break;
284
285                         default:
286                                 break;
287                         }
288                 }
289
290                 RT_TRACE(COMP_QOS,
291                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
292                          AcmCtrl);
293                 write_nic_byte(dev, AcmHwCtrl, AcmCtrl);
294                 break;
295         }
296
297         case HW_VAR_SIFS:
298                 write_nic_byte(dev, SIFS, val[0]);
299                 write_nic_byte(dev, SIFS+1, val[0]);
300                 break;
301
302         case HW_VAR_RF_TIMING:
303         {
304                 u8 Rf_Timing = *((u8 *)val);
305
306                 write_nic_byte(dev, rFPGA0_RFTiming1, Rf_Timing);
307                 break;
308         }
309
310         default:
311                 break;
312         }
313
314 }
315
316 static void rtl8192_read_eeprom_info(struct net_device *dev)
317 {
318         struct r8192_priv *priv = rtllib_priv(dev);
319         const u8 bMac_Tmp_Addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
320         u8 tempval;
321         u8 ICVer8192, ICVer8256;
322         u16 i, usValue, IC_Version;
323         u16 EEPROMId;
324
325         RT_TRACE(COMP_INIT, "====> rtl8192_read_eeprom_info\n");
326
327         EEPROMId = eprom_read(dev, 0);
328         if (EEPROMId != RTL8190_EEPROM_ID) {
329                 netdev_err(dev, "%s(): Invalid EEPROM ID: %x\n", __func__,
330                            EEPROMId);
331                 priv->AutoloadFailFlag = true;
332         } else {
333                 priv->AutoloadFailFlag = false;
334         }
335
336         if (!priv->AutoloadFailFlag) {
337                 priv->eeprom_vid = eprom_read(dev, EEPROM_VID >> 1);
338                 priv->eeprom_did = eprom_read(dev, EEPROM_DID >> 1);
339
340                 usValue = eprom_read(dev, (u16)(EEPROM_Customer_ID>>1)) >> 8;
341                 priv->eeprom_CustomerID = (u8)(usValue & 0xff);
342                 usValue = eprom_read(dev, EEPROM_ICVersion_ChannelPlan>>1);
343                 priv->eeprom_ChannelPlan = usValue&0xff;
344                 IC_Version = (usValue & 0xff00)>>8;
345
346                 ICVer8192 = (IC_Version&0xf);
347                 ICVer8256 = (IC_Version & 0xf0)>>4;
348                 RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192);
349                 RT_TRACE(COMP_INIT, "\nICVer8256 = 0x%x\n", ICVer8256);
350                 if (ICVer8192 == 0x2) {
351                         if (ICVer8256 == 0x5)
352                                 priv->card_8192_version = VERSION_8190_BE;
353                 }
354                 switch (priv->card_8192_version) {
355                 case VERSION_8190_BD:
356                 case VERSION_8190_BE:
357                         break;
358                 default:
359                         priv->card_8192_version = VERSION_8190_BD;
360                         break;
361                 }
362                 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n",
363                           priv->card_8192_version);
364         } else {
365                 priv->card_8192_version = VERSION_8190_BD;
366                 priv->eeprom_vid = 0;
367                 priv->eeprom_did = 0;
368                 priv->eeprom_CustomerID = 0;
369                 priv->eeprom_ChannelPlan = 0;
370                 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 0xff);
371         }
372
373         RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
374         RT_TRACE(COMP_INIT, "EEPROM DID = 0x%4x\n", priv->eeprom_did);
375         RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n",
376                  priv->eeprom_CustomerID);
377
378         if (!priv->AutoloadFailFlag) {
379                 for (i = 0; i < 6; i += 2) {
380                         usValue = eprom_read(dev,
381                                  (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1));
382                         *(u16 *)(&dev->dev_addr[i]) = usValue;
383                 }
384         } else {
385                 ether_addr_copy(dev->dev_addr, bMac_Tmp_Addr);
386         }
387
388         RT_TRACE(COMP_INIT, "Permanent Address = %pM\n",
389                  dev->dev_addr);
390
391         if (priv->card_8192_version > VERSION_8190_BD)
392                 priv->bTXPowerDataReadFromEEPORM = true;
393         else
394                 priv->bTXPowerDataReadFromEEPORM = false;
395
396         priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
397
398         if (priv->card_8192_version > VERSION_8190_BD) {
399                 if (!priv->AutoloadFailFlag) {
400                         tempval = (eprom_read(dev, (EEPROM_RFInd_PowerDiff >>
401                                               1))) & 0xff;
402                         priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf;
403
404                         if (tempval&0x80)
405                                 priv->rf_type = RF_1T2R;
406                         else
407                                 priv->rf_type = RF_2T4R;
408                 } else {
409                         priv->EEPROMLegacyHTTxPowerDiff = 0x04;
410                 }
411                 RT_TRACE(COMP_INIT, "EEPROMLegacyHTTxPowerDiff = %d\n",
412                         priv->EEPROMLegacyHTTxPowerDiff);
413
414                 if (!priv->AutoloadFailFlag)
415                         priv->EEPROMThermalMeter = (u8)(((eprom_read(dev,
416                                                    (EEPROM_ThermalMeter>>1))) &
417                                                    0xff00)>>8);
418                 else
419                         priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
420                 RT_TRACE(COMP_INIT, "ThermalMeter = %d\n",
421                          priv->EEPROMThermalMeter);
422                 priv->TSSI_13dBm = priv->EEPROMThermalMeter * 100;
423
424                 if (priv->epromtype == EEPROM_93C46) {
425                         if (!priv->AutoloadFailFlag) {
426                                 usValue = eprom_read(dev,
427                                           EEPROM_TxPwDiff_CrystalCap >> 1);
428                                 priv->EEPROMAntPwDiff = (usValue&0x0fff);
429                                 priv->EEPROMCrystalCap = (u8)((usValue & 0xf000)
430                                                          >> 12);
431                         } else {
432                                 priv->EEPROMAntPwDiff =
433                                          EEPROM_Default_AntTxPowerDiff;
434                                 priv->EEPROMCrystalCap =
435                                          EEPROM_Default_TxPwDiff_CrystalCap;
436                         }
437                         RT_TRACE(COMP_INIT, "EEPROMAntPwDiff = %d\n",
438                                  priv->EEPROMAntPwDiff);
439                         RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n",
440                                  priv->EEPROMCrystalCap);
441
442                         for (i = 0; i < 14; i += 2) {
443                                 if (!priv->AutoloadFailFlag)
444                                         usValue = eprom_read(dev,
445                                                   (u16)((EEPROM_TxPwIndex_CCK +
446                                                   i) >> 1));
447                                 else
448                                         usValue = EEPROM_Default_TxPower;
449                                 *((u16 *)(&priv->EEPROMTxPowerLevelCCK[i])) =
450                                                                  usValue;
451                                 RT_TRACE(COMP_INIT,
452                                          "CCK Tx Power Level, Index %d = 0x%02x\n",
453                                          i, priv->EEPROMTxPowerLevelCCK[i]);
454                                 RT_TRACE(COMP_INIT,
455                                          "CCK Tx Power Level, Index %d = 0x%02x\n",
456                                          i+1, priv->EEPROMTxPowerLevelCCK[i+1]);
457                         }
458                         for (i = 0; i < 14; i += 2) {
459                                 if (!priv->AutoloadFailFlag)
460                                         usValue = eprom_read(dev,
461                                                 (u16)((EEPROM_TxPwIndex_OFDM_24G
462                                                 + i) >> 1));
463                                 else
464                                         usValue = EEPROM_Default_TxPower;
465                                 *((u16 *)(&priv->EEPROMTxPowerLevelOFDM24G[i]))
466                                                          = usValue;
467                                 RT_TRACE(COMP_INIT,
468                                          "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
469                                          i, priv->EEPROMTxPowerLevelOFDM24G[i]);
470                                 RT_TRACE(COMP_INIT,
471                                          "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
472                                          i + 1,
473                                          priv->EEPROMTxPowerLevelOFDM24G[i+1]);
474                         }
475                 }
476                 if (priv->epromtype == EEPROM_93C46) {
477                         for (i = 0; i < 14; i++) {
478                                 priv->TxPowerLevelCCK[i] =
479                                          priv->EEPROMTxPowerLevelCCK[i];
480                                 priv->TxPowerLevelOFDM24G[i] =
481                                          priv->EEPROMTxPowerLevelOFDM24G[i];
482                         }
483                         priv->LegacyHTTxPowerDiff =
484                                          priv->EEPROMLegacyHTTxPowerDiff;
485                         priv->AntennaTxPwDiff[0] = (priv->EEPROMAntPwDiff &
486                                                     0xf);
487                         priv->AntennaTxPwDiff[1] = (priv->EEPROMAntPwDiff &
488                                                         0xf0) >> 4;
489                         priv->AntennaTxPwDiff[2] = (priv->EEPROMAntPwDiff &
490                                                         0xf00) >> 8;
491                         priv->CrystalCap = priv->EEPROMCrystalCap;
492                         priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
493                                                  0xf);
494                         priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
495                                                      0xf0) >> 4;
496                 } else if (priv->epromtype == EEPROM_93C56) {
497
498                         for (i = 0; i < 3; i++) {
499                                 priv->TxPowerLevelCCK_A[i] =
500                                          priv->EEPROMRfACCKChnl1TxPwLevel[0];
501                                 priv->TxPowerLevelOFDM24G_A[i] =
502                                          priv->EEPROMRfAOfdmChnlTxPwLevel[0];
503                                 priv->TxPowerLevelCCK_C[i] =
504                                          priv->EEPROMRfCCCKChnl1TxPwLevel[0];
505                                 priv->TxPowerLevelOFDM24G_C[i] =
506                                          priv->EEPROMRfCOfdmChnlTxPwLevel[0];
507                         }
508                         for (i = 3; i < 9; i++) {
509                                 priv->TxPowerLevelCCK_A[i]  =
510                                          priv->EEPROMRfACCKChnl1TxPwLevel[1];
511                                 priv->TxPowerLevelOFDM24G_A[i] =
512                                          priv->EEPROMRfAOfdmChnlTxPwLevel[1];
513                                 priv->TxPowerLevelCCK_C[i] =
514                                          priv->EEPROMRfCCCKChnl1TxPwLevel[1];
515                                 priv->TxPowerLevelOFDM24G_C[i] =
516                                          priv->EEPROMRfCOfdmChnlTxPwLevel[1];
517                         }
518                         for (i = 9; i < 14; i++) {
519                                 priv->TxPowerLevelCCK_A[i]  =
520                                          priv->EEPROMRfACCKChnl1TxPwLevel[2];
521                                 priv->TxPowerLevelOFDM24G_A[i] =
522                                          priv->EEPROMRfAOfdmChnlTxPwLevel[2];
523                                 priv->TxPowerLevelCCK_C[i] =
524                                          priv->EEPROMRfCCCKChnl1TxPwLevel[2];
525                                 priv->TxPowerLevelOFDM24G_C[i] =
526                                          priv->EEPROMRfCOfdmChnlTxPwLevel[2];
527                         }
528                         for (i = 0; i < 14; i++)
529                                 RT_TRACE(COMP_INIT,
530                                          "priv->TxPowerLevelCCK_A[%d] = 0x%x\n",
531                                          i, priv->TxPowerLevelCCK_A[i]);
532                         for (i = 0; i < 14; i++)
533                                 RT_TRACE(COMP_INIT,
534                                          "priv->TxPowerLevelOFDM24G_A[%d] = 0x%x\n",
535                                          i, priv->TxPowerLevelOFDM24G_A[i]);
536                         for (i = 0; i < 14; i++)
537                                 RT_TRACE(COMP_INIT,
538                                          "priv->TxPowerLevelCCK_C[%d] = 0x%x\n",
539                                          i, priv->TxPowerLevelCCK_C[i]);
540                         for (i = 0; i < 14; i++)
541                                 RT_TRACE(COMP_INIT,
542                                          "priv->TxPowerLevelOFDM24G_C[%d] = 0x%x\n",
543                                          i, priv->TxPowerLevelOFDM24G_C[i]);
544                         priv->LegacyHTTxPowerDiff =
545                                  priv->EEPROMLegacyHTTxPowerDiff;
546                         priv->AntennaTxPwDiff[0] = 0;
547                         priv->AntennaTxPwDiff[1] = 0;
548                         priv->AntennaTxPwDiff[2] = 0;
549                         priv->CrystalCap = priv->EEPROMCrystalCap;
550                         priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
551                                                  0xf);
552                         priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
553                                                      0xf0) >> 4;
554                 }
555         }
556
557         if (priv->rf_type == RF_1T2R) {
558                 /* no matter what checkpatch says, the braces are needed */
559                 RT_TRACE(COMP_INIT, "\n1T2R config\n");
560         } else if (priv->rf_type == RF_2T4R) {
561                 RT_TRACE(COMP_INIT, "\n2T4R config\n");
562         }
563
564         init_rate_adaptive(dev);
565
566         priv->rf_chip = RF_8256;
567
568         if (priv->RegChannelPlan == 0xf)
569                 priv->ChannelPlan = priv->eeprom_ChannelPlan;
570         else
571                 priv->ChannelPlan = priv->RegChannelPlan;
572
573         if (priv->eeprom_vid == 0x1186 &&  priv->eeprom_did == 0x3304)
574                 priv->CustomerID =  RT_CID_DLINK;
575
576         switch (priv->eeprom_CustomerID) {
577         case EEPROM_CID_DEFAULT:
578                 priv->CustomerID = RT_CID_DEFAULT;
579                 break;
580         case EEPROM_CID_CAMEO:
581                 priv->CustomerID = RT_CID_819x_CAMEO;
582                 break;
583         case  EEPROM_CID_RUNTOP:
584                 priv->CustomerID = RT_CID_819x_RUNTOP;
585                 break;
586         case EEPROM_CID_NetCore:
587                 priv->CustomerID = RT_CID_819x_Netcore;
588                 break;
589         case EEPROM_CID_TOSHIBA:
590                 priv->CustomerID = RT_CID_TOSHIBA;
591                 if (priv->eeprom_ChannelPlan&0x80)
592                         priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f;
593                 else
594                         priv->ChannelPlan = 0x0;
595                 RT_TRACE(COMP_INIT, "Toshiba ChannelPlan = 0x%x\n",
596                         priv->ChannelPlan);
597                 break;
598         case EEPROM_CID_Nettronix:
599                 priv->ScanDelay = 100;
600                 priv->CustomerID = RT_CID_Nettronix;
601                 break;
602         case EEPROM_CID_Pronet:
603                 priv->CustomerID = RT_CID_PRONET;
604                 break;
605         case EEPROM_CID_DLINK:
606                 priv->CustomerID = RT_CID_DLINK;
607                 break;
608
609         case EEPROM_CID_WHQL:
610                 break;
611         default:
612                 break;
613         }
614
615         if (priv->ChannelPlan > CHANNEL_PLAN_LEN - 1)
616                 priv->ChannelPlan = 0;
617         priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13;
618
619         if (priv->eeprom_vid == 0x1186 &&  priv->eeprom_did == 0x3304)
620                 priv->rtllib->bSupportRemoteWakeUp = true;
621         else
622                 priv->rtllib->bSupportRemoteWakeUp = false;
623
624         RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan);
625         RT_TRACE(COMP_INIT, "ChannelPlan = %d\n", priv->ChannelPlan);
626         RT_TRACE(COMP_TRACE, "<==== ReadAdapterInfo\n");
627 }
628
629 void rtl8192_get_eeprom_size(struct net_device *dev)
630 {
631         u16 curCR;
632         struct r8192_priv *priv = rtllib_priv(dev);
633
634         RT_TRACE(COMP_INIT, "===========>%s()\n", __func__);
635         curCR = read_nic_dword(dev, EPROM_CMD);
636         RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD,
637                  curCR);
638         priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 :
639                           EEPROM_93C46;
640         RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __func__,
641                  priv->epromtype);
642         rtl8192_read_eeprom_info(dev);
643 }
644
645 static void rtl8192_hwconfig(struct net_device *dev)
646 {
647         u32 regRATR = 0, regRRSR = 0;
648         u8 regBwOpMode = 0, regTmp = 0;
649         struct r8192_priv *priv = rtllib_priv(dev);
650
651         switch (priv->rtllib->mode) {
652         case WIRELESS_MODE_B:
653                 regBwOpMode = BW_OPMODE_20MHZ;
654                 regRATR = RATE_ALL_CCK;
655                 regRRSR = RATE_ALL_CCK;
656                 break;
657         case WIRELESS_MODE_A:
658                 regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ;
659                 regRATR = RATE_ALL_OFDM_AG;
660                 regRRSR = RATE_ALL_OFDM_AG;
661                 break;
662         case WIRELESS_MODE_G:
663                 regBwOpMode = BW_OPMODE_20MHZ;
664                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
665                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
666                 break;
667         case WIRELESS_MODE_AUTO:
668         case WIRELESS_MODE_N_24G:
669                 regBwOpMode = BW_OPMODE_20MHZ;
670                         regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
671                                   RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
672                         regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
673                 break;
674         case WIRELESS_MODE_N_5G:
675                 regBwOpMode = BW_OPMODE_5G;
676                 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS |
677                           RATE_ALL_OFDM_2SS;
678                 regRRSR = RATE_ALL_OFDM_AG;
679                 break;
680         default:
681                 regBwOpMode = BW_OPMODE_20MHZ;
682                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
683                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
684                 break;
685         }
686
687         write_nic_byte(dev, BW_OPMODE, regBwOpMode);
688         {
689                 u32 ratr_value = 0;
690
691                 ratr_value = regRATR;
692                 if (priv->rf_type == RF_1T2R)
693                         ratr_value &= ~(RATE_ALL_OFDM_2SS);
694                 write_nic_dword(dev, RATR0, ratr_value);
695                 write_nic_byte(dev, UFWP, 1);
696         }
697         regTmp = read_nic_byte(dev, 0x313);
698         regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
699         write_nic_dword(dev, RRSR, regRRSR);
700
701         write_nic_word(dev, RETRY_LIMIT,
702                         priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT |
703                         priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
704 }
705
706 bool rtl8192_adapter_start(struct net_device *dev)
707 {
708         struct r8192_priv *priv = rtllib_priv(dev);
709         u32 ulRegRead;
710         bool rtStatus = true;
711         u8 tmpvalue;
712         u8 ICVersion, SwitchingRegulatorOutput;
713         bool bfirmwareok = true;
714         u32 tmpRegA, tmpRegC, TempCCk;
715         int i = 0;
716         u32 retry_times = 0;
717
718         RT_TRACE(COMP_INIT, "====>%s()\n", __func__);
719         priv->being_init_adapter = true;
720
721 start:
722         rtl8192_pci_resetdescring(dev);
723         priv->Rf_Mode = RF_OP_By_SW_3wire;
724         if (priv->ResetProgress == RESET_TYPE_NORESET) {
725                 write_nic_byte(dev, ANAPAR, 0x37);
726                 mdelay(500);
727         }
728         priv->pFirmware->firmware_status = FW_STATUS_0_INIT;
729
730         if (priv->RegRfOff)
731                 priv->rtllib->eRFPowerState = eRfOff;
732
733         ulRegRead = read_nic_dword(dev, CPU_GEN);
734         if (priv->pFirmware->firmware_status == FW_STATUS_0_INIT)
735                 ulRegRead |= CPU_GEN_SYSTEM_RESET;
736         else if (priv->pFirmware->firmware_status == FW_STATUS_5_READY)
737                 ulRegRead |= CPU_GEN_FIRMWARE_RESET;
738         else
739                 netdev_err(dev, "%s(): undefined firmware state: %d.\n",
740                            __func__, priv->pFirmware->firmware_status);
741
742         write_nic_dword(dev, CPU_GEN, ulRegRead);
743
744         ICVersion = read_nic_byte(dev, IC_VERRSION);
745         if (ICVersion >= 0x4) {
746                 SwitchingRegulatorOutput = read_nic_byte(dev, SWREGULATOR);
747                 if (SwitchingRegulatorOutput  != 0xb8) {
748                         write_nic_byte(dev, SWREGULATOR, 0xa8);
749                         mdelay(1);
750                         write_nic_byte(dev, SWREGULATOR, 0xb8);
751                 }
752         }
753         RT_TRACE(COMP_INIT, "BB Config Start!\n");
754         rtStatus = rtl8192_BBConfig(dev);
755         if (!rtStatus) {
756                 netdev_warn(dev, "%s(): Failed to configure BB\n", __func__);
757                 return rtStatus;
758         }
759         RT_TRACE(COMP_INIT, "BB Config Finished!\n");
760
761         priv->LoopbackMode = RTL819X_NO_LOOPBACK;
762         if (priv->ResetProgress == RESET_TYPE_NORESET) {
763                 ulRegRead = read_nic_dword(dev, CPU_GEN);
764                 if (priv->LoopbackMode == RTL819X_NO_LOOPBACK)
765                         ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) |
766                                      CPU_GEN_NO_LOOPBACK_SET);
767                 else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK)
768                         ulRegRead |= CPU_CCK_LOOPBACK;
769                 else
770                         netdev_err(dev, "%s: Invalid loopback mode setting.\n",
771                                    __func__);
772
773                 write_nic_dword(dev, CPU_GEN, ulRegRead);
774
775                 udelay(500);
776         }
777         rtl8192_hwconfig(dev);
778         write_nic_byte(dev, CMDR, CR_RE | CR_TE);
779
780         write_nic_byte(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
781                        (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT)));
782         write_nic_dword(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
783         write_nic_word(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]);
784         write_nic_dword(dev, RCR, priv->ReceiveConfig);
785
786         write_nic_dword(dev, RQPN1,  NUM_OF_PAGE_IN_FW_QUEUE_BK <<
787                         RSVD_FW_QUEUE_PAGE_BK_SHIFT |
788                         NUM_OF_PAGE_IN_FW_QUEUE_BE <<
789                         RSVD_FW_QUEUE_PAGE_BE_SHIFT |
790                         NUM_OF_PAGE_IN_FW_QUEUE_VI <<
791                         RSVD_FW_QUEUE_PAGE_VI_SHIFT |
792                         NUM_OF_PAGE_IN_FW_QUEUE_VO <<
793                         RSVD_FW_QUEUE_PAGE_VO_SHIFT);
794         write_nic_dword(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT <<
795                         RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
796         write_nic_dword(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW |
797                         NUM_OF_PAGE_IN_FW_QUEUE_BCN <<
798                         RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
799                         NUM_OF_PAGE_IN_FW_QUEUE_PUB <<
800                         RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
801
802         rtl8192_tx_enable(dev);
803         rtl8192_rx_enable(dev);
804         ulRegRead = (0xFFF00000 & read_nic_dword(dev, RRSR))  |
805                      RATE_ALL_OFDM_AG | RATE_ALL_CCK;
806         write_nic_dword(dev, RRSR, ulRegRead);
807         write_nic_dword(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
808
809         write_nic_byte(dev, ACK_TIMEOUT, 0x30);
810
811         if (priv->ResetProgress == RESET_TYPE_NORESET)
812                 rtl8192_SetWirelessMode(dev, priv->rtllib->mode);
813         CamResetAllEntry(dev);
814         {
815                 u8 SECR_value = 0x0;
816
817                 SECR_value |= SCR_TxEncEnable;
818                 SECR_value |= SCR_RxDecEnable;
819                 SECR_value |= SCR_NoSKMC;
820                 write_nic_byte(dev, SECR, SECR_value);
821         }
822         write_nic_word(dev, ATIMWND, 2);
823         write_nic_word(dev, BCN_INTERVAL, 100);
824         {
825                 int i;
826
827                 for (i = 0; i < QOS_QUEUE_NUM; i++)
828                         write_nic_dword(dev, WDCAPARA_ADD[i], 0x005e4332);
829         }
830         write_nic_byte(dev, 0xbe, 0xc0);
831
832         rtl8192_phy_configmac(dev);
833
834         if (priv->card_8192_version > (u8) VERSION_8190_BD) {
835                 rtl8192_phy_getTxPower(dev);
836                 rtl8192_phy_setTxPower(dev, priv->chan);
837         }
838
839         tmpvalue = read_nic_byte(dev, IC_VERRSION);
840         priv->IC_Cut = tmpvalue;
841         RT_TRACE(COMP_INIT, "priv->IC_Cut= 0x%x\n", priv->IC_Cut);
842         if (priv->IC_Cut >= IC_VersionCut_D) {
843                 if (priv->IC_Cut == IC_VersionCut_D) {
844                         /* no matter what checkpatch says, braces are needed */
845                         RT_TRACE(COMP_INIT, "D-cut\n");
846                 } else if (priv->IC_Cut == IC_VersionCut_E) {
847                         RT_TRACE(COMP_INIT, "E-cut\n");
848                 }
849         } else {
850                 RT_TRACE(COMP_INIT, "Before C-cut\n");
851         }
852
853         RT_TRACE(COMP_INIT, "Load Firmware!\n");
854         bfirmwareok = init_firmware(dev);
855         if (!bfirmwareok) {
856                 if (retry_times < 10) {
857                         retry_times++;
858                         goto start;
859                 } else {
860                         rtStatus = false;
861                         goto end;
862                 }
863         }
864         RT_TRACE(COMP_INIT, "Load Firmware finished!\n");
865         if (priv->ResetProgress == RESET_TYPE_NORESET) {
866                 RT_TRACE(COMP_INIT, "RF Config Started!\n");
867                 rtStatus = rtl8192_phy_RFConfig(dev);
868                 if (!rtStatus) {
869                         netdev_info(dev, "RF Config failed\n");
870                         return rtStatus;
871                 }
872                 RT_TRACE(COMP_INIT, "RF Config Finished!\n");
873         }
874         rtl8192_phy_updateInitGain(dev);
875
876         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
877         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
878
879         write_nic_byte(dev, 0x87, 0x0);
880
881         if (priv->RegRfOff) {
882                 RT_TRACE((COMP_INIT | COMP_RF | COMP_POWER),
883                           "%s(): Turn off RF for RegRfOff ----------\n",
884                           __func__);
885                 MgntActSet_RF_State(dev, eRfOff, RF_CHANGE_BY_SW, true);
886         } else if (priv->rtllib->RfOffReason > RF_CHANGE_BY_PS) {
887                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
888                          "%s(): Turn off RF for RfOffReason(%d) ----------\n",
889                          __func__, priv->rtllib->RfOffReason);
890                 MgntActSet_RF_State(dev, eRfOff, priv->rtllib->RfOffReason,
891                                     true);
892         } else if (priv->rtllib->RfOffReason >= RF_CHANGE_BY_IPS) {
893                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
894                          "%s(): Turn off RF for RfOffReason(%d) ----------\n",
895                          __func__, priv->rtllib->RfOffReason);
896                 MgntActSet_RF_State(dev, eRfOff, priv->rtllib->RfOffReason,
897                                     true);
898         } else {
899                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): RF-ON\n",
900                           __func__);
901                 priv->rtllib->eRFPowerState = eRfOn;
902                 priv->rtllib->RfOffReason = 0;
903         }
904
905         if (priv->rtllib->FwRWRF)
906                 priv->Rf_Mode = RF_OP_By_FW;
907         else
908                 priv->Rf_Mode = RF_OP_By_SW_3wire;
909
910         if (priv->ResetProgress == RESET_TYPE_NORESET) {
911                 dm_initialize_txpower_tracking(dev);
912
913                 if (priv->IC_Cut >= IC_VersionCut_D) {
914                         tmpRegA = rtl8192_QueryBBReg(dev,
915                                   rOFDM0_XATxIQImbalance, bMaskDWord);
916                         tmpRegC = rtl8192_QueryBBReg(dev,
917                                   rOFDM0_XCTxIQImbalance, bMaskDWord);
918                         for (i = 0; i < TxBBGainTableLength; i++) {
919                                 if (tmpRegA == dm_tx_bb_gain[i]) {
920                                         priv->rfa_txpowertrackingindex = (u8)i;
921                                         priv->rfa_txpowertrackingindex_real =
922                                                  (u8)i;
923                                         priv->rfa_txpowertracking_default =
924                                                  priv->rfa_txpowertrackingindex;
925                                         break;
926                                 }
927                         }
928
929                         TempCCk = rtl8192_QueryBBReg(dev,
930                                   rCCK0_TxFilter1, bMaskByte2);
931
932                         for (i = 0; i < CCKTxBBGainTableLength; i++) {
933                                 if (TempCCk == dm_cck_tx_bb_gain[i][0]) {
934                                         priv->CCKPresentAttentuation_20Mdefault = (u8)i;
935                                         break;
936                                 }
937                         }
938                         priv->CCKPresentAttentuation_40Mdefault = 0;
939                         priv->CCKPresentAttentuation_difference = 0;
940                         priv->CCKPresentAttentuation =
941                                   priv->CCKPresentAttentuation_20Mdefault;
942                         RT_TRACE(COMP_POWER_TRACKING,
943                                  "priv->rfa_txpowertrackingindex_initial = %d\n",
944                                  priv->rfa_txpowertrackingindex);
945                         RT_TRACE(COMP_POWER_TRACKING,
946                                  "priv->rfa_txpowertrackingindex_real__initial = %d\n",
947                                  priv->rfa_txpowertrackingindex_real);
948                         RT_TRACE(COMP_POWER_TRACKING,
949                                  "priv->CCKPresentAttentuation_difference_initial = %d\n",
950                                   priv->CCKPresentAttentuation_difference);
951                         RT_TRACE(COMP_POWER_TRACKING,
952                                  "priv->CCKPresentAttentuation_initial = %d\n",
953                                  priv->CCKPresentAttentuation);
954                         priv->btxpower_tracking = false;
955                 }
956         }
957         rtl8192_irq_enable(dev);
958 end:
959         priv->being_init_adapter = false;
960         return rtStatus;
961 }
962
963 static void rtl8192_net_update(struct net_device *dev)
964 {
965
966         struct r8192_priv *priv = rtllib_priv(dev);
967         struct rtllib_network *net;
968         u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
969         u16 rate_config = 0;
970
971         net = &priv->rtllib->current_network;
972         rtl8192_config_rate(dev, &rate_config);
973         priv->dot11CurrentPreambleMode = PREAMBLE_AUTO;
974          priv->basic_rate = rate_config &= 0x15f;
975         write_nic_dword(dev, BSSIDR, ((u32 *)net->bssid)[0]);
976         write_nic_word(dev, BSSIDR+4, ((u16 *)net->bssid)[2]);
977
978         if (priv->rtllib->iw_mode == IW_MODE_ADHOC) {
979                 write_nic_word(dev, ATIMWND, 2);
980                 write_nic_word(dev, BCN_DMATIME, 256);
981                 write_nic_word(dev, BCN_INTERVAL, net->beacon_interval);
982                 write_nic_word(dev, BCN_DRV_EARLY_INT, 10);
983                 write_nic_byte(dev, BCN_ERR_THRESH, 100);
984
985                 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
986                 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
987
988                 write_nic_word(dev, BCN_TCFG, BcnTimeCfg);
989         }
990 }
991
992 void rtl8192_link_change(struct net_device *dev)
993 {
994         struct r8192_priv *priv = rtllib_priv(dev);
995         struct rtllib_device *ieee = priv->rtllib;
996
997         if (!priv->up)
998                 return;
999
1000         if (ieee->state == RTLLIB_LINKED) {
1001                 rtl8192_net_update(dev);
1002                 priv->ops->update_ratr_table(dev);
1003                 if ((KEY_TYPE_WEP40 == ieee->pairwise_key_type) ||
1004                     (KEY_TYPE_WEP104 == ieee->pairwise_key_type))
1005                         EnableHWSecurityConfig8192(dev);
1006         } else {
1007                 write_nic_byte(dev, 0x173, 0);
1008         }
1009         rtl8192e_update_msr(dev);
1010
1011         if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) {
1012                 u32 reg = 0;
1013
1014                 reg = read_nic_dword(dev, RCR);
1015                 if (priv->rtllib->state == RTLLIB_LINKED) {
1016                         if (ieee->IntelPromiscuousModeInfo.bPromiscuousOn)
1017                                 ;
1018                         else
1019                                 priv->ReceiveConfig = reg |= RCR_CBSSID;
1020                 } else
1021                         priv->ReceiveConfig = reg &= ~RCR_CBSSID;
1022
1023                 write_nic_dword(dev, RCR, reg);
1024         }
1025 }
1026
1027 void rtl8192_AllowAllDestAddr(struct net_device *dev,
1028                               bool bAllowAllDA, bool WriteIntoReg)
1029 {
1030         struct r8192_priv *priv = rtllib_priv(dev);
1031
1032         if (bAllowAllDA)
1033                 priv->ReceiveConfig |= RCR_AAP;
1034         else
1035                 priv->ReceiveConfig &= ~RCR_AAP;
1036
1037         if (WriteIntoReg)
1038                 write_nic_dword(dev, RCR, priv->ReceiveConfig);
1039 }
1040
1041 static u8 MRateToHwRate8190Pci(u8 rate)
1042 {
1043         u8  ret = DESC90_RATE1M;
1044
1045         switch (rate) {
1046         case MGN_1M:
1047                 ret = DESC90_RATE1M;
1048                 break;
1049         case MGN_2M:
1050                 ret = DESC90_RATE2M;
1051                 break;
1052         case MGN_5_5M:
1053                 ret = DESC90_RATE5_5M;
1054                 break;
1055         case MGN_11M:
1056                 ret = DESC90_RATE11M;
1057                 break;
1058         case MGN_6M:
1059                 ret = DESC90_RATE6M;
1060                 break;
1061         case MGN_9M:
1062                 ret = DESC90_RATE9M;
1063                 break;
1064         case MGN_12M:
1065                 ret = DESC90_RATE12M;
1066                 break;
1067         case MGN_18M:
1068                 ret = DESC90_RATE18M;
1069                 break;
1070         case MGN_24M:
1071                 ret = DESC90_RATE24M;
1072                 break;
1073         case MGN_36M:
1074                 ret = DESC90_RATE36M;
1075                 break;
1076         case MGN_48M:
1077                 ret = DESC90_RATE48M;
1078                 break;
1079         case MGN_54M:
1080                 ret = DESC90_RATE54M;
1081                 break;
1082         case MGN_MCS0:
1083                 ret = DESC90_RATEMCS0;
1084                 break;
1085         case MGN_MCS1:
1086                 ret = DESC90_RATEMCS1;
1087                 break;
1088         case MGN_MCS2:
1089                 ret = DESC90_RATEMCS2;
1090                 break;
1091         case MGN_MCS3:
1092                 ret = DESC90_RATEMCS3;
1093                 break;
1094         case MGN_MCS4:
1095                 ret = DESC90_RATEMCS4;
1096                 break;
1097         case MGN_MCS5:
1098                 ret = DESC90_RATEMCS5;
1099                 break;
1100         case MGN_MCS6:
1101                 ret = DESC90_RATEMCS6;
1102                 break;
1103         case MGN_MCS7:
1104                 ret = DESC90_RATEMCS7;
1105                 break;
1106         case MGN_MCS8:
1107                 ret = DESC90_RATEMCS8;
1108                 break;
1109         case MGN_MCS9:
1110                 ret = DESC90_RATEMCS9;
1111                 break;
1112         case MGN_MCS10:
1113                 ret = DESC90_RATEMCS10;
1114                 break;
1115         case MGN_MCS11:
1116                 ret = DESC90_RATEMCS11;
1117                 break;
1118         case MGN_MCS12:
1119                 ret = DESC90_RATEMCS12;
1120                 break;
1121         case MGN_MCS13:
1122                 ret = DESC90_RATEMCS13;
1123                 break;
1124         case MGN_MCS14:
1125                 ret = DESC90_RATEMCS14;
1126                 break;
1127         case MGN_MCS15:
1128                 ret = DESC90_RATEMCS15;
1129                 break;
1130         case (0x80|0x20):
1131                 ret = DESC90_RATEMCS32;
1132                 break;
1133         default:
1134                 break;
1135         }
1136         return ret;
1137 }
1138
1139 static u8 rtl8192_MapHwQueueToFirmwareQueue(struct net_device *dev, u8 QueueID,
1140                                             u8 priority)
1141 {
1142         u8 QueueSelect = 0x0;
1143
1144         switch (QueueID) {
1145         case BE_QUEUE:
1146                 QueueSelect = QSLT_BE;
1147                 break;
1148
1149         case BK_QUEUE:
1150                 QueueSelect = QSLT_BK;
1151                 break;
1152
1153         case VO_QUEUE:
1154                 QueueSelect = QSLT_VO;
1155                 break;
1156
1157         case VI_QUEUE:
1158                 QueueSelect = QSLT_VI;
1159                 break;
1160         case MGNT_QUEUE:
1161                 QueueSelect = QSLT_MGNT;
1162                 break;
1163         case BEACON_QUEUE:
1164                 QueueSelect = QSLT_BEACON;
1165                 break;
1166         case TXCMD_QUEUE:
1167                 QueueSelect = QSLT_CMD;
1168                 break;
1169         case HIGH_QUEUE:
1170                 QueueSelect = QSLT_HIGH;
1171                 break;
1172         default:
1173                 netdev_warn(dev, "%s(): Impossible Queue Selection: %d\n",
1174                             __func__, QueueID);
1175                 break;
1176         }
1177         return QueueSelect;
1178 }
1179
1180 void  rtl8192_tx_fill_desc(struct net_device *dev, struct tx_desc *pdesc,
1181                            struct cb_desc *cb_desc, struct sk_buff *skb)
1182 {
1183         struct r8192_priv *priv = rtllib_priv(dev);
1184         dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1185                          PCI_DMA_TODEVICE);
1186         struct tx_fwinfo_8190pci *pTxFwInfo = NULL;
1187
1188         pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data;
1189         memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci));
1190         pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0;
1191         pTxFwInfo->TxRate = MRateToHwRate8190Pci((u8)cb_desc->data_rate);
1192         pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur;
1193         pTxFwInfo->Short = rtl8192_QueryIsShort(pTxFwInfo->TxHT,
1194                                                 pTxFwInfo->TxRate,
1195                                                 cb_desc);
1196
1197         if (pci_dma_mapping_error(priv->pdev, mapping))
1198                 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1199         if (cb_desc->bAMPDUEnable) {
1200                 pTxFwInfo->AllowAggregation = 1;
1201                 pTxFwInfo->RxMF = cb_desc->ampdu_factor;
1202                 pTxFwInfo->RxAMD = cb_desc->ampdu_density;
1203         } else {
1204                 pTxFwInfo->AllowAggregation = 0;
1205                 pTxFwInfo->RxMF = 0;
1206                 pTxFwInfo->RxAMD = 0;
1207         }
1208
1209         pTxFwInfo->RtsEnable =  (cb_desc->bRTSEnable) ? 1 : 0;
1210         pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0;
1211         pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0;
1212         pTxFwInfo->RtsHT = (cb_desc->rts_rate&0x80) ? 1 : 0;
1213         pTxFwInfo->RtsRate = MRateToHwRate8190Pci((u8)cb_desc->rts_rate);
1214         pTxFwInfo->RtsBandwidth = 0;
1215         pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC;
1216         pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ?
1217                           (cb_desc->bRTSUseShortPreamble ? 1 : 0) :
1218                           (cb_desc->bRTSUseShortGI ? 1 : 0);
1219         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
1220                 if (cb_desc->bPacketBW) {
1221                         pTxFwInfo->TxBandwidth = 1;
1222                         pTxFwInfo->TxSubCarrier = 0;
1223                 } else {
1224                         pTxFwInfo->TxBandwidth = 0;
1225                         pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
1226                 }
1227         } else {
1228                 pTxFwInfo->TxBandwidth = 0;
1229                 pTxFwInfo->TxSubCarrier = 0;
1230         }
1231
1232         memset((u8 *)pdesc, 0, 12);
1233         pdesc->LINIP = 0;
1234         pdesc->CmdInit = 1;
1235         pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1236         pdesc->PktSize = (u16)skb->len-sizeof(struct tx_fwinfo_8190pci);
1237
1238         pdesc->SecCAMID = 0;
1239         pdesc->RATid = cb_desc->RATRIndex;
1240
1241
1242         pdesc->NoEnc = 1;
1243         pdesc->SecType = 0x0;
1244         if (cb_desc->bHwSec) {
1245                 static u8 tmp;
1246
1247                 if (!tmp) {
1248                         RT_TRACE(COMP_DBG, "==>================hw sec\n");
1249                         tmp = 1;
1250                 }
1251                 switch (priv->rtllib->pairwise_key_type) {
1252                 case KEY_TYPE_WEP40:
1253                 case KEY_TYPE_WEP104:
1254                         pdesc->SecType = 0x1;
1255                         pdesc->NoEnc = 0;
1256                         break;
1257                 case KEY_TYPE_TKIP:
1258                         pdesc->SecType = 0x2;
1259                         pdesc->NoEnc = 0;
1260                         break;
1261                 case KEY_TYPE_CCMP:
1262                         pdesc->SecType = 0x3;
1263                         pdesc->NoEnc = 0;
1264                         break;
1265                 case KEY_TYPE_NA:
1266                         pdesc->SecType = 0x0;
1267                         pdesc->NoEnc = 1;
1268                         break;
1269                 }
1270         }
1271
1272         pdesc->PktId = 0x0;
1273
1274         pdesc->QueueSelect = rtl8192_MapHwQueueToFirmwareQueue(dev,
1275                                                 cb_desc->queue_index,
1276                                                 cb_desc->priority);
1277         pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci);
1278
1279         pdesc->DISFB = cb_desc->bTxDisableRateFallBack;
1280         pdesc->USERATE = cb_desc->bTxUseDriverAssingedRate;
1281
1282         pdesc->FirstSeg = 1;
1283         pdesc->LastSeg = 1;
1284         pdesc->TxBufferSize = skb->len;
1285
1286         pdesc->TxBuffAddr = mapping;
1287 }
1288
1289 void  rtl8192_tx_fill_cmd_desc(struct net_device *dev,
1290                                struct tx_desc_cmd *entry,
1291                                struct cb_desc *cb_desc, struct sk_buff *skb)
1292 {
1293         struct r8192_priv *priv = rtllib_priv(dev);
1294         dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1295                          PCI_DMA_TODEVICE);
1296
1297         if (pci_dma_mapping_error(priv->pdev, mapping))
1298                 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1299         memset(entry, 0, 12);
1300         entry->LINIP = cb_desc->bLastIniPkt;
1301         entry->FirstSeg = 1;
1302         entry->LastSeg = 1;
1303         if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) {
1304                 entry->CmdInit = DESC_PACKET_TYPE_INIT;
1305         } else {
1306                 struct tx_desc *entry_tmp = (struct tx_desc *)entry;
1307
1308                 entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL;
1309                 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1310                 entry_tmp->PktSize = (u16)(cb_desc->pkt_size +
1311                                       entry_tmp->Offset);
1312                 entry_tmp->QueueSelect = QSLT_CMD;
1313                 entry_tmp->TxFWInfoSize = 0x08;
1314                 entry_tmp->RATid = (u8)DESC_PACKET_TYPE_INIT;
1315         }
1316         entry->TxBufferSize = skb->len;
1317         entry->TxBuffAddr = mapping;
1318         entry->OWN = 1;
1319 }
1320
1321 static u8 HwRateToMRate90(bool bIsHT, u8 rate)
1322 {
1323         u8  ret_rate = 0x02;
1324
1325         if (!bIsHT) {
1326                 switch (rate) {
1327                 case DESC90_RATE1M:
1328                         ret_rate = MGN_1M;
1329                         break;
1330                 case DESC90_RATE2M:
1331                         ret_rate = MGN_2M;
1332                         break;
1333                 case DESC90_RATE5_5M:
1334                         ret_rate = MGN_5_5M;
1335                         break;
1336                 case DESC90_RATE11M:
1337                         ret_rate = MGN_11M;
1338                         break;
1339                 case DESC90_RATE6M:
1340                         ret_rate = MGN_6M;
1341                         break;
1342                 case DESC90_RATE9M:
1343                         ret_rate = MGN_9M;
1344                         break;
1345                 case DESC90_RATE12M:
1346                         ret_rate = MGN_12M;
1347                         break;
1348                 case DESC90_RATE18M:
1349                         ret_rate = MGN_18M;
1350                         break;
1351                 case DESC90_RATE24M:
1352                         ret_rate = MGN_24M;
1353                         break;
1354                 case DESC90_RATE36M:
1355                         ret_rate = MGN_36M;
1356                         break;
1357                 case DESC90_RATE48M:
1358                         ret_rate = MGN_48M;
1359                         break;
1360                 case DESC90_RATE54M:
1361                         ret_rate = MGN_54M;
1362                         break;
1363
1364                 default:
1365                         RT_TRACE(COMP_RECV,
1366                                  "HwRateToMRate90(): Non supportedRate [%x], bIsHT = %d!!!\n",
1367                                  rate, bIsHT);
1368                         break;
1369                 }
1370
1371         } else {
1372                 switch (rate) {
1373                 case DESC90_RATEMCS0:
1374                         ret_rate = MGN_MCS0;
1375                         break;
1376                 case DESC90_RATEMCS1:
1377                         ret_rate = MGN_MCS1;
1378                         break;
1379                 case DESC90_RATEMCS2:
1380                         ret_rate = MGN_MCS2;
1381                         break;
1382                 case DESC90_RATEMCS3:
1383                         ret_rate = MGN_MCS3;
1384                         break;
1385                 case DESC90_RATEMCS4:
1386                         ret_rate = MGN_MCS4;
1387                         break;
1388                 case DESC90_RATEMCS5:
1389                         ret_rate = MGN_MCS5;
1390                         break;
1391                 case DESC90_RATEMCS6:
1392                         ret_rate = MGN_MCS6;
1393                         break;
1394                 case DESC90_RATEMCS7:
1395                         ret_rate = MGN_MCS7;
1396                         break;
1397                 case DESC90_RATEMCS8:
1398                         ret_rate = MGN_MCS8;
1399                         break;
1400                 case DESC90_RATEMCS9:
1401                         ret_rate = MGN_MCS9;
1402                         break;
1403                 case DESC90_RATEMCS10:
1404                         ret_rate = MGN_MCS10;
1405                         break;
1406                 case DESC90_RATEMCS11:
1407                         ret_rate = MGN_MCS11;
1408                         break;
1409                 case DESC90_RATEMCS12:
1410                         ret_rate = MGN_MCS12;
1411                         break;
1412                 case DESC90_RATEMCS13:
1413                         ret_rate = MGN_MCS13;
1414                         break;
1415                 case DESC90_RATEMCS14:
1416                         ret_rate = MGN_MCS14;
1417                         break;
1418                 case DESC90_RATEMCS15:
1419                         ret_rate = MGN_MCS15;
1420                         break;
1421                 case DESC90_RATEMCS32:
1422                         ret_rate = (0x80|0x20);
1423                         break;
1424
1425                 default:
1426                         RT_TRACE(COMP_RECV,
1427                                  "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n",
1428                                  rate, bIsHT);
1429                         break;
1430                 }
1431         }
1432
1433         return ret_rate;
1434 }
1435
1436 static long rtl8192_signal_scale_mapping(struct r8192_priv *priv, long currsig)
1437 {
1438         long retsig;
1439
1440         if (currsig >= 61 && currsig <= 100)
1441                 retsig = 90 + ((currsig - 60) / 4);
1442         else if (currsig >= 41 && currsig <= 60)
1443                 retsig = 78 + ((currsig - 40) / 2);
1444         else if (currsig >= 31 && currsig <= 40)
1445                 retsig = 66 + (currsig - 30);
1446         else if (currsig >= 21 && currsig <= 30)
1447                 retsig = 54 + (currsig - 20);
1448         else if (currsig >= 5 && currsig <= 20)
1449                 retsig = 42 + (((currsig - 5) * 2) / 3);
1450         else if (currsig == 4)
1451                 retsig = 36;
1452         else if (currsig == 3)
1453                 retsig = 27;
1454         else if (currsig == 2)
1455                 retsig = 18;
1456         else if (currsig == 1)
1457                 retsig = 9;
1458         else
1459                 retsig = currsig;
1460
1461         return retsig;
1462 }
1463
1464
1465 #define  rx_hal_is_cck_rate(_pdrvinfo)\
1466                         ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
1467                         _pdrvinfo->RxRate == DESC90_RATE2M ||\
1468                         _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
1469                         _pdrvinfo->RxRate == DESC90_RATE11M) &&\
1470                         !_pdrvinfo->RxHT)
1471
1472 static void rtl8192_query_rxphystatus(
1473         struct r8192_priv *priv,
1474         struct rtllib_rx_stats *pstats,
1475         struct rx_desc  *pdesc,
1476         struct rx_fwinfo   *pdrvinfo,
1477         struct rtllib_rx_stats *precord_stats,
1478         bool bpacket_match_bssid,
1479         bool bpacket_toself,
1480         bool bPacketBeacon,
1481         bool bToSelfBA
1482         )
1483 {
1484         struct phy_sts_ofdm_819xpci *pofdm_buf;
1485         struct phy_sts_cck_819xpci *pcck_buf;
1486         struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *prxsc;
1487         u8 *prxpkt;
1488         u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
1489         char rx_pwr[4], rx_pwr_all = 0;
1490         char rx_snrX, rx_evmX;
1491         u8 evm, pwdb_all;
1492         u32 RSSI, total_rssi = 0;
1493         u8 is_cck_rate = 0;
1494         u8 rf_rx_num = 0;
1495         static  u8 check_reg824;
1496         static  u32 reg824_bit9;
1497
1498         priv->stats.numqry_phystatus++;
1499
1500         is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
1501         memset(precord_stats, 0, sizeof(struct rtllib_rx_stats));
1502         pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID =
1503                                     bpacket_match_bssid;
1504         pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
1505         pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;
1506         pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
1507         pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
1508         if (check_reg824 == 0) {
1509                 reg824_bit9 = rtl8192_QueryBBReg(priv->rtllib->dev,
1510                               rFPGA0_XA_HSSIParameter2, 0x200);
1511                 check_reg824 = 1;
1512         }
1513
1514
1515         prxpkt = (u8 *)pdrvinfo;
1516
1517         prxpkt += sizeof(struct rx_fwinfo);
1518
1519         pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt;
1520         pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt;
1521
1522         pstats->RxMIMOSignalQuality[0] = -1;
1523         pstats->RxMIMOSignalQuality[1] = -1;
1524         precord_stats->RxMIMOSignalQuality[0] = -1;
1525         precord_stats->RxMIMOSignalQuality[1] = -1;
1526
1527         if (is_cck_rate) {
1528                 u8 report;
1529
1530                 priv->stats.numqry_phystatusCCK++;
1531                 if (!reg824_bit9) {
1532                         report = pcck_buf->cck_agc_rpt & 0xc0;
1533                         report >>= 6;
1534                         switch (report) {
1535                         case 0x3:
1536                                 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt &
1537                                              0x3e);
1538                                 break;
1539                         case 0x2:
1540                                 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt &
1541                                              0x3e);
1542                                 break;
1543                         case 0x1:
1544                                 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt &
1545                                              0x3e);
1546                                 break;
1547                         case 0x0:
1548                                 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);
1549                                 break;
1550                         }
1551                 } else {
1552                         report = pcck_buf->cck_agc_rpt & 0x60;
1553                         report >>= 5;
1554                         switch (report) {
1555                         case 0x3:
1556                                 rx_pwr_all = -35 -
1557                                         ((pcck_buf->cck_agc_rpt &
1558                                         0x1f) << 1);
1559                                 break;
1560                         case 0x2:
1561                                 rx_pwr_all = -23 -
1562                                         ((pcck_buf->cck_agc_rpt &
1563                                          0x1f) << 1);
1564                                 break;
1565                         case 0x1:
1566                                 rx_pwr_all = -11 -
1567                                          ((pcck_buf->cck_agc_rpt &
1568                                          0x1f) << 1);
1569                                 break;
1570                         case 0x0:
1571                                 rx_pwr_all = -8 -
1572                                          ((pcck_buf->cck_agc_rpt &
1573                                          0x1f) << 1);
1574                                 break;
1575                         }
1576                 }
1577
1578                 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
1579                 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1580                 pstats->RecvSignalPower = rx_pwr_all;
1581
1582                 if (bpacket_match_bssid) {
1583                         u8      sq;
1584
1585                         if (pstats->RxPWDBAll > 40) {
1586                                 sq = 100;
1587                         } else {
1588                                 sq = pcck_buf->sq_rpt;
1589
1590                                 if (pcck_buf->sq_rpt > 64)
1591                                         sq = 0;
1592                                 else if (pcck_buf->sq_rpt < 20)
1593                                         sq = 100;
1594                                 else
1595                                         sq = ((64-sq) * 100) / 44;
1596                         }
1597                         pstats->SignalQuality = sq;
1598                         precord_stats->SignalQuality = sq;
1599                         pstats->RxMIMOSignalQuality[0] = sq;
1600                         precord_stats->RxMIMOSignalQuality[0] = sq;
1601                         pstats->RxMIMOSignalQuality[1] = -1;
1602                         precord_stats->RxMIMOSignalQuality[1] = -1;
1603                 }
1604         } else {
1605                 priv->stats.numqry_phystatusHT++;
1606                 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
1607                         if (priv->brfpath_rxenable[i])
1608                                 rf_rx_num++;
1609
1610                         rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) *
1611                                      2) - 110;
1612
1613                         tmp_rxsnr = pofdm_buf->rxsnr_X[i];
1614                         rx_snrX = (char)(tmp_rxsnr);
1615                         rx_snrX /= 2;
1616                         priv->stats.rxSNRdB[i] = (long)rx_snrX;
1617
1618                         RSSI = rtl819x_query_rxpwrpercentage(rx_pwr[i]);
1619                         if (priv->brfpath_rxenable[i])
1620                                 total_rssi += RSSI;
1621
1622                         if (bpacket_match_bssid) {
1623                                 pstats->RxMIMOSignalStrength[i] = (u8) RSSI;
1624                                 precord_stats->RxMIMOSignalStrength[i] =
1625                                                                 (u8) RSSI;
1626                         }
1627                 }
1628
1629
1630                 rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106;
1631                 pwdb_all = rtl819x_query_rxpwrpercentage(rx_pwr_all);
1632
1633                 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1634                 pstats->RxPower = precord_stats->RxPower =      rx_pwr_all;
1635                 pstats->RecvSignalPower = rx_pwr_all;
1636                 if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 &&
1637                     pdrvinfo->RxRate <= DESC90_RATEMCS15)
1638                         max_spatial_stream = 2;
1639                 else
1640                         max_spatial_stream = 1;
1641
1642                 for (i = 0; i < max_spatial_stream; i++) {
1643                         tmp_rxevm = pofdm_buf->rxevm_X[i];
1644                         rx_evmX = (char)(tmp_rxevm);
1645
1646                         rx_evmX /= 2;
1647
1648                         evm = rtl819x_evm_dbtopercentage(rx_evmX);
1649                         if (bpacket_match_bssid) {
1650                                 if (i == 0) {
1651                                         pstats->SignalQuality = (u8)(evm &
1652                                                                  0xff);
1653                                         precord_stats->SignalQuality = (u8)(evm
1654                                                                         & 0xff);
1655                                 }
1656                                 pstats->RxMIMOSignalQuality[i] = (u8)(evm &
1657                                                                  0xff);
1658                                 precord_stats->RxMIMOSignalQuality[i] = (u8)(evm
1659                                                                         & 0xff);
1660                         }
1661                 }
1662
1663
1664                 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
1665                 prxsc = (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *)
1666                         &rxsc_sgien_exflg;
1667                 if (pdrvinfo->BW)
1668                         priv->stats.received_bwtype[1+prxsc->rxsc]++;
1669                 else
1670                         priv->stats.received_bwtype[0]++;
1671         }
1672
1673         if (is_cck_rate) {
1674                 pstats->SignalStrength = precord_stats->SignalStrength =
1675                                          (u8)(rtl8192_signal_scale_mapping(priv,
1676                                          (long)pwdb_all));
1677
1678         } else {
1679                 if (rf_rx_num != 0)
1680                         pstats->SignalStrength = precord_stats->SignalStrength =
1681                                          (u8)(rtl8192_signal_scale_mapping(priv,
1682                                          (long)(total_rssi /= rf_rx_num)));
1683         }
1684 }
1685
1686 static void rtl8192_process_phyinfo(struct r8192_priv *priv, u8 *buffer,
1687                                     struct rtllib_rx_stats *prev_st,
1688                                     struct rtllib_rx_stats *curr_st)
1689 {
1690         bool bcheck = false;
1691         u8      rfpath;
1692         u32 ij, tmp_val;
1693         static u32 slide_rssi_index, slide_rssi_statistics;
1694         static u32 slide_evm_index, slide_evm_statistics;
1695         static u32 last_rssi, last_evm;
1696         static u32 slide_beacon_adc_pwdb_index;
1697         static u32 slide_beacon_adc_pwdb_statistics;
1698         static u32 last_beacon_adc_pwdb;
1699         struct rtllib_hdr_3addr *hdr;
1700         u16 sc;
1701         unsigned int frag, seq;
1702
1703         hdr = (struct rtllib_hdr_3addr *)buffer;
1704         sc = le16_to_cpu(hdr->seq_ctl);
1705         frag = WLAN_GET_SEQ_FRAG(sc);
1706         seq = WLAN_GET_SEQ_SEQ(sc);
1707         curr_st->Seq_Num = seq;
1708         if (!prev_st->bIsAMPDU)
1709                 bcheck = true;
1710
1711         if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1712                 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
1713                 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
1714                 priv->stats.slide_rssi_total -= last_rssi;
1715         }
1716         priv->stats.slide_rssi_total += prev_st->SignalStrength;
1717
1718         priv->stats.slide_signal_strength[slide_rssi_index++] =
1719                                          prev_st->SignalStrength;
1720         if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
1721                 slide_rssi_index = 0;
1722
1723         tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
1724         priv->stats.signal_strength = rtl819x_translate_todbm(priv,
1725                                       (u8)tmp_val);
1726         curr_st->rssi = priv->stats.signal_strength;
1727         if (!prev_st->bPacketMatchBSSID) {
1728                 if (!prev_st->bToSelfBA)
1729                         return;
1730         }
1731
1732         if (!bcheck)
1733                 return;
1734
1735         rtl819x_process_cck_rxpathsel(priv, prev_st);
1736
1737         priv->stats.num_process_phyinfo++;
1738         if (!prev_st->bIsCCK && prev_st->bPacketToSelf) {
1739                 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) {
1740                         if (!rtl8192_phy_CheckIsLegalRFPath(priv->rtllib->dev,
1741                             rfpath))
1742                                 continue;
1743                         RT_TRACE(COMP_DBG,
1744                                  "Jacken -> pPreviousstats->RxMIMOSignalStrength[rfpath]  = %d\n",
1745                                  prev_st->RxMIMOSignalStrength[rfpath]);
1746                         if (priv->stats.rx_rssi_percentage[rfpath] == 0) {
1747                                 priv->stats.rx_rssi_percentage[rfpath] =
1748                                          prev_st->RxMIMOSignalStrength[rfpath];
1749                         }
1750                         if (prev_st->RxMIMOSignalStrength[rfpath]  >
1751                             priv->stats.rx_rssi_percentage[rfpath]) {
1752                                 priv->stats.rx_rssi_percentage[rfpath] =
1753                                         ((priv->stats.rx_rssi_percentage[rfpath]
1754                                         * (RX_SMOOTH - 1)) +
1755                                         (prev_st->RxMIMOSignalStrength
1756                                         [rfpath])) / (RX_SMOOTH);
1757                                 priv->stats.rx_rssi_percentage[rfpath] =
1758                                          priv->stats.rx_rssi_percentage[rfpath]
1759                                          + 1;
1760                         } else {
1761                                 priv->stats.rx_rssi_percentage[rfpath] =
1762                                    ((priv->stats.rx_rssi_percentage[rfpath] *
1763                                    (RX_SMOOTH-1)) +
1764                                    (prev_st->RxMIMOSignalStrength[rfpath])) /
1765                                    (RX_SMOOTH);
1766                         }
1767                         RT_TRACE(COMP_DBG,
1768                                  "Jacken -> priv->RxStats.RxRSSIPercentage[rfPath]  = %d\n",
1769                                  priv->stats.rx_rssi_percentage[rfpath]);
1770                 }
1771         }
1772
1773
1774         if (prev_st->bPacketBeacon) {
1775                 if (slide_beacon_adc_pwdb_statistics++ >=
1776                     PHY_Beacon_RSSI_SLID_WIN_MAX) {
1777                         slide_beacon_adc_pwdb_statistics =
1778                                          PHY_Beacon_RSSI_SLID_WIN_MAX;
1779                         last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb
1780                                                [slide_beacon_adc_pwdb_index];
1781                         priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
1782                 }
1783                 priv->stats.Slide_Beacon_Total += prev_st->RxPWDBAll;
1784                 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] =
1785                                                          prev_st->RxPWDBAll;
1786                 slide_beacon_adc_pwdb_index++;
1787                 if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
1788                         slide_beacon_adc_pwdb_index = 0;
1789                 prev_st->RxPWDBAll = priv->stats.Slide_Beacon_Total /
1790                                      slide_beacon_adc_pwdb_statistics;
1791                 if (prev_st->RxPWDBAll >= 3)
1792                         prev_st->RxPWDBAll -= 3;
1793         }
1794
1795         RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
1796                                 prev_st->bIsCCK ? "CCK" : "OFDM",
1797                                 prev_st->RxPWDBAll);
1798
1799         if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1800             prev_st->bToSelfBA) {
1801                 if (priv->undecorated_smoothed_pwdb < 0)
1802                         priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll;
1803                 if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) {
1804                         priv->undecorated_smoothed_pwdb =
1805                                         (((priv->undecorated_smoothed_pwdb) *
1806                                         (RX_SMOOTH-1)) +
1807                                         (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1808                         priv->undecorated_smoothed_pwdb =
1809                                          priv->undecorated_smoothed_pwdb + 1;
1810                 } else {
1811                         priv->undecorated_smoothed_pwdb =
1812                                         (((priv->undecorated_smoothed_pwdb) *
1813                                         (RX_SMOOTH-1)) +
1814                                         (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1815                 }
1816                 rtl819x_update_rxsignalstatistics8190pci(priv, prev_st);
1817         }
1818
1819         if (prev_st->SignalQuality != 0) {
1820                 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1821                     prev_st->bToSelfBA) {
1822                         if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1823                                 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
1824                                 last_evm =
1825                                          priv->stats.slide_evm[slide_evm_index];
1826                                 priv->stats.slide_evm_total -= last_evm;
1827                         }
1828
1829                         priv->stats.slide_evm_total += prev_st->SignalQuality;
1830
1831                         priv->stats.slide_evm[slide_evm_index++] =
1832                                                  prev_st->SignalQuality;
1833                         if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
1834                                 slide_evm_index = 0;
1835
1836                         tmp_val = priv->stats.slide_evm_total /
1837                                   slide_evm_statistics;
1838                         priv->stats.signal_quality = tmp_val;
1839                         priv->stats.last_signal_strength_inpercent = tmp_val;
1840                 }
1841
1842                 if (prev_st->bPacketToSelf ||
1843                     prev_st->bPacketBeacon ||
1844                     prev_st->bToSelfBA) {
1845                         for (ij = 0; ij < 2; ij++) {
1846                                 if (prev_st->RxMIMOSignalQuality[ij] != -1) {
1847                                         if (priv->stats.rx_evm_percentage[ij] == 0)
1848                                                 priv->stats.rx_evm_percentage[ij] =
1849                                                    prev_st->RxMIMOSignalQuality[ij];
1850                                         priv->stats.rx_evm_percentage[ij] =
1851                                           ((priv->stats.rx_evm_percentage[ij] *
1852                                           (RX_SMOOTH - 1)) +
1853                                           (prev_st->RxMIMOSignalQuality[ij])) /
1854                                           (RX_SMOOTH);
1855                                 }
1856                         }
1857                 }
1858         }
1859 }
1860
1861 static void rtl8192_TranslateRxSignalStuff(struct net_device *dev,
1862                                            struct sk_buff *skb,
1863                                            struct rtllib_rx_stats *pstats,
1864                                            struct rx_desc *pdesc,
1865                                            struct rx_fwinfo *pdrvinfo)
1866 {
1867         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1868         bool bpacket_match_bssid, bpacket_toself;
1869         bool bPacketBeacon = false;
1870         struct rtllib_hdr_3addr *hdr;
1871         bool bToSelfBA = false;
1872         static struct rtllib_rx_stats  previous_stats;
1873         u16 fc, type;
1874         u8 *tmp_buf;
1875         u8 *praddr;
1876
1877         tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift;
1878
1879         hdr = (struct rtllib_hdr_3addr *)tmp_buf;
1880         fc = le16_to_cpu(hdr->frame_ctl);
1881         type = WLAN_FC_GET_TYPE(fc);
1882         praddr = hdr->addr1;
1883
1884         bpacket_match_bssid =
1885                 ((RTLLIB_FTYPE_CTL != type) &&
1886                  ether_addr_equal(priv->rtllib->current_network.bssid,
1887                                   (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 :
1888                                   (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 :
1889                                   hdr->addr3) &&
1890                  (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV));
1891         bpacket_toself = bpacket_match_bssid &&         /* check this */
1892                          ether_addr_equal(praddr, priv->rtllib->dev->dev_addr);
1893         if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON)
1894                 bPacketBeacon = true;
1895         if (bpacket_match_bssid)
1896                 priv->stats.numpacket_matchbssid++;
1897         if (bpacket_toself)
1898                 priv->stats.numpacket_toself++;
1899         rtl8192_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
1900         rtl8192_query_rxphystatus(priv, pstats, pdesc, pdrvinfo,
1901                                   &previous_stats, bpacket_match_bssid,
1902                                   bpacket_toself, bPacketBeacon, bToSelfBA);
1903         rtl8192_record_rxdesc_forlateruse(pstats, &previous_stats);
1904 }
1905
1906 static void rtl8192_UpdateReceivedRateHistogramStatistics(
1907                                            struct net_device *dev,
1908                                            struct rtllib_rx_stats *pstats)
1909 {
1910         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1911         u32 rcvType = 1;
1912         u32 rateIndex;
1913         u32 preamble_guardinterval;
1914
1915         if (pstats->bCRC)
1916                 rcvType = 2;
1917         else if (pstats->bICV)
1918                 rcvType = 3;
1919
1920         if (pstats->bShortPreamble)
1921                 preamble_guardinterval = 1;
1922         else
1923                 preamble_guardinterval = 0;
1924
1925         switch (pstats->rate) {
1926         case MGN_1M:
1927                 rateIndex = 0;
1928                 break;
1929         case MGN_2M:
1930                 rateIndex = 1;
1931                  break;
1932         case MGN_5_5M:
1933                 rateIndex = 2;
1934                 break;
1935         case MGN_11M:
1936                 rateIndex = 3;
1937                 break;
1938         case MGN_6M:
1939                 rateIndex = 4;
1940                 break;
1941         case MGN_9M:
1942                 rateIndex = 5;
1943                 break;
1944         case MGN_12M:
1945                 rateIndex = 6;
1946                 break;
1947         case MGN_18M:
1948                 rateIndex = 7;
1949                  break;
1950         case MGN_24M:
1951                 rateIndex = 8;
1952                 break;
1953         case MGN_36M:
1954                 rateIndex = 9;
1955                 break;
1956         case MGN_48M:
1957                 rateIndex = 10;
1958                 break;
1959         case MGN_54M:
1960                 rateIndex = 11;
1961                 break;
1962         case MGN_MCS0:
1963                 rateIndex = 12;
1964                 break;
1965         case MGN_MCS1:
1966                 rateIndex = 13;
1967                 break;
1968         case MGN_MCS2:
1969                 rateIndex = 14;
1970                 break;
1971         case MGN_MCS3:
1972                 rateIndex = 15;
1973                 break;
1974         case MGN_MCS4:
1975                 rateIndex = 16;
1976                 break;
1977         case MGN_MCS5:
1978                 rateIndex = 17;
1979                 break;
1980         case MGN_MCS6:
1981                 rateIndex = 18;
1982                 break;
1983         case MGN_MCS7:
1984                 rateIndex = 19;
1985                 break;
1986         case MGN_MCS8:
1987                 rateIndex = 20;
1988                 break;
1989         case MGN_MCS9:
1990                 rateIndex = 21;
1991                 break;
1992         case MGN_MCS10:
1993                 rateIndex = 22;
1994                 break;
1995         case MGN_MCS11:
1996                 rateIndex = 23;
1997                 break;
1998         case MGN_MCS12:
1999                 rateIndex = 24;
2000                 break;
2001         case MGN_MCS13:
2002                 rateIndex = 25;
2003                 break;
2004         case MGN_MCS14:
2005                 rateIndex = 26;
2006                 break;
2007         case MGN_MCS15:
2008                 rateIndex = 27;
2009                 break;
2010         default:
2011                 rateIndex = 28;
2012                 break;
2013         }
2014         priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++;
2015         priv->stats.received_rate_histogram[0][rateIndex]++;
2016         priv->stats.received_rate_histogram[rcvType][rateIndex]++;
2017 }
2018
2019 bool rtl8192_rx_query_status_desc(struct net_device *dev,
2020                                   struct rtllib_rx_stats *stats,
2021                                   struct rx_desc *pdesc,
2022                                   struct sk_buff *skb)
2023 {
2024         struct r8192_priv *priv = rtllib_priv(dev);
2025         struct rx_fwinfo *pDrvInfo = NULL;
2026
2027         stats->bICV = pdesc->ICV;
2028         stats->bCRC = pdesc->CRC32;
2029         stats->bHwError = pdesc->CRC32 | pdesc->ICV;
2030
2031         stats->Length = pdesc->Length;
2032         if (stats->Length < 24)
2033                 stats->bHwError |= 1;
2034
2035         if (stats->bHwError) {
2036                 stats->bShift = false;
2037
2038                 if (pdesc->CRC32) {
2039                         if (pdesc->Length < 500)
2040                                 priv->stats.rxcrcerrmin++;
2041                         else if (pdesc->Length > 1000)
2042                                 priv->stats.rxcrcerrmax++;
2043                         else
2044                                 priv->stats.rxcrcerrmid++;
2045                 }
2046                 return false;
2047         }
2048
2049         stats->RxDrvInfoSize = pdesc->RxDrvInfoSize;
2050         stats->RxBufShift = ((pdesc->Shift)&0x03);
2051         stats->Decrypted = !pdesc->SWDec;
2052
2053         pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift);
2054
2055         stats->rate = HwRateToMRate90((bool)pDrvInfo->RxHT,
2056                                      (u8)pDrvInfo->RxRate);
2057         stats->bShortPreamble = pDrvInfo->SPLCP;
2058
2059         rtl8192_UpdateReceivedRateHistogramStatistics(dev, stats);
2060
2061         stats->bIsAMPDU = (pDrvInfo->PartAggr == 1);
2062         stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) &&
2063                             (pDrvInfo->FirstAGGR == 1);
2064
2065         stats->TimeStampLow = pDrvInfo->TSFL;
2066         stats->TimeStampHigh = read_nic_dword(dev, TSFR+4);
2067
2068         rtl819x_UpdateRxPktTimeStamp(dev, stats);
2069
2070         if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
2071                 stats->bShift = 1;
2072
2073         stats->RxIs40MHzPacket = pDrvInfo->BW;
2074
2075         rtl8192_TranslateRxSignalStuff(dev, skb, stats, pdesc,
2076                                        pDrvInfo);
2077
2078         if (pDrvInfo->FirstAGGR == 1 || pDrvInfo->PartAggr == 1)
2079                 RT_TRACE(COMP_RXDESC,
2080                          "pDrvInfo->FirstAGGR = %d, pDrvInfo->PartAggr = %d\n",
2081                          pDrvInfo->FirstAGGR, pDrvInfo->PartAggr);
2082         skb_trim(skb, skb->len - 4/*sCrcLng*/);
2083
2084
2085         stats->packetlength = stats->Length-4;
2086         stats->fraglength = stats->packetlength;
2087         stats->fragoffset = 0;
2088         stats->ntotalfrag = 1;
2089         return true;
2090 }
2091
2092 void rtl8192_halt_adapter(struct net_device *dev, bool reset)
2093 {
2094         struct r8192_priv *priv = rtllib_priv(dev);
2095         int i;
2096         u8      OpMode;
2097         u8      u1bTmp;
2098         u32     ulRegRead;
2099
2100         OpMode = RT_OP_MODE_NO_LINK;
2101         priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode);
2102
2103         if (!priv->rtllib->bSupportRemoteWakeUp) {
2104                 u1bTmp = 0x0;
2105                 write_nic_byte(dev, CMDR, u1bTmp);
2106         }
2107
2108         mdelay(20);
2109
2110         if (!reset) {
2111                 mdelay(150);
2112
2113                 priv->bHwRfOffAction = 2;
2114
2115                 if (!priv->rtllib->bSupportRemoteWakeUp) {
2116                         PHY_SetRtl8192eRfOff(dev);
2117                         ulRegRead = read_nic_dword(dev, CPU_GEN);
2118                         ulRegRead |= CPU_GEN_SYSTEM_RESET;
2119                         write_nic_dword(dev, CPU_GEN, ulRegRead);
2120                 } else {
2121                         write_nic_dword(dev, WFCRC0, 0xffffffff);
2122                         write_nic_dword(dev, WFCRC1, 0xffffffff);
2123                         write_nic_dword(dev, WFCRC2, 0xffffffff);
2124
2125
2126                         write_nic_byte(dev, PMR, 0x5);
2127                         write_nic_byte(dev, MacBlkCtrl, 0xa);
2128                 }
2129         }
2130
2131         for (i = 0; i < MAX_QUEUE_SIZE; i++)
2132                 skb_queue_purge(&priv->rtllib->skb_waitQ[i]);
2133         for (i = 0; i < MAX_QUEUE_SIZE; i++)
2134                 skb_queue_purge(&priv->rtllib->skb_aggQ[i]);
2135
2136         skb_queue_purge(&priv->skb_queue);
2137 }
2138
2139 void rtl8192_update_ratr_table(struct net_device *dev)
2140 {
2141         struct r8192_priv *priv = rtllib_priv(dev);
2142         struct rtllib_device *ieee = priv->rtllib;
2143         u8 *pMcsRate = ieee->dot11HTOperationalRateSet;
2144         u32 ratr_value = 0;
2145         u16 rate_config = 0;
2146         u8 rate_index = 0;
2147
2148         rtl8192_config_rate(dev, &rate_config);
2149         ratr_value = rate_config | *pMcsRate << 12;
2150         switch (ieee->mode) {
2151         case IEEE_A:
2152                 ratr_value &= 0x00000FF0;
2153                 break;
2154         case IEEE_B:
2155                 ratr_value &= 0x0000000F;
2156                 break;
2157         case IEEE_G:
2158         case IEEE_G|IEEE_B:
2159                 ratr_value &= 0x00000FF7;
2160                 break;
2161         case IEEE_N_24G:
2162         case IEEE_N_5G:
2163                 if (ieee->pHTInfo->PeerMimoPs == 0) {
2164                         ratr_value &= 0x0007F007;
2165                 } else {
2166                         if (priv->rf_type == RF_1T2R)
2167                                 ratr_value &= 0x000FF007;
2168                         else
2169                                 ratr_value &= 0x0F81F007;
2170                 }
2171                 break;
2172         default:
2173                 break;
2174         }
2175         ratr_value &= 0x0FFFFFFF;
2176         if (ieee->pHTInfo->bCurTxBW40MHz &&
2177             ieee->pHTInfo->bCurShortGI40MHz)
2178                 ratr_value |= 0x80000000;
2179         else if (!ieee->pHTInfo->bCurTxBW40MHz &&
2180                   ieee->pHTInfo->bCurShortGI20MHz)
2181                 ratr_value |= 0x80000000;
2182         write_nic_dword(dev, RATR0+rate_index*4, ratr_value);
2183         write_nic_byte(dev, UFWP, 1);
2184 }
2185
2186 void
2187 rtl8192_InitializeVariables(struct net_device  *dev)
2188 {
2189         struct r8192_priv *priv = rtllib_priv(dev);
2190
2191         strcpy(priv->nick, "rtl8192E");
2192
2193         priv->rtllib->softmac_features  = IEEE_SOFTMAC_SCAN |
2194                 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
2195                 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
2196
2197         priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci);
2198
2199         priv->ShortRetryLimit = 0x30;
2200         priv->LongRetryLimit = 0x30;
2201
2202         priv->ReceiveConfig = RCR_ADD3  |
2203                 RCR_AMF | RCR_ADF |
2204                 RCR_AICV |
2205                 RCR_AB | RCR_AM | RCR_APM |
2206                 RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) |
2207                 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT;
2208
2209         priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK |
2210                             IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK |
2211                             IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |
2212                             IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 |
2213                             IMR_RDU | IMR_RXFOVW | IMR_TXFOVW |
2214                             IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
2215
2216         priv->PwrDomainProtect = false;
2217
2218         priv->bfirst_after_down = false;
2219 }
2220
2221 void rtl8192_EnableInterrupt(struct net_device *dev)
2222 {
2223         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2224
2225         priv->irq_enabled = 1;
2226
2227         write_nic_dword(dev, INTA_MASK, priv->irq_mask[0]);
2228
2229 }
2230
2231 void rtl8192_DisableInterrupt(struct net_device *dev)
2232 {
2233         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2234
2235         write_nic_dword(dev, INTA_MASK, 0);
2236
2237         priv->irq_enabled = 0;
2238 }
2239
2240 void rtl8192_ClearInterrupt(struct net_device *dev)
2241 {
2242         u32 tmp = 0;
2243
2244         tmp = read_nic_dword(dev, ISR);
2245         write_nic_dword(dev, ISR, tmp);
2246 }
2247
2248
2249 void rtl8192_enable_rx(struct net_device *dev)
2250 {
2251         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2252
2253         write_nic_dword(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]);
2254 }
2255
2256 static const u32 TX_DESC_BASE[] = {
2257         BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA
2258 };
2259
2260 void rtl8192_enable_tx(struct net_device *dev)
2261 {
2262         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2263         u32 i;
2264
2265         for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
2266                 write_nic_dword(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
2267 }
2268
2269
2270 void rtl8192_interrupt_recognized(struct net_device *dev, u32 *p_inta,
2271                                   u32 *p_intb)
2272 {
2273         *p_inta = read_nic_dword(dev, ISR);
2274         write_nic_dword(dev, ISR, *p_inta);
2275 }
2276
2277 bool rtl8192_HalRxCheckStuck(struct net_device *dev)
2278 {
2279         struct r8192_priv *priv = rtllib_priv(dev);
2280         u16               RegRxCounter = read_nic_word(dev, 0x130);
2281         bool              bStuck = false;
2282         static u8         rx_chk_cnt;
2283         u32             SlotIndex = 0, TotalRxStuckCount = 0;
2284         u8              i;
2285         u8              SilentResetRxSoltNum = 4;
2286
2287         RT_TRACE(COMP_RESET, "%s(): RegRxCounter is %d, RxCounter is %d\n",
2288                  __func__, RegRxCounter, priv->RxCounter);
2289
2290         rx_chk_cnt++;
2291         if (priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) {
2292                 rx_chk_cnt = 0;
2293         } else if ((priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High + 5))
2294           && (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2295           (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_40M))
2296           || ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2297           (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_20M)))) {
2298                 if (rx_chk_cnt < 2)
2299                         return bStuck;
2300                 rx_chk_cnt = 0;
2301         } else if ((((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2302                   (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_40M)) ||
2303                 ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2304                  (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_20M))) &&
2305                 priv->undecorated_smoothed_pwdb >= VeryLowRSSI) {
2306                 if (rx_chk_cnt < 4)
2307                         return bStuck;
2308                 rx_chk_cnt = 0;
2309         } else {
2310                 if (rx_chk_cnt < 8)
2311                         return bStuck;
2312                 rx_chk_cnt = 0;
2313         }
2314
2315
2316         SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum;
2317
2318         if (priv->RxCounter == RegRxCounter) {
2319                 priv->SilentResetRxStuckEvent[SlotIndex] = 1;
2320
2321                 for (i = 0; i < SilentResetRxSoltNum; i++)
2322                         TotalRxStuckCount += priv->SilentResetRxStuckEvent[i];
2323
2324                 if (TotalRxStuckCount == SilentResetRxSoltNum) {
2325                         bStuck = true;
2326                         for (i = 0; i < SilentResetRxSoltNum; i++)
2327                                 TotalRxStuckCount +=
2328                                          priv->SilentResetRxStuckEvent[i];
2329                 }
2330
2331
2332         } else {
2333                 priv->SilentResetRxStuckEvent[SlotIndex] = 0;
2334         }
2335
2336         priv->RxCounter = RegRxCounter;
2337
2338         return bStuck;
2339 }
2340
2341 bool rtl8192_HalTxCheckStuck(struct net_device *dev)
2342 {
2343         struct r8192_priv *priv = rtllib_priv(dev);
2344         bool    bStuck = false;
2345         u16     RegTxCounter = read_nic_word(dev, 0x128);
2346
2347         RT_TRACE(COMP_RESET, "%s():RegTxCounter is %d,TxCounter is %d\n",
2348                  __func__, RegTxCounter, priv->TxCounter);
2349
2350         if (priv->TxCounter == RegTxCounter)
2351                 bStuck = true;
2352
2353         priv->TxCounter = RegTxCounter;
2354
2355         return bStuck;
2356 }
2357
2358 bool rtl8192_GetNmodeSupportBySecCfg(struct net_device *dev)
2359 {
2360         struct r8192_priv *priv = rtllib_priv(dev);
2361         struct rtllib_device *ieee = priv->rtllib;
2362
2363         if (ieee->rtllib_ap_sec_type &&
2364            (ieee->rtllib_ap_sec_type(priv->rtllib)&(SEC_ALG_WEP |
2365                                      SEC_ALG_TKIP))) {
2366                 return false;
2367         } else {
2368                 return true;
2369         }
2370 }
2371
2372 bool rtl8192_GetHalfNmodeSupportByAPs(struct net_device *dev)
2373 {
2374         bool Reval;
2375         struct r8192_priv *priv = rtllib_priv(dev);
2376         struct rtllib_device *ieee = priv->rtllib;
2377
2378         if (ieee->bHalfWirelessN24GMode == true)
2379                 Reval = true;
2380         else
2381                 Reval =  false;
2382
2383         return Reval;
2384 }
2385
2386 u8 rtl8192_QueryIsShort(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc)
2387 {
2388         u8   tmp_Short;
2389
2390         tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) :
2391                         ((tcb_desc->bUseShortPreamble) ? 1 : 0);
2392         if (TxHT == 1 && TxRate != DESC90_RATEMCS15)
2393                 tmp_Short = 0;
2394
2395         return tmp_Short;
2396 }
2397
2398 void ActUpdateChannelAccessSetting(struct net_device *dev,
2399         enum wireless_mode WirelessMode,
2400         struct channel_access_setting *ChnlAccessSetting)
2401 {
2402 }