drivers/staging/rtl8192e/rtl8192e/r8192E_dev.c

   1 /******************************************************************************
   2  * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
   3  *
   4  * Based on the r8180 driver, which is:
   5  * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  18  *
  19  * The full GNU General Public License is included in this distribution in the
  20  * file called LICENSE.
  21  *
  22  * Contact Information:
  23  * wlanfae <wlanfae@realtek.com>
  24 ******************************************************************************/
  25 #include "rtl_core.h"
  26 #include "r8192E_phy.h"
  27 #include "r8192E_phyreg.h"
  28 #include "r8190P_rtl8256.h"
  29 #include "r8192E_cmdpkt.h"
  30 #include "rtl_dm.h"
  31 #include "rtl_wx.h"
  32
  33 static int WDCAPARA_ADD[] = {EDCAPARA_BE, EDCAPARA_BK, EDCAPARA_VI,
  34                              EDCAPARA_VO};
  35
  36 void rtl92e_start_beacon(struct net_device *dev)
  37 {
  38         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
  39         struct rtllib_network *net = &priv->rtllib->current_network;
  40         u16 BcnTimeCfg = 0;
  41         u16 BcnCW = 6;
  42         u16 BcnIFS = 0xf;
  43
  44         rtl92e_irq_disable(dev);
  45
  46         rtl92e_writew(dev, ATIMWND, 2);
  47
  48         rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
  49         rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
  50         rtl92e_writew(dev, BCN_DMATIME, 256);
  51
  52         rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
  53
  54         BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
  55         BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
  56         rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
  57         rtl92e_irq_enable(dev);
  58 }
  59
  60 static void rtl8192e_update_msr(struct net_device *dev)
  61 {
  62         struct r8192_priv *priv = rtllib_priv(dev);
  63         u8 msr;
  64         enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
  65
  66         msr  = rtl92e_readb(dev, MSR);
  67         msr &= ~MSR_LINK_MASK;
  68
  69         switch (priv->rtllib->iw_mode) {
  70         case IW_MODE_INFRA:
  71                 if (priv->rtllib->state == RTLLIB_LINKED)
  72                         msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
  73                 else
  74                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  75                 LedAction = LED_CTL_LINK;
  76                 break;
  77         case IW_MODE_ADHOC:
  78                 if (priv->rtllib->state == RTLLIB_LINKED)
  79                         msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
  80                 else
  81                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  82                 break;
  83         case IW_MODE_MASTER:
  84                 if (priv->rtllib->state == RTLLIB_LINKED)
  85                         msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
  86                 else
  87                         msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
  88                 break;
  89         default:
  90                 break;
  91         }
  92
  93         rtl92e_writeb(dev, MSR, msr);
  94         if (priv->rtllib->LedControlHandler)
  95                 priv->rtllib->LedControlHandler(dev, LedAction);
  96 }
  97
  98 void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val)
  99 {
 100         struct r8192_priv *priv = rtllib_priv(dev);
 101
 102         switch (variable) {
 103         case HW_VAR_BSSID:
 104                 rtl92e_writel(dev, BSSIDR, ((u32 *)(val))[0]);
 105                 rtl92e_writew(dev, BSSIDR+2, ((u16 *)(val+2))[0]);
 106                 break;
 107
 108         case HW_VAR_MEDIA_STATUS:
 109         {
 110                 enum rt_op_mode OpMode = *((enum rt_op_mode *)(val));
 111                 enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
 112                 u8 btMsr = rtl92e_readb(dev, MSR);
 113
 114                 btMsr &= 0xfc;
 115
 116                 switch (OpMode) {
 117                 case RT_OP_MODE_INFRASTRUCTURE:
 118                         btMsr |= MSR_INFRA;
 119                         LedAction = LED_CTL_LINK;
 120                         break;
 121
 122                 case RT_OP_MODE_IBSS:
 123                         btMsr |= MSR_ADHOC;
 124                         break;
 125
 126                 case RT_OP_MODE_AP:
 127                         btMsr |= MSR_AP;
 128                         LedAction = LED_CTL_LINK;
 129                         break;
 130
 131                 default:
 132                         btMsr |= MSR_NOLINK;
 133                         break;
 134                 }
 135
 136                 rtl92e_writeb(dev, MSR, btMsr);
 137
 138         }
 139         break;
 140
 141         case HW_VAR_CECHK_BSSID:
 142         {
 143                 u32     RegRCR, Type;
 144
 145                 Type = ((u8 *)(val))[0];
 146                 RegRCR = rtl92e_readl(dev, RCR);
 147                 priv->ReceiveConfig = RegRCR;
 148
 149                 if (Type == true)
 150                         RegRCR |= (RCR_CBSSID);
 151                 else if (Type == false)
 152                         RegRCR &= (~RCR_CBSSID);
 153
 154                 rtl92e_writel(dev, RCR, RegRCR);
 155                 priv->ReceiveConfig = RegRCR;
 156
 157         }
 158         break;
 159
 160         case HW_VAR_SLOT_TIME:
 161
 162                 priv->slot_time = val[0];
 163                 rtl92e_writeb(dev, SLOT_TIME, val[0]);
 164
 165                 break;
 166
 167         case HW_VAR_ACK_PREAMBLE:
 168         {
 169                 u32 regTmp;
 170
 171                 priv->short_preamble = (bool)(*(u8 *)val);
 172                 regTmp = priv->basic_rate;
 173                 if (priv->short_preamble)
 174                         regTmp |= BRSR_AckShortPmb;
 175                 rtl92e_writel(dev, RRSR, regTmp);
 176                 break;
 177         }
 178
 179         case HW_VAR_CPU_RST:
 180                 rtl92e_writel(dev, CPU_GEN, ((u32 *)(val))[0]);
 181                 break;
 182
 183         case HW_VAR_AC_PARAM:
 184         {
 185                 u8      pAcParam = *((u8 *)val);
 186                 u32     eACI = pAcParam;
 187                 u8              u1bAIFS;
 188                 u32             u4bAcParam;
 189                 u8 mode = priv->rtllib->mode;
 190                 struct rtllib_qos_parameters *qop =
 191                          &priv->rtllib->current_network.qos_data.parameters;
 192
 193                 u1bAIFS = qop->aifs[pAcParam] *
 194                           ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime;
 195
 196                 rtl92e_dm_init_edca_turbo(dev);
 197
 198                 u4bAcParam = (le16_to_cpu(qop->tx_op_limit[pAcParam]) <<
 199                               AC_PARAM_TXOP_LIMIT_OFFSET) |
 200                                 ((le16_to_cpu(qop->cw_max[pAcParam])) <<
 201                                  AC_PARAM_ECW_MAX_OFFSET) |
 202                                 ((le16_to_cpu(qop->cw_min[pAcParam])) <<
 203                                  AC_PARAM_ECW_MIN_OFFSET) |
 204                                 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET);
 205
 206                 RT_TRACE(COMP_DBG, "%s():HW_VAR_AC_PARAM eACI:%x:%x\n",
 207                          __func__, eACI, u4bAcParam);
 208                 switch (eACI) {
 209                 case AC1_BK:
 210                         rtl92e_writel(dev, EDCAPARA_BK, u4bAcParam);
 211                         break;
 212
 213                 case AC0_BE:
 214                         rtl92e_writel(dev, EDCAPARA_BE, u4bAcParam);
 215                         break;
 216
 217                 case AC2_VI:
 218                         rtl92e_writel(dev, EDCAPARA_VI, u4bAcParam);
 219                         break;
 220
 221                 case AC3_VO:
 222                         rtl92e_writel(dev, EDCAPARA_VO, u4bAcParam);
 223                         break;
 224
 225                 default:
 226                         netdev_info(dev, "SetHwReg8185(): invalid ACI: %d !\n",
 227                                     eACI);
 228                         break;
 229                 }
 230                 priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL,
 231                                               (u8 *)(&pAcParam));
 232                 break;
 233         }
 234
 235         case HW_VAR_ACM_CTRL:
 236         {
 237                 struct rtllib_qos_parameters *qos_parameters =
 238                          &priv->rtllib->current_network.qos_data.parameters;
 239                 u8 pAcParam = *((u8 *)val);
 240                 u32 eACI = pAcParam;
 241                 union aci_aifsn *pAciAifsn = (union aci_aifsn *) &
 242                                               (qos_parameters->aifs[0]);
 243                 u8 acm = pAciAifsn->f.acm;
 244                 u8 AcmCtrl = rtl92e_readb(dev, AcmHwCtrl);
 245
 246                 RT_TRACE(COMP_DBG, "===========>%s():HW_VAR_ACM_CTRL:%x\n",
 247                          __func__, eACI);
 248                 AcmCtrl = AcmCtrl | ((priv->AcmMethod == 2) ? 0x0 : 0x1);
 249
 250                 if (acm) {
 251                         switch (eACI) {
 252                         case AC0_BE:
 253                                 AcmCtrl |= AcmHw_BeqEn;
 254                                 break;
 255
 256                         case AC2_VI:
 257                                 AcmCtrl |= AcmHw_ViqEn;
 258                                 break;
 259
 260                         case AC3_VO:
 261                                 AcmCtrl |= AcmHw_VoqEn;
 262                                 break;
 263
 264                         default:
 265                                 RT_TRACE(COMP_QOS,
 266                                          "SetHwReg8185(): [HW_VAR_ACM_CTRL] acm set failed: eACI is %d\n",
 267                                          eACI);
 268                                 break;
 269                         }
 270                 } else {
 271                         switch (eACI) {
 272                         case AC0_BE:
 273                                 AcmCtrl &= (~AcmHw_BeqEn);
 274                                 break;
 275
 276                         case AC2_VI:
 277                                 AcmCtrl &= (~AcmHw_ViqEn);
 278                                 break;
 279
 280                         case AC3_VO:
 281                                 AcmCtrl &= (~AcmHw_BeqEn);
 282                                 break;
 283
 284                         default:
 285                                 break;
 286                         }
 287                 }
 288
 289                 RT_TRACE(COMP_QOS,
 290                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 291                          AcmCtrl);
 292                 rtl92e_writeb(dev, AcmHwCtrl, AcmCtrl);
 293                 break;
 294         }
 295
 296         case HW_VAR_SIFS:
 297                 rtl92e_writeb(dev, SIFS, val[0]);
 298                 rtl92e_writeb(dev, SIFS+1, val[0]);
 299                 break;
 300
 301         case HW_VAR_RF_TIMING:
 302         {
 303                 u8 Rf_Timing = *((u8 *)val);
 304
 305                 rtl92e_writeb(dev, rFPGA0_RFTiming1, Rf_Timing);
 306                 break;
 307         }
 308
 309         default:
 310                 break;
 311         }
 312
 313 }
 314
 315 static void rtl8192_read_eeprom_info(struct net_device *dev)
 316 {
 317         struct r8192_priv *priv = rtllib_priv(dev);
 318         const u8 bMac_Tmp_Addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
 319         u8 tempval;
 320         u8 ICVer8192, ICVer8256;
 321         u16 i, usValue, IC_Version;
 322         u16 EEPROMId;
 323
 324         RT_TRACE(COMP_INIT, "====> rtl8192_read_eeprom_info\n");
 325
 326         EEPROMId = rtl92e_eeprom_read(dev, 0);
 327         if (EEPROMId != RTL8190_EEPROM_ID) {
 328                 netdev_err(dev, "%s(): Invalid EEPROM ID: %x\n", __func__,
 329                            EEPROMId);
 330                 priv->AutoloadFailFlag = true;
 331         } else {
 332                 priv->AutoloadFailFlag = false;
 333         }
 334
 335         if (!priv->AutoloadFailFlag) {
 336                 priv->eeprom_vid = rtl92e_eeprom_read(dev, EEPROM_VID >> 1);
 337                 priv->eeprom_did = rtl92e_eeprom_read(dev, EEPROM_DID >> 1);
 338
 339                 usValue = rtl92e_eeprom_read(dev,
 340                                              (u16)(EEPROM_Customer_ID>>1)) >> 8;
 341                 priv->eeprom_CustomerID = (u8)(usValue & 0xff);
 342                 usValue = rtl92e_eeprom_read(dev,
 343                                              EEPROM_ICVersion_ChannelPlan>>1);
 344                 priv->eeprom_ChannelPlan = usValue&0xff;
 345                 IC_Version = (usValue & 0xff00)>>8;
 346
 347                 ICVer8192 = (IC_Version&0xf);
 348                 ICVer8256 = (IC_Version & 0xf0)>>4;
 349                 RT_TRACE(COMP_INIT, "\nICVer8192 = 0x%x\n", ICVer8192);
 350                 RT_TRACE(COMP_INIT, "\nICVer8256 = 0x%x\n", ICVer8256);
 351                 if (ICVer8192 == 0x2) {
 352                         if (ICVer8256 == 0x5)
 353                                 priv->card_8192_version = VERSION_8190_BE;
 354                 }
 355                 switch (priv->card_8192_version) {
 356                 case VERSION_8190_BD:
 357                 case VERSION_8190_BE:
 358                         break;
 359                 default:
 360                         priv->card_8192_version = VERSION_8190_BD;
 361                         break;
 362                 }
 363                 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n",
 364                           priv->card_8192_version);
 365         } else {
 366                 priv->card_8192_version = VERSION_8190_BD;
 367                 priv->eeprom_vid = 0;
 368                 priv->eeprom_did = 0;
 369                 priv->eeprom_CustomerID = 0;
 370                 priv->eeprom_ChannelPlan = 0;
 371                 RT_TRACE(COMP_INIT, "\nIC Version = 0x%x\n", 0xff);
 372         }
 373
 374         RT_TRACE(COMP_INIT, "EEPROM VID = 0x%4x\n", priv->eeprom_vid);
 375         RT_TRACE(COMP_INIT, "EEPROM DID = 0x%4x\n", priv->eeprom_did);
 376         RT_TRACE(COMP_INIT, "EEPROM Customer ID: 0x%2x\n",
 377                  priv->eeprom_CustomerID);
 378
 379         if (!priv->AutoloadFailFlag) {
 380                 for (i = 0; i < 6; i += 2) {
 381                         usValue = rtl92e_eeprom_read(dev,
 382                                  (u16)((EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1));
 383                         *(u16 *)(&dev->dev_addr[i]) = usValue;
 384                 }
 385         } else {
 386                 ether_addr_copy(dev->dev_addr, bMac_Tmp_Addr);
 387         }
 388
 389         RT_TRACE(COMP_INIT, "Permanent Address = %pM\n",
 390                  dev->dev_addr);
 391
 392         if (priv->card_8192_version > VERSION_8190_BD)
 393                 priv->bTXPowerDataReadFromEEPORM = true;
 394         else
 395                 priv->bTXPowerDataReadFromEEPORM = false;
 396
 397         priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
 398
 399         if (priv->card_8192_version > VERSION_8190_BD) {
 400                 if (!priv->AutoloadFailFlag) {
 401                         tempval = (rtl92e_eeprom_read(dev,
 402                                                       (EEPROM_RFInd_PowerDiff >> 1))) & 0xff;
 403                         priv->EEPROMLegacyHTTxPowerDiff = tempval & 0xf;
 404
 405                         if (tempval&0x80)
 406                                 priv->rf_type = RF_1T2R;
 407                         else
 408                                 priv->rf_type = RF_2T4R;
 409                 } else {
 410                         priv->EEPROMLegacyHTTxPowerDiff = 0x04;
 411                 }
 412                 RT_TRACE(COMP_INIT, "EEPROMLegacyHTTxPowerDiff = %d\n",
 413                         priv->EEPROMLegacyHTTxPowerDiff);
 414
 415                 if (!priv->AutoloadFailFlag)
 416                         priv->EEPROMThermalMeter = (u8)(((rtl92e_eeprom_read(dev,
 417                                                    (EEPROM_ThermalMeter>>1))) &
 418                                                    0xff00)>>8);
 419                 else
 420                         priv->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
 421                 RT_TRACE(COMP_INIT, "ThermalMeter = %d\n",
 422                          priv->EEPROMThermalMeter);
 423                 priv->TSSI_13dBm = priv->EEPROMThermalMeter * 100;
 424
 425                 if (priv->epromtype == EEPROM_93C46) {
 426                         if (!priv->AutoloadFailFlag) {
 427                                 usValue = rtl92e_eeprom_read(dev,
 428                                           EEPROM_TxPwDiff_CrystalCap >> 1);
 429                                 priv->EEPROMAntPwDiff = (usValue&0x0fff);
 430                                 priv->EEPROMCrystalCap = (u8)((usValue & 0xf000)
 431                                                          >> 12);
 432                         } else {
 433                                 priv->EEPROMAntPwDiff =
 434                                          EEPROM_Default_AntTxPowerDiff;
 435                                 priv->EEPROMCrystalCap =
 436                                          EEPROM_Default_TxPwDiff_CrystalCap;
 437                         }
 438                         RT_TRACE(COMP_INIT, "EEPROMAntPwDiff = %d\n",
 439                                  priv->EEPROMAntPwDiff);
 440                         RT_TRACE(COMP_INIT, "EEPROMCrystalCap = %d\n",
 441                                  priv->EEPROMCrystalCap);
 442
 443                         for (i = 0; i < 14; i += 2) {
 444                                 if (!priv->AutoloadFailFlag)
 445                                         usValue = rtl92e_eeprom_read(dev,
 446                                                   (u16)((EEPROM_TxPwIndex_CCK +
 447                                                   i) >> 1));
 448                                 else
 449                                         usValue = EEPROM_Default_TxPower;
 450                                 *((u16 *)(&priv->EEPROMTxPowerLevelCCK[i])) =
 451                                                                  usValue;
 452                                 RT_TRACE(COMP_INIT,
 453                                          "CCK Tx Power Level, Index %d = 0x%02x\n",
 454                                          i, priv->EEPROMTxPowerLevelCCK[i]);
 455                                 RT_TRACE(COMP_INIT,
 456                                          "CCK Tx Power Level, Index %d = 0x%02x\n",
 457                                          i+1, priv->EEPROMTxPowerLevelCCK[i+1]);
 458                         }
 459                         for (i = 0; i < 14; i += 2) {
 460                                 if (!priv->AutoloadFailFlag)
 461                                         usValue = rtl92e_eeprom_read(dev,
 462                                                 (u16)((EEPROM_TxPwIndex_OFDM_24G
 463                                                 + i) >> 1));
 464                                 else
 465                                         usValue = EEPROM_Default_TxPower;
 466                                 *((u16 *)(&priv->EEPROMTxPowerLevelOFDM24G[i]))
 467                                                          = usValue;
 468                                 RT_TRACE(COMP_INIT,
 469                                          "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
 470                                          i, priv->EEPROMTxPowerLevelOFDM24G[i]);
 471                                 RT_TRACE(COMP_INIT,
 472                                          "OFDM 2.4G Tx Power Level, Index %d = 0x%02x\n",
 473                                          i + 1,
 474                                          priv->EEPROMTxPowerLevelOFDM24G[i+1]);
 475                         }
 476                 }
 477                 if (priv->epromtype == EEPROM_93C46) {
 478                         for (i = 0; i < 14; i++) {
 479                                 priv->TxPowerLevelCCK[i] =
 480                                          priv->EEPROMTxPowerLevelCCK[i];
 481                                 priv->TxPowerLevelOFDM24G[i] =
 482                                          priv->EEPROMTxPowerLevelOFDM24G[i];
 483                         }
 484                         priv->LegacyHTTxPowerDiff =
 485                                          priv->EEPROMLegacyHTTxPowerDiff;
 486                         priv->AntennaTxPwDiff[0] = (priv->EEPROMAntPwDiff &
 487                                                     0xf);
 488                         priv->AntennaTxPwDiff[1] = (priv->EEPROMAntPwDiff &
 489                                                         0xf0) >> 4;
 490                         priv->AntennaTxPwDiff[2] = (priv->EEPROMAntPwDiff &
 491                                                         0xf00) >> 8;
 492                         priv->CrystalCap = priv->EEPROMCrystalCap;
 493                         priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
 494                                                  0xf);
 495                         priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
 496                                                      0xf0) >> 4;
 497                 } else if (priv->epromtype == EEPROM_93C56) {
 498
 499                         for (i = 0; i < 3; i++) {
 500                                 priv->TxPowerLevelCCK_A[i] =
 501                                          priv->EEPROMRfACCKChnl1TxPwLevel[0];
 502                                 priv->TxPowerLevelOFDM24G_A[i] =
 503                                          priv->EEPROMRfAOfdmChnlTxPwLevel[0];
 504                                 priv->TxPowerLevelCCK_C[i] =
 505                                          priv->EEPROMRfCCCKChnl1TxPwLevel[0];
 506                                 priv->TxPowerLevelOFDM24G_C[i] =
 507                                          priv->EEPROMRfCOfdmChnlTxPwLevel[0];
 508                         }
 509                         for (i = 3; i < 9; i++) {
 510                                 priv->TxPowerLevelCCK_A[i]  =
 511                                          priv->EEPROMRfACCKChnl1TxPwLevel[1];
 512                                 priv->TxPowerLevelOFDM24G_A[i] =
 513                                          priv->EEPROMRfAOfdmChnlTxPwLevel[1];
 514                                 priv->TxPowerLevelCCK_C[i] =
 515                                          priv->EEPROMRfCCCKChnl1TxPwLevel[1];
 516                                 priv->TxPowerLevelOFDM24G_C[i] =
 517                                          priv->EEPROMRfCOfdmChnlTxPwLevel[1];
 518                         }
 519                         for (i = 9; i < 14; i++) {
 520                                 priv->TxPowerLevelCCK_A[i]  =
 521                                          priv->EEPROMRfACCKChnl1TxPwLevel[2];
 522                                 priv->TxPowerLevelOFDM24G_A[i] =
 523                                          priv->EEPROMRfAOfdmChnlTxPwLevel[2];
 524                                 priv->TxPowerLevelCCK_C[i] =
 525                                          priv->EEPROMRfCCCKChnl1TxPwLevel[2];
 526                                 priv->TxPowerLevelOFDM24G_C[i] =
 527                                          priv->EEPROMRfCOfdmChnlTxPwLevel[2];
 528                         }
 529                         for (i = 0; i < 14; i++)
 530                                 RT_TRACE(COMP_INIT,
 531                                          "priv->TxPowerLevelCCK_A[%d] = 0x%x\n",
 532                                          i, priv->TxPowerLevelCCK_A[i]);
 533                         for (i = 0; i < 14; i++)
 534                                 RT_TRACE(COMP_INIT,
 535                                          "priv->TxPowerLevelOFDM24G_A[%d] = 0x%x\n",
 536                                          i, priv->TxPowerLevelOFDM24G_A[i]);
 537                         for (i = 0; i < 14; i++)
 538                                 RT_TRACE(COMP_INIT,
 539                                          "priv->TxPowerLevelCCK_C[%d] = 0x%x\n",
 540                                          i, priv->TxPowerLevelCCK_C[i]);
 541                         for (i = 0; i < 14; i++)
 542                                 RT_TRACE(COMP_INIT,
 543                                          "priv->TxPowerLevelOFDM24G_C[%d] = 0x%x\n",
 544                                          i, priv->TxPowerLevelOFDM24G_C[i]);
 545                         priv->LegacyHTTxPowerDiff =
 546                                  priv->EEPROMLegacyHTTxPowerDiff;
 547                         priv->AntennaTxPwDiff[0] = 0;
 548                         priv->AntennaTxPwDiff[1] = 0;
 549                         priv->AntennaTxPwDiff[2] = 0;
 550                         priv->CrystalCap = priv->EEPROMCrystalCap;
 551                         priv->ThermalMeter[0] = (priv->EEPROMThermalMeter &
 552                                                  0xf);
 553                         priv->ThermalMeter[1] = (priv->EEPROMThermalMeter &
 554                                                      0xf0) >> 4;
 555                 }
 556         }
 557
 558         if (priv->rf_type == RF_1T2R) {
 559                 /* no matter what checkpatch says, the braces are needed */
 560                 RT_TRACE(COMP_INIT, "\n1T2R config\n");
 561         } else if (priv->rf_type == RF_2T4R) {
 562                 RT_TRACE(COMP_INIT, "\n2T4R config\n");
 563         }
 564
 565         rtl92e_init_adaptive_rate(dev);
 566
 567         priv->rf_chip = RF_8256;
 568
 569         if (priv->RegChannelPlan == 0xf)
 570                 priv->ChannelPlan = priv->eeprom_ChannelPlan;
 571         else
 572                 priv->ChannelPlan = priv->RegChannelPlan;
 573
 574         if (priv->eeprom_vid == 0x1186 &&  priv->eeprom_did == 0x3304)
 575                 priv->CustomerID =  RT_CID_DLINK;
 576
 577         switch (priv->eeprom_CustomerID) {
 578         case EEPROM_CID_DEFAULT:
 579                 priv->CustomerID = RT_CID_DEFAULT;
 580                 break;
 581         case EEPROM_CID_CAMEO:
 582                 priv->CustomerID = RT_CID_819x_CAMEO;
 583                 break;
 584         case  EEPROM_CID_RUNTOP:
 585                 priv->CustomerID = RT_CID_819x_RUNTOP;
 586                 break;
 587         case EEPROM_CID_NetCore:
 588                 priv->CustomerID = RT_CID_819x_Netcore;
 589                 break;
 590         case EEPROM_CID_TOSHIBA:
 591                 priv->CustomerID = RT_CID_TOSHIBA;
 592                 if (priv->eeprom_ChannelPlan&0x80)
 593                         priv->ChannelPlan = priv->eeprom_ChannelPlan&0x7f;
 594                 else
 595                         priv->ChannelPlan = 0x0;
 596                 RT_TRACE(COMP_INIT, "Toshiba ChannelPlan = 0x%x\n",
 597                         priv->ChannelPlan);
 598                 break;
 599         case EEPROM_CID_Nettronix:
 600                 priv->ScanDelay = 100;
 601                 priv->CustomerID = RT_CID_Nettronix;
 602                 break;
 603         case EEPROM_CID_Pronet:
 604                 priv->CustomerID = RT_CID_PRONET;
 605                 break;
 606         case EEPROM_CID_DLINK:
 607                 priv->CustomerID = RT_CID_DLINK;
 608                 break;
 609
 610         case EEPROM_CID_WHQL:
 611                 break;
 612         default:
 613                 break;
 614         }
 615
 616         if (priv->ChannelPlan > CHANNEL_PLAN_LEN - 1)
 617                 priv->ChannelPlan = 0;
 618         priv->ChannelPlan = COUNTRY_CODE_WORLD_WIDE_13;
 619
 620         if (priv->eeprom_vid == 0x1186 &&  priv->eeprom_did == 0x3304)
 621                 priv->rtllib->bSupportRemoteWakeUp = true;
 622         else
 623                 priv->rtllib->bSupportRemoteWakeUp = false;
 624
 625         RT_TRACE(COMP_INIT, "RegChannelPlan(%d)\n", priv->RegChannelPlan);
 626         RT_TRACE(COMP_INIT, "ChannelPlan = %d\n", priv->ChannelPlan);
 627         RT_TRACE(COMP_TRACE, "<==== ReadAdapterInfo\n");
 628 }
 629
 630 void rtl92e_get_eeprom_size(struct net_device *dev)
 631 {
 632         u16 curCR;
 633         struct r8192_priv *priv = rtllib_priv(dev);
 634
 635         RT_TRACE(COMP_INIT, "===========>%s()\n", __func__);
 636         curCR = rtl92e_readl(dev, EPROM_CMD);
 637         RT_TRACE(COMP_INIT, "read from Reg Cmd9346CR(%x):%x\n", EPROM_CMD,
 638                  curCR);
 639         priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 :
 640                           EEPROM_93C46;
 641         RT_TRACE(COMP_INIT, "<===========%s(), epromtype:%d\n", __func__,
 642                  priv->epromtype);
 643         rtl8192_read_eeprom_info(dev);
 644 }
 645
 646 static void rtl8192_hwconfig(struct net_device *dev)
 647 {
 648         u32 regRATR = 0, regRRSR = 0;
 649         u8 regBwOpMode = 0, regTmp = 0;
 650         struct r8192_priv *priv = rtllib_priv(dev);
 651
 652         switch (priv->rtllib->mode) {
 653         case WIRELESS_MODE_B:
 654                 regBwOpMode = BW_OPMODE_20MHZ;
 655                 regRATR = RATE_ALL_CCK;
 656                 regRRSR = RATE_ALL_CCK;
 657                 break;
 658         case WIRELESS_MODE_A:
 659                 regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ;
 660                 regRATR = RATE_ALL_OFDM_AG;
 661                 regRRSR = RATE_ALL_OFDM_AG;
 662                 break;
 663         case WIRELESS_MODE_G:
 664                 regBwOpMode = BW_OPMODE_20MHZ;
 665                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 666                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 667                 break;
 668         case WIRELESS_MODE_AUTO:
 669         case WIRELESS_MODE_N_24G:
 670                 regBwOpMode = BW_OPMODE_20MHZ;
 671                         regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
 672                                   RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 673                         regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 674                 break;
 675         case WIRELESS_MODE_N_5G:
 676                 regBwOpMode = BW_OPMODE_5G;
 677                 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS |
 678                           RATE_ALL_OFDM_2SS;
 679                 regRRSR = RATE_ALL_OFDM_AG;
 680                 break;
 681         default:
 682                 regBwOpMode = BW_OPMODE_20MHZ;
 683                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 684                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 685                 break;
 686         }
 687
 688         rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
 689         {
 690                 u32 ratr_value = 0;
 691
 692                 ratr_value = regRATR;
 693                 if (priv->rf_type == RF_1T2R)
 694                         ratr_value &= ~(RATE_ALL_OFDM_2SS);
 695                 rtl92e_writel(dev, RATR0, ratr_value);
 696                 rtl92e_writeb(dev, UFWP, 1);
 697         }
 698         regTmp = rtl92e_readb(dev, 0x313);
 699         regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
 700         rtl92e_writel(dev, RRSR, regRRSR);
 701
 702         rtl92e_writew(dev, RETRY_LIMIT,
 703                       priv->ShortRetryLimit << RETRY_LIMIT_SHORT_SHIFT |
 704                       priv->LongRetryLimit << RETRY_LIMIT_LONG_SHIFT);
 705 }
 706
 707 bool rtl92e_start_adapter(struct net_device *dev)
 708 {
 709         struct r8192_priv *priv = rtllib_priv(dev);
 710         u32 ulRegRead;
 711         bool rtStatus = true;
 712         u8 tmpvalue;
 713         u8 ICVersion, SwitchingRegulatorOutput;
 714         bool bfirmwareok = true;
 715         u32 tmpRegA, tmpRegC, TempCCk;
 716         int i = 0;
 717         u32 retry_times = 0;
 718
 719         RT_TRACE(COMP_INIT, "====>%s()\n", __func__);
 720         priv->being_init_adapter = true;
 721
 722 start:
 723         rtl92e_reset_desc_ring(dev);
 724         priv->Rf_Mode = RF_OP_By_SW_3wire;
 725         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 726                 rtl92e_writeb(dev, ANAPAR, 0x37);
 727                 mdelay(500);
 728         }
 729         priv->pFirmware->firmware_status = FW_STATUS_0_INIT;
 730
 731         if (priv->RegRfOff)
 732                 priv->rtllib->eRFPowerState = eRfOff;
 733
 734         ulRegRead = rtl92e_readl(dev, CPU_GEN);
 735         if (priv->pFirmware->firmware_status == FW_STATUS_0_INIT)
 736                 ulRegRead |= CPU_GEN_SYSTEM_RESET;
 737         else if (priv->pFirmware->firmware_status == FW_STATUS_5_READY)
 738                 ulRegRead |= CPU_GEN_FIRMWARE_RESET;
 739         else
 740                 netdev_err(dev, "%s(): undefined firmware state: %d.\n",
 741                            __func__, priv->pFirmware->firmware_status);
 742
 743         rtl92e_writel(dev, CPU_GEN, ulRegRead);
 744
 745         ICVersion = rtl92e_readb(dev, IC_VERRSION);
 746         if (ICVersion >= 0x4) {
 747                 SwitchingRegulatorOutput = rtl92e_readb(dev, SWREGULATOR);
 748                 if (SwitchingRegulatorOutput  != 0xb8) {
 749                         rtl92e_writeb(dev, SWREGULATOR, 0xa8);
 750                         mdelay(1);
 751                         rtl92e_writeb(dev, SWREGULATOR, 0xb8);
 752                 }
 753         }
 754         RT_TRACE(COMP_INIT, "BB Config Start!\n");
 755         rtStatus = rtl92e_config_bb(dev);
 756         if (!rtStatus) {
 757                 netdev_warn(dev, "%s(): Failed to configure BB\n", __func__);
 758                 return rtStatus;
 759         }
 760         RT_TRACE(COMP_INIT, "BB Config Finished!\n");
 761
 762         priv->LoopbackMode = RTL819X_NO_LOOPBACK;
 763         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 764                 ulRegRead = rtl92e_readl(dev, CPU_GEN);
 765                 if (priv->LoopbackMode == RTL819X_NO_LOOPBACK)
 766                         ulRegRead = ((ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) |
 767                                      CPU_GEN_NO_LOOPBACK_SET);
 768                 else if (priv->LoopbackMode == RTL819X_MAC_LOOPBACK)
 769                         ulRegRead |= CPU_CCK_LOOPBACK;
 770                 else
 771                         netdev_err(dev, "%s: Invalid loopback mode setting.\n",
 772                                    __func__);
 773
 774                 rtl92e_writel(dev, CPU_GEN, ulRegRead);
 775
 776                 udelay(500);
 777         }
 778         rtl8192_hwconfig(dev);
 779         rtl92e_writeb(dev, CMDR, CR_RE | CR_TE);
 780
 781         rtl92e_writeb(dev, PCIF, ((MXDMA2_NoLimit<<MXDMA2_RX_SHIFT) |
 782                                   (MXDMA2_NoLimit<<MXDMA2_TX_SHIFT)));
 783         rtl92e_writel(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
 784         rtl92e_writew(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]);
 785         rtl92e_writel(dev, RCR, priv->ReceiveConfig);
 786
 787         rtl92e_writel(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK <<
 788                       RSVD_FW_QUEUE_PAGE_BK_SHIFT |
 789                       NUM_OF_PAGE_IN_FW_QUEUE_BE <<
 790                       RSVD_FW_QUEUE_PAGE_BE_SHIFT |
 791                       NUM_OF_PAGE_IN_FW_QUEUE_VI <<
 792                       RSVD_FW_QUEUE_PAGE_VI_SHIFT |
 793                       NUM_OF_PAGE_IN_FW_QUEUE_VO <<
 794                       RSVD_FW_QUEUE_PAGE_VO_SHIFT);
 795         rtl92e_writel(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT <<
 796                       RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
 797         rtl92e_writel(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW |
 798                       NUM_OF_PAGE_IN_FW_QUEUE_BCN <<
 799                       RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
 800                       NUM_OF_PAGE_IN_FW_QUEUE_PUB <<
 801                       RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
 802
 803         rtl92e_tx_enable(dev);
 804         rtl92e_rx_enable(dev);
 805         ulRegRead = (0xFFF00000 & rtl92e_readl(dev, RRSR))  |
 806                      RATE_ALL_OFDM_AG | RATE_ALL_CCK;
 807         rtl92e_writel(dev, RRSR, ulRegRead);
 808         rtl92e_writel(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
 809
 810         rtl92e_writeb(dev, ACK_TIMEOUT, 0x30);
 811
 812         if (priv->ResetProgress == RESET_TYPE_NORESET)
 813                 rtl92e_set_wireless_mode(dev, priv->rtllib->mode);
 814         rtl92e_cam_reset(dev);
 815         {
 816                 u8 SECR_value = 0x0;
 817
 818                 SECR_value |= SCR_TxEncEnable;
 819                 SECR_value |= SCR_RxDecEnable;
 820                 SECR_value |= SCR_NoSKMC;
 821                 rtl92e_writeb(dev, SECR, SECR_value);
 822         }
 823         rtl92e_writew(dev, ATIMWND, 2);
 824         rtl92e_writew(dev, BCN_INTERVAL, 100);
 825         {
 826                 int i;
 827
 828                 for (i = 0; i < QOS_QUEUE_NUM; i++)
 829                         rtl92e_writel(dev, WDCAPARA_ADD[i], 0x005e4332);
 830         }
 831         rtl92e_writeb(dev, 0xbe, 0xc0);
 832
 833         rtl92e_config_mac(dev);
 834
 835         if (priv->card_8192_version > (u8) VERSION_8190_BD) {
 836                 rtl92e_get_tx_power(dev);
 837                 rtl92e_set_tx_power(dev, priv->chan);
 838         }
 839
 840         tmpvalue = rtl92e_readb(dev, IC_VERRSION);
 841         priv->IC_Cut = tmpvalue;
 842         RT_TRACE(COMP_INIT, "priv->IC_Cut= 0x%x\n", priv->IC_Cut);
 843         if (priv->IC_Cut >= IC_VersionCut_D) {
 844                 if (priv->IC_Cut == IC_VersionCut_D) {
 845                         /* no matter what checkpatch says, braces are needed */
 846                         RT_TRACE(COMP_INIT, "D-cut\n");
 847                 } else if (priv->IC_Cut == IC_VersionCut_E) {
 848                         RT_TRACE(COMP_INIT, "E-cut\n");
 849                 }
 850         } else {
 851                 RT_TRACE(COMP_INIT, "Before C-cut\n");
 852         }
 853
 854         RT_TRACE(COMP_INIT, "Load Firmware!\n");
 855         bfirmwareok = rtl92e_init_fw(dev);
 856         if (!bfirmwareok) {
 857                 if (retry_times < 10) {
 858                         retry_times++;
 859                         goto start;
 860                 } else {
 861                         rtStatus = false;
 862                         goto end;
 863                 }
 864         }
 865         RT_TRACE(COMP_INIT, "Load Firmware finished!\n");
 866         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 867                 RT_TRACE(COMP_INIT, "RF Config Started!\n");
 868                 rtStatus = rtl92e_config_phy(dev);
 869                 if (!rtStatus) {
 870                         netdev_info(dev, "RF Config failed\n");
 871                         return rtStatus;
 872                 }
 873                 RT_TRACE(COMP_INIT, "RF Config Finished!\n");
 874         }
 875
 876         rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
 877         rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
 878
 879         rtl92e_writeb(dev, 0x87, 0x0);
 880
 881         if (priv->RegRfOff) {
 882                 RT_TRACE((COMP_INIT | COMP_RF | COMP_POWER),
 883                           "%s(): Turn off RF for RegRfOff ----------\n",
 884                           __func__);
 885                 rtl92e_set_rf_state(dev, eRfOff, RF_CHANGE_BY_SW, true);
 886         } else if (priv->rtllib->RfOffReason > RF_CHANGE_BY_PS) {
 887                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
 888                          "%s(): Turn off RF for RfOffReason(%d) ----------\n",
 889                          __func__, priv->rtllib->RfOffReason);
 890                 rtl92e_set_rf_state(dev, eRfOff, priv->rtllib->RfOffReason,
 891                                     true);
 892         } else if (priv->rtllib->RfOffReason >= RF_CHANGE_BY_IPS) {
 893                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER),
 894                          "%s(): Turn off RF for RfOffReason(%d) ----------\n",
 895                          __func__, priv->rtllib->RfOffReason);
 896                 rtl92e_set_rf_state(dev, eRfOff, priv->rtllib->RfOffReason,
 897                                     true);
 898         } else {
 899                 RT_TRACE((COMP_INIT|COMP_RF|COMP_POWER), "%s(): RF-ON\n",
 900                           __func__);
 901                 priv->rtllib->eRFPowerState = eRfOn;
 902                 priv->rtllib->RfOffReason = 0;
 903         }
 904
 905         if (priv->rtllib->FwRWRF)
 906                 priv->Rf_Mode = RF_OP_By_FW;
 907         else
 908                 priv->Rf_Mode = RF_OP_By_SW_3wire;
 909
 910         if (priv->ResetProgress == RESET_TYPE_NORESET) {
 911                 rtl92e_dm_init_txpower_tracking(dev);
 912
 913                 if (priv->IC_Cut >= IC_VersionCut_D) {
 914                         tmpRegA = rtl92e_get_bb_reg(dev, rOFDM0_XATxIQImbalance,
 915                                                     bMaskDWord);
 916                         tmpRegC = rtl92e_get_bb_reg(dev, rOFDM0_XCTxIQImbalance,
 917                                                     bMaskDWord);
 918                         for (i = 0; i < TxBBGainTableLength; i++) {
 919                                 if (tmpRegA == dm_tx_bb_gain[i]) {
 920                                         priv->rfa_txpowertrackingindex = (u8)i;
 921                                         priv->rfa_txpowertrackingindex_real =
 922                                                  (u8)i;
 923                                         priv->rfa_txpowertracking_default =
 924                                                  priv->rfa_txpowertrackingindex;
 925                                         break;
 926                                 }
 927                         }
 928
 929                         TempCCk = rtl92e_get_bb_reg(dev, rCCK0_TxFilter1,
 930                                                     bMaskByte2);
 931
 932                         for (i = 0; i < CCKTxBBGainTableLength; i++) {
 933                                 if (TempCCk == dm_cck_tx_bb_gain[i][0]) {
 934                                         priv->CCKPresentAttentuation_20Mdefault = (u8)i;
 935                                         break;
 936                                 }
 937                         }
 938                         priv->CCKPresentAttentuation_40Mdefault = 0;
 939                         priv->CCKPresentAttentuation_difference = 0;
 940                         priv->CCKPresentAttentuation =
 941                                   priv->CCKPresentAttentuation_20Mdefault;
 942                         RT_TRACE(COMP_POWER_TRACKING,
 943                                  "priv->rfa_txpowertrackingindex_initial = %d\n",
 944                                  priv->rfa_txpowertrackingindex);
 945                         RT_TRACE(COMP_POWER_TRACKING,
 946                                  "priv->rfa_txpowertrackingindex_real__initial = %d\n",
 947                                  priv->rfa_txpowertrackingindex_real);
 948                         RT_TRACE(COMP_POWER_TRACKING,
 949                                  "priv->CCKPresentAttentuation_difference_initial = %d\n",
 950                                   priv->CCKPresentAttentuation_difference);
 951                         RT_TRACE(COMP_POWER_TRACKING,
 952                                  "priv->CCKPresentAttentuation_initial = %d\n",
 953                                  priv->CCKPresentAttentuation);
 954                         priv->btxpower_tracking = false;
 955                 }
 956         }
 957         rtl92e_irq_enable(dev);
 958 end:
 959         priv->being_init_adapter = false;
 960         return rtStatus;
 961 }
 962
 963 static void rtl8192_net_update(struct net_device *dev)
 964 {
 965
 966         struct r8192_priv *priv = rtllib_priv(dev);
 967         struct rtllib_network *net;
 968         u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
 969         u16 rate_config = 0;
 970
 971         net = &priv->rtllib->current_network;
 972         rtl92e_config_rate(dev, &rate_config);
 973         priv->dot11CurrentPreambleMode = PREAMBLE_AUTO;
 974          priv->basic_rate = rate_config &= 0x15f;
 975         rtl92e_writel(dev, BSSIDR, ((u32 *)net->bssid)[0]);
 976         rtl92e_writew(dev, BSSIDR+4, ((u16 *)net->bssid)[2]);
 977
 978         if (priv->rtllib->iw_mode == IW_MODE_ADHOC) {
 979                 rtl92e_writew(dev, ATIMWND, 2);
 980                 rtl92e_writew(dev, BCN_DMATIME, 256);
 981                 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
 982                 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
 983                 rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
 984
 985                 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
 986                 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
 987
 988                 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
 989         }
 990 }
 991
 992 void rtl92e_link_change(struct net_device *dev)
 993 {
 994         struct r8192_priv *priv = rtllib_priv(dev);
 995         struct rtllib_device *ieee = priv->rtllib;
 996
 997         if (!priv->up)
 998                 return;
 999
1000         if (ieee->state == RTLLIB_LINKED) {
1001                 rtl8192_net_update(dev);
1002                 priv->ops->update_ratr_table(dev);
1003                 if ((KEY_TYPE_WEP40 == ieee->pairwise_key_type) ||
1004                     (KEY_TYPE_WEP104 == ieee->pairwise_key_type))
1005                         rtl92e_enable_hw_security_config(dev);
1006         } else {
1007                 rtl92e_writeb(dev, 0x173, 0);
1008         }
1009         rtl8192e_update_msr(dev);
1010
1011         if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) {
1012                 u32 reg = 0;
1013
1014                 reg = rtl92e_readl(dev, RCR);
1015                 if (priv->rtllib->state == RTLLIB_LINKED) {
1016                         if (ieee->IntelPromiscuousModeInfo.bPromiscuousOn)
1017                                 ;
1018                         else
1019                                 priv->ReceiveConfig = reg |= RCR_CBSSID;
1020                 } else
1021                         priv->ReceiveConfig = reg &= ~RCR_CBSSID;
1022
1023                 rtl92e_writel(dev, RCR, reg);
1024         }
1025 }
1026
1027 void rtl92e_set_monitor_mode(struct net_device *dev, bool bAllowAllDA,
1028                              bool WriteIntoReg)
1029 {
1030         struct r8192_priv *priv = rtllib_priv(dev);
1031
1032         if (bAllowAllDA)
1033                 priv->ReceiveConfig |= RCR_AAP;
1034         else
1035                 priv->ReceiveConfig &= ~RCR_AAP;
1036
1037         if (WriteIntoReg)
1038                 rtl92e_writel(dev, RCR, priv->ReceiveConfig);
1039 }
1040
1041 static u8 MRateToHwRate8190Pci(u8 rate)
1042 {
1043         u8  ret = DESC90_RATE1M;
1044
1045         switch (rate) {
1046         case MGN_1M:
1047                 ret = DESC90_RATE1M;
1048                 break;
1049         case MGN_2M:
1050                 ret = DESC90_RATE2M;
1051                 break;
1052         case MGN_5_5M:
1053                 ret = DESC90_RATE5_5M;
1054                 break;
1055         case MGN_11M:
1056                 ret = DESC90_RATE11M;
1057                 break;
1058         case MGN_6M:
1059                 ret = DESC90_RATE6M;
1060                 break;
1061         case MGN_9M:
1062                 ret = DESC90_RATE9M;
1063                 break;
1064         case MGN_12M:
1065                 ret = DESC90_RATE12M;
1066                 break;
1067         case MGN_18M:
1068                 ret = DESC90_RATE18M;
1069                 break;
1070         case MGN_24M:
1071                 ret = DESC90_RATE24M;
1072                 break;
1073         case MGN_36M:
1074                 ret = DESC90_RATE36M;
1075                 break;
1076         case MGN_48M:
1077                 ret = DESC90_RATE48M;
1078                 break;
1079         case MGN_54M:
1080                 ret = DESC90_RATE54M;
1081                 break;
1082         case MGN_MCS0:
1083                 ret = DESC90_RATEMCS0;
1084                 break;
1085         case MGN_MCS1:
1086                 ret = DESC90_RATEMCS1;
1087                 break;
1088         case MGN_MCS2:
1089                 ret = DESC90_RATEMCS2;
1090                 break;
1091         case MGN_MCS3:
1092                 ret = DESC90_RATEMCS3;
1093                 break;
1094         case MGN_MCS4:
1095                 ret = DESC90_RATEMCS4;
1096                 break;
1097         case MGN_MCS5:
1098                 ret = DESC90_RATEMCS5;
1099                 break;
1100         case MGN_MCS6:
1101                 ret = DESC90_RATEMCS6;
1102                 break;
1103         case MGN_MCS7:
1104                 ret = DESC90_RATEMCS7;
1105                 break;
1106         case MGN_MCS8:
1107                 ret = DESC90_RATEMCS8;
1108                 break;
1109         case MGN_MCS9:
1110                 ret = DESC90_RATEMCS9;
1111                 break;
1112         case MGN_MCS10:
1113                 ret = DESC90_RATEMCS10;
1114                 break;
1115         case MGN_MCS11:
1116                 ret = DESC90_RATEMCS11;
1117                 break;
1118         case MGN_MCS12:
1119                 ret = DESC90_RATEMCS12;
1120                 break;
1121         case MGN_MCS13:
1122                 ret = DESC90_RATEMCS13;
1123                 break;
1124         case MGN_MCS14:
1125                 ret = DESC90_RATEMCS14;
1126                 break;
1127         case MGN_MCS15:
1128                 ret = DESC90_RATEMCS15;
1129                 break;
1130         case (0x80|0x20):
1131                 ret = DESC90_RATEMCS32;
1132                 break;
1133         default:
1134                 break;
1135         }
1136         return ret;
1137 }
1138
1139 static u8 rtl8192_MapHwQueueToFirmwareQueue(struct net_device *dev, u8 QueueID,
1140                                             u8 priority)
1141 {
1142         u8 QueueSelect = 0x0;
1143
1144         switch (QueueID) {
1145         case BE_QUEUE:
1146                 QueueSelect = QSLT_BE;
1147                 break;
1148
1149         case BK_QUEUE:
1150                 QueueSelect = QSLT_BK;
1151                 break;
1152
1153         case VO_QUEUE:
1154                 QueueSelect = QSLT_VO;
1155                 break;
1156
1157         case VI_QUEUE:
1158                 QueueSelect = QSLT_VI;
1159                 break;
1160         case MGNT_QUEUE:
1161                 QueueSelect = QSLT_MGNT;
1162                 break;
1163         case BEACON_QUEUE:
1164                 QueueSelect = QSLT_BEACON;
1165                 break;
1166         case TXCMD_QUEUE:
1167                 QueueSelect = QSLT_CMD;
1168                 break;
1169         case HIGH_QUEUE:
1170                 QueueSelect = QSLT_HIGH;
1171                 break;
1172         default:
1173                 netdev_warn(dev, "%s(): Impossible Queue Selection: %d\n",
1174                             __func__, QueueID);
1175                 break;
1176         }
1177         return QueueSelect;
1178 }
1179
1180 static u8 rtl8192_QueryIsShort(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc)
1181 {
1182         u8   tmp_Short;
1183
1184         tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) :
1185                         ((tcb_desc->bUseShortPreamble) ? 1 : 0);
1186         if (TxHT == 1 && TxRate != DESC90_RATEMCS15)
1187                 tmp_Short = 0;
1188
1189         return tmp_Short;
1190 }
1191
1192 void  rtl92e_fill_tx_desc(struct net_device *dev, struct tx_desc *pdesc,
1193                           struct cb_desc *cb_desc, struct sk_buff *skb)
1194 {
1195         struct r8192_priv *priv = rtllib_priv(dev);
1196         dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1197                          PCI_DMA_TODEVICE);
1198         struct tx_fwinfo_8190pci *pTxFwInfo = NULL;
1199
1200         pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data;
1201         memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci));
1202         pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0;
1203         pTxFwInfo->TxRate = MRateToHwRate8190Pci((u8)cb_desc->data_rate);
1204         pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur;
1205         pTxFwInfo->Short = rtl8192_QueryIsShort(pTxFwInfo->TxHT,
1206                                                 pTxFwInfo->TxRate,
1207                                                 cb_desc);
1208
1209         if (pci_dma_mapping_error(priv->pdev, mapping))
1210                 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1211         if (cb_desc->bAMPDUEnable) {
1212                 pTxFwInfo->AllowAggregation = 1;
1213                 pTxFwInfo->RxMF = cb_desc->ampdu_factor;
1214                 pTxFwInfo->RxAMD = cb_desc->ampdu_density;
1215         } else {
1216                 pTxFwInfo->AllowAggregation = 0;
1217                 pTxFwInfo->RxMF = 0;
1218                 pTxFwInfo->RxAMD = 0;
1219         }
1220
1221         pTxFwInfo->RtsEnable =  (cb_desc->bRTSEnable) ? 1 : 0;
1222         pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0;
1223         pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0;
1224         pTxFwInfo->RtsHT = (cb_desc->rts_rate&0x80) ? 1 : 0;
1225         pTxFwInfo->RtsRate = MRateToHwRate8190Pci((u8)cb_desc->rts_rate);
1226         pTxFwInfo->RtsBandwidth = 0;
1227         pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC;
1228         pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ?
1229                           (cb_desc->bRTSUseShortPreamble ? 1 : 0) :
1230                           (cb_desc->bRTSUseShortGI ? 1 : 0);
1231         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40) {
1232                 if (cb_desc->bPacketBW) {
1233                         pTxFwInfo->TxBandwidth = 1;
1234                         pTxFwInfo->TxSubCarrier = 0;
1235                 } else {
1236                         pTxFwInfo->TxBandwidth = 0;
1237                         pTxFwInfo->TxSubCarrier = priv->nCur40MhzPrimeSC;
1238                 }
1239         } else {
1240                 pTxFwInfo->TxBandwidth = 0;
1241                 pTxFwInfo->TxSubCarrier = 0;
1242         }
1243
1244         memset((u8 *)pdesc, 0, 12);
1245         pdesc->LINIP = 0;
1246         pdesc->CmdInit = 1;
1247         pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1248         pdesc->PktSize = (u16)skb->len-sizeof(struct tx_fwinfo_8190pci);
1249
1250         pdesc->SecCAMID = 0;
1251         pdesc->RATid = cb_desc->RATRIndex;
1252
1253
1254         pdesc->NoEnc = 1;
1255         pdesc->SecType = 0x0;
1256         if (cb_desc->bHwSec) {
1257                 static u8 tmp;
1258
1259                 if (!tmp) {
1260                         RT_TRACE(COMP_DBG, "==>================hw sec\n");
1261                         tmp = 1;
1262                 }
1263                 switch (priv->rtllib->pairwise_key_type) {
1264                 case KEY_TYPE_WEP40:
1265                 case KEY_TYPE_WEP104:
1266                         pdesc->SecType = 0x1;
1267                         pdesc->NoEnc = 0;
1268                         break;
1269                 case KEY_TYPE_TKIP:
1270                         pdesc->SecType = 0x2;
1271                         pdesc->NoEnc = 0;
1272                         break;
1273                 case KEY_TYPE_CCMP:
1274                         pdesc->SecType = 0x3;
1275                         pdesc->NoEnc = 0;
1276                         break;
1277                 case KEY_TYPE_NA:
1278                         pdesc->SecType = 0x0;
1279                         pdesc->NoEnc = 1;
1280                         break;
1281                 }
1282         }
1283
1284         pdesc->PktId = 0x0;
1285
1286         pdesc->QueueSelect = rtl8192_MapHwQueueToFirmwareQueue(dev,
1287                                                 cb_desc->queue_index,
1288                                                 cb_desc->priority);
1289         pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci);
1290
1291         pdesc->DISFB = cb_desc->bTxDisableRateFallBack;
1292         pdesc->USERATE = cb_desc->bTxUseDriverAssingedRate;
1293
1294         pdesc->FirstSeg = 1;
1295         pdesc->LastSeg = 1;
1296         pdesc->TxBufferSize = skb->len;
1297
1298         pdesc->TxBuffAddr = mapping;
1299 }
1300
1301 void  rtl92e_fill_tx_cmd_desc(struct net_device *dev, struct tx_desc_cmd *entry,
1302                               struct cb_desc *cb_desc, struct sk_buff *skb)
1303 {
1304         struct r8192_priv *priv = rtllib_priv(dev);
1305         dma_addr_t mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1306                          PCI_DMA_TODEVICE);
1307
1308         if (pci_dma_mapping_error(priv->pdev, mapping))
1309                 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1310         memset(entry, 0, 12);
1311         entry->LINIP = cb_desc->bLastIniPkt;
1312         entry->FirstSeg = 1;
1313         entry->LastSeg = 1;
1314         if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) {
1315                 entry->CmdInit = DESC_PACKET_TYPE_INIT;
1316         } else {
1317                 struct tx_desc *entry_tmp = (struct tx_desc *)entry;
1318
1319                 entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL;
1320                 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1321                 entry_tmp->PktSize = (u16)(cb_desc->pkt_size +
1322                                       entry_tmp->Offset);
1323                 entry_tmp->QueueSelect = QSLT_CMD;
1324                 entry_tmp->TxFWInfoSize = 0x08;
1325                 entry_tmp->RATid = (u8)DESC_PACKET_TYPE_INIT;
1326         }
1327         entry->TxBufferSize = skb->len;
1328         entry->TxBuffAddr = mapping;
1329         entry->OWN = 1;
1330 }
1331
1332 static u8 HwRateToMRate90(bool bIsHT, u8 rate)
1333 {
1334         u8  ret_rate = 0x02;
1335
1336         if (!bIsHT) {
1337                 switch (rate) {
1338                 case DESC90_RATE1M:
1339                         ret_rate = MGN_1M;
1340                         break;
1341                 case DESC90_RATE2M:
1342                         ret_rate = MGN_2M;
1343                         break;
1344                 case DESC90_RATE5_5M:
1345                         ret_rate = MGN_5_5M;
1346                         break;
1347                 case DESC90_RATE11M:
1348                         ret_rate = MGN_11M;
1349                         break;
1350                 case DESC90_RATE6M:
1351                         ret_rate = MGN_6M;
1352                         break;
1353                 case DESC90_RATE9M:
1354                         ret_rate = MGN_9M;
1355                         break;
1356                 case DESC90_RATE12M:
1357                         ret_rate = MGN_12M;
1358                         break;
1359                 case DESC90_RATE18M:
1360                         ret_rate = MGN_18M;
1361                         break;
1362                 case DESC90_RATE24M:
1363                         ret_rate = MGN_24M;
1364                         break;
1365                 case DESC90_RATE36M:
1366                         ret_rate = MGN_36M;
1367                         break;
1368                 case DESC90_RATE48M:
1369                         ret_rate = MGN_48M;
1370                         break;
1371                 case DESC90_RATE54M:
1372                         ret_rate = MGN_54M;
1373                         break;
1374
1375                 default:
1376                         RT_TRACE(COMP_RECV,
1377                                  "HwRateToMRate90(): Non supportedRate [%x], bIsHT = %d!!!\n",
1378                                  rate, bIsHT);
1379                         break;
1380                 }
1381
1382         } else {
1383                 switch (rate) {
1384                 case DESC90_RATEMCS0:
1385                         ret_rate = MGN_MCS0;
1386                         break;
1387                 case DESC90_RATEMCS1:
1388                         ret_rate = MGN_MCS1;
1389                         break;
1390                 case DESC90_RATEMCS2:
1391                         ret_rate = MGN_MCS2;
1392                         break;
1393                 case DESC90_RATEMCS3:
1394                         ret_rate = MGN_MCS3;
1395                         break;
1396                 case DESC90_RATEMCS4:
1397                         ret_rate = MGN_MCS4;
1398                         break;
1399                 case DESC90_RATEMCS5:
1400                         ret_rate = MGN_MCS5;
1401                         break;
1402                 case DESC90_RATEMCS6:
1403                         ret_rate = MGN_MCS6;
1404                         break;
1405                 case DESC90_RATEMCS7:
1406                         ret_rate = MGN_MCS7;
1407                         break;
1408                 case DESC90_RATEMCS8:
1409                         ret_rate = MGN_MCS8;
1410                         break;
1411                 case DESC90_RATEMCS9:
1412                         ret_rate = MGN_MCS9;
1413                         break;
1414                 case DESC90_RATEMCS10:
1415                         ret_rate = MGN_MCS10;
1416                         break;
1417                 case DESC90_RATEMCS11:
1418                         ret_rate = MGN_MCS11;
1419                         break;
1420                 case DESC90_RATEMCS12:
1421                         ret_rate = MGN_MCS12;
1422                         break;
1423                 case DESC90_RATEMCS13:
1424                         ret_rate = MGN_MCS13;
1425                         break;
1426                 case DESC90_RATEMCS14:
1427                         ret_rate = MGN_MCS14;
1428                         break;
1429                 case DESC90_RATEMCS15:
1430                         ret_rate = MGN_MCS15;
1431                         break;
1432                 case DESC90_RATEMCS32:
1433                         ret_rate = (0x80|0x20);
1434                         break;
1435
1436                 default:
1437                         RT_TRACE(COMP_RECV,
1438                                  "HwRateToMRate90(): Non supported Rate [%x], bIsHT = %d!!!\n",
1439                                  rate, bIsHT);
1440                         break;
1441                 }
1442         }
1443
1444         return ret_rate;
1445 }
1446
1447 static long rtl8192_signal_scale_mapping(struct r8192_priv *priv, long currsig)
1448 {
1449         long retsig;
1450
1451         if (currsig >= 61 && currsig <= 100)
1452                 retsig = 90 + ((currsig - 60) / 4);
1453         else if (currsig >= 41 && currsig <= 60)
1454                 retsig = 78 + ((currsig - 40) / 2);
1455         else if (currsig >= 31 && currsig <= 40)
1456                 retsig = 66 + (currsig - 30);
1457         else if (currsig >= 21 && currsig <= 30)
1458                 retsig = 54 + (currsig - 20);
1459         else if (currsig >= 5 && currsig <= 20)
1460                 retsig = 42 + (((currsig - 5) * 2) / 3);
1461         else if (currsig == 4)
1462                 retsig = 36;
1463         else if (currsig == 3)
1464                 retsig = 27;
1465         else if (currsig == 2)
1466                 retsig = 18;
1467         else if (currsig == 1)
1468                 retsig = 9;
1469         else
1470                 retsig = currsig;
1471
1472         return retsig;
1473 }
1474
1475
1476 #define  rx_hal_is_cck_rate(_pdrvinfo)\
1477                         ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
1478                         _pdrvinfo->RxRate == DESC90_RATE2M ||\
1479                         _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
1480                         _pdrvinfo->RxRate == DESC90_RATE11M) &&\
1481                         !_pdrvinfo->RxHT)
1482
1483 static void rtl8192_query_rxphystatus(
1484         struct r8192_priv *priv,
1485         struct rtllib_rx_stats *pstats,
1486         struct rx_desc  *pdesc,
1487         struct rx_fwinfo   *pdrvinfo,
1488         struct rtllib_rx_stats *precord_stats,
1489         bool bpacket_match_bssid,
1490         bool bpacket_toself,
1491         bool bPacketBeacon,
1492         bool bToSelfBA
1493         )
1494 {
1495         struct phy_sts_ofdm_819xpci *pofdm_buf;
1496         struct phy_sts_cck_819xpci *pcck_buf;
1497         struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *prxsc;
1498         u8 *prxpkt;
1499         u8 i, max_spatial_stream, tmp_rxsnr, tmp_rxevm, rxsc_sgien_exflg;
1500         char rx_pwr[4], rx_pwr_all = 0;
1501         char rx_snrX, rx_evmX;
1502         u8 evm, pwdb_all;
1503         u32 RSSI, total_rssi = 0;
1504         u8 is_cck_rate = 0;
1505         u8 rf_rx_num = 0;
1506         static  u8 check_reg824;
1507         static  u32 reg824_bit9;
1508
1509         priv->stats.numqry_phystatus++;
1510
1511         is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
1512         memset(precord_stats, 0, sizeof(struct rtllib_rx_stats));
1513         pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID =
1514                                     bpacket_match_bssid;
1515         pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
1516         pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;
1517         pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
1518         pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
1519         if (check_reg824 == 0) {
1520                 reg824_bit9 = rtl92e_get_bb_reg(priv->rtllib->dev,
1521                                                 rFPGA0_XA_HSSIParameter2,
1522                                                 0x200);
1523                 check_reg824 = 1;
1524         }
1525
1526
1527         prxpkt = (u8 *)pdrvinfo;
1528
1529         prxpkt += sizeof(struct rx_fwinfo);
1530
1531         pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt;
1532         pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt;
1533
1534         pstats->RxMIMOSignalQuality[0] = -1;
1535         pstats->RxMIMOSignalQuality[1] = -1;
1536         precord_stats->RxMIMOSignalQuality[0] = -1;
1537         precord_stats->RxMIMOSignalQuality[1] = -1;
1538
1539         if (is_cck_rate) {
1540                 u8 report;
1541
1542                 priv->stats.numqry_phystatusCCK++;
1543                 if (!reg824_bit9) {
1544                         report = pcck_buf->cck_agc_rpt & 0xc0;
1545                         report >>= 6;
1546                         switch (report) {
1547                         case 0x3:
1548                                 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt &
1549                                              0x3e);
1550                                 break;
1551                         case 0x2:
1552                                 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt &
1553                                              0x3e);
1554                                 break;
1555                         case 0x1:
1556                                 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt &
1557                                              0x3e);
1558                                 break;
1559                         case 0x0:
1560                                 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);
1561                                 break;
1562                         }
1563                 } else {
1564                         report = pcck_buf->cck_agc_rpt & 0x60;
1565                         report >>= 5;
1566                         switch (report) {
1567                         case 0x3:
1568                                 rx_pwr_all = -35 -
1569                                         ((pcck_buf->cck_agc_rpt &
1570                                         0x1f) << 1);
1571                                 break;
1572                         case 0x2:
1573                                 rx_pwr_all = -23 -
1574                                         ((pcck_buf->cck_agc_rpt &
1575                                          0x1f) << 1);
1576                                 break;
1577                         case 0x1:
1578                                 rx_pwr_all = -11 -
1579                                          ((pcck_buf->cck_agc_rpt &
1580                                          0x1f) << 1);
1581                                 break;
1582                         case 0x0:
1583                                 rx_pwr_all = -8 -
1584                                          ((pcck_buf->cck_agc_rpt &
1585                                          0x1f) << 1);
1586                                 break;
1587                         }
1588                 }
1589
1590                 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1591                 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1592                 pstats->RecvSignalPower = rx_pwr_all;
1593
1594                 if (bpacket_match_bssid) {
1595                         u8      sq;
1596
1597                         if (pstats->RxPWDBAll > 40) {
1598                                 sq = 100;
1599                         } else {
1600                                 sq = pcck_buf->sq_rpt;
1601
1602                                 if (pcck_buf->sq_rpt > 64)
1603                                         sq = 0;
1604                                 else if (pcck_buf->sq_rpt < 20)
1605                                         sq = 100;
1606                                 else
1607                                         sq = ((64-sq) * 100) / 44;
1608                         }
1609                         pstats->SignalQuality = sq;
1610                         precord_stats->SignalQuality = sq;
1611                         pstats->RxMIMOSignalQuality[0] = sq;
1612                         precord_stats->RxMIMOSignalQuality[0] = sq;
1613                         pstats->RxMIMOSignalQuality[1] = -1;
1614                         precord_stats->RxMIMOSignalQuality[1] = -1;
1615                 }
1616         } else {
1617                 priv->stats.numqry_phystatusHT++;
1618                 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
1619                         if (priv->brfpath_rxenable[i])
1620                                 rf_rx_num++;
1621
1622                         rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) *
1623                                      2) - 110;
1624
1625                         tmp_rxsnr = pofdm_buf->rxsnr_X[i];
1626                         rx_snrX = (char)(tmp_rxsnr);
1627                         rx_snrX /= 2;
1628                         priv->stats.rxSNRdB[i] = (long)rx_snrX;
1629
1630                         RSSI = rtl92e_rx_db_to_percent(rx_pwr[i]);
1631                         if (priv->brfpath_rxenable[i])
1632                                 total_rssi += RSSI;
1633
1634                         if (bpacket_match_bssid) {
1635                                 pstats->RxMIMOSignalStrength[i] = (u8) RSSI;
1636                                 precord_stats->RxMIMOSignalStrength[i] =
1637                                                                 (u8) RSSI;
1638                         }
1639                 }
1640
1641
1642                 rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106;
1643                 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1644
1645                 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1646                 pstats->RxPower = precord_stats->RxPower =      rx_pwr_all;
1647                 pstats->RecvSignalPower = rx_pwr_all;
1648                 if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 &&
1649                     pdrvinfo->RxRate <= DESC90_RATEMCS15)
1650                         max_spatial_stream = 2;
1651                 else
1652                         max_spatial_stream = 1;
1653
1654                 for (i = 0; i < max_spatial_stream; i++) {
1655                         tmp_rxevm = pofdm_buf->rxevm_X[i];
1656                         rx_evmX = (char)(tmp_rxevm);
1657
1658                         rx_evmX /= 2;
1659
1660                         evm = rtl92e_evm_db_to_percent(rx_evmX);
1661                         if (bpacket_match_bssid) {
1662                                 if (i == 0) {
1663                                         pstats->SignalQuality = (u8)(evm &
1664                                                                  0xff);
1665                                         precord_stats->SignalQuality = (u8)(evm
1666                                                                         & 0xff);
1667                                 }
1668                                 pstats->RxMIMOSignalQuality[i] = (u8)(evm &
1669                                                                  0xff);
1670                                 precord_stats->RxMIMOSignalQuality[i] = (u8)(evm
1671                                                                         & 0xff);
1672                         }
1673                 }
1674
1675
1676                 rxsc_sgien_exflg = pofdm_buf->rxsc_sgien_exflg;
1677                 prxsc = (struct phy_ofdm_rx_status_rxsc_sgien_exintfflag *)
1678                         &rxsc_sgien_exflg;
1679                 if (pdrvinfo->BW)
1680                         priv->stats.received_bwtype[1+prxsc->rxsc]++;
1681                 else
1682                         priv->stats.received_bwtype[0]++;
1683         }
1684
1685         if (is_cck_rate) {
1686                 pstats->SignalStrength = precord_stats->SignalStrength =
1687                                          (u8)(rtl8192_signal_scale_mapping(priv,
1688                                          (long)pwdb_all));
1689
1690         } else {
1691                 if (rf_rx_num != 0)
1692                         pstats->SignalStrength = precord_stats->SignalStrength =
1693                                          (u8)(rtl8192_signal_scale_mapping(priv,
1694                                          (long)(total_rssi /= rf_rx_num)));
1695         }
1696 }
1697
1698 static void rtl8192_process_phyinfo(struct r8192_priv *priv, u8 *buffer,
1699                                     struct rtllib_rx_stats *prev_st,
1700                                     struct rtllib_rx_stats *curr_st)
1701 {
1702         bool bcheck = false;
1703         u8      rfpath;
1704         u32 ij, tmp_val;
1705         static u32 slide_rssi_index, slide_rssi_statistics;
1706         static u32 slide_evm_index, slide_evm_statistics;
1707         static u32 last_rssi, last_evm;
1708         static u32 slide_beacon_adc_pwdb_index;
1709         static u32 slide_beacon_adc_pwdb_statistics;
1710         static u32 last_beacon_adc_pwdb;
1711         struct rtllib_hdr_3addr *hdr;
1712         u16 sc;
1713         unsigned int frag, seq;
1714
1715         hdr = (struct rtllib_hdr_3addr *)buffer;
1716         sc = le16_to_cpu(hdr->seq_ctl);
1717         frag = WLAN_GET_SEQ_FRAG(sc);
1718         seq = WLAN_GET_SEQ_SEQ(sc);
1719         curr_st->Seq_Num = seq;
1720         if (!prev_st->bIsAMPDU)
1721                 bcheck = true;
1722
1723         if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1724                 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
1725                 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
1726                 priv->stats.slide_rssi_total -= last_rssi;
1727         }
1728         priv->stats.slide_rssi_total += prev_st->SignalStrength;
1729
1730         priv->stats.slide_signal_strength[slide_rssi_index++] =
1731                                          prev_st->SignalStrength;
1732         if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
1733                 slide_rssi_index = 0;
1734
1735         tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
1736         priv->stats.signal_strength = rtl92e_translate_to_dbm(priv,
1737                                                               (u8)tmp_val);
1738         curr_st->rssi = priv->stats.signal_strength;
1739         if (!prev_st->bPacketMatchBSSID) {
1740                 if (!prev_st->bToSelfBA)
1741                         return;
1742         }
1743
1744         if (!bcheck)
1745                 return;
1746
1747         priv->stats.num_process_phyinfo++;
1748         if (!prev_st->bIsCCK && prev_st->bPacketToSelf) {
1749                 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) {
1750                         if (!rtl92e_is_legal_rf_path(priv->rtllib->dev, rfpath))
1751                                 continue;
1752                         RT_TRACE(COMP_DBG,
1753                                  "Jacken -> pPreviousstats->RxMIMOSignalStrength[rfpath]  = %d\n",
1754                                  prev_st->RxMIMOSignalStrength[rfpath]);
1755                         if (priv->stats.rx_rssi_percentage[rfpath] == 0) {
1756                                 priv->stats.rx_rssi_percentage[rfpath] =
1757                                          prev_st->RxMIMOSignalStrength[rfpath];
1758                         }
1759                         if (prev_st->RxMIMOSignalStrength[rfpath]  >
1760                             priv->stats.rx_rssi_percentage[rfpath]) {
1761                                 priv->stats.rx_rssi_percentage[rfpath] =
1762                                         ((priv->stats.rx_rssi_percentage[rfpath]
1763                                         * (RX_SMOOTH - 1)) +
1764                                         (prev_st->RxMIMOSignalStrength
1765                                         [rfpath])) / (RX_SMOOTH);
1766                                 priv->stats.rx_rssi_percentage[rfpath] =
1767                                          priv->stats.rx_rssi_percentage[rfpath]
1768                                          + 1;
1769                         } else {
1770                                 priv->stats.rx_rssi_percentage[rfpath] =
1771                                    ((priv->stats.rx_rssi_percentage[rfpath] *
1772                                    (RX_SMOOTH-1)) +
1773                                    (prev_st->RxMIMOSignalStrength[rfpath])) /
1774                                    (RX_SMOOTH);
1775                         }
1776                         RT_TRACE(COMP_DBG,
1777                                  "Jacken -> priv->RxStats.RxRSSIPercentage[rfPath]  = %d\n",
1778                                  priv->stats.rx_rssi_percentage[rfpath]);
1779                 }
1780         }
1781
1782
1783         if (prev_st->bPacketBeacon) {
1784                 if (slide_beacon_adc_pwdb_statistics++ >=
1785                     PHY_Beacon_RSSI_SLID_WIN_MAX) {
1786                         slide_beacon_adc_pwdb_statistics =
1787                                          PHY_Beacon_RSSI_SLID_WIN_MAX;
1788                         last_beacon_adc_pwdb = priv->stats.Slide_Beacon_pwdb
1789                                                [slide_beacon_adc_pwdb_index];
1790                         priv->stats.Slide_Beacon_Total -= last_beacon_adc_pwdb;
1791                 }
1792                 priv->stats.Slide_Beacon_Total += prev_st->RxPWDBAll;
1793                 priv->stats.Slide_Beacon_pwdb[slide_beacon_adc_pwdb_index] =
1794                                                          prev_st->RxPWDBAll;
1795                 slide_beacon_adc_pwdb_index++;
1796                 if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
1797                         slide_beacon_adc_pwdb_index = 0;
1798                 prev_st->RxPWDBAll = priv->stats.Slide_Beacon_Total /
1799                                      slide_beacon_adc_pwdb_statistics;
1800                 if (prev_st->RxPWDBAll >= 3)
1801                         prev_st->RxPWDBAll -= 3;
1802         }
1803
1804         RT_TRACE(COMP_RXDESC, "Smooth %s PWDB = %d\n",
1805                                 prev_st->bIsCCK ? "CCK" : "OFDM",
1806                                 prev_st->RxPWDBAll);
1807
1808         if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1809             prev_st->bToSelfBA) {
1810                 if (priv->undecorated_smoothed_pwdb < 0)
1811                         priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll;
1812                 if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) {
1813                         priv->undecorated_smoothed_pwdb =
1814                                         (((priv->undecorated_smoothed_pwdb) *
1815                                         (RX_SMOOTH-1)) +
1816                                         (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1817                         priv->undecorated_smoothed_pwdb =
1818                                          priv->undecorated_smoothed_pwdb + 1;
1819                 } else {
1820                         priv->undecorated_smoothed_pwdb =
1821                                         (((priv->undecorated_smoothed_pwdb) *
1822                                         (RX_SMOOTH-1)) +
1823                                         (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1824                 }
1825                 rtl92e_update_rx_statistics(priv, prev_st);
1826         }
1827
1828         if (prev_st->SignalQuality != 0) {
1829                 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1830                     prev_st->bToSelfBA) {
1831                         if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1832                                 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
1833                                 last_evm =
1834                                          priv->stats.slide_evm[slide_evm_index];
1835                                 priv->stats.slide_evm_total -= last_evm;
1836                         }
1837
1838                         priv->stats.slide_evm_total += prev_st->SignalQuality;
1839
1840                         priv->stats.slide_evm[slide_evm_index++] =
1841                                                  prev_st->SignalQuality;
1842                         if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
1843                                 slide_evm_index = 0;
1844
1845                         tmp_val = priv->stats.slide_evm_total /
1846                                   slide_evm_statistics;
1847                         priv->stats.signal_quality = tmp_val;
1848                         priv->stats.last_signal_strength_inpercent = tmp_val;
1849                 }
1850
1851                 if (prev_st->bPacketToSelf ||
1852                     prev_st->bPacketBeacon ||
1853                     prev_st->bToSelfBA) {
1854                         for (ij = 0; ij < 2; ij++) {
1855                                 if (prev_st->RxMIMOSignalQuality[ij] != -1) {
1856                                         if (priv->stats.rx_evm_percentage[ij] == 0)
1857                                                 priv->stats.rx_evm_percentage[ij] =
1858                                                    prev_st->RxMIMOSignalQuality[ij];
1859                                         priv->stats.rx_evm_percentage[ij] =
1860                                           ((priv->stats.rx_evm_percentage[ij] *
1861                                           (RX_SMOOTH - 1)) +
1862                                           (prev_st->RxMIMOSignalQuality[ij])) /
1863                                           (RX_SMOOTH);
1864                                 }
1865                         }
1866                 }
1867         }
1868 }
1869
1870 static void rtl8192_TranslateRxSignalStuff(struct net_device *dev,
1871                                            struct sk_buff *skb,
1872                                            struct rtllib_rx_stats *pstats,
1873                                            struct rx_desc *pdesc,
1874                                            struct rx_fwinfo *pdrvinfo)
1875 {
1876         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1877         bool bpacket_match_bssid, bpacket_toself;
1878         bool bPacketBeacon = false;
1879         struct rtllib_hdr_3addr *hdr;
1880         bool bToSelfBA = false;
1881         static struct rtllib_rx_stats  previous_stats;
1882         u16 fc, type;
1883         u8 *tmp_buf;
1884         u8 *praddr;
1885
1886         tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift;
1887
1888         hdr = (struct rtllib_hdr_3addr *)tmp_buf;
1889         fc = le16_to_cpu(hdr->frame_ctl);
1890         type = WLAN_FC_GET_TYPE(fc);
1891         praddr = hdr->addr1;
1892
1893         bpacket_match_bssid =
1894                 ((RTLLIB_FTYPE_CTL != type) &&
1895                  ether_addr_equal(priv->rtllib->current_network.bssid,
1896                                   (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 :
1897                                   (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 :
1898                                   hdr->addr3) &&
1899                  (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV));
1900         bpacket_toself = bpacket_match_bssid &&         /* check this */
1901                          ether_addr_equal(praddr, priv->rtllib->dev->dev_addr);
1902         if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON)
1903                 bPacketBeacon = true;
1904         if (bpacket_match_bssid)
1905                 priv->stats.numpacket_matchbssid++;
1906         if (bpacket_toself)
1907                 priv->stats.numpacket_toself++;
1908         rtl8192_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
1909         rtl8192_query_rxphystatus(priv, pstats, pdesc, pdrvinfo,
1910                                   &previous_stats, bpacket_match_bssid,
1911                                   bpacket_toself, bPacketBeacon, bToSelfBA);
1912         rtl92e_copy_mpdu_stats(pstats, &previous_stats);
1913 }
1914
1915 static void rtl8192_UpdateReceivedRateHistogramStatistics(
1916                                            struct net_device *dev,
1917                                            struct rtllib_rx_stats *pstats)
1918 {
1919         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1920         u32 rcvType = 1;
1921         u32 rateIndex;
1922         u32 preamble_guardinterval;
1923
1924         if (pstats->bCRC)
1925                 rcvType = 2;
1926         else if (pstats->bICV)
1927                 rcvType = 3;
1928
1929         if (pstats->bShortPreamble)
1930                 preamble_guardinterval = 1;
1931         else
1932                 preamble_guardinterval = 0;
1933
1934         switch (pstats->rate) {
1935         case MGN_1M:
1936                 rateIndex = 0;
1937                 break;
1938         case MGN_2M:
1939                 rateIndex = 1;
1940                  break;
1941         case MGN_5_5M:
1942                 rateIndex = 2;
1943                 break;
1944         case MGN_11M:
1945                 rateIndex = 3;
1946                 break;
1947         case MGN_6M:
1948                 rateIndex = 4;
1949                 break;
1950         case MGN_9M:
1951                 rateIndex = 5;
1952                 break;
1953         case MGN_12M:
1954                 rateIndex = 6;
1955                 break;
1956         case MGN_18M:
1957                 rateIndex = 7;
1958                  break;
1959         case MGN_24M:
1960                 rateIndex = 8;
1961                 break;
1962         case MGN_36M:
1963                 rateIndex = 9;
1964                 break;
1965         case MGN_48M:
1966                 rateIndex = 10;
1967                 break;
1968         case MGN_54M:
1969                 rateIndex = 11;
1970                 break;
1971         case MGN_MCS0:
1972                 rateIndex = 12;
1973                 break;
1974         case MGN_MCS1:
1975                 rateIndex = 13;
1976                 break;
1977         case MGN_MCS2:
1978                 rateIndex = 14;
1979                 break;
1980         case MGN_MCS3:
1981                 rateIndex = 15;
1982                 break;
1983         case MGN_MCS4:
1984                 rateIndex = 16;
1985                 break;
1986         case MGN_MCS5:
1987                 rateIndex = 17;
1988                 break;
1989         case MGN_MCS6:
1990                 rateIndex = 18;
1991                 break;
1992         case MGN_MCS7:
1993                 rateIndex = 19;
1994                 break;
1995         case MGN_MCS8:
1996                 rateIndex = 20;
1997                 break;
1998         case MGN_MCS9:
1999                 rateIndex = 21;
2000                 break;
2001         case MGN_MCS10:
2002                 rateIndex = 22;
2003                 break;
2004         case MGN_MCS11:
2005                 rateIndex = 23;
2006                 break;
2007         case MGN_MCS12:
2008                 rateIndex = 24;
2009                 break;
2010         case MGN_MCS13:
2011                 rateIndex = 25;
2012                 break;
2013         case MGN_MCS14:
2014                 rateIndex = 26;
2015                 break;
2016         case MGN_MCS15:
2017                 rateIndex = 27;
2018                 break;
2019         default:
2020                 rateIndex = 28;
2021                 break;
2022         }
2023         priv->stats.received_preamble_GI[preamble_guardinterval][rateIndex]++;
2024         priv->stats.received_rate_histogram[0][rateIndex]++;
2025         priv->stats.received_rate_histogram[rcvType][rateIndex]++;
2026 }
2027
2028 bool rtl92e_get_rx_stats(struct net_device *dev, struct rtllib_rx_stats *stats,
2029                          struct rx_desc *pdesc, struct sk_buff *skb)
2030 {
2031         struct r8192_priv *priv = rtllib_priv(dev);
2032         struct rx_fwinfo *pDrvInfo = NULL;
2033
2034         stats->bICV = pdesc->ICV;
2035         stats->bCRC = pdesc->CRC32;
2036         stats->bHwError = pdesc->CRC32 | pdesc->ICV;
2037
2038         stats->Length = pdesc->Length;
2039         if (stats->Length < 24)
2040                 stats->bHwError |= 1;
2041
2042         if (stats->bHwError) {
2043                 stats->bShift = false;
2044
2045                 if (pdesc->CRC32) {
2046                         if (pdesc->Length < 500)
2047                                 priv->stats.rxcrcerrmin++;
2048                         else if (pdesc->Length > 1000)
2049                                 priv->stats.rxcrcerrmax++;
2050                         else
2051                                 priv->stats.rxcrcerrmid++;
2052                 }
2053                 return false;
2054         }
2055
2056         stats->RxDrvInfoSize = pdesc->RxDrvInfoSize;
2057         stats->RxBufShift = ((pdesc->Shift)&0x03);
2058         stats->Decrypted = !pdesc->SWDec;
2059
2060         pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift);
2061
2062         stats->rate = HwRateToMRate90((bool)pDrvInfo->RxHT,
2063                                      (u8)pDrvInfo->RxRate);
2064         stats->bShortPreamble = pDrvInfo->SPLCP;
2065
2066         rtl8192_UpdateReceivedRateHistogramStatistics(dev, stats);
2067
2068         stats->bIsAMPDU = (pDrvInfo->PartAggr == 1);
2069         stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) &&
2070                             (pDrvInfo->FirstAGGR == 1);
2071
2072         stats->TimeStampLow = pDrvInfo->TSFL;
2073         stats->TimeStampHigh = rtl92e_readl(dev, TSFR+4);
2074
2075         rtl92e_update_rx_pkt_timestamp(dev, stats);
2076
2077         if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
2078                 stats->bShift = 1;
2079
2080         stats->RxIs40MHzPacket = pDrvInfo->BW;
2081
2082         rtl8192_TranslateRxSignalStuff(dev, skb, stats, pdesc,
2083                                        pDrvInfo);
2084
2085         if (pDrvInfo->FirstAGGR == 1 || pDrvInfo->PartAggr == 1)
2086                 RT_TRACE(COMP_RXDESC,
2087                          "pDrvInfo->FirstAGGR = %d, pDrvInfo->PartAggr = %d\n",
2088                          pDrvInfo->FirstAGGR, pDrvInfo->PartAggr);
2089         skb_trim(skb, skb->len - 4/*sCrcLng*/);
2090
2091
2092         stats->packetlength = stats->Length-4;
2093         stats->fraglength = stats->packetlength;
2094         stats->fragoffset = 0;
2095         stats->ntotalfrag = 1;
2096         return true;
2097 }
2098
2099 void rtl92e_stop_adapter(struct net_device *dev, bool reset)
2100 {
2101         struct r8192_priv *priv = rtllib_priv(dev);
2102         int i;
2103         u8      OpMode;
2104         u8      u1bTmp;
2105         u32     ulRegRead;
2106
2107         OpMode = RT_OP_MODE_NO_LINK;
2108         priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode);
2109
2110         if (!priv->rtllib->bSupportRemoteWakeUp) {
2111                 u1bTmp = 0x0;
2112                 rtl92e_writeb(dev, CMDR, u1bTmp);
2113         }
2114
2115         mdelay(20);
2116
2117         if (!reset) {
2118                 mdelay(150);
2119
2120                 priv->bHwRfOffAction = 2;
2121
2122                 if (!priv->rtllib->bSupportRemoteWakeUp) {
2123                         rtl92e_set_rf_off(dev);
2124                         ulRegRead = rtl92e_readl(dev, CPU_GEN);
2125                         ulRegRead |= CPU_GEN_SYSTEM_RESET;
2126                         rtl92e_writel(dev, CPU_GEN, ulRegRead);
2127                 } else {
2128                         rtl92e_writel(dev, WFCRC0, 0xffffffff);
2129                         rtl92e_writel(dev, WFCRC1, 0xffffffff);
2130                         rtl92e_writel(dev, WFCRC2, 0xffffffff);
2131
2132
2133                         rtl92e_writeb(dev, PMR, 0x5);
2134                         rtl92e_writeb(dev, MacBlkCtrl, 0xa);
2135                 }
2136         }
2137
2138         for (i = 0; i < MAX_QUEUE_SIZE; i++)
2139                 skb_queue_purge(&priv->rtllib->skb_waitQ[i]);
2140         for (i = 0; i < MAX_QUEUE_SIZE; i++)
2141                 skb_queue_purge(&priv->rtllib->skb_aggQ[i]);
2142
2143         skb_queue_purge(&priv->skb_queue);
2144 }
2145
2146 void rtl92e_update_ratr_table(struct net_device *dev)
2147 {
2148         struct r8192_priv *priv = rtllib_priv(dev);
2149         struct rtllib_device *ieee = priv->rtllib;
2150         u8 *pMcsRate = ieee->dot11HTOperationalRateSet;
2151         u32 ratr_value = 0;
2152         u16 rate_config = 0;
2153         u8 rate_index = 0;
2154
2155         rtl92e_config_rate(dev, &rate_config);
2156         ratr_value = rate_config | *pMcsRate << 12;
2157         switch (ieee->mode) {
2158         case IEEE_A:
2159                 ratr_value &= 0x00000FF0;
2160                 break;
2161         case IEEE_B:
2162                 ratr_value &= 0x0000000F;
2163                 break;
2164         case IEEE_G:
2165         case IEEE_G|IEEE_B:
2166                 ratr_value &= 0x00000FF7;
2167                 break;
2168         case IEEE_N_24G:
2169         case IEEE_N_5G:
2170                 if (ieee->pHTInfo->PeerMimoPs == 0) {
2171                         ratr_value &= 0x0007F007;
2172                 } else {
2173                         if (priv->rf_type == RF_1T2R)
2174                                 ratr_value &= 0x000FF007;
2175                         else
2176                                 ratr_value &= 0x0F81F007;
2177                 }
2178                 break;
2179         default:
2180                 break;
2181         }
2182         ratr_value &= 0x0FFFFFFF;
2183         if (ieee->pHTInfo->bCurTxBW40MHz &&
2184             ieee->pHTInfo->bCurShortGI40MHz)
2185                 ratr_value |= 0x80000000;
2186         else if (!ieee->pHTInfo->bCurTxBW40MHz &&
2187                   ieee->pHTInfo->bCurShortGI20MHz)
2188                 ratr_value |= 0x80000000;
2189         rtl92e_writel(dev, RATR0+rate_index*4, ratr_value);
2190         rtl92e_writeb(dev, UFWP, 1);
2191 }
2192
2193 void
2194 rtl92e_init_variables(struct net_device  *dev)
2195 {
2196         struct r8192_priv *priv = rtllib_priv(dev);
2197
2198         strcpy(priv->nick, "rtl8192E");
2199
2200         priv->rtllib->softmac_features  = IEEE_SOFTMAC_SCAN |
2201                 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
2202                 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
2203
2204         priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci);
2205
2206         priv->ShortRetryLimit = 0x30;
2207         priv->LongRetryLimit = 0x30;
2208
2209         priv->ReceiveConfig = RCR_ADD3  |
2210                 RCR_AMF | RCR_ADF |
2211                 RCR_AICV |
2212                 RCR_AB | RCR_AM | RCR_APM |
2213                 RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) |
2214                 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT;
2215
2216         priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK |
2217                             IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK |
2218                             IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |
2219                             IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 |
2220                             IMR_RDU | IMR_RXFOVW | IMR_TXFOVW |
2221                             IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
2222
2223         priv->PwrDomainProtect = false;
2224
2225         priv->bfirst_after_down = false;
2226 }
2227
2228 void rtl92e_enable_irq(struct net_device *dev)
2229 {
2230         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2231
2232         priv->irq_enabled = 1;
2233
2234         rtl92e_writel(dev, INTA_MASK, priv->irq_mask[0]);
2235
2236 }
2237
2238 void rtl92e_disable_irq(struct net_device *dev)
2239 {
2240         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2241
2242         rtl92e_writel(dev, INTA_MASK, 0);
2243
2244         priv->irq_enabled = 0;
2245 }
2246
2247 void rtl92e_clear_irq(struct net_device *dev)
2248 {
2249         u32 tmp = 0;
2250
2251         tmp = rtl92e_readl(dev, ISR);
2252         rtl92e_writel(dev, ISR, tmp);
2253 }
2254
2255
2256 void rtl92e_enable_rx(struct net_device *dev)
2257 {
2258         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2259
2260         rtl92e_writel(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]);
2261 }
2262
2263 static const u32 TX_DESC_BASE[] = {
2264         BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA
2265 };
2266
2267 void rtl92e_enable_tx(struct net_device *dev)
2268 {
2269         struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
2270         u32 i;
2271
2272         for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
2273                 rtl92e_writel(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
2274 }
2275
2276
2277 void rtl92e_ack_irq(struct net_device *dev, u32 *p_inta, u32 *p_intb)
2278 {
2279         *p_inta = rtl92e_readl(dev, ISR);
2280         rtl92e_writel(dev, ISR, *p_inta);
2281 }
2282
2283 bool rtl92e_is_rx_stuck(struct net_device *dev)
2284 {
2285         struct r8192_priv *priv = rtllib_priv(dev);
2286         u16               RegRxCounter = rtl92e_readw(dev, 0x130);
2287         bool              bStuck = false;
2288         static u8         rx_chk_cnt;
2289         u32             SlotIndex = 0, TotalRxStuckCount = 0;
2290         u8              i;
2291         u8              SilentResetRxSoltNum = 4;
2292
2293         RT_TRACE(COMP_RESET, "%s(): RegRxCounter is %d, RxCounter is %d\n",
2294                  __func__, RegRxCounter, priv->RxCounter);
2295
2296         rx_chk_cnt++;
2297         if (priv->undecorated_smoothed_pwdb >= (RateAdaptiveTH_High+5)) {
2298                 rx_chk_cnt = 0;
2299         } else if ((priv->undecorated_smoothed_pwdb < (RateAdaptiveTH_High + 5))
2300           && (((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2301           (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_40M))
2302           || ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2303           (priv->undecorated_smoothed_pwdb >= RateAdaptiveTH_Low_20M)))) {
2304                 if (rx_chk_cnt < 2)
2305                         return bStuck;
2306                 rx_chk_cnt = 0;
2307         } else if ((((priv->CurrentChannelBW != HT_CHANNEL_WIDTH_20) &&
2308                   (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_40M)) ||
2309                 ((priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20) &&
2310                  (priv->undecorated_smoothed_pwdb < RateAdaptiveTH_Low_20M))) &&
2311                 priv->undecorated_smoothed_pwdb >= VeryLowRSSI) {
2312                 if (rx_chk_cnt < 4)
2313                         return bStuck;
2314                 rx_chk_cnt = 0;
2315         } else {
2316                 if (rx_chk_cnt < 8)
2317                         return bStuck;
2318                 rx_chk_cnt = 0;
2319         }
2320
2321
2322         SlotIndex = (priv->SilentResetRxSlotIndex++)%SilentResetRxSoltNum;
2323
2324         if (priv->RxCounter == RegRxCounter) {
2325                 priv->SilentResetRxStuckEvent[SlotIndex] = 1;
2326
2327                 for (i = 0; i < SilentResetRxSoltNum; i++)
2328                         TotalRxStuckCount += priv->SilentResetRxStuckEvent[i];
2329
2330                 if (TotalRxStuckCount == SilentResetRxSoltNum) {
2331                         bStuck = true;
2332                         for (i = 0; i < SilentResetRxSoltNum; i++)
2333                                 TotalRxStuckCount +=
2334                                          priv->SilentResetRxStuckEvent[i];
2335                 }
2336
2337
2338         } else {
2339                 priv->SilentResetRxStuckEvent[SlotIndex] = 0;
2340         }
2341
2342         priv->RxCounter = RegRxCounter;
2343
2344         return bStuck;
2345 }
2346
2347 bool rtl92e_is_tx_stuck(struct net_device *dev)
2348 {
2349         struct r8192_priv *priv = rtllib_priv(dev);
2350         bool    bStuck = false;
2351         u16     RegTxCounter = rtl92e_readw(dev, 0x128);
2352
2353         RT_TRACE(COMP_RESET, "%s():RegTxCounter is %d,TxCounter is %d\n",
2354                  __func__, RegTxCounter, priv->TxCounter);
2355
2356         if (priv->TxCounter == RegTxCounter)
2357                 bStuck = true;
2358
2359         priv->TxCounter = RegTxCounter;
2360
2361         return bStuck;
2362 }
2363
2364 bool rtl92e_get_nmode_support_by_sec(struct net_device *dev)
2365 {
2366         struct r8192_priv *priv = rtllib_priv(dev);
2367         struct rtllib_device *ieee = priv->rtllib;
2368
2369         if (ieee->rtllib_ap_sec_type &&
2370            (ieee->rtllib_ap_sec_type(priv->rtllib)&(SEC_ALG_WEP |
2371                                      SEC_ALG_TKIP))) {
2372                 return false;
2373         } else {
2374                 return true;
2375         }
2376 }
2377
2378 bool rtl92e_is_halfn_supported_by_ap(struct net_device *dev)
2379 {
2380         bool Reval;
2381         struct r8192_priv *priv = rtllib_priv(dev);
2382         struct rtllib_device *ieee = priv->rtllib;
2383
2384         if (ieee->bHalfWirelessN24GMode == true)
2385                 Reval = true;
2386         else
2387                 Reval =  false;
2388
2389         return Reval;
2390 }
2391
2392 void ActUpdateChannelAccessSetting(struct net_device *dev,
2393         enum wireless_mode WirelessMode,
2394         struct channel_access_setting *ChnlAccessSetting)
2395 {
2396 }