2 * AD5933 AD5934 Impedance Converter, Network Analyzer
4 * Copyright 2011 Analog Devices Inc.
6 * Licensed under the GPL-2.
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/sysfs.h>
13 #include <linux/i2c.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/slab.h>
16 #include <linux/types.h>
17 #include <linux/err.h>
18 #include <linux/delay.h>
19 #include <linux/module.h>
20 #include <asm/div64.h>
22 #include <linux/iio/iio.h>
23 #include <linux/iio/sysfs.h>
24 #include <linux/iio/buffer.h>
25 #include <linux/iio/kfifo_buf.h>
29 /* AD5933/AD5934 Registers */
30 #define AD5933_REG_CONTROL_HB 0x80 /* R/W, 2 bytes */
31 #define AD5933_REG_CONTROL_LB 0x81 /* R/W, 2 bytes */
32 #define AD5933_REG_FREQ_START 0x82 /* R/W, 3 bytes */
33 #define AD5933_REG_FREQ_INC 0x85 /* R/W, 3 bytes */
34 #define AD5933_REG_INC_NUM 0x88 /* R/W, 2 bytes, 9 bit */
35 #define AD5933_REG_SETTLING_CYCLES 0x8A /* R/W, 2 bytes */
36 #define AD5933_REG_STATUS 0x8F /* R, 1 byte */
37 #define AD5933_REG_TEMP_DATA 0x92 /* R, 2 bytes*/
38 #define AD5933_REG_REAL_DATA 0x94 /* R, 2 bytes*/
39 #define AD5933_REG_IMAG_DATA 0x96 /* R, 2 bytes*/
41 /* AD5933_REG_CONTROL_HB Bits */
42 #define AD5933_CTRL_INIT_START_FREQ (0x1 << 4)
43 #define AD5933_CTRL_START_SWEEP (0x2 << 4)
44 #define AD5933_CTRL_INC_FREQ (0x3 << 4)
45 #define AD5933_CTRL_REPEAT_FREQ (0x4 << 4)
46 #define AD5933_CTRL_MEASURE_TEMP (0x9 << 4)
47 #define AD5933_CTRL_POWER_DOWN (0xA << 4)
48 #define AD5933_CTRL_STANDBY (0xB << 4)
50 #define AD5933_CTRL_RANGE_2000mVpp (0x0 << 1)
51 #define AD5933_CTRL_RANGE_200mVpp (0x1 << 1)
52 #define AD5933_CTRL_RANGE_400mVpp (0x2 << 1)
53 #define AD5933_CTRL_RANGE_1000mVpp (0x3 << 1)
54 #define AD5933_CTRL_RANGE(x) ((x) << 1)
56 #define AD5933_CTRL_PGA_GAIN_1 (0x1 << 0)
57 #define AD5933_CTRL_PGA_GAIN_5 (0x0 << 0)
59 /* AD5933_REG_CONTROL_LB Bits */
60 #define AD5933_CTRL_RESET (0x1 << 4)
61 #define AD5933_CTRL_INT_SYSCLK (0x0 << 3)
62 #define AD5933_CTRL_EXT_SYSCLK (0x1 << 3)
64 /* AD5933_REG_STATUS Bits */
65 #define AD5933_STAT_TEMP_VALID (0x1 << 0)
66 #define AD5933_STAT_DATA_VALID (0x1 << 1)
67 #define AD5933_STAT_SWEEP_DONE (0x1 << 2)
69 /* I2C Block Commands */
70 #define AD5933_I2C_BLOCK_WRITE 0xA0
71 #define AD5933_I2C_BLOCK_READ 0xA1
72 #define AD5933_I2C_ADDR_POINTER 0xB0
75 #define AD5933_INT_OSC_FREQ_Hz 16776000
76 #define AD5933_MAX_OUTPUT_FREQ_Hz 100000
77 #define AD5933_MAX_RETRIES 100
79 #define AD5933_OUT_RANGE 1
80 #define AD5933_OUT_RANGE_AVAIL 2
81 #define AD5933_OUT_SETTLING_CYCLES 3
82 #define AD5933_IN_PGA_GAIN 4
83 #define AD5933_IN_PGA_GAIN_AVAIL 5
84 #define AD5933_FREQ_POINTS 6
86 #define AD5933_POLL_TIME_ms 10
87 #define AD5933_INIT_EXCITATION_TIME_ms 100
90 struct i2c_client *client;
91 struct regulator *reg;
92 struct ad5933_platform_data *pdata;
93 struct delayed_work work;
94 unsigned long mclk_hz;
95 unsigned char ctrl_hb;
96 unsigned char ctrl_lb;
97 unsigned range_avail[4];
98 unsigned short vref_mv;
99 unsigned short settling_cycles;
100 unsigned short freq_points;
104 unsigned poll_time_jiffies;
107 static struct ad5933_platform_data ad5933_default_pdata = {
111 static const struct iio_chan_spec ad5933_channels[] = {
116 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
117 .address = AD5933_REG_TEMP_DATA,
124 }, { /* Ring Channels */
128 .extend_name = "real",
129 .address = AD5933_REG_REAL_DATA,
140 .extend_name = "imag",
141 .address = AD5933_REG_IMAG_DATA,
151 static int ad5933_i2c_write(struct i2c_client *client,
152 u8 reg, u8 len, u8 *data)
157 ret = i2c_smbus_write_byte_data(client, reg++, *data++);
159 dev_err(&client->dev, "I2C write error\n");
166 static int ad5933_i2c_read(struct i2c_client *client,
167 u8 reg, u8 len, u8 *data)
172 ret = i2c_smbus_read_byte_data(client, reg++);
174 dev_err(&client->dev, "I2C read error\n");
182 static int ad5933_cmd(struct ad5933_state *st, unsigned char cmd)
184 unsigned char dat = st->ctrl_hb | cmd;
186 return ad5933_i2c_write(st->client,
187 AD5933_REG_CONTROL_HB, 1, &dat);
190 static int ad5933_reset(struct ad5933_state *st)
192 unsigned char dat = st->ctrl_lb | AD5933_CTRL_RESET;
193 return ad5933_i2c_write(st->client,
194 AD5933_REG_CONTROL_LB, 1, &dat);
197 static int ad5933_wait_busy(struct ad5933_state *st, unsigned char event)
199 unsigned char val, timeout = AD5933_MAX_RETRIES;
203 ret = ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &val);
215 static int ad5933_set_freq(struct ad5933_state *st,
216 unsigned reg, unsigned long freq)
218 unsigned long long freqreg;
224 freqreg = (u64) freq * (u64) (1 << 27);
225 do_div(freqreg, st->mclk_hz / 4);
228 case AD5933_REG_FREQ_START:
229 st->freq_start = freq;
231 case AD5933_REG_FREQ_INC:
238 dat.d32 = cpu_to_be32(freqreg);
239 return ad5933_i2c_write(st->client, reg, 3, &dat.d8[1]);
242 static int ad5933_setup(struct ad5933_state *st)
247 ret = ad5933_reset(st);
251 ret = ad5933_set_freq(st, AD5933_REG_FREQ_START, 10000);
255 ret = ad5933_set_freq(st, AD5933_REG_FREQ_INC, 200);
259 st->settling_cycles = 10;
260 dat = cpu_to_be16(st->settling_cycles);
262 ret = ad5933_i2c_write(st->client,
263 AD5933_REG_SETTLING_CYCLES, 2, (u8 *)&dat);
267 st->freq_points = 100;
268 dat = cpu_to_be16(st->freq_points);
270 return ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2, (u8 *)&dat);
273 static void ad5933_calc_out_ranges(struct ad5933_state *st)
276 unsigned normalized_3v3[4] = {1980, 198, 383, 970};
278 for (i = 0; i < 4; i++)
279 st->range_avail[i] = normalized_3v3[i] * st->vref_mv / 3300;
284 * handles: AD5933_REG_FREQ_START and AD5933_REG_FREQ_INC
287 static ssize_t ad5933_show_frequency(struct device *dev,
288 struct device_attribute *attr,
291 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
292 struct ad5933_state *st = iio_priv(indio_dev);
293 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
295 unsigned long long freqreg;
301 mutex_lock(&indio_dev->mlock);
302 ret = ad5933_i2c_read(st->client, this_attr->address, 3, &dat.d8[1]);
303 mutex_unlock(&indio_dev->mlock);
307 freqreg = be32_to_cpu(dat.d32) & 0xFFFFFF;
309 freqreg = (u64) freqreg * (u64) (st->mclk_hz / 4);
310 do_div(freqreg, 1 << 27);
312 return sprintf(buf, "%d\n", (int) freqreg);
315 static ssize_t ad5933_store_frequency(struct device *dev,
316 struct device_attribute *attr,
320 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
321 struct ad5933_state *st = iio_priv(indio_dev);
322 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
326 ret = strict_strtoul(buf, 10, &val);
330 if (val > AD5933_MAX_OUTPUT_FREQ_Hz)
333 mutex_lock(&indio_dev->mlock);
334 ret = ad5933_set_freq(st, this_attr->address, val);
335 mutex_unlock(&indio_dev->mlock);
337 return ret ? ret : len;
340 static IIO_DEVICE_ATTR(out_voltage0_freq_start, S_IRUGO | S_IWUSR,
341 ad5933_show_frequency,
342 ad5933_store_frequency,
343 AD5933_REG_FREQ_START);
345 static IIO_DEVICE_ATTR(out_voltage0_freq_increment, S_IRUGO | S_IWUSR,
346 ad5933_show_frequency,
347 ad5933_store_frequency,
348 AD5933_REG_FREQ_INC);
350 static ssize_t ad5933_show(struct device *dev,
351 struct device_attribute *attr,
354 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
355 struct ad5933_state *st = iio_priv(indio_dev);
356 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
357 int ret = 0, len = 0;
359 mutex_lock(&indio_dev->mlock);
360 switch ((u32) this_attr->address) {
361 case AD5933_OUT_RANGE:
362 len = sprintf(buf, "%d\n",
363 st->range_avail[(st->ctrl_hb >> 1) & 0x3]);
365 case AD5933_OUT_RANGE_AVAIL:
366 len = sprintf(buf, "%d %d %d %d\n", st->range_avail[0],
367 st->range_avail[3], st->range_avail[2],
370 case AD5933_OUT_SETTLING_CYCLES:
371 len = sprintf(buf, "%d\n", st->settling_cycles);
373 case AD5933_IN_PGA_GAIN:
374 len = sprintf(buf, "%s\n",
375 (st->ctrl_hb & AD5933_CTRL_PGA_GAIN_1) ?
378 case AD5933_IN_PGA_GAIN_AVAIL:
379 len = sprintf(buf, "1 0.2\n");
381 case AD5933_FREQ_POINTS:
382 len = sprintf(buf, "%d\n", st->freq_points);
388 mutex_unlock(&indio_dev->mlock);
389 return ret ? ret : len;
392 static ssize_t ad5933_store(struct device *dev,
393 struct device_attribute *attr,
397 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
398 struct ad5933_state *st = iio_priv(indio_dev);
399 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
404 if (this_attr->address != AD5933_IN_PGA_GAIN) {
405 ret = strict_strtol(buf, 10, &val);
410 mutex_lock(&indio_dev->mlock);
411 switch ((u32) this_attr->address) {
412 case AD5933_OUT_RANGE:
413 for (i = 0; i < 4; i++)
414 if (val == st->range_avail[i]) {
415 st->ctrl_hb &= ~AD5933_CTRL_RANGE(0x3);
416 st->ctrl_hb |= AD5933_CTRL_RANGE(i);
417 ret = ad5933_cmd(st, 0);
422 case AD5933_IN_PGA_GAIN:
423 if (sysfs_streq(buf, "1")) {
424 st->ctrl_hb |= AD5933_CTRL_PGA_GAIN_1;
425 } else if (sysfs_streq(buf, "0.2")) {
426 st->ctrl_hb &= ~AD5933_CTRL_PGA_GAIN_1;
431 ret = ad5933_cmd(st, 0);
433 case AD5933_OUT_SETTLING_CYCLES:
434 val = clamp(val, 0L, 0x7FFL);
435 st->settling_cycles = val;
437 /* 2x, 4x handling, see datasheet */
439 val = (val >> 1) | (1 << 9);
441 val = (val >> 2) | (3 << 9);
443 dat = cpu_to_be16(val);
444 ret = ad5933_i2c_write(st->client,
445 AD5933_REG_SETTLING_CYCLES, 2, (u8 *)&dat);
447 case AD5933_FREQ_POINTS:
448 val = clamp(val, 0L, 511L);
449 st->freq_points = val;
451 dat = cpu_to_be16(val);
452 ret = ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2,
459 mutex_unlock(&indio_dev->mlock);
460 return ret ? ret : len;
463 static IIO_DEVICE_ATTR(out_voltage0_scale, S_IRUGO | S_IWUSR,
468 static IIO_DEVICE_ATTR(out_voltage0_scale_available, S_IRUGO,
471 AD5933_OUT_RANGE_AVAIL);
473 static IIO_DEVICE_ATTR(in_voltage0_scale, S_IRUGO | S_IWUSR,
478 static IIO_DEVICE_ATTR(in_voltage0_scale_available, S_IRUGO,
481 AD5933_IN_PGA_GAIN_AVAIL);
483 static IIO_DEVICE_ATTR(out_voltage0_freq_points, S_IRUGO | S_IWUSR,
488 static IIO_DEVICE_ATTR(out_voltage0_settling_cycles, S_IRUGO | S_IWUSR,
491 AD5933_OUT_SETTLING_CYCLES);
494 * ideally we would handle the scale attributes via the iio_info
495 * (read|write)_raw methods, however this part is a untypical since we
496 * don't create dedicated sysfs channel attributes for out0 and in0.
498 static struct attribute *ad5933_attributes[] = {
499 &iio_dev_attr_out_voltage0_scale.dev_attr.attr,
500 &iio_dev_attr_out_voltage0_scale_available.dev_attr.attr,
501 &iio_dev_attr_out_voltage0_freq_start.dev_attr.attr,
502 &iio_dev_attr_out_voltage0_freq_increment.dev_attr.attr,
503 &iio_dev_attr_out_voltage0_freq_points.dev_attr.attr,
504 &iio_dev_attr_out_voltage0_settling_cycles.dev_attr.attr,
505 &iio_dev_attr_in_voltage0_scale.dev_attr.attr,
506 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
510 static const struct attribute_group ad5933_attribute_group = {
511 .attrs = ad5933_attributes,
514 static int ad5933_read_raw(struct iio_dev *indio_dev,
515 struct iio_chan_spec const *chan,
520 struct ad5933_state *st = iio_priv(indio_dev);
524 mutex_lock(&indio_dev->mlock);
526 case IIO_CHAN_INFO_RAW:
527 case IIO_CHAN_INFO_PROCESSED:
528 if (iio_buffer_enabled(indio_dev)) {
532 ret = ad5933_cmd(st, AD5933_CTRL_MEASURE_TEMP);
535 ret = ad5933_wait_busy(st, AD5933_STAT_TEMP_VALID);
539 ret = ad5933_i2c_read(st->client,
540 AD5933_REG_TEMP_DATA, 2,
544 mutex_unlock(&indio_dev->mlock);
545 ret = be16_to_cpu(dat);
546 /* Temp in Milli degrees Celsius */
548 *val = ret * 1000 / 32;
550 *val = (ret - 16384) * 1000 / 32;
556 mutex_unlock(&indio_dev->mlock);
560 static const struct iio_info ad5933_info = {
561 .read_raw = &ad5933_read_raw,
562 .attrs = &ad5933_attribute_group,
563 .driver_module = THIS_MODULE,
566 static int ad5933_ring_preenable(struct iio_dev *indio_dev)
568 struct ad5933_state *st = iio_priv(indio_dev);
571 if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
574 ret = iio_sw_buffer_preenable(indio_dev);
578 ret = ad5933_reset(st);
582 ret = ad5933_cmd(st, AD5933_CTRL_STANDBY);
586 ret = ad5933_cmd(st, AD5933_CTRL_INIT_START_FREQ);
590 st->state = AD5933_CTRL_INIT_START_FREQ;
595 static int ad5933_ring_postenable(struct iio_dev *indio_dev)
597 struct ad5933_state *st = iio_priv(indio_dev);
599 /* AD5933_CTRL_INIT_START_FREQ:
600 * High Q complex circuits require a long time to reach steady state.
601 * To facilitate the measurement of such impedances, this mode allows
602 * the user full control of the settling time requirement before
603 * entering start frequency sweep mode where the impedance measurement
604 * takes place. In this mode the impedance is excited with the
605 * programmed start frequency (ad5933_ring_preenable),
606 * but no measurement takes place.
609 schedule_delayed_work(&st->work,
610 msecs_to_jiffies(AD5933_INIT_EXCITATION_TIME_ms));
614 static int ad5933_ring_postdisable(struct iio_dev *indio_dev)
616 struct ad5933_state *st = iio_priv(indio_dev);
618 cancel_delayed_work_sync(&st->work);
619 return ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
622 static const struct iio_buffer_setup_ops ad5933_ring_setup_ops = {
623 .preenable = &ad5933_ring_preenable,
624 .postenable = &ad5933_ring_postenable,
625 .postdisable = &ad5933_ring_postdisable,
628 static int ad5933_register_ring_funcs_and_init(struct iio_dev *indio_dev)
630 indio_dev->buffer = iio_kfifo_allocate(indio_dev);
631 if (!indio_dev->buffer)
634 /* Ring buffer functions - here trigger setup related */
635 indio_dev->setup_ops = &ad5933_ring_setup_ops;
637 indio_dev->modes |= INDIO_BUFFER_HARDWARE;
642 static void ad5933_work(struct work_struct *work)
644 struct ad5933_state *st = container_of(work,
645 struct ad5933_state, work.work);
646 struct iio_dev *indio_dev = i2c_get_clientdata(st->client);
648 unsigned char status;
650 mutex_lock(&indio_dev->mlock);
651 if (st->state == AD5933_CTRL_INIT_START_FREQ) {
653 ad5933_cmd(st, AD5933_CTRL_START_SWEEP);
654 st->state = AD5933_CTRL_START_SWEEP;
655 schedule_delayed_work(&st->work, st->poll_time_jiffies);
656 mutex_unlock(&indio_dev->mlock);
660 ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &status);
662 if (status & AD5933_STAT_DATA_VALID) {
663 int scan_count = bitmap_weight(indio_dev->active_scan_mask,
664 indio_dev->masklength);
665 ad5933_i2c_read(st->client,
666 test_bit(1, indio_dev->active_scan_mask) ?
667 AD5933_REG_REAL_DATA : AD5933_REG_IMAG_DATA,
668 scan_count * 2, (u8 *)buf);
670 if (scan_count == 2) {
671 buf[0] = be16_to_cpu(buf[0]);
672 buf[1] = be16_to_cpu(buf[1]);
674 buf[0] = be16_to_cpu(buf[0]);
676 iio_push_to_buffers(indio_dev, (u8 *)buf);
678 /* no data available - try again later */
679 schedule_delayed_work(&st->work, st->poll_time_jiffies);
680 mutex_unlock(&indio_dev->mlock);
684 if (status & AD5933_STAT_SWEEP_DONE) {
685 /* last sample received - power down do nothing until
686 * the ring enable is toggled */
687 ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
689 /* we just received a valid datum, move on to the next */
690 ad5933_cmd(st, AD5933_CTRL_INC_FREQ);
691 schedule_delayed_work(&st->work, st->poll_time_jiffies);
694 mutex_unlock(&indio_dev->mlock);
697 static int ad5933_probe(struct i2c_client *client,
698 const struct i2c_device_id *id)
700 int ret, voltage_uv = 0;
701 struct ad5933_platform_data *pdata = client->dev.platform_data;
702 struct ad5933_state *st;
703 struct iio_dev *indio_dev = iio_device_alloc(sizeof(*st));
704 if (indio_dev == NULL)
707 st = iio_priv(indio_dev);
708 i2c_set_clientdata(client, indio_dev);
712 st->pdata = &ad5933_default_pdata;
716 st->reg = regulator_get(&client->dev, "vcc");
717 if (!IS_ERR(st->reg)) {
718 ret = regulator_enable(st->reg);
721 voltage_uv = regulator_get_voltage(st->reg);
725 st->vref_mv = voltage_uv / 1000;
727 st->vref_mv = st->pdata->vref_mv;
729 if (st->pdata->ext_clk_Hz) {
730 st->mclk_hz = st->pdata->ext_clk_Hz;
731 st->ctrl_lb = AD5933_CTRL_EXT_SYSCLK;
733 st->mclk_hz = AD5933_INT_OSC_FREQ_Hz;
734 st->ctrl_lb = AD5933_CTRL_INT_SYSCLK;
737 ad5933_calc_out_ranges(st);
738 INIT_DELAYED_WORK(&st->work, ad5933_work);
739 st->poll_time_jiffies = msecs_to_jiffies(AD5933_POLL_TIME_ms);
741 indio_dev->dev.parent = &client->dev;
742 indio_dev->info = &ad5933_info;
743 indio_dev->name = id->name;
744 indio_dev->modes = INDIO_DIRECT_MODE;
745 indio_dev->channels = ad5933_channels;
746 indio_dev->num_channels = ARRAY_SIZE(ad5933_channels);
748 ret = ad5933_register_ring_funcs_and_init(indio_dev);
750 goto error_disable_reg;
752 ret = iio_buffer_register(indio_dev, ad5933_channels,
753 ARRAY_SIZE(ad5933_channels));
755 goto error_unreg_ring;
757 /* enable both REAL and IMAG channels by default */
758 iio_scan_mask_set(indio_dev, indio_dev->buffer, 0);
759 iio_scan_mask_set(indio_dev, indio_dev->buffer, 1);
761 ret = ad5933_setup(st);
763 goto error_uninitialize_ring;
765 ret = iio_device_register(indio_dev);
767 goto error_uninitialize_ring;
771 error_uninitialize_ring:
772 iio_buffer_unregister(indio_dev);
774 iio_kfifo_free(indio_dev->buffer);
776 if (!IS_ERR(st->reg))
777 regulator_disable(st->reg);
779 if (!IS_ERR(st->reg))
780 regulator_put(st->reg);
782 iio_device_free(indio_dev);
787 static int ad5933_remove(struct i2c_client *client)
789 struct iio_dev *indio_dev = i2c_get_clientdata(client);
790 struct ad5933_state *st = iio_priv(indio_dev);
792 iio_device_unregister(indio_dev);
793 iio_buffer_unregister(indio_dev);
794 iio_kfifo_free(indio_dev->buffer);
795 if (!IS_ERR(st->reg)) {
796 regulator_disable(st->reg);
797 regulator_put(st->reg);
799 iio_device_free(indio_dev);
804 static const struct i2c_device_id ad5933_id[] = {
810 MODULE_DEVICE_TABLE(i2c, ad5933_id);
812 static struct i2c_driver ad5933_driver = {
816 .probe = ad5933_probe,
817 .remove = ad5933_remove,
818 .id_table = ad5933_id,
820 module_i2c_driver(ad5933_driver);
822 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
823 MODULE_DESCRIPTION("Analog Devices AD5933 Impedance Conv. Network Analyzer");
824 MODULE_LICENSE("GPL v2");