drivers/staging/iio/accel/lis3l02dq_core.c

   1 /*
   2  * lis3l02dq.c  support STMicroelectronics LISD02DQ
   3  *              3d 2g Linear Accelerometers via SPI
   4  *
   5  * Copyright (c) 2007 Jonathan Cameron <jic23@kernel.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Settings:
  12  * 16 bit left justified mode used.
  13  */
  14
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/gpio.h>
  18 #include <linux/of_gpio.h>
  19 #include <linux/mutex.h>
  20 #include <linux/device.h>
  21 #include <linux/kernel.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/slab.h>
  24 #include <linux/sysfs.h>
  25 #include <linux/module.h>
  26
  27 #include <linux/iio/iio.h>
  28 #include <linux/iio/sysfs.h>
  29 #include <linux/iio/events.h>
  30 #include <linux/iio/buffer.h>
  31
  32 #include "lis3l02dq.h"
  33
  34 /* At the moment the spi framework doesn't allow global setting of cs_change.
  35  * It's in the likely to be added comment at the top of spi.h.
  36  * This means that use cannot be made of spi_write etc.
  37  */
  38 /* direct copy of the irq_default_primary_handler */
  39 #ifndef CONFIG_IIO_BUFFER
  40 static irqreturn_t lis3l02dq_nobuffer(int irq, void *private)
  41 {
  42         return IRQ_WAKE_THREAD;
  43 }
  44 #endif
  45
  46 /**
  47  * lis3l02dq_spi_read_reg_8() - read single byte from a single register
  48  * @indio_dev: iio_dev for this actual device
  49  * @reg_address: the address of the register to be read
  50  * @val: pass back the resulting value
  51  **/
  52 int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
  53                              u8 reg_address, u8 *val)
  54 {
  55         struct lis3l02dq_state *st = iio_priv(indio_dev);
  56         int ret;
  57         struct spi_transfer xfer = {
  58                 .tx_buf = st->tx,
  59                 .rx_buf = st->rx,
  60                 .bits_per_word = 8,
  61                 .len = 2,
  62         };
  63
  64         mutex_lock(&st->buf_lock);
  65         st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
  66         st->tx[1] = 0;
  67
  68         ret = spi_sync_transfer(st->us, &xfer, 1);
  69         *val = st->rx[1];
  70         mutex_unlock(&st->buf_lock);
  71
  72         return ret;
  73 }
  74
  75 /**
  76  * lis3l02dq_spi_write_reg_8() - write single byte to a register
  77  * @indio_dev: iio_dev for this device
  78  * @reg_address: the address of the register to be written
  79  * @val: the value to write
  80  **/
  81 int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
  82                               u8 reg_address,
  83                               u8 val)
  84 {
  85         int ret;
  86         struct lis3l02dq_state *st = iio_priv(indio_dev);
  87
  88         mutex_lock(&st->buf_lock);
  89         st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
  90         st->tx[1] = val;
  91         ret = spi_write(st->us, st->tx, 2);
  92         mutex_unlock(&st->buf_lock);
  93
  94         return ret;
  95 }
  96
  97 /**
  98  * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
  99  * @indio_dev: iio_dev for this device
 100  * @lower_reg_address: the address of the lower of the two registers.
 101  *               Second register is assumed to have address one greater.
 102  * @value: value to be written
 103  **/
 104 static int lis3l02dq_spi_write_reg_s16(struct iio_dev *indio_dev,
 105                                        u8 lower_reg_address,
 106                                        s16 value)
 107 {
 108         int ret;
 109         struct lis3l02dq_state *st = iio_priv(indio_dev);
 110         struct spi_transfer xfers[] = { {
 111                         .tx_buf = st->tx,
 112                         .bits_per_word = 8,
 113                         .len = 2,
 114                         .cs_change = 1,
 115                 }, {
 116                         .tx_buf = st->tx + 2,
 117                         .bits_per_word = 8,
 118                         .len = 2,
 119                 },
 120         };
 121
 122         mutex_lock(&st->buf_lock);
 123         st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
 124         st->tx[1] = value & 0xFF;
 125         st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
 126         st->tx[3] = (value >> 8) & 0xFF;
 127
 128         ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
 129         mutex_unlock(&st->buf_lock);
 130
 131         return ret;
 132 }
 133
 134 static int lis3l02dq_read_reg_s16(struct iio_dev *indio_dev,
 135                                   u8 lower_reg_address,
 136                                   int *val)
 137 {
 138         struct lis3l02dq_state *st = iio_priv(indio_dev);
 139         int ret;
 140         s16 tempval;
 141         struct spi_transfer xfers[] = { {
 142                         .tx_buf = st->tx,
 143                         .rx_buf = st->rx,
 144                         .bits_per_word = 8,
 145                         .len = 2,
 146                         .cs_change = 1,
 147                 }, {
 148                         .tx_buf = st->tx + 2,
 149                         .rx_buf = st->rx + 2,
 150                         .bits_per_word = 8,
 151                         .len = 2,
 152                 },
 153         };
 154
 155         mutex_lock(&st->buf_lock);
 156         st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
 157         st->tx[1] = 0;
 158         st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address + 1);
 159         st->tx[3] = 0;
 160
 161         ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
 162         if (ret) {
 163                 dev_err(&st->us->dev, "problem when reading 16 bit register");
 164                 goto error_ret;
 165         }
 166         tempval = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
 167
 168         *val = tempval;
 169 error_ret:
 170         mutex_unlock(&st->buf_lock);
 171         return ret;
 172 }
 173
 174 enum lis3l02dq_rm_ind {
 175         LIS3L02DQ_ACCEL,
 176         LIS3L02DQ_GAIN,
 177         LIS3L02DQ_BIAS,
 178 };
 179
 180 static u8 lis3l02dq_axis_map[3][3] = {
 181         [LIS3L02DQ_ACCEL] = { LIS3L02DQ_REG_OUT_X_L_ADDR,
 182                               LIS3L02DQ_REG_OUT_Y_L_ADDR,
 183                               LIS3L02DQ_REG_OUT_Z_L_ADDR },
 184         [LIS3L02DQ_GAIN] = { LIS3L02DQ_REG_GAIN_X_ADDR,
 185                              LIS3L02DQ_REG_GAIN_Y_ADDR,
 186                              LIS3L02DQ_REG_GAIN_Z_ADDR },
 187         [LIS3L02DQ_BIAS] = { LIS3L02DQ_REG_OFFSET_X_ADDR,
 188                              LIS3L02DQ_REG_OFFSET_Y_ADDR,
 189                              LIS3L02DQ_REG_OFFSET_Z_ADDR }
 190 };
 191
 192 static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
 193                                  u64 e,
 194                                  int *val)
 195 {
 196         return lis3l02dq_read_reg_s16(indio_dev, LIS3L02DQ_REG_THS_L_ADDR, val);
 197 }
 198
 199 static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
 200                                   u64 event_code,
 201                                   int val)
 202 {
 203         u16 value = val;
 204         return lis3l02dq_spi_write_reg_s16(indio_dev,
 205                                            LIS3L02DQ_REG_THS_L_ADDR,
 206                                            value);
 207 }
 208
 209 static int lis3l02dq_write_raw(struct iio_dev *indio_dev,
 210                                struct iio_chan_spec const *chan,
 211                                int val,
 212                                int val2,
 213                                long mask)
 214 {
 215         int ret = -EINVAL, reg;
 216         u8 uval;
 217         s8 sval;
 218         switch (mask) {
 219         case IIO_CHAN_INFO_CALIBBIAS:
 220                 if (val > 255 || val < -256)
 221                         return -EINVAL;
 222                 sval = val;
 223                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 224                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, sval);
 225                 break;
 226         case IIO_CHAN_INFO_CALIBSCALE:
 227                 if (val & ~0xFF)
 228                         return -EINVAL;
 229                 uval = val;
 230                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 231                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, uval);
 232                 break;
 233         }
 234         return ret;
 235 }
 236
 237 static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
 238                               struct iio_chan_spec const *chan,
 239                               int *val,
 240                               int *val2,
 241                               long mask)
 242 {
 243         u8 utemp;
 244         s8 stemp;
 245         ssize_t ret = 0;
 246         u8 reg;
 247
 248         switch (mask) {
 249         case IIO_CHAN_INFO_RAW:
 250                 /* Take the iio_dev status lock */
 251                 mutex_lock(&indio_dev->mlock);
 252                 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) {
 253                         ret = -EBUSY;
 254                 } else {
 255                         reg = lis3l02dq_axis_map
 256                                 [LIS3L02DQ_ACCEL][chan->address];
 257                         ret = lis3l02dq_read_reg_s16(indio_dev, reg, val);
 258                 }
 259                 mutex_unlock(&indio_dev->mlock);
 260                 return IIO_VAL_INT;
 261         case IIO_CHAN_INFO_SCALE:
 262                 *val = 0;
 263                 *val2 = 9580;
 264                 return IIO_VAL_INT_PLUS_MICRO;
 265         case IIO_CHAN_INFO_CALIBSCALE:
 266                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 267                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, &utemp);
 268                 if (ret)
 269                         goto error_ret;
 270                 /* to match with what previous code does */
 271                 *val = utemp;
 272                 return IIO_VAL_INT;
 273
 274         case IIO_CHAN_INFO_CALIBBIAS:
 275                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 276                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, (u8 *)&stemp);
 277                 /* to match with what previous code does */
 278                 *val = stemp;
 279                 return IIO_VAL_INT;
 280         }
 281 error_ret:
 282         return ret;
 283 }
 284
 285 static ssize_t lis3l02dq_read_frequency(struct device *dev,
 286                                         struct device_attribute *attr,
 287                                         char *buf)
 288 {
 289         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 290         int ret, len = 0;
 291         s8 t;
 292         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 293                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 294                                        (u8 *)&t);
 295         if (ret)
 296                 return ret;
 297         t &= LIS3L02DQ_DEC_MASK;
 298         switch (t) {
 299         case LIS3L02DQ_REG_CTRL_1_DF_128:
 300                 len = sprintf(buf, "280\n");
 301                 break;
 302         case LIS3L02DQ_REG_CTRL_1_DF_64:
 303                 len = sprintf(buf, "560\n");
 304                 break;
 305         case LIS3L02DQ_REG_CTRL_1_DF_32:
 306                 len = sprintf(buf, "1120\n");
 307                 break;
 308         case LIS3L02DQ_REG_CTRL_1_DF_8:
 309                 len = sprintf(buf, "4480\n");
 310                 break;
 311         }
 312         return len;
 313 }
 314
 315 static ssize_t lis3l02dq_write_frequency(struct device *dev,
 316                                          struct device_attribute *attr,
 317                                          const char *buf,
 318                                          size_t len)
 319 {
 320         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 321         unsigned long val;
 322         int ret;
 323         u8 t;
 324
 325         ret = kstrtoul(buf, 10, &val);
 326         if (ret)
 327                 return ret;
 328
 329         mutex_lock(&indio_dev->mlock);
 330         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 331                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 332                                        &t);
 333         if (ret)
 334                 goto error_ret_mutex;
 335         /* Wipe the bits clean */
 336         t &= ~LIS3L02DQ_DEC_MASK;
 337         switch (val) {
 338         case 280:
 339                 t |= LIS3L02DQ_REG_CTRL_1_DF_128;
 340                 break;
 341         case 560:
 342                 t |= LIS3L02DQ_REG_CTRL_1_DF_64;
 343                 break;
 344         case 1120:
 345                 t |= LIS3L02DQ_REG_CTRL_1_DF_32;
 346                 break;
 347         case 4480:
 348                 t |= LIS3L02DQ_REG_CTRL_1_DF_8;
 349                 break;
 350         default:
 351                 ret = -EINVAL;
 352                 goto error_ret_mutex;
 353         }
 354
 355         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 356                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 357                                         t);
 358
 359 error_ret_mutex:
 360         mutex_unlock(&indio_dev->mlock);
 361
 362         return ret ? ret : len;
 363 }
 364
 365 static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
 366 {
 367         struct lis3l02dq_state *st = iio_priv(indio_dev);
 368         int ret;
 369         u8 val, valtest;
 370
 371         st->us->mode = SPI_MODE_3;
 372
 373         spi_setup(st->us);
 374
 375         val = LIS3L02DQ_DEFAULT_CTRL1;
 376         /* Write suitable defaults to ctrl1 */
 377         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 378                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 379                                         val);
 380         if (ret) {
 381                 dev_err(&st->us->dev, "problem with setup control register 1");
 382                 goto err_ret;
 383         }
 384         /* Repeat as sometimes doesn't work first time? */
 385         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 386                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 387                                         val);
 388         if (ret) {
 389                 dev_err(&st->us->dev, "problem with setup control register 1");
 390                 goto err_ret;
 391         }
 392
 393         /* Read back to check this has worked acts as loose test of correct
 394          * chip */
 395         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 396                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 397                                        &valtest);
 398         if (ret || (valtest != val)) {
 399                 dev_err(&indio_dev->dev,
 400                         "device not playing ball %d %d\n", valtest, val);
 401                 ret = -EINVAL;
 402                 goto err_ret;
 403         }
 404
 405         val = LIS3L02DQ_DEFAULT_CTRL2;
 406         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 407                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 408                                         val);
 409         if (ret) {
 410                 dev_err(&st->us->dev, "problem with setup control register 2");
 411                 goto err_ret;
 412         }
 413
 414         val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
 415         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 416                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 417                                         val);
 418         if (ret)
 419                 dev_err(&st->us->dev, "problem with interrupt cfg register");
 420 err_ret:
 421
 422         return ret;
 423 }
 424
 425 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
 426                               lis3l02dq_read_frequency,
 427                               lis3l02dq_write_frequency);
 428
 429 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
 430
 431 static irqreturn_t lis3l02dq_event_handler(int irq, void *private)
 432 {
 433         struct iio_dev *indio_dev = private;
 434         u8 t;
 435
 436         s64 timestamp = iio_get_time_ns();
 437
 438         lis3l02dq_spi_read_reg_8(indio_dev,
 439                                  LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
 440                                  &t);
 441
 442         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
 443                 iio_push_event(indio_dev,
 444                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 445                                                   0,
 446                                                   IIO_MOD_Z,
 447                                                   IIO_EV_TYPE_THRESH,
 448                                                   IIO_EV_DIR_RISING),
 449                                timestamp);
 450
 451         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
 452                 iio_push_event(indio_dev,
 453                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 454                                                   0,
 455                                                   IIO_MOD_Z,
 456                                                   IIO_EV_TYPE_THRESH,
 457                                                   IIO_EV_DIR_FALLING),
 458                                timestamp);
 459
 460         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
 461                 iio_push_event(indio_dev,
 462                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 463                                                   0,
 464                                                   IIO_MOD_Y,
 465                                                   IIO_EV_TYPE_THRESH,
 466                                                   IIO_EV_DIR_RISING),
 467                                timestamp);
 468
 469         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
 470                 iio_push_event(indio_dev,
 471                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 472                                                   0,
 473                                                   IIO_MOD_Y,
 474                                                   IIO_EV_TYPE_THRESH,
 475                                                   IIO_EV_DIR_FALLING),
 476                                timestamp);
 477
 478         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
 479                 iio_push_event(indio_dev,
 480                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 481                                                   0,
 482                                                   IIO_MOD_X,
 483                                                   IIO_EV_TYPE_THRESH,
 484                                                   IIO_EV_DIR_RISING),
 485                                timestamp);
 486
 487         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
 488                 iio_push_event(indio_dev,
 489                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 490                                                   0,
 491                                                   IIO_MOD_X,
 492                                                   IIO_EV_TYPE_THRESH,
 493                                                   IIO_EV_DIR_FALLING),
 494                                timestamp);
 495
 496         /* Ack and allow for new interrupts */
 497         lis3l02dq_spi_read_reg_8(indio_dev,
 498                                  LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
 499                                  &t);
 500
 501         return IRQ_HANDLED;
 502 }
 503
 504 #define LIS3L02DQ_EVENT_MASK                                    \
 505         (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) |    \
 506          IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
 507
 508 #define LIS3L02DQ_CHAN(index, mod)                              \
 509         {                                                       \
 510                 .type = IIO_ACCEL,                              \
 511                 .modified = 1,                                  \
 512                 .channel2 = mod,                                \
 513                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |  \
 514                         BIT(IIO_CHAN_INFO_CALIBSCALE) |         \
 515                         BIT(IIO_CHAN_INFO_CALIBBIAS),           \
 516                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
 517                 .address = index,                               \
 518                 .scan_index = index,                            \
 519                 .scan_type = {                                  \
 520                         .sign = 's',                            \
 521                         .realbits = 12,                         \
 522                         .storagebits = 16,                      \
 523                 },                                              \
 524                 .event_mask = LIS3L02DQ_EVENT_MASK,             \
 525          }
 526
 527 static const struct iio_chan_spec lis3l02dq_channels[] = {
 528         LIS3L02DQ_CHAN(0, IIO_MOD_X),
 529         LIS3L02DQ_CHAN(1, IIO_MOD_Y),
 530         LIS3L02DQ_CHAN(2, IIO_MOD_Z),
 531         IIO_CHAN_SOFT_TIMESTAMP(3)
 532 };
 533
 534
 535 static int lis3l02dq_read_event_config(struct iio_dev *indio_dev,
 536                                            u64 event_code)
 537 {
 538
 539         u8 val;
 540         int ret;
 541         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 542                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 543                           IIO_EV_DIR_RISING)));
 544         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 545                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 546                                        &val);
 547         if (ret < 0)
 548                 return ret;
 549
 550         return !!(val & mask);
 551 }
 552
 553 int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
 554 {
 555         int ret;
 556         u8 control, val;
 557
 558         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 559                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 560                                        &control);
 561
 562         control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
 563         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 564                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 565                                         control);
 566         if (ret)
 567                 goto error_ret;
 568         /* Also for consistency clear the mask */
 569         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 570                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 571                                        &val);
 572         if (ret)
 573                 goto error_ret;
 574         val &= ~0x3f;
 575
 576         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 577                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 578                                         val);
 579         if (ret)
 580                 goto error_ret;
 581
 582         ret = control;
 583 error_ret:
 584         return ret;
 585 }
 586
 587 static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
 588                                         u64 event_code,
 589                                         int state)
 590 {
 591         int ret = 0;
 592         u8 val, control;
 593         u8 currentlyset;
 594         bool changed = false;
 595         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 596                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 597                           IIO_EV_DIR_RISING)));
 598
 599         mutex_lock(&indio_dev->mlock);
 600         /* read current control */
 601         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 602                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 603                                        &control);
 604         if (ret)
 605                 goto error_ret;
 606         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 607                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 608                                        &val);
 609         if (ret < 0)
 610                 goto error_ret;
 611         currentlyset = val & mask;
 612
 613         if (!currentlyset && state) {
 614                 changed = true;
 615                 val |= mask;
 616         } else if (currentlyset && !state) {
 617                 changed = true;
 618                 val &= ~mask;
 619         }
 620
 621         if (changed) {
 622                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 623                                                 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 624                                                 val);
 625                 if (ret)
 626                         goto error_ret;
 627                 control = val & 0x3f ?
 628                         (control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
 629                         (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
 630                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 631                                                LIS3L02DQ_REG_CTRL_2_ADDR,
 632                                                control);
 633                 if (ret)
 634                         goto error_ret;
 635         }
 636
 637 error_ret:
 638         mutex_unlock(&indio_dev->mlock);
 639         return ret;
 640 }
 641
 642 static struct attribute *lis3l02dq_attributes[] = {
 643         &iio_dev_attr_sampling_frequency.dev_attr.attr,
 644         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 645         NULL
 646 };
 647
 648 static const struct attribute_group lis3l02dq_attribute_group = {
 649         .attrs = lis3l02dq_attributes,
 650 };
 651
 652 static const struct iio_info lis3l02dq_info = {
 653         .read_raw = &lis3l02dq_read_raw,
 654         .write_raw = &lis3l02dq_write_raw,
 655         .read_event_value = &lis3l02dq_read_thresh,
 656         .write_event_value = &lis3l02dq_write_thresh,
 657         .write_event_config = &lis3l02dq_write_event_config,
 658         .read_event_config = &lis3l02dq_read_event_config,
 659         .driver_module = THIS_MODULE,
 660         .attrs = &lis3l02dq_attribute_group,
 661 };
 662
 663 static int lis3l02dq_probe(struct spi_device *spi)
 664 {
 665         int ret;
 666         struct lis3l02dq_state *st;
 667         struct iio_dev *indio_dev;
 668
 669         indio_dev = iio_device_alloc(sizeof *st);
 670         if (indio_dev == NULL) {
 671                 ret = -ENOMEM;
 672                 goto error_ret;
 673         }
 674         st = iio_priv(indio_dev);
 675         /* this is only used for removal purposes */
 676         spi_set_drvdata(spi, indio_dev);
 677
 678         st->us = spi;
 679         st->gpio = of_get_gpio(spi->dev.of_node, 0);
 680         mutex_init(&st->buf_lock);
 681         indio_dev->name = spi->dev.driver->name;
 682         indio_dev->dev.parent = &spi->dev;
 683         indio_dev->info = &lis3l02dq_info;
 684         indio_dev->channels = lis3l02dq_channels;
 685         indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
 686
 687         indio_dev->modes = INDIO_DIRECT_MODE;
 688
 689         ret = lis3l02dq_configure_buffer(indio_dev);
 690         if (ret)
 691                 goto error_free_dev;
 692
 693         ret = iio_buffer_register(indio_dev,
 694                                   lis3l02dq_channels,
 695                                   ARRAY_SIZE(lis3l02dq_channels));
 696         if (ret) {
 697                 printk(KERN_ERR "failed to initialize the buffer\n");
 698                 goto error_unreg_buffer_funcs;
 699         }
 700
 701         if (spi->irq) {
 702                 ret = request_threaded_irq(st->us->irq,
 703                                            &lis3l02dq_th,
 704                                            &lis3l02dq_event_handler,
 705                                            IRQF_TRIGGER_RISING,
 706                                            "lis3l02dq",
 707                                            indio_dev);
 708                 if (ret)
 709                         goto error_uninitialize_buffer;
 710
 711                 ret = lis3l02dq_probe_trigger(indio_dev);
 712                 if (ret)
 713                         goto error_free_interrupt;
 714         }
 715
 716         /* Get the device into a sane initial state */
 717         ret = lis3l02dq_initial_setup(indio_dev);
 718         if (ret)
 719                 goto error_remove_trigger;
 720
 721         ret = iio_device_register(indio_dev);
 722         if (ret)
 723                 goto error_remove_trigger;
 724
 725         return 0;
 726
 727 error_remove_trigger:
 728         if (spi->irq)
 729                 lis3l02dq_remove_trigger(indio_dev);
 730 error_free_interrupt:
 731         if (spi->irq)
 732                 free_irq(st->us->irq, indio_dev);
 733 error_uninitialize_buffer:
 734         iio_buffer_unregister(indio_dev);
 735 error_unreg_buffer_funcs:
 736         lis3l02dq_unconfigure_buffer(indio_dev);
 737 error_free_dev:
 738         iio_device_free(indio_dev);
 739 error_ret:
 740         return ret;
 741 }
 742
 743 /* Power down the device */
 744 static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
 745 {
 746         int ret;
 747         struct lis3l02dq_state *st = iio_priv(indio_dev);
 748         u8 val = 0;
 749
 750         mutex_lock(&indio_dev->mlock);
 751         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 752                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 753                                         val);
 754         if (ret) {
 755                 dev_err(&st->us->dev, "problem with turning device off: ctrl1");
 756                 goto err_ret;
 757         }
 758
 759         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 760                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 761                                         val);
 762         if (ret)
 763                 dev_err(&st->us->dev, "problem with turning device off: ctrl2");
 764 err_ret:
 765         mutex_unlock(&indio_dev->mlock);
 766         return ret;
 767 }
 768
 769 /* fixme, confirm ordering in this function */
 770 static int lis3l02dq_remove(struct spi_device *spi)
 771 {
 772         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 773         struct lis3l02dq_state *st = iio_priv(indio_dev);
 774
 775         iio_device_unregister(indio_dev);
 776
 777         lis3l02dq_disable_all_events(indio_dev);
 778         lis3l02dq_stop_device(indio_dev);
 779
 780         if (spi->irq)
 781                 free_irq(st->us->irq, indio_dev);
 782
 783         lis3l02dq_remove_trigger(indio_dev);
 784         iio_buffer_unregister(indio_dev);
 785         lis3l02dq_unconfigure_buffer(indio_dev);
 786
 787         iio_device_free(indio_dev);
 788
 789         return 0;
 790 }
 791
 792 static struct spi_driver lis3l02dq_driver = {
 793         .driver = {
 794                 .name = "lis3l02dq",
 795                 .owner = THIS_MODULE,
 796         },
 797         .probe = lis3l02dq_probe,
 798         .remove = lis3l02dq_remove,
 799 };
 800 module_spi_driver(lis3l02dq_driver);
 801
 802 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
 803 MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
 804 MODULE_LICENSE("GPL v2");
 805 MODULE_ALIAS("spi:lis3l02dq");