drivers/staging/iio/accel/lis3l02dq_core.c

   1 /*
   2  * lis3l02dq.c  support STMicroelectronics LISD02DQ
   3  *              3d 2g Linear Accelerometers via SPI
   4  *
   5  * Copyright (c) 2007 Jonathan Cameron <jic23@kernel.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Settings:
  12  * 16 bit left justified mode used.
  13  */
  14
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/gpio.h>
  18 #include <linux/of_gpio.h>
  19 #include <linux/mutex.h>
  20 #include <linux/device.h>
  21 #include <linux/kernel.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/slab.h>
  24 #include <linux/sysfs.h>
  25 #include <linux/module.h>
  26
  27 #include <linux/iio/iio.h>
  28 #include <linux/iio/sysfs.h>
  29 #include <linux/iio/events.h>
  30 #include <linux/iio/buffer.h>
  31
  32 #include "lis3l02dq.h"
  33
  34 /* At the moment the spi framework doesn't allow global setting of cs_change.
  35  * It's in the likely to be added comment at the top of spi.h.
  36  * This means that use cannot be made of spi_write etc.
  37  */
  38 /* direct copy of the irq_default_primary_handler */
  39 #ifndef CONFIG_IIO_BUFFER
  40 static irqreturn_t lis3l02dq_nobuffer(int irq, void *private)
  41 {
  42         return IRQ_WAKE_THREAD;
  43 }
  44 #endif
  45
  46 /**
  47  * lis3l02dq_spi_read_reg_8() - read single byte from a single register
  48  * @indio_dev: iio_dev for this actual device
  49  * @reg_address: the address of the register to be read
  50  * @val: pass back the resulting value
  51  **/
  52 int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
  53                              u8 reg_address, u8 *val)
  54 {
  55         struct lis3l02dq_state *st = iio_priv(indio_dev);
  56         int ret;
  57         struct spi_transfer xfer = {
  58                 .tx_buf = st->tx,
  59                 .rx_buf = st->rx,
  60                 .bits_per_word = 8,
  61                 .len = 2,
  62         };
  63
  64         mutex_lock(&st->buf_lock);
  65         st->tx[0] = LIS3L02DQ_READ_REG(reg_address);
  66         st->tx[1] = 0;
  67
  68         ret = spi_sync_transfer(st->us, &xfer, 1);
  69         *val = st->rx[1];
  70         mutex_unlock(&st->buf_lock);
  71
  72         return ret;
  73 }
  74
  75 /**
  76  * lis3l02dq_spi_write_reg_8() - write single byte to a register
  77  * @indio_dev: iio_dev for this device
  78  * @reg_address: the address of the register to be written
  79  * @val: the value to write
  80  **/
  81 int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
  82                               u8 reg_address,
  83                               u8 val)
  84 {
  85         int ret;
  86         struct lis3l02dq_state *st = iio_priv(indio_dev);
  87
  88         mutex_lock(&st->buf_lock);
  89         st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
  90         st->tx[1] = val;
  91         ret = spi_write(st->us, st->tx, 2);
  92         mutex_unlock(&st->buf_lock);
  93
  94         return ret;
  95 }
  96
  97 /**
  98  * lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
  99  * @indio_dev: iio_dev for this device
 100  * @lower_reg_address: the address of the lower of the two registers.
 101  *               Second register is assumed to have address one greater.
 102  * @value: value to be written
 103  **/
 104 static int lis3l02dq_spi_write_reg_s16(struct iio_dev *indio_dev,
 105                                        u8 lower_reg_address,
 106                                        s16 value)
 107 {
 108         int ret;
 109         struct lis3l02dq_state *st = iio_priv(indio_dev);
 110         struct spi_transfer xfers[] = { {
 111                         .tx_buf = st->tx,
 112                         .bits_per_word = 8,
 113                         .len = 2,
 114                         .cs_change = 1,
 115                 }, {
 116                         .tx_buf = st->tx + 2,
 117                         .bits_per_word = 8,
 118                         .len = 2,
 119                 },
 120         };
 121
 122         mutex_lock(&st->buf_lock);
 123         st->tx[0] = LIS3L02DQ_WRITE_REG(lower_reg_address);
 124         st->tx[1] = value & 0xFF;
 125         st->tx[2] = LIS3L02DQ_WRITE_REG(lower_reg_address + 1);
 126         st->tx[3] = (value >> 8) & 0xFF;
 127
 128         ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
 129         mutex_unlock(&st->buf_lock);
 130
 131         return ret;
 132 }
 133
 134 static int lis3l02dq_read_reg_s16(struct iio_dev *indio_dev,
 135                                   u8 lower_reg_address,
 136                                   int *val)
 137 {
 138         struct lis3l02dq_state *st = iio_priv(indio_dev);
 139         int ret;
 140         s16 tempval;
 141         struct spi_transfer xfers[] = { {
 142                         .tx_buf = st->tx,
 143                         .rx_buf = st->rx,
 144                         .bits_per_word = 8,
 145                         .len = 2,
 146                         .cs_change = 1,
 147                 }, {
 148                         .tx_buf = st->tx + 2,
 149                         .rx_buf = st->rx + 2,
 150                         .bits_per_word = 8,
 151                         .len = 2,
 152                 },
 153         };
 154
 155         mutex_lock(&st->buf_lock);
 156         st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
 157         st->tx[1] = 0;
 158         st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address + 1);
 159         st->tx[3] = 0;
 160
 161         ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
 162         if (ret) {
 163                 dev_err(&st->us->dev, "problem when reading 16 bit register");
 164                 goto error_ret;
 165         }
 166         tempval = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
 167
 168         *val = tempval;
 169 error_ret:
 170         mutex_unlock(&st->buf_lock);
 171         return ret;
 172 }
 173
 174 enum lis3l02dq_rm_ind {
 175         LIS3L02DQ_ACCEL,
 176         LIS3L02DQ_GAIN,
 177         LIS3L02DQ_BIAS,
 178 };
 179
 180 static u8 lis3l02dq_axis_map[3][3] = {
 181         [LIS3L02DQ_ACCEL] = { LIS3L02DQ_REG_OUT_X_L_ADDR,
 182                               LIS3L02DQ_REG_OUT_Y_L_ADDR,
 183                               LIS3L02DQ_REG_OUT_Z_L_ADDR },
 184         [LIS3L02DQ_GAIN] = { LIS3L02DQ_REG_GAIN_X_ADDR,
 185                              LIS3L02DQ_REG_GAIN_Y_ADDR,
 186                              LIS3L02DQ_REG_GAIN_Z_ADDR },
 187         [LIS3L02DQ_BIAS] = { LIS3L02DQ_REG_OFFSET_X_ADDR,
 188                              LIS3L02DQ_REG_OFFSET_Y_ADDR,
 189                              LIS3L02DQ_REG_OFFSET_Z_ADDR }
 190 };
 191
 192 static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
 193                                  u64 e,
 194                                  int *val)
 195 {
 196         return lis3l02dq_read_reg_s16(indio_dev, LIS3L02DQ_REG_THS_L_ADDR, val);
 197 }
 198
 199 static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
 200                                   u64 event_code,
 201                                   int val)
 202 {
 203         u16 value = val;
 204         return lis3l02dq_spi_write_reg_s16(indio_dev,
 205                                            LIS3L02DQ_REG_THS_L_ADDR,
 206                                            value);
 207 }
 208
 209 static int lis3l02dq_write_raw(struct iio_dev *indio_dev,
 210                                struct iio_chan_spec const *chan,
 211                                int val,
 212                                int val2,
 213                                long mask)
 214 {
 215         int ret = -EINVAL, reg;
 216         u8 uval;
 217         s8 sval;
 218         switch (mask) {
 219         case IIO_CHAN_INFO_CALIBBIAS:
 220                 if (val > 255 || val < -256)
 221                         return -EINVAL;
 222                 sval = val;
 223                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 224                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, sval);
 225                 break;
 226         case IIO_CHAN_INFO_CALIBSCALE:
 227                 if (val & ~0xFF)
 228                         return -EINVAL;
 229                 uval = val;
 230                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 231                 ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, uval);
 232                 break;
 233         }
 234         return ret;
 235 }
 236
 237 static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
 238                               struct iio_chan_spec const *chan,
 239                               int *val,
 240                               int *val2,
 241                               long mask)
 242 {
 243         u8 utemp;
 244         s8 stemp;
 245         ssize_t ret = 0;
 246         u8 reg;
 247
 248         switch (mask) {
 249         case IIO_CHAN_INFO_RAW:
 250                 /* Take the iio_dev status lock */
 251                 mutex_lock(&indio_dev->mlock);
 252                 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) {
 253                         ret = -EBUSY;
 254                 } else {
 255                         reg = lis3l02dq_axis_map
 256                                 [LIS3L02DQ_ACCEL][chan->address];
 257                         ret = lis3l02dq_read_reg_s16(indio_dev, reg, val);
 258                 }
 259                 mutex_unlock(&indio_dev->mlock);
 260                 if (ret < 0)
 261                         goto error_ret;
 262                 return IIO_VAL_INT;
 263         case IIO_CHAN_INFO_SCALE:
 264                 *val = 0;
 265                 *val2 = 9580;
 266                 return IIO_VAL_INT_PLUS_MICRO;
 267         case IIO_CHAN_INFO_CALIBSCALE:
 268                 reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
 269                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, &utemp);
 270                 if (ret)
 271                         goto error_ret;
 272                 /* to match with what previous code does */
 273                 *val = utemp;
 274                 return IIO_VAL_INT;
 275
 276         case IIO_CHAN_INFO_CALIBBIAS:
 277                 reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
 278                 ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, (u8 *)&stemp);
 279                 /* to match with what previous code does */
 280                 *val = stemp;
 281                 return IIO_VAL_INT;
 282         }
 283 error_ret:
 284         return ret;
 285 }
 286
 287 static ssize_t lis3l02dq_read_frequency(struct device *dev,
 288                                         struct device_attribute *attr,
 289                                         char *buf)
 290 {
 291         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 292         int ret, len = 0;
 293         s8 t;
 294         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 295                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 296                                        (u8 *)&t);
 297         if (ret)
 298                 return ret;
 299         t &= LIS3L02DQ_DEC_MASK;
 300         switch (t) {
 301         case LIS3L02DQ_REG_CTRL_1_DF_128:
 302                 len = sprintf(buf, "280\n");
 303                 break;
 304         case LIS3L02DQ_REG_CTRL_1_DF_64:
 305                 len = sprintf(buf, "560\n");
 306                 break;
 307         case LIS3L02DQ_REG_CTRL_1_DF_32:
 308                 len = sprintf(buf, "1120\n");
 309                 break;
 310         case LIS3L02DQ_REG_CTRL_1_DF_8:
 311                 len = sprintf(buf, "4480\n");
 312                 break;
 313         }
 314         return len;
 315 }
 316
 317 static ssize_t lis3l02dq_write_frequency(struct device *dev,
 318                                          struct device_attribute *attr,
 319                                          const char *buf,
 320                                          size_t len)
 321 {
 322         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 323         unsigned long val;
 324         int ret;
 325         u8 t;
 326
 327         ret = kstrtoul(buf, 10, &val);
 328         if (ret)
 329                 return ret;
 330
 331         mutex_lock(&indio_dev->mlock);
 332         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 333                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 334                                        &t);
 335         if (ret)
 336                 goto error_ret_mutex;
 337         /* Wipe the bits clean */
 338         t &= ~LIS3L02DQ_DEC_MASK;
 339         switch (val) {
 340         case 280:
 341                 t |= LIS3L02DQ_REG_CTRL_1_DF_128;
 342                 break;
 343         case 560:
 344                 t |= LIS3L02DQ_REG_CTRL_1_DF_64;
 345                 break;
 346         case 1120:
 347                 t |= LIS3L02DQ_REG_CTRL_1_DF_32;
 348                 break;
 349         case 4480:
 350                 t |= LIS3L02DQ_REG_CTRL_1_DF_8;
 351                 break;
 352         default:
 353                 ret = -EINVAL;
 354                 goto error_ret_mutex;
 355         }
 356
 357         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 358                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 359                                         t);
 360
 361 error_ret_mutex:
 362         mutex_unlock(&indio_dev->mlock);
 363
 364         return ret ? ret : len;
 365 }
 366
 367 static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
 368 {
 369         struct lis3l02dq_state *st = iio_priv(indio_dev);
 370         int ret;
 371         u8 val, valtest;
 372
 373         st->us->mode = SPI_MODE_3;
 374
 375         spi_setup(st->us);
 376
 377         val = LIS3L02DQ_DEFAULT_CTRL1;
 378         /* Write suitable defaults to ctrl1 */
 379         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 380                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 381                                         val);
 382         if (ret) {
 383                 dev_err(&st->us->dev, "problem with setup control register 1");
 384                 goto err_ret;
 385         }
 386         /* Repeat as sometimes doesn't work first time? */
 387         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 388                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 389                                         val);
 390         if (ret) {
 391                 dev_err(&st->us->dev, "problem with setup control register 1");
 392                 goto err_ret;
 393         }
 394
 395         /* Read back to check this has worked acts as loose test of correct
 396          * chip */
 397         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 398                                        LIS3L02DQ_REG_CTRL_1_ADDR,
 399                                        &valtest);
 400         if (ret || (valtest != val)) {
 401                 dev_err(&indio_dev->dev,
 402                         "device not playing ball %d %d\n", valtest, val);
 403                 ret = -EINVAL;
 404                 goto err_ret;
 405         }
 406
 407         val = LIS3L02DQ_DEFAULT_CTRL2;
 408         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 409                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 410                                         val);
 411         if (ret) {
 412                 dev_err(&st->us->dev, "problem with setup control register 2");
 413                 goto err_ret;
 414         }
 415
 416         val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
 417         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 418                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 419                                         val);
 420         if (ret)
 421                 dev_err(&st->us->dev, "problem with interrupt cfg register");
 422 err_ret:
 423
 424         return ret;
 425 }
 426
 427 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
 428                               lis3l02dq_read_frequency,
 429                               lis3l02dq_write_frequency);
 430
 431 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
 432
 433 static irqreturn_t lis3l02dq_event_handler(int irq, void *private)
 434 {
 435         struct iio_dev *indio_dev = private;
 436         u8 t;
 437
 438         s64 timestamp = iio_get_time_ns();
 439
 440         lis3l02dq_spi_read_reg_8(indio_dev,
 441                                  LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
 442                                  &t);
 443
 444         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
 445                 iio_push_event(indio_dev,
 446                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 447                                                   0,
 448                                                   IIO_MOD_Z,
 449                                                   IIO_EV_TYPE_THRESH,
 450                                                   IIO_EV_DIR_RISING),
 451                                timestamp);
 452
 453         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
 454                 iio_push_event(indio_dev,
 455                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 456                                                   0,
 457                                                   IIO_MOD_Z,
 458                                                   IIO_EV_TYPE_THRESH,
 459                                                   IIO_EV_DIR_FALLING),
 460                                timestamp);
 461
 462         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
 463                 iio_push_event(indio_dev,
 464                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 465                                                   0,
 466                                                   IIO_MOD_Y,
 467                                                   IIO_EV_TYPE_THRESH,
 468                                                   IIO_EV_DIR_RISING),
 469                                timestamp);
 470
 471         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
 472                 iio_push_event(indio_dev,
 473                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 474                                                   0,
 475                                                   IIO_MOD_Y,
 476                                                   IIO_EV_TYPE_THRESH,
 477                                                   IIO_EV_DIR_FALLING),
 478                                timestamp);
 479
 480         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
 481                 iio_push_event(indio_dev,
 482                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 483                                                   0,
 484                                                   IIO_MOD_X,
 485                                                   IIO_EV_TYPE_THRESH,
 486                                                   IIO_EV_DIR_RISING),
 487                                timestamp);
 488
 489         if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
 490                 iio_push_event(indio_dev,
 491                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
 492                                                   0,
 493                                                   IIO_MOD_X,
 494                                                   IIO_EV_TYPE_THRESH,
 495                                                   IIO_EV_DIR_FALLING),
 496                                timestamp);
 497
 498         /* Ack and allow for new interrupts */
 499         lis3l02dq_spi_read_reg_8(indio_dev,
 500                                  LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
 501                                  &t);
 502
 503         return IRQ_HANDLED;
 504 }
 505
 506 #define LIS3L02DQ_EVENT_MASK                                    \
 507         (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) |    \
 508          IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
 509
 510 #define LIS3L02DQ_CHAN(index, mod)                              \
 511         {                                                       \
 512                 .type = IIO_ACCEL,                              \
 513                 .modified = 1,                                  \
 514                 .channel2 = mod,                                \
 515                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |  \
 516                         BIT(IIO_CHAN_INFO_CALIBSCALE) |         \
 517                         BIT(IIO_CHAN_INFO_CALIBBIAS),           \
 518                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
 519                 .address = index,                               \
 520                 .scan_index = index,                            \
 521                 .scan_type = {                                  \
 522                         .sign = 's',                            \
 523                         .realbits = 12,                         \
 524                         .storagebits = 16,                      \
 525                 },                                              \
 526                 .event_mask = LIS3L02DQ_EVENT_MASK,             \
 527          }
 528
 529 static const struct iio_chan_spec lis3l02dq_channels[] = {
 530         LIS3L02DQ_CHAN(0, IIO_MOD_X),
 531         LIS3L02DQ_CHAN(1, IIO_MOD_Y),
 532         LIS3L02DQ_CHAN(2, IIO_MOD_Z),
 533         IIO_CHAN_SOFT_TIMESTAMP(3)
 534 };
 535
 536
 537 static int lis3l02dq_read_event_config(struct iio_dev *indio_dev,
 538                                            u64 event_code)
 539 {
 540
 541         u8 val;
 542         int ret;
 543         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 544                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 545                           IIO_EV_DIR_RISING)));
 546         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 547                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 548                                        &val);
 549         if (ret < 0)
 550                 return ret;
 551
 552         return !!(val & mask);
 553 }
 554
 555 int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
 556 {
 557         int ret;
 558         u8 control, val;
 559
 560         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 561                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 562                                        &control);
 563
 564         control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
 565         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 566                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 567                                         control);
 568         if (ret)
 569                 goto error_ret;
 570         /* Also for consistency clear the mask */
 571         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 572                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 573                                        &val);
 574         if (ret)
 575                 goto error_ret;
 576         val &= ~0x3f;
 577
 578         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 579                                         LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 580                                         val);
 581         if (ret)
 582                 goto error_ret;
 583
 584         ret = control;
 585 error_ret:
 586         return ret;
 587 }
 588
 589 static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
 590                                         u64 event_code,
 591                                         int state)
 592 {
 593         int ret = 0;
 594         u8 val, control;
 595         u8 currentlyset;
 596         bool changed = false;
 597         u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
 598                          (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
 599                           IIO_EV_DIR_RISING)));
 600
 601         mutex_lock(&indio_dev->mlock);
 602         /* read current control */
 603         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 604                                        LIS3L02DQ_REG_CTRL_2_ADDR,
 605                                        &control);
 606         if (ret)
 607                 goto error_ret;
 608         ret = lis3l02dq_spi_read_reg_8(indio_dev,
 609                                        LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 610                                        &val);
 611         if (ret < 0)
 612                 goto error_ret;
 613         currentlyset = val & mask;
 614
 615         if (!currentlyset && state) {
 616                 changed = true;
 617                 val |= mask;
 618         } else if (currentlyset && !state) {
 619                 changed = true;
 620                 val &= ~mask;
 621         }
 622
 623         if (changed) {
 624                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 625                                                 LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
 626                                                 val);
 627                 if (ret)
 628                         goto error_ret;
 629                 control = val & 0x3f ?
 630                         (control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
 631                         (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
 632                 ret = lis3l02dq_spi_write_reg_8(indio_dev,
 633                                                LIS3L02DQ_REG_CTRL_2_ADDR,
 634                                                control);
 635                 if (ret)
 636                         goto error_ret;
 637         }
 638
 639 error_ret:
 640         mutex_unlock(&indio_dev->mlock);
 641         return ret;
 642 }
 643
 644 static struct attribute *lis3l02dq_attributes[] = {
 645         &iio_dev_attr_sampling_frequency.dev_attr.attr,
 646         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 647         NULL
 648 };
 649
 650 static const struct attribute_group lis3l02dq_attribute_group = {
 651         .attrs = lis3l02dq_attributes,
 652 };
 653
 654 static const struct iio_info lis3l02dq_info = {
 655         .read_raw = &lis3l02dq_read_raw,
 656         .write_raw = &lis3l02dq_write_raw,
 657         .read_event_value = &lis3l02dq_read_thresh,
 658         .write_event_value = &lis3l02dq_write_thresh,
 659         .write_event_config = &lis3l02dq_write_event_config,
 660         .read_event_config = &lis3l02dq_read_event_config,
 661         .driver_module = THIS_MODULE,
 662         .attrs = &lis3l02dq_attribute_group,
 663 };
 664
 665 static int lis3l02dq_probe(struct spi_device *spi)
 666 {
 667         int ret;
 668         struct lis3l02dq_state *st;
 669         struct iio_dev *indio_dev;
 670
 671         indio_dev = iio_device_alloc(sizeof *st);
 672         if (indio_dev == NULL) {
 673                 ret = -ENOMEM;
 674                 goto error_ret;
 675         }
 676         st = iio_priv(indio_dev);
 677         /* this is only used for removal purposes */
 678         spi_set_drvdata(spi, indio_dev);
 679
 680         st->us = spi;
 681         st->gpio = of_get_gpio(spi->dev.of_node, 0);
 682         mutex_init(&st->buf_lock);
 683         indio_dev->name = spi->dev.driver->name;
 684         indio_dev->dev.parent = &spi->dev;
 685         indio_dev->info = &lis3l02dq_info;
 686         indio_dev->channels = lis3l02dq_channels;
 687         indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
 688
 689         indio_dev->modes = INDIO_DIRECT_MODE;
 690
 691         ret = lis3l02dq_configure_buffer(indio_dev);
 692         if (ret)
 693                 goto error_free_dev;
 694
 695         ret = iio_buffer_register(indio_dev,
 696                                   lis3l02dq_channels,
 697                                   ARRAY_SIZE(lis3l02dq_channels));
 698         if (ret) {
 699                 printk(KERN_ERR "failed to initialize the buffer\n");
 700                 goto error_unreg_buffer_funcs;
 701         }
 702
 703         if (spi->irq) {
 704                 ret = request_threaded_irq(st->us->irq,
 705                                            &lis3l02dq_th,
 706                                            &lis3l02dq_event_handler,
 707                                            IRQF_TRIGGER_RISING,
 708                                            "lis3l02dq",
 709                                            indio_dev);
 710                 if (ret)
 711                         goto error_uninitialize_buffer;
 712
 713                 ret = lis3l02dq_probe_trigger(indio_dev);
 714                 if (ret)
 715                         goto error_free_interrupt;
 716         }
 717
 718         /* Get the device into a sane initial state */
 719         ret = lis3l02dq_initial_setup(indio_dev);
 720         if (ret)
 721                 goto error_remove_trigger;
 722
 723         ret = iio_device_register(indio_dev);
 724         if (ret)
 725                 goto error_remove_trigger;
 726
 727         return 0;
 728
 729 error_remove_trigger:
 730         if (spi->irq)
 731                 lis3l02dq_remove_trigger(indio_dev);
 732 error_free_interrupt:
 733         if (spi->irq)
 734                 free_irq(st->us->irq, indio_dev);
 735 error_uninitialize_buffer:
 736         iio_buffer_unregister(indio_dev);
 737 error_unreg_buffer_funcs:
 738         lis3l02dq_unconfigure_buffer(indio_dev);
 739 error_free_dev:
 740         iio_device_free(indio_dev);
 741 error_ret:
 742         return ret;
 743 }
 744
 745 /* Power down the device */
 746 static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
 747 {
 748         int ret;
 749         struct lis3l02dq_state *st = iio_priv(indio_dev);
 750         u8 val = 0;
 751
 752         mutex_lock(&indio_dev->mlock);
 753         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 754                                         LIS3L02DQ_REG_CTRL_1_ADDR,
 755                                         val);
 756         if (ret) {
 757                 dev_err(&st->us->dev, "problem with turning device off: ctrl1");
 758                 goto err_ret;
 759         }
 760
 761         ret = lis3l02dq_spi_write_reg_8(indio_dev,
 762                                         LIS3L02DQ_REG_CTRL_2_ADDR,
 763                                         val);
 764         if (ret)
 765                 dev_err(&st->us->dev, "problem with turning device off: ctrl2");
 766 err_ret:
 767         mutex_unlock(&indio_dev->mlock);
 768         return ret;
 769 }
 770
 771 /* fixme, confirm ordering in this function */
 772 static int lis3l02dq_remove(struct spi_device *spi)
 773 {
 774         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 775         struct lis3l02dq_state *st = iio_priv(indio_dev);
 776
 777         iio_device_unregister(indio_dev);
 778
 779         lis3l02dq_disable_all_events(indio_dev);
 780         lis3l02dq_stop_device(indio_dev);
 781
 782         if (spi->irq)
 783                 free_irq(st->us->irq, indio_dev);
 784
 785         lis3l02dq_remove_trigger(indio_dev);
 786         iio_buffer_unregister(indio_dev);
 787         lis3l02dq_unconfigure_buffer(indio_dev);
 788
 789         iio_device_free(indio_dev);
 790
 791         return 0;
 792 }
 793
 794 static struct spi_driver lis3l02dq_driver = {
 795         .driver = {
 796                 .name = "lis3l02dq",
 797                 .owner = THIS_MODULE,
 798         },
 799         .probe = lis3l02dq_probe,
 800         .remove = lis3l02dq_remove,
 801 };
 802 module_spi_driver(lis3l02dq_driver);
 803
 804 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
 805 MODULE_DESCRIPTION("ST LIS3L02DQ Accelerometer SPI driver");
 806 MODULE_LICENSE("GPL v2");
 807 MODULE_ALIAS("spi:lis3l02dq");