drivers/staging/dwc2/hcd_intr.c

   1 /*
   2  * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * This file contains the interrupt handlers for Host mode
  39  */
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/dma-mapping.h>
  45 #include <linux/io.h>
  46 #include <linux/slab.h>
  47 #include <linux/usb.h>
  48
  49 #include <linux/usb/hcd.h>
  50 #include <linux/usb/ch11.h>
  51
  52 #include "core.h"
  53 #include "hcd.h"
  54
  55 /* This function is for debug only */
  56 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
  57 {
  58 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
  59         u16 curr_frame_number = hsotg->frame_number;
  60
  61         if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
  62                 if (((hsotg->last_frame_num + 1) & HFNUM_MAX_FRNUM) !=
  63                     curr_frame_number) {
  64                         hsotg->frame_num_array[hsotg->frame_num_idx] =
  65                                         curr_frame_number;
  66                         hsotg->last_frame_num_array[hsotg->frame_num_idx] =
  67                                         hsotg->last_frame_num;
  68                         hsotg->frame_num_idx++;
  69                 }
  70         } else if (!hsotg->dumped_frame_num_array) {
  71                 int i;
  72
  73                 dev_info(hsotg->dev, "Frame     Last Frame\n");
  74                 dev_info(hsotg->dev, "-----     ----------\n");
  75                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
  76                         dev_info(hsotg->dev, "0x%04x    0x%04x\n",
  77                                  hsotg->frame_num_array[i],
  78                                  hsotg->last_frame_num_array[i]);
  79                 }
  80                 hsotg->dumped_frame_num_array = 1;
  81         }
  82         hsotg->last_frame_num = curr_frame_number;
  83 #endif
  84 }
  85
  86 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
  87                                     struct dwc2_host_chan *chan,
  88                                     struct dwc2_qtd *qtd)
  89 {
  90         struct urb *usb_urb;
  91
  92         if (!chan->qh || !qtd->urb)
  93                 return;
  94
  95         usb_urb = qtd->urb->priv;
  96         if (!usb_urb || !usb_urb->dev)
  97                 return;
  98
  99         if (chan->qh->dev_speed != USB_SPEED_HIGH &&
 100             qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
 101                 chan->qh->tt_buffer_dirty = 1;
 102                 if (usb_hub_clear_tt_buffer(usb_urb))
 103                         /* Clear failed; let's hope things work anyway */
 104                         chan->qh->tt_buffer_dirty = 0;
 105         }
 106 }
 107
 108 /*
 109  * Handles the start-of-frame interrupt in host mode. Non-periodic
 110  * transactions may be queued to the DWC_otg controller for the current
 111  * (micro)frame. Periodic transactions may be queued to the controller
 112  * for the next (micro)frame.
 113  */
 114 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
 115 {
 116         struct list_head *qh_entry;
 117         struct dwc2_qh *qh;
 118         u32 hfnum;
 119         enum dwc2_transaction_type tr_type;
 120
 121 #ifdef DEBUG_SOF
 122         dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
 123 #endif
 124
 125         hfnum = readl(hsotg->regs + HFNUM);
 126         hsotg->frame_number = hfnum >> HFNUM_FRNUM_SHIFT &
 127                             HFNUM_FRNUM_MASK >> HFNUM_FRNUM_SHIFT;
 128
 129         dwc2_track_missed_sofs(hsotg);
 130
 131         /* Determine whether any periodic QHs should be executed */
 132         qh_entry = hsotg->periodic_sched_inactive.next;
 133         while (qh_entry != &hsotg->periodic_sched_inactive) {
 134                 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
 135                 qh_entry = qh_entry->next;
 136                 if (dwc2_frame_num_le(qh->sched_frame, hsotg->frame_number))
 137                         /*
 138                          * Move QH to the ready list to be executed next
 139                          * (micro)frame
 140                          */
 141                         list_move(&qh->qh_list_entry,
 142                                   &hsotg->periodic_sched_ready);
 143         }
 144         tr_type = dwc2_hcd_select_transactions(hsotg);
 145         if (tr_type != DWC2_TRANSACTION_NONE)
 146                 dwc2_hcd_queue_transactions(hsotg, tr_type);
 147
 148         /* Clear interrupt */
 149         writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
 150 }
 151
 152 /*
 153  * Handles the Rx FIFO Level Interrupt, which indicates that there is
 154  * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
 155  * memory if the DWC_otg controller is operating in Slave mode.
 156  */
 157 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
 158 {
 159         u32 grxsts, chnum, bcnt, dpid, pktsts;
 160         struct dwc2_host_chan *chan;
 161
 162         if (dbg_perio())
 163                 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
 164
 165         grxsts = readl(hsotg->regs + GRXSTSP);
 166         chnum = grxsts >> GRXSTS_HCHNUM_SHIFT &
 167                 GRXSTS_HCHNUM_MASK >> GRXSTS_HCHNUM_SHIFT;
 168         chan = hsotg->hc_ptr_array[chnum];
 169         if (!chan) {
 170                 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
 171                 return;
 172         }
 173
 174         bcnt = grxsts >> GRXSTS_BYTECNT_SHIFT &
 175                GRXSTS_BYTECNT_MASK >> GRXSTS_BYTECNT_SHIFT;
 176         dpid = grxsts >> GRXSTS_DPID_SHIFT &
 177                GRXSTS_DPID_MASK >> GRXSTS_DPID_SHIFT;
 178         pktsts = grxsts & GRXSTS_PKTSTS_MASK;
 179
 180         /* Packet Status */
 181         if (dbg_perio()) {
 182                 dev_vdbg(hsotg->dev, "    Ch num = %d\n", chnum);
 183                 dev_vdbg(hsotg->dev, "    Count = %d\n", bcnt);
 184                 dev_vdbg(hsotg->dev, "    DPID = %d, chan.dpid = %d\n", dpid,
 185                          chan->data_pid_start);
 186                 dev_vdbg(hsotg->dev, "    PStatus = %d\n",
 187                          pktsts >> GRXSTS_PKTSTS_SHIFT &
 188                          GRXSTS_PKTSTS_MASK >> GRXSTS_PKTSTS_SHIFT);
 189         }
 190
 191         switch (pktsts) {
 192         case GRXSTS_PKTSTS_HCHIN:
 193                 /* Read the data into the host buffer */
 194                 if (bcnt > 0) {
 195                         dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
 196
 197                         /* Update the HC fields for the next packet received */
 198                         chan->xfer_count += bcnt;
 199                         chan->xfer_buf += bcnt;
 200                 }
 201                 break;
 202         case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
 203         case GRXSTS_PKTSTS_DATATOGGLEERR:
 204         case GRXSTS_PKTSTS_HCHHALTED:
 205                 /* Handled in interrupt, just ignore data */
 206                 break;
 207         default:
 208                 dev_err(hsotg->dev,
 209                         "RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
 210                 break;
 211         }
 212 }
 213
 214 /*
 215  * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
 216  * data packets may be written to the FIFO for OUT transfers. More requests
 217  * may be written to the non-periodic request queue for IN transfers. This
 218  * interrupt is enabled only in Slave mode.
 219  */
 220 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 221 {
 222         dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
 223         dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
 224 }
 225
 226 /*
 227  * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
 228  * packets may be written to the FIFO for OUT transfers. More requests may be
 229  * written to the periodic request queue for IN transfers. This interrupt is
 230  * enabled only in Slave mode.
 231  */
 232 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
 233 {
 234         if (dbg_perio())
 235                 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
 236         dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
 237 }
 238
 239 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
 240                               u32 *hprt0_modify)
 241 {
 242         struct dwc2_core_params *params = hsotg->core_params;
 243         int do_reset = 0;
 244         u32 usbcfg;
 245         u32 prtspd;
 246         u32 hcfg;
 247         u32 hfir;
 248
 249         dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
 250
 251         /* Every time when port enables calculate HFIR.FrInterval */
 252         hfir = readl(hsotg->regs + HFIR);
 253         hfir &= ~HFIR_FRINT_MASK;
 254         hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
 255                 HFIR_FRINT_MASK;
 256         writel(hfir, hsotg->regs + HFIR);
 257
 258         /* Check if we need to adjust the PHY clock speed for low power */
 259         if (!params->host_support_fs_ls_low_power) {
 260                 /* Port has been enabled, set the reset change flag */
 261                 hsotg->flags.b.port_reset_change = 1;
 262                 return;
 263         }
 264
 265         usbcfg = readl(hsotg->regs + GUSBCFG);
 266         prtspd = hprt0 & HPRT0_SPD_MASK;
 267
 268         if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
 269                 /* Low power */
 270                 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
 271                         /* Set PHY low power clock select for FS/LS devices */
 272                         usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
 273                         writel(usbcfg, hsotg->regs + GUSBCFG);
 274                         do_reset = 1;
 275                 }
 276
 277                 hcfg = readl(hsotg->regs + HCFG);
 278
 279                 if (prtspd == HPRT0_SPD_LOW_SPEED &&
 280                     params->host_ls_low_power_phy_clk ==
 281                     DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
 282                         /* 6 MHZ */
 283                         dev_vdbg(hsotg->dev,
 284                                  "FS_PHY programming HCFG to 6 MHz\n");
 285                         if ((hcfg & HCFG_FSLSPCLKSEL_MASK) !=
 286                             HCFG_FSLSPCLKSEL_6_MHZ) {
 287                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 288                                 hcfg |= HCFG_FSLSPCLKSEL_6_MHZ;
 289                                 writel(hcfg, hsotg->regs + HCFG);
 290                                 do_reset = 1;
 291                         }
 292                 } else {
 293                         /* 48 MHZ */
 294                         dev_vdbg(hsotg->dev,
 295                                  "FS_PHY programming HCFG to 48 MHz\n");
 296                         if ((hcfg & HCFG_FSLSPCLKSEL_MASK) !=
 297                             HCFG_FSLSPCLKSEL_48_MHZ) {
 298                                 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 299                                 hcfg |= HCFG_FSLSPCLKSEL_48_MHZ;
 300                                 writel(hcfg, hsotg->regs + HCFG);
 301                                 do_reset = 1;
 302                         }
 303                 }
 304         } else {
 305                 /* Not low power */
 306                 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
 307                         usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
 308                         writel(usbcfg, hsotg->regs + GUSBCFG);
 309                         do_reset = 1;
 310                 }
 311         }
 312
 313         if (do_reset) {
 314                 *hprt0_modify |= HPRT0_RST;
 315                 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
 316                                    msecs_to_jiffies(60));
 317         } else {
 318                 /* Port has been enabled, set the reset change flag */
 319                 hsotg->flags.b.port_reset_change = 1;
 320         }
 321 }
 322
 323 /*
 324  * There are multiple conditions that can cause a port interrupt. This function
 325  * determines which interrupt conditions have occurred and handles them
 326  * appropriately.
 327  */
 328 static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
 329 {
 330         u32 hprt0;
 331         u32 hprt0_modify;
 332
 333         dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
 334
 335         hprt0 = readl(hsotg->regs + HPRT0);
 336         hprt0_modify = hprt0;
 337
 338         /*
 339          * Clear appropriate bits in HPRT0 to clear the interrupt bit in
 340          * GINTSTS
 341          */
 342         hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
 343                           HPRT0_OVRCURRCHG);
 344
 345         /*
 346          * Port Connect Detected
 347          * Set flag and clear if detected
 348          */
 349         if (hprt0 & HPRT0_CONNDET) {
 350                 dev_vdbg(hsotg->dev,
 351                          "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
 352                          hprt0);
 353                 hsotg->flags.b.port_connect_status_change = 1;
 354                 hsotg->flags.b.port_connect_status = 1;
 355                 hprt0_modify |= HPRT0_CONNDET;
 356
 357                 /*
 358                  * The Hub driver asserts a reset when it sees port connect
 359                  * status change flag
 360                  */
 361         }
 362
 363         /*
 364          * Port Enable Changed
 365          * Clear if detected - Set internal flag if disabled
 366          */
 367         if (hprt0 & HPRT0_ENACHG) {
 368                 dev_vdbg(hsotg->dev,
 369                          "  --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
 370                          hprt0, !!(hprt0 & HPRT0_ENA));
 371                 hprt0_modify |= HPRT0_ENACHG;
 372                 if (hprt0 & HPRT0_ENA)
 373                         dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
 374                 else
 375                         hsotg->flags.b.port_enable_change = 1;
 376         }
 377
 378         /* Overcurrent Change Interrupt */
 379         if (hprt0 & HPRT0_OVRCURRCHG) {
 380                 dev_vdbg(hsotg->dev,
 381                          "  --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
 382                          hprt0);
 383                 hsotg->flags.b.port_over_current_change = 1;
 384                 hprt0_modify |= HPRT0_OVRCURRCHG;
 385         }
 386
 387         /* Clear Port Interrupts */
 388         writel(hprt0_modify, hsotg->regs + HPRT0);
 389 }
 390
 391 /*
 392  * Gets the actual length of a transfer after the transfer halts. halt_status
 393  * holds the reason for the halt.
 394  *
 395  * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
 396  * is set to 1 upon return if less than the requested number of bytes were
 397  * transferred. short_read may also be NULL on entry, in which case it remains
 398  * unchanged.
 399  */
 400 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
 401                                        struct dwc2_host_chan *chan, int chnum,
 402                                        struct dwc2_qtd *qtd,
 403                                        enum dwc2_halt_status halt_status,
 404                                        int *short_read)
 405 {
 406         u32 hctsiz, count, length;
 407
 408         hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
 409
 410         if (halt_status == DWC2_HC_XFER_COMPLETE) {
 411                 if (chan->ep_is_in) {
 412                         count = hctsiz >> TSIZ_XFERSIZE_SHIFT &
 413                                 TSIZ_XFERSIZE_MASK >> TSIZ_XFERSIZE_SHIFT;
 414                         length = chan->xfer_len - count;
 415                         if (short_read != NULL)
 416                                 *short_read = (count != 0);
 417                 } else if (chan->qh->do_split) {
 418                         length = qtd->ssplit_out_xfer_count;
 419                 } else {
 420                         length = chan->xfer_len;
 421                 }
 422         } else {
 423                 /*
 424                  * Must use the hctsiz.pktcnt field to determine how much data
 425                  * has been transferred. This field reflects the number of
 426                  * packets that have been transferred via the USB. This is
 427                  * always an integral number of packets if the transfer was
 428                  * halted before its normal completion. (Can't use the
 429                  * hctsiz.xfersize field because that reflects the number of
 430                  * bytes transferred via the AHB, not the USB).
 431                  */
 432                 count = hctsiz >> TSIZ_PKTCNT_SHIFT &
 433                         TSIZ_PKTCNT_MASK >> TSIZ_PKTCNT_SHIFT;
 434                 length = (chan->start_pkt_count - count) * chan->max_packet;
 435         }
 436
 437         return length;
 438 }
 439
 440 /**
 441  * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
 442  * Complete interrupt on the host channel. Updates the actual_length field
 443  * of the URB based on the number of bytes transferred via the host channel.
 444  * Sets the URB status if the data transfer is finished.
 445  *
 446  * Return: 1 if the data transfer specified by the URB is completely finished,
 447  * 0 otherwise
 448  */
 449 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
 450                                  struct dwc2_host_chan *chan, int chnum,
 451                                  struct dwc2_hcd_urb *urb,
 452                                  struct dwc2_qtd *qtd)
 453 {
 454         u32 hctsiz;
 455         int xfer_done = 0;
 456         int short_read = 0;
 457         int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 458                                                       DWC2_HC_XFER_COMPLETE,
 459                                                       &short_read);
 460
 461         if (urb->actual_length + xfer_length > urb->length) {
 462                 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
 463                 xfer_length = urb->length - urb->actual_length;
 464         }
 465
 466         /* Non DWORD-aligned buffer case handling */
 467         if (chan->align_buf && xfer_length && chan->ep_is_in) {
 468                 dev_dbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
 469                 dma_sync_single_for_cpu(hsotg->dev, urb->dma, urb->length,
 470                                         DMA_FROM_DEVICE);
 471                 memcpy(urb->buf + urb->actual_length, chan->qh->dw_align_buf,
 472                        xfer_length);
 473                 dma_sync_single_for_device(hsotg->dev, urb->dma, urb->length,
 474                                            DMA_FROM_DEVICE);
 475         }
 476
 477         dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
 478                  urb->actual_length, xfer_length);
 479         urb->actual_length += xfer_length;
 480
 481         if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
 482             (urb->flags & URB_SEND_ZERO_PACKET) &&
 483             urb->actual_length >= urb->length &&
 484             !(urb->length % chan->max_packet)) {
 485                 xfer_done = 0;
 486         } else if (short_read || urb->actual_length >= urb->length) {
 487                 xfer_done = 1;
 488                 urb->status = 0;
 489         }
 490
 491         hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
 492         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
 493                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
 494         dev_vdbg(hsotg->dev, "  chan->xfer_len %d\n", chan->xfer_len);
 495         dev_vdbg(hsotg->dev, "  hctsiz.xfersize %d\n",
 496                  hctsiz >> TSIZ_XFERSIZE_SHIFT &
 497                  TSIZ_XFERSIZE_MASK >> TSIZ_XFERSIZE_SHIFT);
 498         dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n", urb->length);
 499         dev_vdbg(hsotg->dev, "  urb->actual_length %d\n", urb->actual_length);
 500         dev_vdbg(hsotg->dev, "  short_read %d, xfer_done %d\n", short_read,
 501                  xfer_done);
 502
 503         return xfer_done;
 504 }
 505
 506 /*
 507  * Save the starting data toggle for the next transfer. The data toggle is
 508  * saved in the QH for non-control transfers and it's saved in the QTD for
 509  * control transfers.
 510  */
 511 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
 512                                struct dwc2_host_chan *chan, int chnum,
 513                                struct dwc2_qtd *qtd)
 514 {
 515         u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
 516         u32 pid = hctsiz & TSIZ_SC_MC_PID_MASK;
 517
 518         if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
 519                 if (pid == TSIZ_SC_MC_PID_DATA0)
 520                         chan->qh->data_toggle = DWC2_HC_PID_DATA0;
 521                 else
 522                         chan->qh->data_toggle = DWC2_HC_PID_DATA1;
 523         } else {
 524                 if (pid == TSIZ_SC_MC_PID_DATA0)
 525                         qtd->data_toggle = DWC2_HC_PID_DATA0;
 526                 else
 527                         qtd->data_toggle = DWC2_HC_PID_DATA1;
 528         }
 529 }
 530
 531 /**
 532  * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
 533  * the transfer is stopped for any reason. The fields of the current entry in
 534  * the frame descriptor array are set based on the transfer state and the input
 535  * halt_status. Completes the Isochronous URB if all the URB frames have been
 536  * completed.
 537  *
 538  * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
 539  * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
 540  */
 541 static enum dwc2_halt_status dwc2_update_isoc_urb_state(
 542                 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
 543                 int chnum, struct dwc2_qtd *qtd,
 544                 enum dwc2_halt_status halt_status)
 545 {
 546         struct dwc2_hcd_iso_packet_desc *frame_desc;
 547         struct dwc2_hcd_urb *urb = qtd->urb;
 548
 549         if (!urb)
 550                 return DWC2_HC_XFER_NO_HALT_STATUS;
 551
 552         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 553
 554         switch (halt_status) {
 555         case DWC2_HC_XFER_COMPLETE:
 556                 frame_desc->status = 0;
 557                 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 558                                         chan, chnum, qtd, halt_status, NULL);
 559
 560                 /* Non DWORD-aligned buffer case handling */
 561                 if (chan->align_buf && frame_desc->actual_length &&
 562                     chan->ep_is_in) {
 563                         dev_dbg(hsotg->dev, "%s(): non-aligned buffer\n",
 564                                 __func__);
 565                         dma_sync_single_for_cpu(hsotg->dev, urb->dma,
 566                                                 urb->length, DMA_FROM_DEVICE);
 567                         memcpy(urb->buf + frame_desc->offset +
 568                                qtd->isoc_split_offset, chan->qh->dw_align_buf,
 569                                frame_desc->actual_length);
 570                         dma_sync_single_for_device(hsotg->dev, urb->dma,
 571                                                    urb->length,
 572                                                    DMA_FROM_DEVICE);
 573                 }
 574                 break;
 575         case DWC2_HC_XFER_FRAME_OVERRUN:
 576                 urb->error_count++;
 577                 if (chan->ep_is_in)
 578                         frame_desc->status = -ENOSR;
 579                 else
 580                         frame_desc->status = -ECOMM;
 581                 frame_desc->actual_length = 0;
 582                 break;
 583         case DWC2_HC_XFER_BABBLE_ERR:
 584                 urb->error_count++;
 585                 frame_desc->status = -EOVERFLOW;
 586                 /* Don't need to update actual_length in this case */
 587                 break;
 588         case DWC2_HC_XFER_XACT_ERR:
 589                 urb->error_count++;
 590                 frame_desc->status = -EPROTO;
 591                 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
 592                                         chan, chnum, qtd, halt_status, NULL);
 593
 594                 /* Non DWORD-aligned buffer case handling */
 595                 if (chan->align_buf && frame_desc->actual_length &&
 596                     chan->ep_is_in) {
 597                         dev_dbg(hsotg->dev, "%s(): non-aligned buffer\n",
 598                                 __func__);
 599                         dma_sync_single_for_cpu(hsotg->dev, urb->dma,
 600                                                 urb->length, DMA_FROM_DEVICE);
 601                         memcpy(urb->buf + frame_desc->offset +
 602                                qtd->isoc_split_offset, chan->qh->dw_align_buf,
 603                                frame_desc->actual_length);
 604                         dma_sync_single_for_device(hsotg->dev, urb->dma,
 605                                                    urb->length,
 606                                                    DMA_FROM_DEVICE);
 607                 }
 608
 609                 /* Skip whole frame */
 610                 if (chan->qh->do_split &&
 611                     chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
 612                     hsotg->core_params->dma_enable > 0) {
 613                         qtd->complete_split = 0;
 614                         qtd->isoc_split_offset = 0;
 615                 }
 616
 617                 break;
 618         default:
 619                 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
 620                         halt_status);
 621                 break;
 622         }
 623
 624         if (++qtd->isoc_frame_index == urb->packet_count) {
 625                 /*
 626                  * urb->status is not used for isoc transfers. The individual
 627                  * frame_desc statuses are used instead.
 628                  */
 629                 dwc2_host_complete(hsotg, urb->priv, urb, 0);
 630                 halt_status = DWC2_HC_XFER_URB_COMPLETE;
 631         } else {
 632                 halt_status = DWC2_HC_XFER_COMPLETE;
 633         }
 634
 635         return halt_status;
 636 }
 637
 638 /*
 639  * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
 640  * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
 641  * still linked to the QH, the QH is added to the end of the inactive
 642  * non-periodic schedule. For periodic QHs, removes the QH from the periodic
 643  * schedule if no more QTDs are linked to the QH.
 644  */
 645 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 646                                int free_qtd)
 647 {
 648         int continue_split = 0;
 649         struct dwc2_qtd *qtd;
 650
 651         if (dbg_qh(qh))
 652                 dev_vdbg(hsotg->dev, "  %s(%p,%p,%d)\n", __func__,
 653                          hsotg, qh, free_qtd);
 654
 655         if (list_empty(&qh->qtd_list)) {
 656                 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
 657                 goto no_qtd;
 658         }
 659
 660         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
 661
 662         if (qtd->complete_split)
 663                 continue_split = 1;
 664         else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
 665                  qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
 666                 continue_split = 1;
 667
 668         if (free_qtd) {
 669                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 670                 continue_split = 0;
 671         }
 672
 673 no_qtd:
 674         if (qh->channel)
 675                 qh->channel->align_buf = 0;
 676         qh->channel = NULL;
 677         dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
 678 }
 679
 680 /**
 681  * dwc2_release_channel() - Releases a host channel for use by other transfers
 682  *
 683  * @hsotg:       The HCD state structure
 684  * @chan:        The host channel to release
 685  * @qtd:         The QTD associated with the host channel. This QTD may be
 686  *               freed if the transfer is complete or an error has occurred.
 687  * @halt_status: Reason the channel is being released. This status
 688  *               determines the actions taken by this function.
 689  *
 690  * Also attempts to select and queue more transactions since at least one host
 691  * channel is available.
 692  */
 693 static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
 694                                  struct dwc2_host_chan *chan,
 695                                  struct dwc2_qtd *qtd,
 696                                  enum dwc2_halt_status halt_status)
 697 {
 698         enum dwc2_transaction_type tr_type;
 699         u32 haintmsk;
 700         int free_qtd = 0;
 701
 702         if (dbg_hc(chan))
 703                 dev_vdbg(hsotg->dev, "  %s: channel %d, halt_status %d\n",
 704                          __func__, chan->hc_num, halt_status);
 705
 706         switch (halt_status) {
 707         case DWC2_HC_XFER_URB_COMPLETE:
 708                 free_qtd = 1;
 709                 break;
 710         case DWC2_HC_XFER_AHB_ERR:
 711         case DWC2_HC_XFER_STALL:
 712         case DWC2_HC_XFER_BABBLE_ERR:
 713                 free_qtd = 1;
 714                 break;
 715         case DWC2_HC_XFER_XACT_ERR:
 716                 if (qtd && qtd->error_count >= 3) {
 717                         dev_vdbg(hsotg->dev,
 718                                  "  Complete URB with transaction error\n");
 719                         free_qtd = 1;
 720                         if (qtd->urb) {
 721                                 qtd->urb->status = -EPROTO;
 722                                 dwc2_host_complete(hsotg, qtd->urb->priv,
 723                                                    qtd->urb, -EPROTO);
 724                         }
 725                 }
 726                 break;
 727         case DWC2_HC_XFER_URB_DEQUEUE:
 728                 /*
 729                  * The QTD has already been removed and the QH has been
 730                  * deactivated. Don't want to do anything except release the
 731                  * host channel and try to queue more transfers.
 732                  */
 733                 goto cleanup;
 734         case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
 735                 dev_vdbg(hsotg->dev, "  Complete URB with I/O error\n");
 736                 free_qtd = 1;
 737                 if (qtd && qtd->urb) {
 738                         qtd->urb->status = -EIO;
 739                         dwc2_host_complete(hsotg, qtd->urb->priv, qtd->urb,
 740                                            -EIO);
 741                 }
 742                 break;
 743         case DWC2_HC_XFER_NO_HALT_STATUS:
 744         default:
 745                 break;
 746         }
 747
 748         dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
 749
 750 cleanup:
 751         /*
 752          * Release the host channel for use by other transfers. The cleanup
 753          * function clears the channel interrupt enables and conditions, so
 754          * there's no need to clear the Channel Halted interrupt separately.
 755          */
 756         if (!list_empty(&chan->hc_list_entry))
 757                 list_del(&chan->hc_list_entry);
 758         dwc2_hc_cleanup(hsotg, chan);
 759         list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
 760
 761         switch (chan->ep_type) {
 762         case USB_ENDPOINT_XFER_CONTROL:
 763         case USB_ENDPOINT_XFER_BULK:
 764                 hsotg->non_periodic_channels--;
 765                 break;
 766         default:
 767                 /*
 768                  * Don't release reservations for periodic channels here.
 769                  * That's done when a periodic transfer is descheduled (i.e.
 770                  * when the QH is removed from the periodic schedule).
 771                  */
 772                 break;
 773         }
 774
 775         haintmsk = readl(hsotg->regs + HAINTMSK);
 776         haintmsk &= ~(1 << chan->hc_num);
 777         writel(haintmsk, hsotg->regs + HAINTMSK);
 778
 779         /* Try to queue more transfers now that there's a free channel */
 780         tr_type = dwc2_hcd_select_transactions(hsotg);
 781         if (tr_type != DWC2_TRANSACTION_NONE)
 782                 dwc2_hcd_queue_transactions(hsotg, tr_type);
 783 }
 784
 785 /*
 786  * Halts a host channel. If the channel cannot be halted immediately because
 787  * the request queue is full, this function ensures that the FIFO empty
 788  * interrupt for the appropriate queue is enabled so that the halt request can
 789  * be queued when there is space in the request queue.
 790  *
 791  * This function may also be called in DMA mode. In that case, the channel is
 792  * simply released since the core always halts the channel automatically in
 793  * DMA mode.
 794  */
 795 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
 796                               struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
 797                               enum dwc2_halt_status halt_status)
 798 {
 799         if (dbg_hc(chan))
 800                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 801
 802         if (hsotg->core_params->dma_enable > 0) {
 803                 if (dbg_hc(chan))
 804                         dev_vdbg(hsotg->dev, "DMA enabled\n");
 805                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 806                 return;
 807         }
 808
 809         /* Slave mode processing */
 810         dwc2_hc_halt(hsotg, chan, halt_status);
 811
 812         if (chan->halt_on_queue) {
 813                 u32 gintmsk;
 814
 815                 dev_vdbg(hsotg->dev, "Halt on queue\n");
 816                 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
 817                     chan->ep_type == USB_ENDPOINT_XFER_BULK) {
 818                         dev_vdbg(hsotg->dev, "control/bulk\n");
 819                         /*
 820                          * Make sure the Non-periodic Tx FIFO empty interrupt
 821                          * is enabled so that the non-periodic schedule will
 822                          * be processed
 823                          */
 824                         gintmsk = readl(hsotg->regs + GINTMSK);
 825                         gintmsk |= GINTSTS_NPTXFEMP;
 826                         writel(gintmsk, hsotg->regs + GINTMSK);
 827                 } else {
 828                         dev_vdbg(hsotg->dev, "isoc/intr\n");
 829                         /*
 830                          * Move the QH from the periodic queued schedule to
 831                          * the periodic assigned schedule. This allows the
 832                          * halt to be queued when the periodic schedule is
 833                          * processed.
 834                          */
 835                         list_move(&chan->qh->qh_list_entry,
 836                                   &hsotg->periodic_sched_assigned);
 837
 838                         /*
 839                          * Make sure the Periodic Tx FIFO Empty interrupt is
 840                          * enabled so that the periodic schedule will be
 841                          * processed
 842                          */
 843                         gintmsk = readl(hsotg->regs + GINTMSK);
 844                         gintmsk |= GINTSTS_PTXFEMP;
 845                         writel(gintmsk, hsotg->regs + GINTMSK);
 846                 }
 847         }
 848 }
 849
 850 /*
 851  * Performs common cleanup for non-periodic transfers after a Transfer
 852  * Complete interrupt. This function should be called after any endpoint type
 853  * specific handling is finished to release the host channel.
 854  */
 855 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
 856                                             struct dwc2_host_chan *chan,
 857                                             int chnum, struct dwc2_qtd *qtd,
 858                                             enum dwc2_halt_status halt_status)
 859 {
 860         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 861
 862         qtd->error_count = 0;
 863
 864         if (chan->hcint & HCINTMSK_NYET) {
 865                 /*
 866                  * Got a NYET on the last transaction of the transfer. This
 867                  * means that the endpoint should be in the PING state at the
 868                  * beginning of the next transfer.
 869                  */
 870                 dev_vdbg(hsotg->dev, "got NYET\n");
 871                 chan->qh->ping_state = 1;
 872         }
 873
 874         /*
 875          * Always halt and release the host channel to make it available for
 876          * more transfers. There may still be more phases for a control
 877          * transfer or more data packets for a bulk transfer at this point,
 878          * but the host channel is still halted. A channel will be reassigned
 879          * to the transfer when the non-periodic schedule is processed after
 880          * the channel is released. This allows transactions to be queued
 881          * properly via dwc2_hcd_queue_transactions, which also enables the
 882          * Tx FIFO Empty interrupt if necessary.
 883          */
 884         if (chan->ep_is_in) {
 885                 /*
 886                  * IN transfers in Slave mode require an explicit disable to
 887                  * halt the channel. (In DMA mode, this call simply releases
 888                  * the channel.)
 889                  */
 890                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 891         } else {
 892                 /*
 893                  * The channel is automatically disabled by the core for OUT
 894                  * transfers in Slave mode
 895                  */
 896                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 897         }
 898 }
 899
 900 /*
 901  * Performs common cleanup for periodic transfers after a Transfer Complete
 902  * interrupt. This function should be called after any endpoint type specific
 903  * handling is finished to release the host channel.
 904  */
 905 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
 906                                         struct dwc2_host_chan *chan, int chnum,
 907                                         struct dwc2_qtd *qtd,
 908                                         enum dwc2_halt_status halt_status)
 909 {
 910         u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
 911
 912         qtd->error_count = 0;
 913
 914         if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
 915                 /* Core halts channel in these cases */
 916                 dwc2_release_channel(hsotg, chan, qtd, halt_status);
 917         else
 918                 /* Flush any outstanding requests from the Tx queue */
 919                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
 920 }
 921
 922 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
 923                                        struct dwc2_host_chan *chan, int chnum,
 924                                        struct dwc2_qtd *qtd)
 925 {
 926         struct dwc2_hcd_iso_packet_desc *frame_desc;
 927         u32 len;
 928
 929         if (!qtd->urb)
 930                 return 0;
 931
 932         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
 933         len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
 934                                           DWC2_HC_XFER_COMPLETE, NULL);
 935         if (!len) {
 936                 qtd->complete_split = 0;
 937                 qtd->isoc_split_offset = 0;
 938                 return 0;
 939         }
 940
 941         frame_desc->actual_length += len;
 942
 943         if (chan->align_buf && len) {
 944                 dev_dbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
 945                 dma_sync_single_for_cpu(hsotg->dev, qtd->urb->dma,
 946                                         qtd->urb->length, DMA_FROM_DEVICE);
 947                 memcpy(qtd->urb->buf + frame_desc->offset +
 948                        qtd->isoc_split_offset, chan->qh->dw_align_buf, len);
 949                 dma_sync_single_for_device(hsotg->dev, qtd->urb->dma,
 950                                            qtd->urb->length, DMA_FROM_DEVICE);
 951         }
 952
 953         qtd->isoc_split_offset += len;
 954
 955         if (frame_desc->actual_length >= frame_desc->length) {
 956                 frame_desc->status = 0;
 957                 qtd->isoc_frame_index++;
 958                 qtd->complete_split = 0;
 959                 qtd->isoc_split_offset = 0;
 960         }
 961
 962         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
 963                 dwc2_host_complete(hsotg, qtd->urb->priv, qtd->urb, 0);
 964                 dwc2_release_channel(hsotg, chan, qtd,
 965                                      DWC2_HC_XFER_URB_COMPLETE);
 966         } else {
 967                 dwc2_release_channel(hsotg, chan, qtd,
 968                                      DWC2_HC_XFER_NO_HALT_STATUS);
 969         }
 970
 971         return 1;       /* Indicates that channel released */
 972 }
 973
 974 /*
 975  * Handles a host channel Transfer Complete interrupt. This handler may be
 976  * called in either DMA mode or Slave mode.
 977  */
 978 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
 979                                   struct dwc2_host_chan *chan, int chnum,
 980                                   struct dwc2_qtd *qtd)
 981 {
 982         struct dwc2_hcd_urb *urb = qtd->urb;
 983         int pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
 984         enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
 985         int urb_xfer_done;
 986
 987         if (dbg_hc(chan))
 988                 dev_vdbg(hsotg->dev,
 989                          "--Host Channel %d Interrupt: Transfer Complete--\n",
 990                          chnum);
 991
 992         if (hsotg->core_params->dma_desc_enable > 0) {
 993                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
 994                 if (pipe_type == USB_ENDPOINT_XFER_ISOC)
 995                         /* Do not disable the interrupt, just clear it */
 996                         return;
 997                 goto handle_xfercomp_done;
 998         }
 999
1000         /* Handle xfer complete on CSPLIT */
1001         if (chan->qh->do_split) {
1002                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
1003                     hsotg->core_params->dma_enable > 0) {
1004                         if (qtd->complete_split &&
1005                             dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
1006                                                         qtd))
1007                                 goto handle_xfercomp_done;
1008                 } else {
1009                         qtd->complete_split = 0;
1010                 }
1011         }
1012
1013         if (!urb)
1014                 goto handle_xfercomp_done;
1015
1016         /* Update the QTD and URB states */
1017         switch (pipe_type) {
1018         case USB_ENDPOINT_XFER_CONTROL:
1019                 switch (qtd->control_phase) {
1020                 case DWC2_CONTROL_SETUP:
1021                         if (urb->length > 0)
1022                                 qtd->control_phase = DWC2_CONTROL_DATA;
1023                         else
1024                                 qtd->control_phase = DWC2_CONTROL_STATUS;
1025                         dev_vdbg(hsotg->dev,
1026                                  "  Control setup transaction done\n");
1027                         halt_status = DWC2_HC_XFER_COMPLETE;
1028                         break;
1029                 case DWC2_CONTROL_DATA:
1030                         urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1031                                                               chnum, urb, qtd);
1032                         if (urb_xfer_done) {
1033                                 qtd->control_phase = DWC2_CONTROL_STATUS;
1034                                 dev_vdbg(hsotg->dev,
1035                                          "  Control data transfer done\n");
1036                         } else {
1037                                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1038                                                           qtd);
1039                         }
1040                         halt_status = DWC2_HC_XFER_COMPLETE;
1041                         break;
1042                 case DWC2_CONTROL_STATUS:
1043                         dev_vdbg(hsotg->dev, "  Control transfer complete\n");
1044                         if (urb->status == -EINPROGRESS)
1045                                 urb->status = 0;
1046                         dwc2_host_complete(hsotg, urb->priv, urb, urb->status);
1047                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1048                         break;
1049                 }
1050
1051                 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1052                                                 halt_status);
1053                 break;
1054         case USB_ENDPOINT_XFER_BULK:
1055                 dev_vdbg(hsotg->dev, "  Bulk transfer complete\n");
1056                 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1057                                                       qtd);
1058                 if (urb_xfer_done) {
1059                         dwc2_host_complete(hsotg, urb->priv, urb, urb->status);
1060                         halt_status = DWC2_HC_XFER_URB_COMPLETE;
1061                 } else {
1062                         halt_status = DWC2_HC_XFER_COMPLETE;
1063                 }
1064
1065                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1066                 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1067                                                 halt_status);
1068                 break;
1069         case USB_ENDPOINT_XFER_INT:
1070                 dev_vdbg(hsotg->dev, "  Interrupt transfer complete\n");
1071                 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1072                                                       qtd);
1073
1074                 /*
1075                  * Interrupt URB is done on the first transfer complete
1076                  * interrupt
1077                  */
1078                 if (urb_xfer_done) {
1079                                 dwc2_host_complete(hsotg, urb->priv, urb,
1080                                                    urb->status);
1081                                 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1082                 } else {
1083                                 halt_status = DWC2_HC_XFER_COMPLETE;
1084                 }
1085
1086                 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1087                 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1088                                             halt_status);
1089                 break;
1090         case USB_ENDPOINT_XFER_ISOC:
1091                 if (dbg_perio())
1092                         dev_vdbg(hsotg->dev, "  Isochronous transfer complete\n");
1093                 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1094                         halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1095                                         chnum, qtd, DWC2_HC_XFER_COMPLETE);
1096                 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1097                                             halt_status);
1098                 break;
1099         }
1100
1101 handle_xfercomp_done:
1102         disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1103 }
1104
1105 /*
1106  * Handles a host channel STALL interrupt. This handler may be called in
1107  * either DMA mode or Slave mode.
1108  */
1109 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1110                                struct dwc2_host_chan *chan, int chnum,
1111                                struct dwc2_qtd *qtd)
1112 {
1113         struct dwc2_hcd_urb *urb = qtd->urb;
1114         int pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1115
1116         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1117                 chnum);
1118
1119         if (hsotg->core_params->dma_desc_enable > 0) {
1120                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1121                                             DWC2_HC_XFER_STALL);
1122                 goto handle_stall_done;
1123         }
1124
1125         if (!urb)
1126                 goto handle_stall_halt;
1127
1128         if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
1129                 dwc2_host_complete(hsotg, urb->priv, urb, -EPIPE);
1130
1131         if (pipe_type == USB_ENDPOINT_XFER_BULK ||
1132             pipe_type == USB_ENDPOINT_XFER_INT) {
1133                 dwc2_host_complete(hsotg, urb->priv, urb, -EPIPE);
1134                 /*
1135                  * USB protocol requires resetting the data toggle for bulk
1136                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1137                  * setup command is issued to the endpoint. Anticipate the
1138                  * CLEAR_FEATURE command since a STALL has occurred and reset
1139                  * the data toggle now.
1140                  */
1141                 chan->qh->data_toggle = 0;
1142         }
1143
1144 handle_stall_halt:
1145         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1146
1147 handle_stall_done:
1148         disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1149 }
1150
1151 /*
1152  * Updates the state of the URB when a transfer has been stopped due to an
1153  * abnormal condition before the transfer completes. Modifies the
1154  * actual_length field of the URB to reflect the number of bytes that have
1155  * actually been transferred via the host channel.
1156  */
1157 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1158                                       struct dwc2_host_chan *chan, int chnum,
1159                                       struct dwc2_hcd_urb *urb,
1160                                       struct dwc2_qtd *qtd,
1161                                       enum dwc2_halt_status halt_status)
1162 {
1163         u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1164                                                       qtd, halt_status, NULL);
1165         u32 hctsiz;
1166
1167         if (urb->actual_length + xfer_length > urb->length) {
1168                 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1169                 xfer_length = urb->length - urb->actual_length;
1170         }
1171
1172         /* Non DWORD-aligned buffer case handling */
1173         if (chan->align_buf && xfer_length && chan->ep_is_in) {
1174                 dev_dbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
1175                 dma_sync_single_for_cpu(hsotg->dev, urb->dma, urb->length,
1176                                         DMA_FROM_DEVICE);
1177                 memcpy(urb->buf + urb->actual_length, chan->qh->dw_align_buf,
1178                        xfer_length);
1179                 dma_sync_single_for_device(hsotg->dev, urb->dma, urb->length,
1180                                            DMA_FROM_DEVICE);
1181         }
1182
1183         urb->actual_length += xfer_length;
1184
1185         hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
1186         dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1187                  __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1188         dev_vdbg(hsotg->dev, "  chan->start_pkt_count %d\n",
1189                  chan->start_pkt_count);
1190         dev_vdbg(hsotg->dev, "  hctsiz.pktcnt %d\n",
1191                  hctsiz >> TSIZ_PKTCNT_SHIFT &
1192                  TSIZ_PKTCNT_MASK >> TSIZ_PKTCNT_SHIFT);
1193         dev_vdbg(hsotg->dev, "  chan->max_packet %d\n", chan->max_packet);
1194         dev_vdbg(hsotg->dev, "  bytes_transferred %d\n",
1195                  xfer_length);
1196         dev_vdbg(hsotg->dev, "  urb->actual_length %d\n",
1197                  urb->actual_length);
1198         dev_vdbg(hsotg->dev, "  urb->transfer_buffer_length %d\n",
1199                  urb->length);
1200 }
1201
1202 /*
1203  * Handles a host channel NAK interrupt. This handler may be called in either
1204  * DMA mode or Slave mode.
1205  */
1206 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1207                              struct dwc2_host_chan *chan, int chnum,
1208                              struct dwc2_qtd *qtd)
1209 {
1210         if (dbg_hc(chan))
1211                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1212                          chnum);
1213
1214         /*
1215          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1216          * interrupt. Re-start the SSPLIT transfer.
1217          */
1218         if (chan->do_split) {
1219                 if (chan->complete_split)
1220                         qtd->error_count = 0;
1221                 qtd->complete_split = 0;
1222                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1223                 goto handle_nak_done;
1224         }
1225
1226         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1227         case USB_ENDPOINT_XFER_CONTROL:
1228         case USB_ENDPOINT_XFER_BULK:
1229                 if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) {
1230                         /*
1231                          * NAK interrupts are enabled on bulk/control IN
1232                          * transfers in DMA mode for the sole purpose of
1233                          * resetting the error count after a transaction error
1234                          * occurs. The core will continue transferring data.
1235                          */
1236                         qtd->error_count = 0;
1237                         break;
1238                 }
1239
1240                 /*
1241                  * NAK interrupts normally occur during OUT transfers in DMA
1242                  * or Slave mode. For IN transfers, more requests will be
1243                  * queued as request queue space is available.
1244                  */
1245                 qtd->error_count = 0;
1246
1247                 if (!chan->qh->ping_state) {
1248                         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1249                                                   qtd, DWC2_HC_XFER_NAK);
1250                         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1251
1252                         if (chan->speed == USB_SPEED_HIGH)
1253                                 chan->qh->ping_state = 1;
1254                 }
1255
1256                 /*
1257                  * Halt the channel so the transfer can be re-started from
1258                  * the appropriate point or the PING protocol will
1259                  * start/continue
1260                  */
1261                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1262                 break;
1263         case USB_ENDPOINT_XFER_INT:
1264                 qtd->error_count = 0;
1265                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1266                 break;
1267         case USB_ENDPOINT_XFER_ISOC:
1268                 /* Should never get called for isochronous transfers */
1269                 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1270                 break;
1271         }
1272
1273 handle_nak_done:
1274         disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1275 }
1276
1277 /*
1278  * Handles a host channel ACK interrupt. This interrupt is enabled when
1279  * performing the PING protocol in Slave mode, when errors occur during
1280  * either Slave mode or DMA mode, and during Start Split transactions.
1281  */
1282 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1283                              struct dwc2_host_chan *chan, int chnum,
1284                              struct dwc2_qtd *qtd)
1285 {
1286         struct dwc2_hcd_iso_packet_desc *frame_desc;
1287
1288         if (dbg_hc(chan))
1289                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1290                          chnum);
1291
1292         if (chan->do_split) {
1293                 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
1294                 if (!chan->ep_is_in &&
1295                     chan->data_pid_start != DWC2_HC_PID_SETUP)
1296                         qtd->ssplit_out_xfer_count = chan->xfer_len;
1297
1298                 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
1299                         qtd->complete_split = 1;
1300                         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1301                 } else {
1302                         /* ISOC OUT */
1303                         switch (chan->xact_pos) {
1304                         case DWC2_HCSPLT_XACTPOS_ALL:
1305                                 break;
1306                         case DWC2_HCSPLT_XACTPOS_END:
1307                                 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1308                                 qtd->isoc_split_offset = 0;
1309                                 break;
1310                         case DWC2_HCSPLT_XACTPOS_BEGIN:
1311                         case DWC2_HCSPLT_XACTPOS_MID:
1312                                 /*
1313                                  * For BEGIN or MID, calculate the length for
1314                                  * the next microframe to determine the correct
1315                                  * SSPLIT token, either MID or END
1316                                  */
1317                                 frame_desc = &qtd->urb->iso_descs[
1318                                                 qtd->isoc_frame_index];
1319                                 qtd->isoc_split_offset += 188;
1320
1321                                 if (frame_desc->length - qtd->isoc_split_offset
1322                                                         <= 188)
1323                                         qtd->isoc_split_pos =
1324                                                         DWC2_HCSPLT_XACTPOS_END;
1325                                 else
1326                                         qtd->isoc_split_pos =
1327                                                         DWC2_HCSPLT_XACTPOS_MID;
1328                                 break;
1329                         }
1330                 }
1331         } else {
1332                 qtd->error_count = 0;
1333
1334                 if (chan->qh->ping_state) {
1335                         chan->qh->ping_state = 0;
1336                         /*
1337                          * Halt the channel so the transfer can be re-started
1338                          * from the appropriate point. This only happens in
1339                          * Slave mode. In DMA mode, the ping_state is cleared
1340                          * when the transfer is started because the core
1341                          * automatically executes the PING, then the transfer.
1342                          */
1343                         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1344                 }
1345         }
1346
1347         /*
1348          * If the ACK occurred when _not_ in the PING state, let the channel
1349          * continue transferring data after clearing the error count
1350          */
1351         disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1352 }
1353
1354 /*
1355  * Handles a host channel NYET interrupt. This interrupt should only occur on
1356  * Bulk and Control OUT endpoints and for complete split transactions. If a
1357  * NYET occurs at the same time as a Transfer Complete interrupt, it is
1358  * handled in the xfercomp interrupt handler, not here. This handler may be
1359  * called in either DMA mode or Slave mode.
1360  */
1361 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1362                               struct dwc2_host_chan *chan, int chnum,
1363                               struct dwc2_qtd *qtd)
1364 {
1365         if (dbg_hc(chan))
1366                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1367                          chnum);
1368
1369         /*
1370          * NYET on CSPLIT
1371          * re-do the CSPLIT immediately on non-periodic
1372          */
1373         if (chan->do_split && chan->complete_split) {
1374                 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
1375                     hsotg->core_params->dma_enable > 0) {
1376                         qtd->complete_split = 0;
1377                         qtd->isoc_split_offset = 0;
1378                         if (qtd->urb &&
1379                             ++qtd->isoc_frame_index == qtd->urb->packet_count) {
1380                                 dwc2_host_complete(hsotg, qtd->urb->priv,
1381                                                    qtd->urb, 0);
1382                                 dwc2_release_channel(hsotg, chan, qtd,
1383                                                      DWC2_HC_XFER_URB_COMPLETE);
1384                         } else {
1385                                 dwc2_release_channel(hsotg, chan, qtd,
1386                                                 DWC2_HC_XFER_NO_HALT_STATUS);
1387                         }
1388                         goto handle_nyet_done;
1389                 }
1390
1391                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1392                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1393                         int frnum = dwc2_hcd_get_frame_number(hsotg);
1394
1395                         if (dwc2_full_frame_num(frnum) !=
1396                             dwc2_full_frame_num(chan->qh->sched_frame)) {
1397                                 /*
1398                                  * No longer in the same full speed frame.
1399                                  * Treat this as a transaction error.
1400                                  */
1401 #if 0
1402                                 /*
1403                                  * Todo: Fix system performance so this can
1404                                  * be treated as an error. Right now complete
1405                                  * splits cannot be scheduled precisely enough
1406                                  * due to other system activity, so this error
1407                                  * occurs regularly in Slave mode.
1408                                  */
1409                                 qtd->error_count++;
1410 #endif
1411                                 qtd->complete_split = 0;
1412                                 dwc2_halt_channel(hsotg, chan, qtd,
1413                                                   DWC2_HC_XFER_XACT_ERR);
1414                                 /* Todo: add support for isoc release */
1415                                 goto handle_nyet_done;
1416                         }
1417                 }
1418
1419                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1420                 goto handle_nyet_done;
1421         }
1422
1423         chan->qh->ping_state = 1;
1424         qtd->error_count = 0;
1425
1426         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1427                                   DWC2_HC_XFER_NYET);
1428         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1429
1430         /*
1431          * Halt the channel and re-start the transfer so the PING protocol
1432          * will start
1433          */
1434         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1435
1436 handle_nyet_done:
1437         disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1438 }
1439
1440 /*
1441  * Handles a host channel babble interrupt. This handler may be called in
1442  * either DMA mode or Slave mode.
1443  */
1444 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1445                                 struct dwc2_host_chan *chan, int chnum,
1446                                 struct dwc2_qtd *qtd)
1447 {
1448         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1449                 chnum);
1450
1451         if (hsotg->core_params->dma_desc_enable > 0) {
1452                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1453                                             DWC2_HC_XFER_BABBLE_ERR);
1454                 goto handle_babble_done;
1455         }
1456
1457         if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1458                 if (qtd->urb)
1459                         dwc2_host_complete(hsotg, qtd->urb->priv, qtd->urb,
1460                                            -EOVERFLOW);
1461                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1462         } else {
1463                 enum dwc2_halt_status halt_status;
1464
1465                 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1466                                                 qtd, DWC2_HC_XFER_BABBLE_ERR);
1467                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1468         }
1469
1470 handle_babble_done:
1471         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1472         disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1473 }
1474
1475 /*
1476  * Handles a host channel AHB error interrupt. This handler is only called in
1477  * DMA mode.
1478  */
1479 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1480                                 struct dwc2_host_chan *chan, int chnum,
1481                                 struct dwc2_qtd *qtd)
1482 {
1483         struct dwc2_hcd_urb *urb = qtd->urb;
1484         char *pipetype, *speed;
1485         u32 hcchar;
1486         u32 hcsplt;
1487         u32 hctsiz;
1488         u32 hc_dma;
1489
1490         dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1491                 chnum);
1492
1493         if (!urb)
1494                 goto handle_ahberr_halt;
1495
1496         hcchar = readl(hsotg->regs + HCCHAR(chnum));
1497         hcsplt = readl(hsotg->regs + HCSPLT(chnum));
1498         hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
1499         hc_dma = readl(hsotg->regs + HCDMA(chnum));
1500
1501         dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1502         dev_err(hsotg->dev, "  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1503         dev_err(hsotg->dev, "  hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1504         dev_err(hsotg->dev, "  Device address: %d\n",
1505                 dwc2_hcd_get_dev_addr(&urb->pipe_info));
1506         dev_err(hsotg->dev, "  Endpoint: %d, %s\n",
1507                 dwc2_hcd_get_ep_num(&urb->pipe_info),
1508                 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
1509
1510         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
1511         case USB_ENDPOINT_XFER_CONTROL:
1512                 pipetype = "CONTROL";
1513                 break;
1514         case USB_ENDPOINT_XFER_BULK:
1515                 pipetype = "BULK";
1516                 break;
1517         case USB_ENDPOINT_XFER_INT:
1518                 pipetype = "INTERRUPT";
1519                 break;
1520         case USB_ENDPOINT_XFER_ISOC:
1521                 pipetype = "ISOCHRONOUS";
1522                 break;
1523         default:
1524                 pipetype = "UNKNOWN";
1525                 break;
1526         }
1527
1528         dev_err(hsotg->dev, "  Endpoint type: %s\n", pipetype);
1529
1530         switch (chan->speed) {
1531         case USB_SPEED_HIGH:
1532                 speed = "HIGH";
1533                 break;
1534         case USB_SPEED_FULL:
1535                 speed = "FULL";
1536                 break;
1537         case USB_SPEED_LOW:
1538                 speed = "LOW";
1539                 break;
1540         default:
1541                 speed = "UNKNOWN";
1542                 break;
1543         }
1544
1545         dev_err(hsotg->dev, "  Speed: %s\n", speed);
1546
1547         dev_err(hsotg->dev, "  Max packet size: %d\n",
1548                 dwc2_hcd_get_mps(&urb->pipe_info));
1549         dev_err(hsotg->dev, "  Data buffer length: %d\n", urb->length);
1550         dev_err(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
1551                 urb->buf, (unsigned long)urb->dma);
1552         dev_err(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
1553                 urb->setup_packet, (unsigned long)urb->setup_dma);
1554         dev_err(hsotg->dev, "  Interval: %d\n", urb->interval);
1555
1556         /* Core halts the channel for Descriptor DMA mode */
1557         if (hsotg->core_params->dma_desc_enable > 0) {
1558                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1559                                             DWC2_HC_XFER_AHB_ERR);
1560                 goto handle_ahberr_done;
1561         }
1562
1563         dwc2_host_complete(hsotg, urb->priv, urb, -EIO);
1564
1565 handle_ahberr_halt:
1566         /*
1567          * Force a channel halt. Don't call dwc2_halt_channel because that won't
1568          * write to the HCCHARn register in DMA mode to force the halt.
1569          */
1570         dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1571
1572 handle_ahberr_done:
1573         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1574         disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1575 }
1576
1577 /*
1578  * Handles a host channel transaction error interrupt. This handler may be
1579  * called in either DMA mode or Slave mode.
1580  */
1581 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1582                                  struct dwc2_host_chan *chan, int chnum,
1583                                  struct dwc2_qtd *qtd)
1584 {
1585         dev_dbg(hsotg->dev,
1586                 "--Host Channel %d Interrupt: Transaction Error--\n", chnum);
1587
1588         if (hsotg->core_params->dma_desc_enable > 0) {
1589                 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1590                                             DWC2_HC_XFER_XACT_ERR);
1591                 goto handle_xacterr_done;
1592         }
1593
1594         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1595         case USB_ENDPOINT_XFER_CONTROL:
1596         case USB_ENDPOINT_XFER_BULK:
1597                 qtd->error_count++;
1598                 if (!chan->qh->ping_state) {
1599
1600                         dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1601                                                   qtd, DWC2_HC_XFER_XACT_ERR);
1602                         dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1603                         if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
1604                                 chan->qh->ping_state = 1;
1605                 }
1606
1607                 /*
1608                  * Halt the channel so the transfer can be re-started from
1609                  * the appropriate point or the PING protocol will start
1610                  */
1611                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1612                 break;
1613         case USB_ENDPOINT_XFER_INT:
1614                 qtd->error_count++;
1615                 if (chan->do_split && chan->complete_split)
1616                         qtd->complete_split = 0;
1617                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1618                 break;
1619         case USB_ENDPOINT_XFER_ISOC:
1620                 {
1621                         enum dwc2_halt_status halt_status;
1622
1623                         halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1624                                         chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1625                         dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1626                 }
1627                 break;
1628         }
1629
1630 handle_xacterr_done:
1631         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1632         disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1633 }
1634
1635 /*
1636  * Handles a host channel frame overrun interrupt. This handler may be called
1637  * in either DMA mode or Slave mode.
1638  */
1639 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1640                                   struct dwc2_host_chan *chan, int chnum,
1641                                   struct dwc2_qtd *qtd)
1642 {
1643         enum dwc2_halt_status halt_status;
1644
1645         if (dbg_hc(chan))
1646                 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1647                         chnum);
1648
1649         switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1650         case USB_ENDPOINT_XFER_CONTROL:
1651         case USB_ENDPOINT_XFER_BULK:
1652                 break;
1653         case USB_ENDPOINT_XFER_INT:
1654                 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1655                 break;
1656         case USB_ENDPOINT_XFER_ISOC:
1657                 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1658                                         qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1659                 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1660                 break;
1661         }
1662
1663         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1664         disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1665 }
1666
1667 /*
1668  * Handles a host channel data toggle error interrupt. This handler may be
1669  * called in either DMA mode or Slave mode.
1670  */
1671 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1672                                     struct dwc2_host_chan *chan, int chnum,
1673                                     struct dwc2_qtd *qtd)
1674 {
1675         dev_dbg(hsotg->dev,
1676                 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
1677
1678         if (chan->ep_is_in)
1679                 qtd->error_count = 0;
1680         else
1681                 dev_err(hsotg->dev,
1682                         "Data Toggle Error on OUT transfer, channel %d\n",
1683                         chnum);
1684
1685         dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1686         disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1687 }
1688
1689 /*
1690  * For debug only. It checks that a valid halt status is set and that
1691  * HCCHARn.chdis is clear. If there's a problem, corrective action is
1692  * taken and a warning is issued.
1693  *
1694  * Return: true if halt status is ok, false otherwise
1695  */
1696 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1697                                 struct dwc2_host_chan *chan, int chnum,
1698                                 struct dwc2_qtd *qtd)
1699 {
1700 #ifdef DEBUG
1701         u32 hcchar;
1702         u32 hctsiz;
1703         u32 hcintmsk;
1704         u32 hcsplt;
1705
1706         if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
1707                 /*
1708                  * This code is here only as a check. This condition should
1709                  * never happen. Ignore the halt if it does occur.
1710                  */
1711                 hcchar = readl(hsotg->regs + HCCHAR(chnum));
1712                 hctsiz = readl(hsotg->regs + HCTSIZ(chnum));
1713                 hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
1714                 hcsplt = readl(hsotg->regs + HCSPLT(chnum));
1715                 dev_dbg(hsotg->dev,
1716                         "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1717                          __func__);
1718                 dev_dbg(hsotg->dev,
1719                         "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
1720                         chnum, hcchar, hctsiz);
1721                 dev_dbg(hsotg->dev,
1722                         "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
1723                         chan->hcint, hcintmsk, hcsplt);
1724                 if (qtd)
1725                         dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1726                                 qtd->complete_split);
1727                 dev_warn(hsotg->dev,
1728                          "%s: no halt status, channel %d, ignoring interrupt\n",
1729                          __func__, chnum);
1730                 return false;
1731         }
1732
1733         /*
1734          * This code is here only as a check. hcchar.chdis should never be set
1735          * when the halt interrupt occurs. Halt the channel again if it does
1736          * occur.
1737          */
1738         hcchar = readl(hsotg->regs + HCCHAR(chnum));
1739         if (hcchar & HCCHAR_CHDIS) {
1740                 dev_warn(hsotg->dev,
1741                          "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
1742                          __func__, hcchar);
1743                 chan->halt_pending = 0;
1744                 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1745                 return false;
1746         }
1747 #endif
1748
1749         return true;
1750 }
1751
1752 /*
1753  * Handles a host Channel Halted interrupt in DMA mode. This handler
1754  * determines the reason the channel halted and proceeds accordingly.
1755  */
1756 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1757                                     struct dwc2_host_chan *chan, int chnum,
1758                                     struct dwc2_qtd *qtd)
1759 {
1760         u32 hcintmsk;
1761         int out_nak_enh = 0;
1762
1763         if (dbg_hc(chan))
1764                 dev_vdbg(hsotg->dev,
1765                          "--Host Channel %d Interrupt: DMA Channel Halted--\n",
1766                          chnum);
1767
1768         /*
1769          * For core with OUT NAK enhancement, the flow for high-speed
1770          * CONTROL/BULK OUT is handled a little differently
1771          */
1772         if (hsotg->snpsid >= DWC2_CORE_REV_2_71a) {
1773                 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
1774                     (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1775                      chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
1776                         out_nak_enh = 1;
1777                 }
1778         }
1779
1780         if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1781             (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
1782              hsotg->core_params->dma_desc_enable <= 0)) {
1783                 if (hsotg->core_params->dma_desc_enable > 0)
1784                         dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1785                                                     chan->halt_status);
1786                 else
1787                         /*
1788                          * Just release the channel. A dequeue can happen on a
1789                          * transfer timeout. In the case of an AHB Error, the
1790                          * channel was forced to halt because there's no way to
1791                          * gracefully recover.
1792                          */
1793                         dwc2_release_channel(hsotg, chan, qtd,
1794                                              chan->halt_status);
1795                 return;
1796         }
1797
1798         hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
1799
1800         if (chan->hcint & HCINTMSK_XFERCOMPL) {
1801                 /*
1802                  * Todo: This is here because of a possible hardware bug. Spec
1803                  * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1804                  * interrupt w/ACK bit set should occur, but I only see the
1805                  * XFERCOMP bit, even with it masked out. This is a workaround
1806                  * for that behavior. Should fix this when hardware is fixed.
1807                  */
1808                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
1809                         dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1810                 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1811         } else if (chan->hcint & HCINTMSK_STALL) {
1812                 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1813         } else if ((chan->hcint & HCINTMSK_XACTERR) &&
1814                    hsotg->core_params->dma_desc_enable <= 0) {
1815                 if (out_nak_enh) {
1816                         if (chan->hcint &
1817                             (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
1818                                 dev_vdbg(hsotg->dev,
1819                                          "XactErr with NYET/NAK/ACK\n");
1820                                 qtd->error_count = 0;
1821                         } else {
1822                                 dev_vdbg(hsotg->dev,
1823                                          "XactErr without NYET/NAK/ACK\n");
1824                         }
1825                 }
1826
1827                 /*
1828                  * Must handle xacterr before nak or ack. Could get a xacterr
1829                  * at the same time as either of these on a BULK/CONTROL OUT
1830                  * that started with a PING. The xacterr takes precedence.
1831                  */
1832                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1833         } else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
1834                    hsotg->core_params->dma_desc_enable > 0) {
1835                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1836         } else if ((chan->hcint & HCINTMSK_AHBERR) &&
1837                    hsotg->core_params->dma_desc_enable > 0) {
1838                 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1839         } else if (chan->hcint & HCINTMSK_BBLERR) {
1840                 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1841         } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
1842                 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1843         } else if (!out_nak_enh) {
1844                 if (chan->hcint & HCINTMSK_NYET) {
1845                         /*
1846                          * Must handle nyet before nak or ack. Could get a nyet
1847                          * at the same time as either of those on a BULK/CONTROL
1848                          * OUT that started with a PING. The nyet takes
1849                          * precedence.
1850                          */
1851                         dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1852                 } else if ((chan->hcint & HCINTMSK_NAK) &&
1853                            !(hcintmsk & HCINTMSK_NAK)) {
1854                         /*
1855                          * If nak is not masked, it's because a non-split IN
1856                          * transfer is in an error state. In that case, the nak
1857                          * is handled by the nak interrupt handler, not here.
1858                          * Handle nak here for BULK/CONTROL OUT transfers, which
1859                          * halt on a NAK to allow rewinding the buffer pointer.
1860                          */
1861                         dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1862                 } else if ((chan->hcint & HCINTMSK_ACK) &&
1863                            !(hcintmsk & HCINTMSK_ACK)) {
1864                         /*
1865                          * If ack is not masked, it's because a non-split IN
1866                          * transfer is in an error state. In that case, the ack
1867                          * is handled by the ack interrupt handler, not here.
1868                          * Handle ack here for split transfers. Start splits
1869                          * halt on ACK.
1870                          */
1871                         dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1872                 } else {
1873                         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1874                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1875                                 /*
1876                                  * A periodic transfer halted with no other
1877                                  * channel interrupts set. Assume it was halted
1878                                  * by the core because it could not be completed
1879                                  * in its scheduled (micro)frame.
1880                                  */
1881                                 dev_dbg(hsotg->dev,
1882                                         "%s: Halt channel %d (assume incomplete periodic transfer)\n",
1883                                         __func__, chnum);
1884                                 dwc2_halt_channel(hsotg, chan, qtd,
1885                                         DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1886                         } else {
1887                                 dev_err(hsotg->dev,
1888                                         "%s: Channel %d - ChHltd set, but reason is unknown\n",
1889                                         __func__, chnum);
1890                                 dev_err(hsotg->dev,
1891                                         "hcint 0x%08x, intsts 0x%08x\n",
1892                                         chan->hcint,
1893                                         readl(hsotg->regs + GINTSTS));
1894                         }
1895                 }
1896         } else {
1897                 dev_info(hsotg->dev,
1898                          "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1899                          chan->hcint);
1900         }
1901 }
1902
1903 /*
1904  * Handles a host channel Channel Halted interrupt
1905  *
1906  * In slave mode, this handler is called only when the driver specifically
1907  * requests a halt. This occurs during handling other host channel interrupts
1908  * (e.g. nak, xacterr, stall, nyet, etc.).
1909  *
1910  * In DMA mode, this is the interrupt that occurs when the core has finished
1911  * processing a transfer on a channel. Other host channel interrupts (except
1912  * ahberr) are disabled in DMA mode.
1913  */
1914 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
1915                                 struct dwc2_host_chan *chan, int chnum,
1916                                 struct dwc2_qtd *qtd)
1917 {
1918         if (dbg_hc(chan))
1919                 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
1920                          chnum);
1921
1922         if (hsotg->core_params->dma_enable > 0) {
1923                 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
1924         } else {
1925                 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
1926                         return;
1927                 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
1928         }
1929 }
1930
1931 /* Handles interrupt for a specific Host Channel */
1932 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
1933 {
1934         struct dwc2_qtd *qtd;
1935         struct dwc2_host_chan *chan;
1936         u32 hcint, hcintmsk;
1937
1938         chan = hsotg->hc_ptr_array[chnum];
1939
1940         if (dbg_hc(chan))
1941                 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
1942                          chnum);
1943
1944         hcint = readl(hsotg->regs + HCINT(chnum));
1945         hcintmsk = readl(hsotg->regs + HCINTMSK(chnum));
1946         if (dbg_hc(chan))
1947                 dev_vdbg(hsotg->dev,
1948                          "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
1949                          hcint, hcintmsk, hcint & hcintmsk);
1950
1951         if (!chan) {
1952                 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
1953                 writel(hcint, hsotg->regs + HCINT(chnum));
1954                 return;
1955         }
1956
1957         writel(hcint, hsotg->regs + HCINT(chnum));
1958         chan->hcint = hcint;
1959         hcint &= hcintmsk;
1960
1961         /*
1962          * If the channel was halted due to a dequeue, the qtd list might
1963          * be empty or at least the first entry will not be the active qtd.
1964          * In this case, take a shortcut and just release the channel.
1965          */
1966         if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
1967                 /*
1968                  * If the channel was halted, this should be the only
1969                  * interrupt unmasked
1970                  */
1971                 WARN_ON(hcint != HCINTMSK_CHHLTD);
1972                 if (hsotg->core_params->dma_desc_enable > 0)
1973                         dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1974                                                     chan->halt_status);
1975                 else
1976                         dwc2_release_channel(hsotg, chan, NULL,
1977                                              chan->halt_status);
1978                 return;
1979         }
1980
1981         if (list_empty(&chan->qh->qtd_list)) {
1982                 /*
1983                  * TODO: Will this ever happen with the
1984                  * DWC2_HC_XFER_URB_DEQUEUE handling above?
1985                  */
1986                 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
1987                         chnum);
1988                 dev_dbg(hsotg->dev,
1989                         "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
1990                         chan->hcint, hcintmsk, hcint);
1991                 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
1992                 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
1993                 chan->hcint = 0;
1994                 return;
1995         }
1996
1997         qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
1998                                qtd_list_entry);
1999
2000         if (hsotg->core_params->dma_enable <= 0) {
2001                 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
2002                         hcint &= ~HCINTMSK_CHHLTD;
2003         }
2004
2005         if (hcint & HCINTMSK_XFERCOMPL) {
2006                 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2007                 /*
2008                  * If NYET occurred at same time as Xfer Complete, the NYET is
2009                  * handled by the Xfer Complete interrupt handler. Don't want
2010                  * to call the NYET interrupt handler in this case.
2011                  */
2012                 hcint &= ~HCINTMSK_NYET;
2013         }
2014         if (hcint & HCINTMSK_CHHLTD)
2015                 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2016         if (hcint & HCINTMSK_AHBERR)
2017                 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2018         if (hcint & HCINTMSK_STALL)
2019                 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2020         if (hcint & HCINTMSK_NAK)
2021                 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2022         if (hcint & HCINTMSK_ACK)
2023                 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2024         if (hcint & HCINTMSK_NYET)
2025                 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2026         if (hcint & HCINTMSK_XACTERR)
2027                 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2028         if (hcint & HCINTMSK_BBLERR)
2029                 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2030         if (hcint & HCINTMSK_FRMOVRUN)
2031                 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2032         if (hcint & HCINTMSK_DATATGLERR)
2033                 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2034
2035         chan->hcint = 0;
2036 }
2037
2038 /*
2039  * This interrupt indicates that one or more host channels has a pending
2040  * interrupt. There are multiple conditions that can cause each host channel
2041  * interrupt. This function determines which conditions have occurred for each
2042  * host channel interrupt and handles them appropriately.
2043  */
2044 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2045 {
2046         u32 haint;
2047         int i;
2048
2049         haint = readl(hsotg->regs + HAINT);
2050         if (dbg_perio()) {
2051                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2052
2053                 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2054         }
2055
2056         for (i = 0; i < hsotg->core_params->host_channels; i++) {
2057                 if (haint & (1 << i))
2058                         dwc2_hc_n_intr(hsotg, i);
2059         }
2060 }
2061
2062 /* This function handles interrupts for the HCD */
2063 int dwc2_hcd_intr(struct dwc2_hsotg *hsotg)
2064 {
2065         u32 gintsts, dbg_gintsts;
2066         int retval = 0;
2067
2068         if (dwc2_check_core_status(hsotg) < 0) {
2069                 dev_warn(hsotg->dev, "Controller is disconnected\n");
2070                 return 0;
2071         }
2072
2073         spin_lock(&hsotg->lock);
2074
2075         /* Check if HOST Mode */
2076         if (dwc2_is_host_mode(hsotg)) {
2077                 gintsts = dwc2_read_core_intr(hsotg);
2078                 if (!gintsts) {
2079                         spin_unlock(&hsotg->lock);
2080                         return 0;
2081                 }
2082
2083                 retval = 1;
2084
2085                 dbg_gintsts = gintsts;
2086 #ifndef DEBUG_SOF
2087                 dbg_gintsts &= ~GINTSTS_SOF;
2088 #endif
2089                 if (!dbg_perio())
2090                         dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
2091                                          GINTSTS_PTXFEMP);
2092
2093                 /* Only print if there are any non-suppressed interrupts left */
2094                 if (dbg_gintsts)
2095                         dev_vdbg(hsotg->dev,
2096                                  "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
2097                                  gintsts);
2098
2099                 if (gintsts & GINTSTS_SOF)
2100                         dwc2_sof_intr(hsotg);
2101                 if (gintsts & GINTSTS_RXFLVL)
2102                         dwc2_rx_fifo_level_intr(hsotg);
2103                 if (gintsts & GINTSTS_NPTXFEMP)
2104                         dwc2_np_tx_fifo_empty_intr(hsotg);
2105                 if (gintsts & GINTSTS_I2CINT)
2106                         /* Todo: Implement i2cintr handler */
2107                         writel(GINTSTS_I2CINT, hsotg->regs + GINTSTS);
2108                 if (gintsts & GINTSTS_PRTINT)
2109                         dwc2_port_intr(hsotg);
2110                 if (gintsts & GINTSTS_HCHINT)
2111                         dwc2_hc_intr(hsotg);
2112                 if (gintsts & GINTSTS_PTXFEMP)
2113                         dwc2_perio_tx_fifo_empty_intr(hsotg);
2114
2115                 if (dbg_gintsts) {
2116                         dev_vdbg(hsotg->dev,
2117                                  "DWC OTG HCD Finished Servicing Interrupts\n");
2118                         dev_vdbg(hsotg->dev,
2119                                  "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2120                                  readl(hsotg->regs + GINTSTS),
2121                                  readl(hsotg->regs + GINTMSK));
2122                 }
2123         }
2124
2125         spin_unlock(&hsotg->lock);
2126
2127         return retval;
2128 }