drivers/staging/comedi/drivers/ni_pcimio.c

   1 /*
   2     comedi/drivers/ni_pcimio.c
   3     Hardware driver for NI PCI-MIO E series cards
   4
   5     COMEDI - Linux Control and Measurement Device Interface
   6     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21 */
  22 /*
  23 Driver: ni_pcimio
  24 Description: National Instruments PCI-MIO-E series and M series (all boards)
  25 Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
  26   Herman Bruyninckx, Terry Barnaby
  27 Status: works
  28 Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
  29   PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
  30   PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
  31   PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
  32   PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224,
  33   PCI-6225, PXI-6225, PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PXIe-6251,
  34   PCI-6254, PCI-6259, PCIe-6259,
  35   PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
  36   PCI-6711, PXI-6711, PCI-6713, PXI-6713,
  37   PXI-6071E, PCI-6070E, PXI-6070E,
  38   PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
  39   PCI-6143, PXI-6143
  40 Updated: Mon, 09 Jan 2012 14:52:48 +0000
  41
  42 These boards are almost identical to the AT-MIO E series, except that
  43 they use the PCI bus instead of ISA (i.e., AT).  See the notes for
  44 the ni_atmio.o driver for additional information about these boards.
  45
  46 Autocalibration is supported on many of the devices, using the
  47 comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
  48 M-Series boards do analog input and analog output calibration entirely
  49 in software. The software calibration corrects
  50 the analog input for offset, gain and
  51 nonlinearity.  The analog outputs are corrected for offset and gain.
  52 See the comedilib documentation on comedi_get_softcal_converter() for
  53 more information.
  54
  55 By default, the driver uses DMA to transfer analog input data to
  56 memory.  When DMA is enabled, not all triggering features are
  57 supported.
  58
  59 Digital I/O may not work on 673x.
  60
  61 Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
  62 With this board all of the convertors perform one simultaineous sample during
  63 a scan interval. The period for a scan is used for the convert time in a
  64 Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
  65
  66 The RTSI trigger bus is supported on these cards on
  67 subdevice 10. See the comedilib documentation for details.
  68
  69 Information (number of channels, bits, etc.) for some devices may be
  70 incorrect.  Please check this and submit a bug if there are problems
  71 for your device.
  72
  73 SCXI is probably broken for m-series boards.
  74
  75 Bugs:
  76  - When DMA is enabled, COMEDI_EV_CONVERT does
  77    not work correctly.
  78
  79 */
  80 /*
  81         The PCI-MIO E series driver was originally written by
  82         Tomasz Motylewski <...>, and ported to comedi by ds.
  83
  84         References:
  85
  86            341079b.pdf  PCI E Series Register-Level Programmer Manual
  87            340934b.pdf  DAQ-STC reference manual
  88
  89            322080b.pdf  6711/6713/6715 User Manual
  90
  91            320945c.pdf  PCI E Series User Manual
  92            322138a.pdf  PCI-6052E and DAQPad-6052E User Manual
  93
  94         ISSUES:
  95
  96         need to deal with external reference for DAC, and other DAC
  97         properties in board properties
  98
  99         deal with at-mio-16de-10 revision D to N changes, etc.
 100
 101         need to add other CALDAC type
 102
 103         need to slow down DAC loading.  I don't trust NI's claim that
 104         two writes to the PCI bus slows IO enough.  I would prefer to
 105         use udelay().  Timing specs: (clock)
 106                 AD8522          30ns
 107                 DAC8043         120ns
 108                 DAC8800         60ns
 109                 MB88341         ?
 110
 111 */
 112
 113 #include "../comedidev.h"
 114
 115 #include <asm/byteorder.h>
 116 #include <linux/delay.h>
 117
 118 #include "ni_stc.h"
 119 #include "mite.h"
 120
 121 /* #define PCI_DEBUG */
 122
 123 #define PCIDMA
 124
 125 #define PCIMIO 1
 126 #undef ATMIO
 127
 128 #define MAX_N_CALDACS (16+16+2)
 129
 130 #define DRV_NAME "ni_pcimio"
 131
 132 /* These are not all the possible ao ranges for 628x boards.
 133  They can do OFFSET +- REFERENCE where OFFSET can be
 134  0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
 135  be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>.  That's
 136  63 different possibilities.  An AO channel
 137  can not act as it's own OFFSET or REFERENCE.
 138 */
 139 static const struct comedi_lrange range_ni_M_628x_ao = { 8, {
 140                                                              RANGE(-10, 10),
 141                                                              RANGE(-5, 5),
 142                                                              RANGE(-2, 2),
 143                                                              RANGE(-1, 1),
 144                                                              RANGE(-5, 15),
 145                                                              RANGE(0, 10),
 146                                                              RANGE(3, 7),
 147                                                              RANGE(4, 6),
 148                                                              RANGE_ext(-1, 1)
 149                                                              }
 150 };
 151
 152 static const struct comedi_lrange range_ni_M_625x_ao = { 3, {
 153                                                              RANGE(-10, 10),
 154                                                              RANGE(-5, 5),
 155                                                              RANGE_ext(-1, 1)
 156                                                              }
 157 };
 158
 159 static const struct comedi_lrange range_ni_M_622x_ao = { 1, {
 160                                                              RANGE(-10, 10),
 161                                                              }
 162 };
 163
 164 static const struct ni_board_struct ni_boards[] = {
 165         {
 166          .device_id = 0x0162,   /*  NI also says 0x1620.  typo? */
 167          .name = "pci-mio-16xe-50",
 168          .n_adchan = 16,
 169          .adbits = 16,
 170          .ai_fifo_depth = 2048,
 171          .alwaysdither = 1,
 172          .gainlkup = ai_gain_8,
 173          .ai_speed = 50000,
 174          .n_aochan = 2,
 175          .aobits = 12,
 176          .ao_fifo_depth = 0,
 177          .ao_range_table = &range_bipolar10,
 178          .ao_unipolar = 0,
 179          .ao_speed = 50000,
 180          .num_p0_dio_channels = 8,
 181          .caldac = {dac8800, dac8043},
 182          .has_8255 = 0,
 183          },
 184         {
 185          .device_id = 0x1170,
 186          .name = "pci-mio-16xe-10",     /*  aka pci-6030E */
 187          .n_adchan = 16,
 188          .adbits = 16,
 189          .ai_fifo_depth = 512,
 190          .alwaysdither = 1,
 191          .gainlkup = ai_gain_14,
 192          .ai_speed = 10000,
 193          .n_aochan = 2,
 194          .aobits = 16,
 195          .ao_fifo_depth = 2048,
 196          .ao_range_table = &range_ni_E_ao_ext,
 197          .ao_unipolar = 1,
 198          .ao_speed = 10000,
 199          .num_p0_dio_channels = 8,
 200          .caldac = {dac8800, dac8043, ad8522},
 201          .has_8255 = 0,
 202          },
 203         {
 204          .device_id = 0x28c0,
 205          .name = "pci-6014",
 206          .n_adchan = 16,
 207          .adbits = 16,
 208          .ai_fifo_depth = 512,
 209          .alwaysdither = 1,
 210          .gainlkup = ai_gain_4,
 211          .ai_speed = 5000,
 212          .n_aochan = 2,
 213          .aobits = 16,
 214          .ao_fifo_depth = 0,
 215          .ao_range_table = &range_bipolar10,
 216          .ao_unipolar = 0,
 217          .ao_speed = 100000,
 218          .num_p0_dio_channels = 8,
 219          .caldac = {ad8804_debug},
 220          .has_8255 = 0,
 221          },
 222         {
 223          .device_id = 0x11d0,
 224          .name = "pxi-6030e",
 225          .n_adchan = 16,
 226          .adbits = 16,
 227          .ai_fifo_depth = 512,
 228          .alwaysdither = 1,
 229          .gainlkup = ai_gain_14,
 230          .ai_speed = 10000,
 231          .n_aochan = 2,
 232          .aobits = 16,
 233          .ao_fifo_depth = 2048,
 234          .ao_range_table = &range_ni_E_ao_ext,
 235          .ao_unipolar = 1,
 236          .ao_speed = 10000,
 237          .num_p0_dio_channels = 8,
 238          .caldac = {dac8800, dac8043, ad8522},
 239          .has_8255 = 0,
 240          },
 241         {
 242          .device_id = 0x1180,
 243          .name = "pci-mio-16e-1",       /* aka pci-6070e */
 244          .n_adchan = 16,
 245          .adbits = 12,
 246          .ai_fifo_depth = 512,
 247          .alwaysdither = 0,
 248          .gainlkup = ai_gain_16,
 249          .ai_speed = 800,
 250          .n_aochan = 2,
 251          .aobits = 12,
 252          .ao_fifo_depth = 2048,
 253          .ao_range_table = &range_ni_E_ao_ext,
 254          .ao_unipolar = 1,
 255          .ao_speed = 1000,
 256          .num_p0_dio_channels = 8,
 257          .caldac = {mb88341},
 258          .has_8255 = 0,
 259          },
 260         {
 261          .device_id = 0x1190,
 262          .name = "pci-mio-16e-4",       /* aka pci-6040e */
 263          .n_adchan = 16,
 264          .adbits = 12,
 265          .ai_fifo_depth = 512,
 266          .alwaysdither = 0,
 267          .gainlkup = ai_gain_16,
 268          /*      .Note = there have been reported problems with full speed
 269           * on this board */
 270          .ai_speed = 2000,
 271          .n_aochan = 2,
 272          .aobits = 12,
 273          .ao_fifo_depth = 512,
 274          .ao_range_table = &range_ni_E_ao_ext,
 275          .ao_unipolar = 1,
 276          .ao_speed = 1000,
 277          .num_p0_dio_channels = 8,
 278          .caldac = {ad8804_debug},      /*  doc says mb88341 */
 279          .has_8255 = 0,
 280          },
 281         {
 282          .device_id = 0x11c0,
 283          .name = "pxi-6040e",
 284          .n_adchan = 16,
 285          .adbits = 12,
 286          .ai_fifo_depth = 512,
 287          .alwaysdither = 0,
 288          .gainlkup = ai_gain_16,
 289          .ai_speed = 2000,
 290          .n_aochan = 2,
 291          .aobits = 12,
 292          .ao_fifo_depth = 512,
 293          .ao_range_table = &range_ni_E_ao_ext,
 294          .ao_unipolar = 1,
 295          .ao_speed = 1000,
 296          .num_p0_dio_channels = 8,
 297          .caldac = {mb88341},
 298          .has_8255 = 0,
 299          },
 300
 301         {
 302          .device_id = 0x1330,
 303          .name = "pci-6031e",
 304          .n_adchan = 64,
 305          .adbits = 16,
 306          .ai_fifo_depth = 512,
 307          .alwaysdither = 1,
 308          .gainlkup = ai_gain_14,
 309          .ai_speed = 10000,
 310          .n_aochan = 2,
 311          .aobits = 16,
 312          .ao_fifo_depth = 2048,
 313          .ao_range_table = &range_ni_E_ao_ext,
 314          .ao_unipolar = 1,
 315          .ao_speed = 10000,
 316          .num_p0_dio_channels = 8,
 317          .caldac = {dac8800, dac8043, ad8522},
 318          .has_8255 = 0,
 319          },
 320         {
 321          .device_id = 0x1270,
 322          .name = "pci-6032e",
 323          .n_adchan = 16,
 324          .adbits = 16,
 325          .ai_fifo_depth = 512,
 326          .alwaysdither = 1,
 327          .gainlkup = ai_gain_14,
 328          .ai_speed = 10000,
 329          .n_aochan = 0,
 330          .aobits = 0,
 331          .ao_fifo_depth = 0,
 332          .ao_unipolar = 0,
 333          .num_p0_dio_channels = 8,
 334          .caldac = {dac8800, dac8043, ad8522},
 335          .has_8255 = 0,
 336          },
 337         {
 338          .device_id = 0x1340,
 339          .name = "pci-6033e",
 340          .n_adchan = 64,
 341          .adbits = 16,
 342          .ai_fifo_depth = 512,
 343          .alwaysdither = 1,
 344          .gainlkup = ai_gain_14,
 345          .ai_speed = 10000,
 346          .n_aochan = 0,
 347          .aobits = 0,
 348          .ao_fifo_depth = 0,
 349          .ao_unipolar = 0,
 350          .num_p0_dio_channels = 8,
 351          .caldac = {dac8800, dac8043, ad8522},
 352          .has_8255 = 0,
 353          },
 354         {
 355          .device_id = 0x1350,
 356          .name = "pci-6071e",
 357          .n_adchan = 64,
 358          .adbits = 12,
 359          .ai_fifo_depth = 512,
 360          .alwaysdither = 1,
 361          .gainlkup = ai_gain_16,
 362          .ai_speed = 800,
 363          .n_aochan = 2,
 364          .aobits = 12,
 365          .ao_fifo_depth = 2048,
 366          .ao_range_table = &range_ni_E_ao_ext,
 367          .ao_unipolar = 1,
 368          .ao_speed = 1000,
 369          .num_p0_dio_channels = 8,
 370          .caldac = {ad8804_debug},
 371          .has_8255 = 0,
 372          },
 373         {
 374          .device_id = 0x2a60,
 375          .name = "pci-6023e",
 376          .n_adchan = 16,
 377          .adbits = 12,
 378          .ai_fifo_depth = 512,
 379          .alwaysdither = 0,
 380          .gainlkup = ai_gain_4,
 381          .ai_speed = 5000,
 382          .n_aochan = 0,
 383          .aobits = 0,
 384          .ao_unipolar = 0,
 385          .num_p0_dio_channels = 8,
 386          .caldac = {ad8804_debug},      /* manual is wrong */
 387          .has_8255 = 0,
 388          },
 389         {
 390          .device_id = 0x2a70,
 391          .name = "pci-6024e",
 392          .n_adchan = 16,
 393          .adbits = 12,
 394          .ai_fifo_depth = 512,
 395          .alwaysdither = 0,
 396          .gainlkup = ai_gain_4,
 397          .ai_speed = 5000,
 398          .n_aochan = 2,
 399          .aobits = 12,
 400          .ao_fifo_depth = 0,
 401          .ao_range_table = &range_bipolar10,
 402          .ao_unipolar = 0,
 403          .ao_speed = 100000,
 404          .num_p0_dio_channels = 8,
 405          .caldac = {ad8804_debug},      /* manual is wrong */
 406          .has_8255 = 0,
 407          },
 408         {
 409          .device_id = 0x2a80,
 410          .name = "pci-6025e",
 411          .n_adchan = 16,
 412          .adbits = 12,
 413          .ai_fifo_depth = 512,
 414          .alwaysdither = 0,
 415          .gainlkup = ai_gain_4,
 416          .ai_speed = 5000,
 417          .n_aochan = 2,
 418          .aobits = 12,
 419          .ao_fifo_depth = 0,
 420          .ao_range_table = &range_bipolar10,
 421          .ao_unipolar = 0,
 422          .ao_speed = 100000,
 423          .num_p0_dio_channels = 8,
 424          .caldac = {ad8804_debug},      /* manual is wrong */
 425          .has_8255 = 1,
 426          },
 427         {
 428          .device_id = 0x2ab0,
 429          .name = "pxi-6025e",
 430          .n_adchan = 16,
 431          .adbits = 12,
 432          .ai_fifo_depth = 512,
 433          .alwaysdither = 0,
 434          .gainlkup = ai_gain_4,
 435          .ai_speed = 5000,
 436          .n_aochan = 2,
 437          .aobits = 12,
 438          .ao_fifo_depth = 0,
 439          .ao_range_table = &range_ni_E_ao_ext,
 440          .ao_unipolar = 1,
 441          .ao_speed = 100000,
 442          .num_p0_dio_channels = 8,
 443          .caldac = {ad8804_debug},      /* manual is wrong */
 444          .has_8255 = 1,
 445          },
 446
 447         {
 448          .device_id = 0x2ca0,
 449          .name = "pci-6034e",
 450          .n_adchan = 16,
 451          .adbits = 16,
 452          .ai_fifo_depth = 512,
 453          .alwaysdither = 1,
 454          .gainlkup = ai_gain_4,
 455          .ai_speed = 5000,
 456          .n_aochan = 0,
 457          .aobits = 0,
 458          .ao_fifo_depth = 0,
 459          .ao_unipolar = 0,
 460          .num_p0_dio_channels = 8,
 461          .caldac = {ad8804_debug},
 462          .has_8255 = 0,
 463          },
 464         {
 465          .device_id = 0x2c80,
 466          .name = "pci-6035e",
 467          .n_adchan = 16,
 468          .adbits = 16,
 469          .ai_fifo_depth = 512,
 470          .alwaysdither = 1,
 471          .gainlkup = ai_gain_4,
 472          .ai_speed = 5000,
 473          .n_aochan = 2,
 474          .aobits = 12,
 475          .ao_fifo_depth = 0,
 476          .ao_range_table = &range_bipolar10,
 477          .ao_unipolar = 0,
 478          .ao_speed = 100000,
 479          .num_p0_dio_channels = 8,
 480          .caldac = {ad8804_debug},
 481          .has_8255 = 0,
 482          },
 483         {
 484          .device_id = 0x18b0,
 485          .name = "pci-6052e",
 486          .n_adchan = 16,
 487          .adbits = 16,
 488          .ai_fifo_depth = 512,
 489          .alwaysdither = 1,
 490          .gainlkup = ai_gain_16,
 491          .ai_speed = 3000,
 492          .n_aochan = 2,
 493          .aobits = 16,
 494          .ao_unipolar = 1,
 495          .ao_fifo_depth = 2048,
 496          .ao_range_table = &range_ni_E_ao_ext,
 497          .ao_speed = 3000,
 498          .num_p0_dio_channels = 8,
 499          .caldac = {ad8804_debug, ad8804_debug, ad8522},        /* manual is wrong */
 500          },
 501         {.device_id = 0x14e0,
 502          .name = "pci-6110",
 503          .n_adchan = 4,
 504          .adbits = 12,
 505          .ai_fifo_depth = 8192,
 506          .alwaysdither = 0,
 507          .gainlkup = ai_gain_611x,
 508          .ai_speed = 200,
 509          .n_aochan = 2,
 510          .aobits = 16,
 511          .reg_type = ni_reg_611x,
 512          .ao_range_table = &range_bipolar10,
 513          .ao_unipolar = 0,
 514          .ao_fifo_depth = 2048,
 515          .ao_speed = 250,
 516          .num_p0_dio_channels = 8,
 517          .caldac = {ad8804, ad8804},
 518          },
 519         {
 520          .device_id = 0x14f0,
 521          .name = "pci-6111",
 522          .n_adchan = 2,
 523          .adbits = 12,
 524          .ai_fifo_depth = 8192,
 525          .alwaysdither = 0,
 526          .gainlkup = ai_gain_611x,
 527          .ai_speed = 200,
 528          .n_aochan = 2,
 529          .aobits = 16,
 530          .reg_type = ni_reg_611x,
 531          .ao_range_table = &range_bipolar10,
 532          .ao_unipolar = 0,
 533          .ao_fifo_depth = 2048,
 534          .ao_speed = 250,
 535          .num_p0_dio_channels = 8,
 536          .caldac = {ad8804, ad8804},
 537          },
 538 #if 0
 539         /* The 6115 boards probably need their own driver */
 540         {
 541          .device_id = 0x2ed0,
 542          .name = "pci-6115",
 543          .n_adchan = 4,
 544          .adbits = 12,
 545          .ai_fifo_depth = 8192,
 546          .alwaysdither = 0,
 547          .gainlkup = ai_gain_611x,
 548          .ai_speed = 100,
 549          .n_aochan = 2,
 550          .aobits = 16,
 551          .ao_671x = 1,
 552          .ao_unipolar = 0,
 553          .ao_fifo_depth = 2048,
 554          .ao_speed = 250,
 555          .num_p0_dio_channels = 8,
 556          .reg_611x = 1,
 557          .caldac = {ad8804_debug, ad8804_debug, ad8804_debug},  /* XXX */
 558          },
 559 #endif
 560 #if 0
 561         {
 562          .device_id = 0x0000,
 563          .name = "pxi-6115",
 564          .n_adchan = 4,
 565          .adbits = 12,
 566          .ai_fifo_depth = 8192,
 567          .alwaysdither = 0,
 568          .gainlkup = ai_gain_611x,
 569          .ai_speed = 100,
 570          .n_aochan = 2,
 571          .aobits = 16,
 572          .ao_671x = 1,
 573          .ao_unipolar = 0,
 574          .ao_fifo_depth = 2048,
 575          .ao_speed = 250,
 576          .reg_611x = 1,
 577          .num_p0_dio_channels = 8,
 578          caldac = {ad8804_debug, ad8804_debug, ad8804_debug},   /* XXX */
 579          },
 580 #endif
 581         {
 582          .device_id = 0x1880,
 583          .name = "pci-6711",
 584          .n_adchan = 0,         /* no analog input */
 585          .n_aochan = 4,
 586          .aobits = 12,
 587          .ao_unipolar = 0,
 588          .ao_fifo_depth = 16384,
 589          /* data sheet says 8192, but fifo really holds 16384 samples */
 590          .ao_range_table = &range_bipolar10,
 591          .ao_speed = 1000,
 592          .num_p0_dio_channels = 8,
 593          .reg_type = ni_reg_6711,
 594          .caldac = {ad8804_debug},
 595          },
 596         {
 597          .device_id = 0x2b90,
 598          .name = "pxi-6711",
 599          .n_adchan = 0,         /* no analog input */
 600          .n_aochan = 4,
 601          .aobits = 12,
 602          .ao_unipolar = 0,
 603          .ao_fifo_depth = 16384,
 604          .ao_range_table = &range_bipolar10,
 605          .ao_speed = 1000,
 606          .num_p0_dio_channels = 8,
 607          .reg_type = ni_reg_6711,
 608          .caldac = {ad8804_debug},
 609          },
 610         {
 611          .device_id = 0x1870,
 612          .name = "pci-6713",
 613          .n_adchan = 0,         /* no analog input */
 614          .n_aochan = 8,
 615          .aobits = 12,
 616          .ao_unipolar = 0,
 617          .ao_fifo_depth = 16384,
 618          .ao_range_table = &range_bipolar10,
 619          .ao_speed = 1000,
 620          .num_p0_dio_channels = 8,
 621          .reg_type = ni_reg_6713,
 622          .caldac = {ad8804_debug, ad8804_debug},
 623          },
 624         {
 625          .device_id = 0x2b80,
 626          .name = "pxi-6713",
 627          .n_adchan = 0,         /* no analog input */
 628          .n_aochan = 8,
 629          .aobits = 12,
 630          .ao_unipolar = 0,
 631          .ao_fifo_depth = 16384,
 632          .ao_range_table = &range_bipolar10,
 633          .ao_speed = 1000,
 634          .num_p0_dio_channels = 8,
 635          .reg_type = ni_reg_6713,
 636          .caldac = {ad8804_debug, ad8804_debug},
 637          },
 638         {
 639          .device_id = 0x2430,
 640          .name = "pci-6731",
 641          .n_adchan = 0,         /* no analog input */
 642          .n_aochan = 4,
 643          .aobits = 16,
 644          .ao_unipolar = 0,
 645          .ao_fifo_depth = 8192,
 646          .ao_range_table = &range_bipolar10,
 647          .ao_speed = 1000,
 648          .num_p0_dio_channels = 8,
 649          .reg_type = ni_reg_6711,
 650          .caldac = {ad8804_debug},
 651          },
 652 #if 0                           /* need device ids */
 653         {
 654          .device_id = 0x0,
 655          .name = "pxi-6731",
 656          .n_adchan = 0,         /* no analog input */
 657          .n_aochan = 4,
 658          .aobits = 16,
 659          .ao_unipolar = 0,
 660          .ao_fifo_depth = 8192,
 661          .ao_range_table = &range_bipolar10,
 662          .num_p0_dio_channels = 8,
 663          .reg_type = ni_reg_6711,
 664          .caldac = {ad8804_debug},
 665          },
 666 #endif
 667         {
 668          .device_id = 0x2410,
 669          .name = "pci-6733",
 670          .n_adchan = 0,         /* no analog input */
 671          .n_aochan = 8,
 672          .aobits = 16,
 673          .ao_unipolar = 0,
 674          .ao_fifo_depth = 16384,
 675          .ao_range_table = &range_bipolar10,
 676          .ao_speed = 1000,
 677          .num_p0_dio_channels = 8,
 678          .reg_type = ni_reg_6713,
 679          .caldac = {ad8804_debug, ad8804_debug},
 680          },
 681         {
 682          .device_id = 0x2420,
 683          .name = "pxi-6733",
 684          .n_adchan = 0,         /* no analog input */
 685          .n_aochan = 8,
 686          .aobits = 16,
 687          .ao_unipolar = 0,
 688          .ao_fifo_depth = 16384,
 689          .ao_range_table = &range_bipolar10,
 690          .ao_speed = 1000,
 691          .num_p0_dio_channels = 8,
 692          .reg_type = ni_reg_6713,
 693          .caldac = {ad8804_debug, ad8804_debug},
 694          },
 695         {
 696          .device_id = 0x15b0,
 697          .name = "pxi-6071e",
 698          .n_adchan = 64,
 699          .adbits = 12,
 700          .ai_fifo_depth = 512,
 701          .alwaysdither = 1,
 702          .gainlkup = ai_gain_16,
 703          .ai_speed = 800,
 704          .n_aochan = 2,
 705          .aobits = 12,
 706          .ao_fifo_depth = 2048,
 707          .ao_range_table = &range_ni_E_ao_ext,
 708          .ao_unipolar = 1,
 709          .ao_speed = 1000,
 710          .num_p0_dio_channels = 8,
 711          .caldac = {ad8804_debug},
 712          .has_8255 = 0,
 713          },
 714         {
 715          .device_id = 0x11b0,
 716          .name = "pxi-6070e",
 717          .n_adchan = 16,
 718          .adbits = 12,
 719          .ai_fifo_depth = 512,
 720          .alwaysdither = 1,
 721          .gainlkup = ai_gain_16,
 722          .ai_speed = 800,
 723          .n_aochan = 2,
 724          .aobits = 12,
 725          .ao_fifo_depth = 2048,
 726          .ao_range_table = &range_ni_E_ao_ext,
 727          .ao_unipolar = 1,
 728          .ao_speed = 1000,
 729          .num_p0_dio_channels = 8,
 730          .caldac = {ad8804_debug},
 731          .has_8255 = 0,
 732          },
 733         {
 734          .device_id = 0x18c0,
 735          .name = "pxi-6052e",
 736          .n_adchan = 16,
 737          .adbits = 16,
 738          .ai_fifo_depth = 512,
 739          .alwaysdither = 1,
 740          .gainlkup = ai_gain_16,
 741          .ai_speed = 3000,
 742          .n_aochan = 2,
 743          .aobits = 16,
 744          .ao_unipolar = 1,
 745          .ao_fifo_depth = 2048,
 746          .ao_range_table = &range_ni_E_ao_ext,
 747          .ao_speed = 3000,
 748          .num_p0_dio_channels = 8,
 749          .caldac = {mb88341, mb88341, ad8522},
 750          },
 751         {
 752          .device_id = 0x1580,
 753          .name = "pxi-6031e",
 754          .n_adchan = 64,
 755          .adbits = 16,
 756          .ai_fifo_depth = 512,
 757          .alwaysdither = 1,
 758          .gainlkup = ai_gain_14,
 759          .ai_speed = 10000,
 760          .n_aochan = 2,
 761          .aobits = 16,
 762          .ao_fifo_depth = 2048,
 763          .ao_range_table = &range_ni_E_ao_ext,
 764          .ao_unipolar = 1,
 765          .ao_speed = 10000,
 766          .num_p0_dio_channels = 8,
 767          .caldac = {dac8800, dac8043, ad8522},
 768          },
 769         {
 770          .device_id = 0x2890,
 771          .name = "pci-6036e",
 772          .n_adchan = 16,
 773          .adbits = 16,
 774          .ai_fifo_depth = 512,
 775          .alwaysdither = 1,
 776          .gainlkup = ai_gain_4,
 777          .ai_speed = 5000,
 778          .n_aochan = 2,
 779          .aobits = 16,
 780          .ao_fifo_depth = 0,
 781          .ao_range_table = &range_bipolar10,
 782          .ao_unipolar = 0,
 783          .ao_speed = 100000,
 784          .num_p0_dio_channels = 8,
 785          .caldac = {ad8804_debug},
 786          .has_8255 = 0,
 787          },
 788         {
 789          .device_id = 0x70b0,
 790          .name = "pci-6220",
 791          .n_adchan = 16,
 792          .adbits = 16,
 793          .ai_fifo_depth = 512,
 794          /*      .FIXME = guess */
 795          .gainlkup = ai_gain_622x,
 796          .ai_speed = 4000,
 797          .n_aochan = 0,
 798          .aobits = 0,
 799          .ao_fifo_depth = 0,
 800          .num_p0_dio_channels = 8,
 801          .reg_type = ni_reg_622x,
 802          .ao_unipolar = 0,
 803          .caldac = {caldac_none},
 804          .has_8255 = 0,
 805          },
 806         {
 807          .device_id = 0x70af,
 808          .name = "pci-6221",
 809          .n_adchan = 16,
 810          .adbits = 16,
 811          .ai_fifo_depth = 4095,
 812          .gainlkup = ai_gain_622x,
 813          .ai_speed = 4000,
 814          .n_aochan = 2,
 815          .aobits = 16,
 816          .ao_fifo_depth = 8191,
 817          .ao_range_table = &range_ni_M_622x_ao,
 818          .reg_type = ni_reg_622x,
 819          .ao_unipolar = 0,
 820          .ao_speed = 1200,
 821          .num_p0_dio_channels = 8,
 822          .caldac = {caldac_none},
 823          .has_8255 = 0,
 824          },
 825         {
 826          .device_id = 0x71bc,
 827          .name = "pci-6221_37pin",
 828          .n_adchan = 16,
 829          .adbits = 16,
 830          .ai_fifo_depth = 4095,
 831          .gainlkup = ai_gain_622x,
 832          .ai_speed = 4000,
 833          .n_aochan = 2,
 834          .aobits = 16,
 835          .ao_fifo_depth = 8191,
 836          .ao_range_table = &range_ni_M_622x_ao,
 837          .reg_type = ni_reg_622x,
 838          .ao_unipolar = 0,
 839          .ao_speed = 1200,
 840          .num_p0_dio_channels = 8,
 841          .caldac = {caldac_none},
 842          .has_8255 = 0,
 843          },
 844         {
 845          .device_id = 0x70f2,
 846          .name = "pci-6224",
 847          .n_adchan = 32,
 848          .adbits = 16,
 849          .ai_fifo_depth = 4095,
 850          .gainlkup = ai_gain_622x,
 851          .ai_speed = 4000,
 852          .n_aochan = 0,
 853          .aobits = 0,
 854          .ao_fifo_depth = 0,
 855          .reg_type = ni_reg_622x,
 856          .ao_unipolar = 0,
 857          .num_p0_dio_channels = 32,
 858          .caldac = {caldac_none},
 859          .has_8255 = 0,
 860          },
 861         {
 862          .device_id = 0x70f3,
 863          .name = "pxi-6224",
 864          .n_adchan = 32,
 865          .adbits = 16,
 866          .ai_fifo_depth = 4095,
 867          .gainlkup = ai_gain_622x,
 868          .ai_speed = 4000,
 869          .n_aochan = 0,
 870          .aobits = 0,
 871          .ao_fifo_depth = 0,
 872          .reg_type = ni_reg_622x,
 873          .ao_unipolar = 0,
 874          .num_p0_dio_channels = 32,
 875          .caldac = {caldac_none},
 876          .has_8255 = 0,
 877          },
 878         {
 879          .device_id = 0x716c,
 880          .name = "pci-6225",
 881          .n_adchan = 80,
 882          .adbits = 16,
 883          .ai_fifo_depth = 4095,
 884          .gainlkup = ai_gain_622x,
 885          .ai_speed = 4000,
 886          .n_aochan = 2,
 887          .aobits = 16,
 888          .ao_fifo_depth = 8191,
 889          .ao_range_table = &range_ni_M_622x_ao,
 890          .reg_type = ni_reg_622x,
 891          .ao_unipolar = 0,
 892          .ao_speed = 1200,
 893          .num_p0_dio_channels = 32,
 894          .caldac = {caldac_none},
 895          .has_8255 = 0,
 896          },
 897         {
 898          .device_id = 0x716d,
 899          .name = "pxi-6225",
 900          .n_adchan = 80,
 901          .adbits = 16,
 902          .ai_fifo_depth = 4095,
 903          .gainlkup = ai_gain_622x,
 904          .ai_speed = 4000,
 905          .n_aochan = 2,
 906          .aobits = 16,
 907          .ao_fifo_depth = 8191,
 908          .ao_range_table = &range_ni_M_622x_ao,
 909          .reg_type = ni_reg_622x,
 910          .ao_unipolar = 0,
 911          .ao_speed = 1200,
 912          .num_p0_dio_channels = 32,
 913          .caldac = {caldac_none},
 914          .has_8255 = 0,
 915         },
 916         {
 917          .device_id = 0x70aa,
 918          .name = "pci-6229",
 919          .n_adchan = 32,
 920          .adbits = 16,
 921          .ai_fifo_depth = 4095,
 922          .gainlkup = ai_gain_622x,
 923          .ai_speed = 4000,
 924          .n_aochan = 4,
 925          .aobits = 16,
 926          .ao_fifo_depth = 8191,
 927          .ao_range_table = &range_ni_M_622x_ao,
 928          .reg_type = ni_reg_622x,
 929          .ao_unipolar = 0,
 930          .ao_speed = 1200,
 931          .num_p0_dio_channels = 32,
 932          .caldac = {caldac_none},
 933          .has_8255 = 0,
 934          },
 935         {
 936          .device_id = 0x70b4,
 937          .name = "pci-6250",
 938          .n_adchan = 16,
 939          .adbits = 16,
 940          .ai_fifo_depth = 4095,
 941          .gainlkup = ai_gain_628x,
 942          .ai_speed = 800,
 943          .n_aochan = 0,
 944          .aobits = 0,
 945          .ao_fifo_depth = 0,
 946          .reg_type = ni_reg_625x,
 947          .ao_unipolar = 0,
 948          .num_p0_dio_channels = 8,
 949          .caldac = {caldac_none},
 950          .has_8255 = 0,
 951          },
 952         {
 953          .device_id = 0x70b8,
 954          .name = "pci-6251",
 955          .n_adchan = 16,
 956          .adbits = 16,
 957          .ai_fifo_depth = 4095,
 958          .gainlkup = ai_gain_628x,
 959          .ai_speed = 800,
 960          .n_aochan = 2,
 961          .aobits = 16,
 962          .ao_fifo_depth = 8191,
 963          .ao_range_table = &range_ni_M_625x_ao,
 964          .reg_type = ni_reg_625x,
 965          .ao_unipolar = 0,
 966          .ao_speed = 357,
 967          .num_p0_dio_channels = 8,
 968          .caldac = {caldac_none},
 969          .has_8255 = 0,
 970          },
 971         {
 972          .device_id = 0x717d,
 973          .name = "pcie-6251",
 974          .n_adchan = 16,
 975          .adbits = 16,
 976          .ai_fifo_depth = 4095,
 977          .gainlkup = ai_gain_628x,
 978          .ai_speed = 800,
 979          .n_aochan = 2,
 980          .aobits = 16,
 981          .ao_fifo_depth = 8191,
 982          .ao_range_table = &range_ni_M_625x_ao,
 983          .reg_type = ni_reg_625x,
 984          .ao_unipolar = 0,
 985          .ao_speed = 357,
 986          .num_p0_dio_channels = 8,
 987          .caldac = {caldac_none},
 988          .has_8255 = 0,
 989          },
 990         {
 991          .device_id = 0x72e8,
 992          .name = "pxie-6251",
 993          .n_adchan = 16,
 994          .adbits = 16,
 995          .ai_fifo_depth = 4095,
 996          .gainlkup = ai_gain_628x,
 997          .ai_speed = 800,
 998          .n_aochan = 2,
 999          .aobits = 16,
1000          .ao_fifo_depth = 8191,
1001          .ao_range_table = &range_ni_M_625x_ao,
1002          .reg_type = ni_reg_625x,
1003          .ao_unipolar = 0,
1004          .ao_speed = 357,
1005          .num_p0_dio_channels = 8,
1006          .caldac = {caldac_none},
1007          .has_8255 = 0,
1008          },
1009         {
1010          .device_id = 0x70b7,
1011          .name = "pci-6254",
1012          .n_adchan = 32,
1013          .adbits = 16,
1014          .ai_fifo_depth = 4095,
1015          .gainlkup = ai_gain_628x,
1016          .ai_speed = 800,
1017          .n_aochan = 0,
1018          .aobits = 0,
1019          .ao_fifo_depth = 0,
1020          .reg_type = ni_reg_625x,
1021          .ao_unipolar = 0,
1022          .num_p0_dio_channels = 32,
1023          .caldac = {caldac_none},
1024          .has_8255 = 0,
1025          },
1026         {
1027          .device_id = 0x70ab,
1028          .name = "pci-6259",
1029          .n_adchan = 32,
1030          .adbits = 16,
1031          .ai_fifo_depth = 4095,
1032          .gainlkup = ai_gain_628x,
1033          .ai_speed = 800,
1034          .n_aochan = 4,
1035          .aobits = 16,
1036          .ao_fifo_depth = 8191,
1037          .ao_range_table = &range_ni_M_625x_ao,
1038          .reg_type = ni_reg_625x,
1039          .ao_unipolar = 0,
1040          .ao_speed = 357,
1041          .num_p0_dio_channels = 32,
1042          .caldac = {caldac_none},
1043          .has_8255 = 0,
1044          },
1045         {
1046          .device_id = 0x717f,
1047          .name = "pcie-6259",
1048          .n_adchan = 32,
1049          .adbits = 16,
1050          .ai_fifo_depth = 4095,
1051          .gainlkup = ai_gain_628x,
1052          .ai_speed = 800,
1053          .n_aochan = 4,
1054          .aobits = 16,
1055          .ao_fifo_depth = 8191,
1056          .ao_range_table = &range_ni_M_625x_ao,
1057          .reg_type = ni_reg_625x,
1058          .ao_unipolar = 0,
1059          .ao_speed = 357,
1060          .num_p0_dio_channels = 32,
1061          .caldac = {caldac_none},
1062          .has_8255 = 0,
1063          },
1064         {
1065          .device_id = 0x70b6,
1066          .name = "pci-6280",
1067          .n_adchan = 16,
1068          .adbits = 18,
1069          .ai_fifo_depth = 2047,
1070          .gainlkup = ai_gain_628x,
1071          .ai_speed = 1600,
1072          .n_aochan = 0,
1073          .aobits = 0,
1074          .ao_fifo_depth = 8191,
1075          .reg_type = ni_reg_628x,
1076          .ao_unipolar = 0,
1077          .num_p0_dio_channels = 8,
1078          .caldac = {caldac_none},
1079          .has_8255 = 0,
1080          },
1081         {
1082          .device_id = 0x70bd,
1083          .name = "pci-6281",
1084          .n_adchan = 16,
1085          .adbits = 18,
1086          .ai_fifo_depth = 2047,
1087          .gainlkup = ai_gain_628x,
1088          .ai_speed = 1600,
1089          .n_aochan = 2,
1090          .aobits = 16,
1091          .ao_fifo_depth = 8191,
1092          .ao_range_table = &range_ni_M_628x_ao,
1093          .reg_type = ni_reg_628x,
1094          .ao_unipolar = 1,
1095          .ao_speed = 357,
1096          .num_p0_dio_channels = 8,
1097          .caldac = {caldac_none},
1098          .has_8255 = 0,
1099          },
1100         {
1101          .device_id = 0x70bf,
1102          .name = "pxi-6281",
1103          .n_adchan = 16,
1104          .adbits = 18,
1105          .ai_fifo_depth = 2047,
1106          .gainlkup = ai_gain_628x,
1107          .ai_speed = 1600,
1108          .n_aochan = 2,
1109          .aobits = 16,
1110          .ao_fifo_depth = 8191,
1111          .ao_range_table = &range_ni_M_628x_ao,
1112          .reg_type = ni_reg_628x,
1113          .ao_unipolar = 1,
1114          .ao_speed = 357,
1115          .num_p0_dio_channels = 8,
1116          .caldac = {caldac_none},
1117          .has_8255 = 0,
1118          },
1119         {
1120          .device_id = 0x70bc,
1121          .name = "pci-6284",
1122          .n_adchan = 32,
1123          .adbits = 18,
1124          .ai_fifo_depth = 2047,
1125          .gainlkup = ai_gain_628x,
1126          .ai_speed = 1600,
1127          .n_aochan = 0,
1128          .aobits = 0,
1129          .ao_fifo_depth = 0,
1130          .reg_type = ni_reg_628x,
1131          .ao_unipolar = 0,
1132          .num_p0_dio_channels = 32,
1133          .caldac = {caldac_none},
1134          .has_8255 = 0,
1135          },
1136         {
1137          .device_id = 0x70ac,
1138          .name = "pci-6289",
1139          .n_adchan = 32,
1140          .adbits = 18,
1141          .ai_fifo_depth = 2047,
1142          .gainlkup = ai_gain_628x,
1143          .ai_speed = 1600,
1144          .n_aochan = 4,
1145          .aobits = 16,
1146          .ao_fifo_depth = 8191,
1147          .ao_range_table = &range_ni_M_628x_ao,
1148          .reg_type = ni_reg_628x,
1149          .ao_unipolar = 1,
1150          .ao_speed = 357,
1151          .num_p0_dio_channels = 32,
1152          .caldac = {caldac_none},
1153          .has_8255 = 0,
1154          },
1155         {
1156          .device_id = 0x70C0,
1157          .name = "pci-6143",
1158          .n_adchan = 8,
1159          .adbits = 16,
1160          .ai_fifo_depth = 1024,
1161          .alwaysdither = 0,
1162          .gainlkup = ai_gain_6143,
1163          .ai_speed = 4000,
1164          .n_aochan = 0,
1165          .aobits = 0,
1166          .reg_type = ni_reg_6143,
1167          .ao_unipolar = 0,
1168          .ao_fifo_depth = 0,
1169          .num_p0_dio_channels = 8,
1170          .caldac = {ad8804_debug, ad8804_debug},
1171          },
1172         {
1173          .device_id = 0x710D,
1174          .name = "pxi-6143",
1175          .n_adchan = 8,
1176          .adbits = 16,
1177          .ai_fifo_depth = 1024,
1178          .alwaysdither = 0,
1179          .gainlkup = ai_gain_6143,
1180          .ai_speed = 4000,
1181          .n_aochan = 0,
1182          .aobits = 0,
1183          .reg_type = ni_reg_6143,
1184          .ao_unipolar = 0,
1185          .ao_fifo_depth = 0,
1186          .num_p0_dio_channels = 8,
1187          .caldac = {ad8804_debug, ad8804_debug},
1188          },
1189 };
1190
1191 struct ni_private {
1192 NI_PRIVATE_COMMON};
1193 #define devpriv ((struct ni_private *)dev->private)
1194
1195 /* How we access registers */
1196
1197 #define ni_writel(a, b) (writel((a), devpriv->mite->daq_io_addr + (b)))
1198 #define ni_readl(a)     (readl(devpriv->mite->daq_io_addr + (a)))
1199 #define ni_writew(a, b) (writew((a), devpriv->mite->daq_io_addr + (b)))
1200 #define ni_readw(a)     (readw(devpriv->mite->daq_io_addr + (a)))
1201 #define ni_writeb(a, b) (writeb((a), devpriv->mite->daq_io_addr + (b)))
1202 #define ni_readb(a)     (readb(devpriv->mite->daq_io_addr + (a)))
1203
1204 /* How we access STC registers */
1205
1206 /* We automatically take advantage of STC registers that can be
1207  * read/written directly in the I/O space of the board.  Most
1208  * PCIMIO devices map the low 8 STC registers to iobase+addr*2.
1209  * The 611x devices map the write registers to iobase+addr*2, and
1210  * the read registers to iobase+(addr-1)*2. */
1211 /* However, the 611x boards still aren't working, so I'm disabling
1212  * non-windowed STC access temporarily */
1213
1214 static void e_series_win_out(struct comedi_device *dev, uint16_t data, int reg)
1215 {
1216         unsigned long flags;
1217
1218         spin_lock_irqsave(&devpriv->window_lock, flags);
1219         ni_writew(reg, Window_Address);
1220         ni_writew(data, Window_Data);
1221         spin_unlock_irqrestore(&devpriv->window_lock, flags);
1222 }
1223
1224 static uint16_t e_series_win_in(struct comedi_device *dev, int reg)
1225 {
1226         unsigned long flags;
1227         uint16_t ret;
1228
1229         spin_lock_irqsave(&devpriv->window_lock, flags);
1230         ni_writew(reg, Window_Address);
1231         ret = ni_readw(Window_Data);
1232         spin_unlock_irqrestore(&devpriv->window_lock, flags);
1233
1234         return ret;
1235 }
1236
1237 static void m_series_stc_writew(struct comedi_device *dev, uint16_t data,
1238                                 int reg)
1239 {
1240         unsigned offset;
1241         switch (reg) {
1242         case ADC_FIFO_Clear:
1243                 offset = M_Offset_AI_FIFO_Clear;
1244                 break;
1245         case AI_Command_1_Register:
1246                 offset = M_Offset_AI_Command_1;
1247                 break;
1248         case AI_Command_2_Register:
1249                 offset = M_Offset_AI_Command_2;
1250                 break;
1251         case AI_Mode_1_Register:
1252                 offset = M_Offset_AI_Mode_1;
1253                 break;
1254         case AI_Mode_2_Register:
1255                 offset = M_Offset_AI_Mode_2;
1256                 break;
1257         case AI_Mode_3_Register:
1258                 offset = M_Offset_AI_Mode_3;
1259                 break;
1260         case AI_Output_Control_Register:
1261                 offset = M_Offset_AI_Output_Control;
1262                 break;
1263         case AI_Personal_Register:
1264                 offset = M_Offset_AI_Personal;
1265                 break;
1266         case AI_SI2_Load_A_Register:
1267                 /*  this is actually a 32 bit register on m series boards */
1268                 ni_writel(data, M_Offset_AI_SI2_Load_A);
1269                 return;
1270                 break;
1271         case AI_SI2_Load_B_Register:
1272                 /*  this is actually a 32 bit register on m series boards */
1273                 ni_writel(data, M_Offset_AI_SI2_Load_B);
1274                 return;
1275                 break;
1276         case AI_START_STOP_Select_Register:
1277                 offset = M_Offset_AI_START_STOP_Select;
1278                 break;
1279         case AI_Trigger_Select_Register:
1280                 offset = M_Offset_AI_Trigger_Select;
1281                 break;
1282         case Analog_Trigger_Etc_Register:
1283                 offset = M_Offset_Analog_Trigger_Etc;
1284                 break;
1285         case AO_Command_1_Register:
1286                 offset = M_Offset_AO_Command_1;
1287                 break;
1288         case AO_Command_2_Register:
1289                 offset = M_Offset_AO_Command_2;
1290                 break;
1291         case AO_Mode_1_Register:
1292                 offset = M_Offset_AO_Mode_1;
1293                 break;
1294         case AO_Mode_2_Register:
1295                 offset = M_Offset_AO_Mode_2;
1296                 break;
1297         case AO_Mode_3_Register:
1298                 offset = M_Offset_AO_Mode_3;
1299                 break;
1300         case AO_Output_Control_Register:
1301                 offset = M_Offset_AO_Output_Control;
1302                 break;
1303         case AO_Personal_Register:
1304                 offset = M_Offset_AO_Personal;
1305                 break;
1306         case AO_Start_Select_Register:
1307                 offset = M_Offset_AO_Start_Select;
1308                 break;
1309         case AO_Trigger_Select_Register:
1310                 offset = M_Offset_AO_Trigger_Select;
1311                 break;
1312         case Clock_and_FOUT_Register:
1313                 offset = M_Offset_Clock_and_FOUT;
1314                 break;
1315         case Configuration_Memory_Clear:
1316                 offset = M_Offset_Configuration_Memory_Clear;
1317                 break;
1318         case DAC_FIFO_Clear:
1319                 offset = M_Offset_AO_FIFO_Clear;
1320                 break;
1321         case DIO_Control_Register:
1322                 printk
1323                     ("%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n",
1324                      __func__, reg);
1325                 return;
1326                 break;
1327         case G_Autoincrement_Register(0):
1328                 offset = M_Offset_G0_Autoincrement;
1329                 break;
1330         case G_Autoincrement_Register(1):
1331                 offset = M_Offset_G1_Autoincrement;
1332                 break;
1333         case G_Command_Register(0):
1334                 offset = M_Offset_G0_Command;
1335                 break;
1336         case G_Command_Register(1):
1337                 offset = M_Offset_G1_Command;
1338                 break;
1339         case G_Input_Select_Register(0):
1340                 offset = M_Offset_G0_Input_Select;
1341                 break;
1342         case G_Input_Select_Register(1):
1343                 offset = M_Offset_G1_Input_Select;
1344                 break;
1345         case G_Mode_Register(0):
1346                 offset = M_Offset_G0_Mode;
1347                 break;
1348         case G_Mode_Register(1):
1349                 offset = M_Offset_G1_Mode;
1350                 break;
1351         case Interrupt_A_Ack_Register:
1352                 offset = M_Offset_Interrupt_A_Ack;
1353                 break;
1354         case Interrupt_A_Enable_Register:
1355                 offset = M_Offset_Interrupt_A_Enable;
1356                 break;
1357         case Interrupt_B_Ack_Register:
1358                 offset = M_Offset_Interrupt_B_Ack;
1359                 break;
1360         case Interrupt_B_Enable_Register:
1361                 offset = M_Offset_Interrupt_B_Enable;
1362                 break;
1363         case Interrupt_Control_Register:
1364                 offset = M_Offset_Interrupt_Control;
1365                 break;
1366         case IO_Bidirection_Pin_Register:
1367                 offset = M_Offset_IO_Bidirection_Pin;
1368                 break;
1369         case Joint_Reset_Register:
1370                 offset = M_Offset_Joint_Reset;
1371                 break;
1372         case RTSI_Trig_A_Output_Register:
1373                 offset = M_Offset_RTSI_Trig_A_Output;
1374                 break;
1375         case RTSI_Trig_B_Output_Register:
1376                 offset = M_Offset_RTSI_Trig_B_Output;
1377                 break;
1378         case RTSI_Trig_Direction_Register:
1379                 offset = M_Offset_RTSI_Trig_Direction;
1380                 break;
1381                 /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit)
1382                    and M_Offset_SCXI_Serial_Data_Out (8 bit) */
1383         default:
1384                 printk(KERN_WARNING "%s: bug! unhandled register=0x%x in switch.\n",
1385                        __func__, reg);
1386                 BUG();
1387                 return;
1388                 break;
1389         }
1390         ni_writew(data, offset);
1391 }
1392
1393 static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
1394 {
1395         unsigned offset;
1396         switch (reg) {
1397         case AI_Status_1_Register:
1398                 offset = M_Offset_AI_Status_1;
1399                 break;
1400         case AO_Status_1_Register:
1401                 offset = M_Offset_AO_Status_1;
1402                 break;
1403         case AO_Status_2_Register:
1404                 offset = M_Offset_AO_Status_2;
1405                 break;
1406         case DIO_Serial_Input_Register:
1407                 return ni_readb(M_Offset_SCXI_Serial_Data_In);
1408                 break;
1409         case Joint_Status_1_Register:
1410                 offset = M_Offset_Joint_Status_1;
1411                 break;
1412         case Joint_Status_2_Register:
1413                 offset = M_Offset_Joint_Status_2;
1414                 break;
1415         case G_Status_Register:
1416                 offset = M_Offset_G01_Status;
1417                 break;
1418         default:
1419                 printk(KERN_WARNING "%s: bug! unhandled register=0x%x in switch.\n",
1420                        __func__, reg);
1421                 BUG();
1422                 return 0;
1423                 break;
1424         }
1425         return ni_readw(offset);
1426 }
1427
1428 static void m_series_stc_writel(struct comedi_device *dev, uint32_t data,
1429                                 int reg)
1430 {
1431         unsigned offset;
1432         switch (reg) {
1433         case AI_SC_Load_A_Registers:
1434                 offset = M_Offset_AI_SC_Load_A;
1435                 break;
1436         case AI_SI_Load_A_Registers:
1437                 offset = M_Offset_AI_SI_Load_A;
1438                 break;
1439         case AO_BC_Load_A_Register:
1440                 offset = M_Offset_AO_BC_Load_A;
1441                 break;
1442         case AO_UC_Load_A_Register:
1443                 offset = M_Offset_AO_UC_Load_A;
1444                 break;
1445         case AO_UI_Load_A_Register:
1446                 offset = M_Offset_AO_UI_Load_A;
1447                 break;
1448         case G_Load_A_Register(0):
1449                 offset = M_Offset_G0_Load_A;
1450                 break;
1451         case G_Load_A_Register(1):
1452                 offset = M_Offset_G1_Load_A;
1453                 break;
1454         case G_Load_B_Register(0):
1455                 offset = M_Offset_G0_Load_B;
1456                 break;
1457         case G_Load_B_Register(1):
1458                 offset = M_Offset_G1_Load_B;
1459                 break;
1460         default:
1461                 printk(KERN_WARNING "%s: bug! unhandled register=0x%x in switch.\n",
1462                        __func__, reg);
1463                 BUG();
1464                 return;
1465                 break;
1466         }
1467         ni_writel(data, offset);
1468 }
1469
1470 static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
1471 {
1472         unsigned offset;
1473         switch (reg) {
1474         case G_HW_Save_Register(0):
1475                 offset = M_Offset_G0_HW_Save;
1476                 break;
1477         case G_HW_Save_Register(1):
1478                 offset = M_Offset_G1_HW_Save;
1479                 break;
1480         case G_Save_Register(0):
1481                 offset = M_Offset_G0_Save;
1482                 break;
1483         case G_Save_Register(1):
1484                 offset = M_Offset_G1_Save;
1485                 break;
1486         default:
1487                 printk(KERN_WARNING "%s: bug! unhandled register=0x%x in switch.\n",
1488                        __func__, reg);
1489                 BUG();
1490                 return 0;
1491                 break;
1492         }
1493         return ni_readl(offset);
1494 }
1495
1496 #define interrupt_pin(a)        0
1497 #define IRQ_POLARITY 1
1498
1499 #define NI_E_IRQ_FLAGS          IRQF_SHARED
1500
1501 #include "ni_mio_common.c"
1502
1503 static int pcimio_ai_change(struct comedi_device *dev,
1504                             struct comedi_subdevice *s, unsigned long new_size);
1505 static int pcimio_ao_change(struct comedi_device *dev,
1506                             struct comedi_subdevice *s, unsigned long new_size);
1507 static int pcimio_gpct0_change(struct comedi_device *dev,
1508                                struct comedi_subdevice *s,
1509                                unsigned long new_size);
1510 static int pcimio_gpct1_change(struct comedi_device *dev,
1511                                struct comedi_subdevice *s,
1512                                unsigned long new_size);
1513 static int pcimio_dio_change(struct comedi_device *dev,
1514                              struct comedi_subdevice *s,
1515                              unsigned long new_size);
1516
1517 static void m_series_init_eeprom_buffer(struct comedi_device *dev)
1518 {
1519         static const int Start_Cal_EEPROM = 0x400;
1520         static const unsigned window_size = 10;
1521         static const int serial_number_eeprom_offset = 0x4;
1522         static const int serial_number_eeprom_length = 0x4;
1523         unsigned old_iodwbsr_bits;
1524         unsigned old_iodwbsr1_bits;
1525         unsigned old_iodwcr1_bits;
1526         int i;
1527
1528         old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR);
1529         old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1530         old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1531         writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1532         writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr),
1533                devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1534         writel(0x1 | old_iodwcr1_bits,
1535                devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1536         writel(0xf, devpriv->mite->mite_io_addr + 0x30);
1537
1538         BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1539         for (i = 0; i < serial_number_eeprom_length; ++i) {
1540                 char *byte_ptr = (char *)&devpriv->serial_number + i;
1541                 *byte_ptr = ni_readb(serial_number_eeprom_offset + i);
1542         }
1543         devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1544
1545         for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i)
1546                 devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i);
1547
1548         writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1549         writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1550         writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1551         writel(0x0, devpriv->mite->mite_io_addr + 0x30);
1552 }
1553
1554 static void init_6143(struct comedi_device *dev)
1555 {
1556         /*  Disable interrupts */
1557         devpriv->stc_writew(dev, 0, Interrupt_Control_Register);
1558
1559         /*  Initialise 6143 AI specific bits */
1560         ni_writeb(0x00, Magic_6143);    /*  Set G0,G1 DMA mode to E series version */
1561         ni_writeb(0x80, PipelineDelay_6143);    /*  Set EOCMode, ADCMode and pipelinedelay */
1562         ni_writeb(0x00, EOC_Set_6143);  /*  Set EOC Delay */
1563
1564         ni_writel(boardtype.ai_fifo_depth / 2, AIFIFO_Flag_6143);       /*  Set the FIFO half full level */
1565
1566         /*  Strobe Relay disable bit */
1567         devpriv->ai_calib_source_enabled = 0;
1568         ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff,
1569                   Calibration_Channel_6143);
1570         ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1571 }
1572
1573 static void pcimio_detach(struct comedi_device *dev)
1574 {
1575         mio_common_detach(dev);
1576         if (dev->irq)
1577                 free_irq(dev->irq, dev);
1578         if (dev->private) {
1579                 mite_free_ring(devpriv->ai_mite_ring);
1580                 mite_free_ring(devpriv->ao_mite_ring);
1581                 mite_free_ring(devpriv->cdo_mite_ring);
1582                 mite_free_ring(devpriv->gpct_mite_ring[0]);
1583                 mite_free_ring(devpriv->gpct_mite_ring[1]);
1584                 if (devpriv->mite) {
1585                         mite_unsetup(devpriv->mite);
1586                         mite_free(devpriv->mite);
1587                 }
1588         }
1589 }
1590
1591 static const struct ni_board_struct *
1592 pcimio_find_boardinfo(struct pci_dev *pcidev)
1593 {
1594         unsigned int device_id = pcidev->device;
1595         unsigned int n;
1596
1597         for (n = 0; n < ARRAY_SIZE(ni_boards); n++) {
1598                 const struct ni_board_struct *board = &ni_boards[n];
1599                 if (board->device_id == device_id)
1600                         return board;
1601         }
1602         return NULL;
1603 }
1604
1605 static int __devinit pcimio_attach_pci(struct comedi_device *dev,
1606                                        struct pci_dev *pcidev)
1607 {
1608         int ret;
1609
1610         dev_info(dev->class_dev, "ni_pcimio: attach %s\n", pci_name(pcidev));
1611
1612         ret = ni_alloc_private(dev);
1613         if (ret < 0)
1614                 return ret;
1615
1616         dev->board_ptr = pcimio_find_boardinfo(pcidev);
1617         if (!dev->board_ptr)
1618                 return -ENODEV;
1619
1620         devpriv->mite = mite_alloc(pcidev);
1621         if (!devpriv->mite)
1622                 return -ENOMEM;
1623
1624         dev_dbg(dev->class_dev, "%s\n", boardtype.name);
1625         dev->board_name = boardtype.name;
1626
1627         if (boardtype.reg_type & ni_reg_m_series_mask) {
1628                 devpriv->stc_writew = &m_series_stc_writew;
1629                 devpriv->stc_readw = &m_series_stc_readw;
1630                 devpriv->stc_writel = &m_series_stc_writel;
1631                 devpriv->stc_readl = &m_series_stc_readl;
1632         } else {
1633                 devpriv->stc_writew = &e_series_win_out;
1634                 devpriv->stc_readw = &e_series_win_in;
1635                 devpriv->stc_writel = &win_out2;
1636                 devpriv->stc_readl = &win_in2;
1637         }
1638
1639         ret = mite_setup(devpriv->mite);
1640         if (ret < 0) {
1641                 pr_warn("error setting up mite\n");
1642                 return ret;
1643         }
1644         comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev);
1645         devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1646         if (devpriv->ai_mite_ring == NULL)
1647                 return -ENOMEM;
1648         devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1649         if (devpriv->ao_mite_ring == NULL)
1650                 return -ENOMEM;
1651         devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1652         if (devpriv->cdo_mite_ring == NULL)
1653                 return -ENOMEM;
1654         devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1655         if (devpriv->gpct_mite_ring[0] == NULL)
1656                 return -ENOMEM;
1657         devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1658         if (devpriv->gpct_mite_ring[1] == NULL)
1659                 return -ENOMEM;
1660
1661         if (boardtype.reg_type & ni_reg_m_series_mask)
1662                 m_series_init_eeprom_buffer(dev);
1663         if (boardtype.reg_type == ni_reg_6143)
1664                 init_6143(dev);
1665
1666         dev->irq = mite_irq(devpriv->mite);
1667
1668         if (dev->irq == 0) {
1669                 pr_warn("unknown irq (bad)\n");
1670         } else {
1671                 pr_debug("( irq = %u )\n", dev->irq);
1672                 ret = request_irq(dev->irq, ni_E_interrupt, NI_E_IRQ_FLAGS,
1673                                   DRV_NAME, dev);
1674                 if (ret < 0) {
1675                         pr_warn("irq not available\n");
1676                         dev->irq = 0;
1677                 }
1678         }
1679
1680         ret = ni_E_init(dev);
1681         if (ret < 0)
1682                 return ret;
1683
1684         dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1685         dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1686         dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1687         dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1688         dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1689
1690         return ret;
1691 }
1692
1693 static int pcimio_ai_change(struct comedi_device *dev,
1694                             struct comedi_subdevice *s, unsigned long new_size)
1695 {
1696         int ret;
1697
1698         ret = mite_buf_change(devpriv->ai_mite_ring, s->async);
1699         if (ret < 0)
1700                 return ret;
1701
1702         return 0;
1703 }
1704
1705 static int pcimio_ao_change(struct comedi_device *dev,
1706                             struct comedi_subdevice *s, unsigned long new_size)
1707 {
1708         int ret;
1709
1710         ret = mite_buf_change(devpriv->ao_mite_ring, s->async);
1711         if (ret < 0)
1712                 return ret;
1713
1714         return 0;
1715 }
1716
1717 static int pcimio_gpct0_change(struct comedi_device *dev,
1718                                struct comedi_subdevice *s,
1719                                unsigned long new_size)
1720 {
1721         int ret;
1722
1723         ret = mite_buf_change(devpriv->gpct_mite_ring[0], s->async);
1724         if (ret < 0)
1725                 return ret;
1726
1727         return 0;
1728 }
1729
1730 static int pcimio_gpct1_change(struct comedi_device *dev,
1731                                struct comedi_subdevice *s,
1732                                unsigned long new_size)
1733 {
1734         int ret;
1735
1736         ret = mite_buf_change(devpriv->gpct_mite_ring[1], s->async);
1737         if (ret < 0)
1738                 return ret;
1739
1740         return 0;
1741 }
1742
1743 static int pcimio_dio_change(struct comedi_device *dev,
1744                              struct comedi_subdevice *s, unsigned long new_size)
1745 {
1746         int ret;
1747
1748         ret = mite_buf_change(devpriv->cdo_mite_ring, s->async);
1749         if (ret < 0)
1750                 return ret;
1751
1752         return 0;
1753 }
1754
1755 static struct comedi_driver ni_pcimio_driver = {
1756         .driver_name    = "ni_pcimio",
1757         .module         = THIS_MODULE,
1758         .attach_pci     = pcimio_attach_pci,
1759         .detach         = pcimio_detach,
1760 };
1761
1762 static int __devinit ni_pcimio_pci_probe(struct pci_dev *dev,
1763                                          const struct pci_device_id *ent)
1764 {
1765         return comedi_pci_auto_config(dev, &ni_pcimio_driver);
1766 }
1767
1768 static void __devexit ni_pcimio_pci_remove(struct pci_dev *dev)
1769 {
1770         comedi_pci_auto_unconfig(dev);
1771 }
1772
1773 static DEFINE_PCI_DEVICE_TABLE(ni_pcimio_pci_table) = {
1774         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x0162) },
1775         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1170) },
1776         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1180) },
1777         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1190) },
1778         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11b0) },
1779         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11c0) },
1780         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11d0) },
1781         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1270) },
1782         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1330) },
1783         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1340) },
1784         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1350) },
1785         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x14e0) },
1786         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x14f0) },
1787         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1580) },
1788         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x15b0) },
1789         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1880) },
1790         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1870) },
1791         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x18b0) },
1792         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x18c0) },
1793         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2410) },
1794         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2420) },
1795         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2430) },
1796         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2890) },
1797         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x28c0) },
1798         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a60) },
1799         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a70) },
1800         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a80) },
1801         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2ab0) },
1802         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b80) },
1803         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b90) },
1804         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2c80) },
1805         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2ca0) },
1806         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70aa) },
1807         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70ab) },
1808         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70ac) },
1809         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70af) },
1810         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b0) },
1811         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b4) },
1812         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b6) },
1813         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b7) },
1814         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b8) },
1815         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bc) },
1816         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bd) },
1817         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bf) },
1818         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70c0) },
1819         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70f2) },
1820         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x710d) },
1821         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x716c) },
1822         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x716d) },
1823         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x717f) },
1824         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x71bc) },
1825         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x717d) },
1826         { PCI_DEVICE(PCI_VENDOR_ID_NI, 0x72e8) },
1827         { 0 }
1828 };
1829 MODULE_DEVICE_TABLE(pci, ni_pcimio_pci_table);
1830
1831 static struct pci_driver ni_pcimio_pci_driver = {
1832         .name           = "ni_pcimio",
1833         .id_table       = ni_pcimio_pci_table,
1834         .probe          = ni_pcimio_pci_probe,
1835         .remove         = __devexit_p(ni_pcimio_pci_remove)
1836 };
1837 module_comedi_pci_driver(ni_pcimio_driver, ni_pcimio_pci_driver);
1838
1839 MODULE_AUTHOR("Comedi http://www.comedi.org");
1840 MODULE_DESCRIPTION("Comedi low-level driver");
1841 MODULE_LICENSE("GPL");