2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
21 This file is meant to be included by another file, e.g.,
22 ni_atmio.c or ni_pcimio.c.
24 Interrupt support originally added by Truxton Fulton
27 References (from ftp://ftp.natinst.com/support/manuals):
29 340747b.pdf AT-MIO E series Register Level Programmer Manual
30 341079b.pdf PCI E Series RLPM
31 340934b.pdf DAQ-STC reference manual
32 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
35 Other possibly relevant info:
37 320517c.pdf User manual (obsolete)
38 320517f.pdf User manual (new)
40 320906c.pdf maximum signal ratings
42 321791a.pdf discontinuation of at-mio-16e-10 rev. c
43 321808a.pdf about at-mio-16e-10 rev P
44 321837a.pdf discontinuation of at-mio-16de-10 rev d
45 321838a.pdf about at-mio-16de-10 rev N
49 - the interrupt routine needs to be cleaned up
51 2006-02-07: S-Series PCI-6143: Support has been added but is not
52 fully tested as yet. Terry Barnaby, BEAM Ltd.
55 #include <linux/interrupt.h>
56 #include <linux/sched.h>
57 #include <linux/delay.h>
62 #define NI_TIMEOUT 1000
64 /* Note: this table must match the ai_gain_* definitions */
65 static const short ni_gainlkup[][16] = {
66 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
67 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
68 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
69 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
70 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
71 [ai_gain_4] = {0, 1, 4, 7},
72 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
73 0x003, 0x004, 0x005, 0x006},
74 [ai_gain_622x] = {0, 1, 4, 5},
75 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
76 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
79 static const struct comedi_lrange range_ni_E_ai = {
100 static const struct comedi_lrange range_ni_E_ai_limited = {
113 static const struct comedi_lrange range_ni_E_ai_limited14 = {
132 static const struct comedi_lrange range_ni_E_ai_bipolar4 = {
141 static const struct comedi_lrange range_ni_E_ai_611x = {
154 static const struct comedi_lrange range_ni_M_ai_622x = {
163 static const struct comedi_lrange range_ni_M_ai_628x = {
175 static const struct comedi_lrange range_ni_E_ao_ext = {
184 static const struct comedi_lrange *const ni_range_lkup[] = {
185 [ai_gain_16] = &range_ni_E_ai,
186 [ai_gain_8] = &range_ni_E_ai_limited,
187 [ai_gain_14] = &range_ni_E_ai_limited14,
188 [ai_gain_4] = &range_ni_E_ai_bipolar4,
189 [ai_gain_611x] = &range_ni_E_ai_611x,
190 [ai_gain_622x] = &range_ni_M_ai_622x,
191 [ai_gain_628x] = &range_ni_M_ai_628x,
192 [ai_gain_6143] = &range_bipolar5
197 AIMODE_HALF_FULL = 1,
202 enum ni_common_subdevices {
208 NI_CALIBRATION_SUBDEV,
211 NI_CS5529_CALIBRATION_SUBDEV,
219 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
221 switch (counter_index) {
223 return NI_GPCT0_SUBDEV;
225 return NI_GPCT1_SUBDEV;
230 return NI_GPCT0_SUBDEV;
233 enum timebase_nanoseconds {
235 TIMEBASE_2_NS = 10000
238 #define SERIAL_DISABLED 0
239 #define SERIAL_600NS 600
240 #define SERIAL_1_2US 1200
241 #define SERIAL_10US 10000
243 static const int num_adc_stages_611x = 3;
245 static void ni_writel(struct comedi_device *dev, uint32_t data, int reg)
248 writel(data, dev->mmio + reg);
250 outl(data, dev->iobase + reg);
253 static void ni_writew(struct comedi_device *dev, uint16_t data, int reg)
256 writew(data, dev->mmio + reg);
258 outw(data, dev->iobase + reg);
261 static void ni_writeb(struct comedi_device *dev, uint8_t data, int reg)
264 writeb(data, dev->mmio + reg);
266 outb(data, dev->iobase + reg);
269 static uint32_t ni_readl(struct comedi_device *dev, int reg)
272 return readl(dev->mmio + reg);
274 return inl(dev->iobase + reg);
277 static uint16_t ni_readw(struct comedi_device *dev, int reg)
280 return readw(dev->mmio + reg);
282 return inw(dev->iobase + reg);
285 static uint8_t ni_readb(struct comedi_device *dev, int reg)
288 return readb(dev->mmio + reg);
290 return inb(dev->iobase + reg);
294 * We automatically take advantage of STC registers that can be
295 * read/written directly in the I/O space of the board.
297 * The AT-MIO and DAQCard devices map the low 8 STC registers to
300 * Most PCIMIO devices also map the low 8 STC registers but the
301 * 611x devices map the read registers to iobase+(addr-1)*2.
302 * For now non-windowed STC access is disabled if a PCIMIO device
303 * is detected (devpriv->mite has been initialized).
305 * The M series devices do not used windowed registers for the
306 * STC registers. The functions below handle the mapping of the
307 * windowed STC registers to the m series register offsets.
311 unsigned int mio_reg;
315 static const struct mio_regmap m_series_stc_write_regmap[] = {
316 [NISTC_INTA_ACK_REG] = { 0x104, 2 },
317 [NISTC_INTB_ACK_REG] = { 0x106, 2 },
318 [NISTC_AI_CMD2_REG] = { 0x108, 2 },
319 [NISTC_AO_CMD2_REG] = { 0x10a, 2 },
320 [NISTC_G0_CMD_REG] = { 0x10c, 2 },
321 [NISTC_G1_CMD_REG] = { 0x10e, 2 },
322 [NISTC_AI_CMD1_REG] = { 0x110, 2 },
323 [NISTC_AO_CMD1_REG] = { 0x112, 2 },
325 * NISTC_DIO_OUT_REG maps to:
326 * { NI_M_DIO_REG, 4 } and { NI_M_SCXI_SER_DO_REG, 1 }
328 [NISTC_DIO_OUT_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
329 [NISTC_DIO_CTRL_REG] = { 0, 0 }, /* DOES NOT MAP CLEANLY */
330 [NISTC_AI_MODE1_REG] = { 0x118, 2 },
331 [NISTC_AI_MODE2_REG] = { 0x11a, 2 },
332 [NISTC_AI_SI_LOADA_REG] = { 0x11c, 4 },
333 [NISTC_AI_SI_LOADB_REG] = { 0x120, 4 },
334 [NISTC_AI_SC_LOADA_REG] = { 0x124, 4 },
335 [NISTC_AI_SC_LOADB_REG] = { 0x128, 4 },
336 [NISTC_AI_SI2_LOADA_REG] = { 0x12c, 4 },
337 [NISTC_AI_SI2_LOADB_REG] = { 0x130, 4 },
338 [NISTC_G0_MODE_REG] = { 0x134, 2 },
339 [NISTC_G1_MODE_REG] = { 0x136, 2 },
340 [NISTC_G0_LOADA_REG] = { 0x138, 4 },
341 [NISTC_G0_LOADB_REG] = { 0x13c, 4 },
342 [NISTC_G1_LOADA_REG] = { 0x140, 4 },
343 [NISTC_G1_LOADB_REG] = { 0x144, 4 },
344 [NISTC_G0_INPUT_SEL_REG] = { 0x148, 2 },
345 [NISTC_G1_INPUT_SEL_REG] = { 0x14a, 2 },
346 [NISTC_AO_MODE1_REG] = { 0x14c, 2 },
347 [NISTC_AO_MODE2_REG] = { 0x14e, 2 },
348 [NISTC_AO_UI_LOADA_REG] = { 0x150, 4 },
349 [NISTC_AO_UI_LOADB_REG] = { 0x154, 4 },
350 [NISTC_AO_BC_LOADA_REG] = { 0x158, 4 },
351 [NISTC_AO_BC_LOADB_REG] = { 0x15c, 4 },
352 [NISTC_AO_UC_LOADA_REG] = { 0x160, 4 },
353 [NISTC_AO_UC_LOADB_REG] = { 0x164, 4 },
354 [NISTC_CLK_FOUT_REG] = { 0x170, 2 },
355 [NISTC_IO_BIDIR_PIN_REG] = { 0x172, 2 },
356 [NISTC_RTSI_TRIG_DIR_REG] = { 0x174, 2 },
357 [NISTC_INT_CTRL_REG] = { 0x176, 2 },
358 [NISTC_AI_OUT_CTRL_REG] = { 0x178, 2 },
359 [NISTC_ATRIG_ETC_REG] = { 0x17a, 2 },
360 [NISTC_AI_START_STOP_REG] = { 0x17c, 2 },
361 [NISTC_AI_TRIG_SEL_REG] = { 0x17e, 2 },
362 [NISTC_AI_DIV_LOADA_REG] = { 0x180, 4 },
363 [NISTC_AO_START_SEL_REG] = { 0x184, 2 },
364 [NISTC_AO_TRIG_SEL_REG] = { 0x186, 2 },
365 [NISTC_G0_AUTOINC_REG] = { 0x188, 2 },
366 [NISTC_G1_AUTOINC_REG] = { 0x18a, 2 },
367 [NISTC_AO_MODE3_REG] = { 0x18c, 2 },
368 [NISTC_RESET_REG] = { 0x190, 2 },
369 [NISTC_INTA_ENA_REG] = { 0x192, 2 },
370 [NISTC_INTA2_ENA_REG] = { 0, 0 }, /* E-Series only */
371 [NISTC_INTB_ENA_REG] = { 0x196, 2 },
372 [NISTC_INTB2_ENA_REG] = { 0, 0 }, /* E-Series only */
373 [NISTC_AI_PERSONAL_REG] = { 0x19a, 2 },
374 [NISTC_AO_PERSONAL_REG] = { 0x19c, 2 },
375 [NISTC_RTSI_TRIGA_OUT_REG] = { 0x19e, 2 },
376 [NISTC_RTSI_TRIGB_OUT_REG] = { 0x1a0, 2 },
377 [NISTC_RTSI_BOARD_REG] = { 0, 0 }, /* Unknown */
378 [NISTC_CFG_MEM_CLR_REG] = { 0x1a4, 2 },
379 [NISTC_ADC_FIFO_CLR_REG] = { 0x1a6, 2 },
380 [NISTC_DAC_FIFO_CLR_REG] = { 0x1a8, 2 },
381 [NISTC_AO_OUT_CTRL_REG] = { 0x1ac, 2 },
382 [NISTC_AI_MODE3_REG] = { 0x1ae, 2 },
385 static void m_series_stc_write(struct comedi_device *dev,
386 unsigned int data, unsigned int reg)
388 const struct mio_regmap *regmap;
390 if (reg < ARRAY_SIZE(m_series_stc_write_regmap)) {
391 regmap = &m_series_stc_write_regmap[reg];
393 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
398 switch (regmap->size) {
400 ni_writel(dev, data, regmap->mio_reg);
403 ni_writew(dev, data, regmap->mio_reg);
406 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
412 static const struct mio_regmap m_series_stc_read_regmap[] = {
413 [NISTC_AI_STATUS1_REG] = { 0x104, 2 },
414 [NISTC_AO_STATUS1_REG] = { 0x106, 2 },
415 [NISTC_G01_STATUS_REG] = { 0x108, 2 },
416 [NISTC_AI_STATUS2_REG] = { 0, 0 }, /* Unknown */
417 [NISTC_AO_STATUS2_REG] = { 0x10c, 2 },
418 [NISTC_DIO_IN_REG] = { 0, 0 }, /* Unknown */
419 [NISTC_G0_HW_SAVE_REG] = { 0x110, 4 },
420 [NISTC_G1_HW_SAVE_REG] = { 0x114, 4 },
421 [NISTC_G0_SAVE_REG] = { 0x118, 4 },
422 [NISTC_G1_SAVE_REG] = { 0x11c, 4 },
423 [NISTC_AO_UI_SAVE_REG] = { 0x120, 4 },
424 [NISTC_AO_BC_SAVE_REG] = { 0x124, 4 },
425 [NISTC_AO_UC_SAVE_REG] = { 0x128, 4 },
426 [NISTC_STATUS1_REG] = { 0x136, 2 },
427 [NISTC_DIO_SERIAL_IN_REG] = { 0x009, 1 },
428 [NISTC_STATUS2_REG] = { 0x13a, 2 },
429 [NISTC_AI_SI_SAVE_REG] = { 0x180, 4 },
430 [NISTC_AI_SC_SAVE_REG] = { 0x184, 4 },
433 static unsigned int m_series_stc_read(struct comedi_device *dev,
436 const struct mio_regmap *regmap;
438 if (reg < ARRAY_SIZE(m_series_stc_read_regmap)) {
439 regmap = &m_series_stc_read_regmap[reg];
441 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
446 switch (regmap->size) {
448 return ni_readl(dev, regmap->mio_reg);
450 return ni_readw(dev, regmap->mio_reg);
452 return ni_readb(dev, regmap->mio_reg);
454 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n",
460 static void ni_stc_writew(struct comedi_device *dev, uint16_t data, int reg)
462 struct ni_private *devpriv = dev->private;
465 if (devpriv->is_m_series) {
466 m_series_stc_write(dev, data, reg);
468 spin_lock_irqsave(&devpriv->window_lock, flags);
469 if (!devpriv->mite && reg < 8) {
470 ni_writew(dev, data, reg * 2);
472 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
473 ni_writew(dev, data, NI_E_STC_WINDOW_DATA_REG);
475 spin_unlock_irqrestore(&devpriv->window_lock, flags);
479 static void ni_stc_writel(struct comedi_device *dev, uint32_t data, int reg)
481 struct ni_private *devpriv = dev->private;
483 if (devpriv->is_m_series) {
484 m_series_stc_write(dev, data, reg);
486 ni_stc_writew(dev, data >> 16, reg);
487 ni_stc_writew(dev, data & 0xffff, reg + 1);
491 static uint16_t ni_stc_readw(struct comedi_device *dev, int reg)
493 struct ni_private *devpriv = dev->private;
497 if (devpriv->is_m_series) {
498 val = m_series_stc_read(dev, reg);
500 spin_lock_irqsave(&devpriv->window_lock, flags);
501 if (!devpriv->mite && reg < 8) {
502 val = ni_readw(dev, reg * 2);
504 ni_writew(dev, reg, NI_E_STC_WINDOW_ADDR_REG);
505 val = ni_readw(dev, NI_E_STC_WINDOW_DATA_REG);
507 spin_unlock_irqrestore(&devpriv->window_lock, flags);
512 static uint32_t ni_stc_readl(struct comedi_device *dev, int reg)
514 struct ni_private *devpriv = dev->private;
517 if (devpriv->is_m_series) {
518 val = m_series_stc_read(dev, reg);
520 val = ni_stc_readw(dev, reg) << 16;
521 val |= ni_stc_readw(dev, reg + 1);
526 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
527 unsigned bit_mask, unsigned bit_values)
529 struct ni_private *devpriv = dev->private;
532 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
534 case NISTC_INTA_ENA_REG:
535 devpriv->int_a_enable_reg &= ~bit_mask;
536 devpriv->int_a_enable_reg |= bit_values & bit_mask;
537 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg);
539 case NISTC_INTB_ENA_REG:
540 devpriv->int_b_enable_reg &= ~bit_mask;
541 devpriv->int_b_enable_reg |= bit_values & bit_mask;
542 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg);
544 case NISTC_IO_BIDIR_PIN_REG:
545 devpriv->io_bidirection_pin_reg &= ~bit_mask;
546 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
547 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg);
549 case NI_E_DMA_AI_AO_SEL_REG:
550 devpriv->ai_ao_select_reg &= ~bit_mask;
551 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
552 ni_writeb(dev, devpriv->ai_ao_select_reg, reg);
554 case NI_E_DMA_G0_G1_SEL_REG:
555 devpriv->g0_g1_select_reg &= ~bit_mask;
556 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
557 ni_writeb(dev, devpriv->g0_g1_select_reg, reg);
560 dev_err(dev->class_dev, "called with invalid register %d\n",
565 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
569 /* DMA channel setup */
570 static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel)
582 /* negative channel means no channel */
583 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
588 bits = ni_stc_dma_channel_select_bitfield(channel);
590 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
591 NI_E_DMA_AI_SEL_MASK, NI_E_DMA_AI_SEL(bits));
594 /* negative channel means no channel */
595 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
600 bits = ni_stc_dma_channel_select_bitfield(channel);
602 ni_set_bitfield(dev, NI_E_DMA_AI_AO_SEL_REG,
603 NI_E_DMA_AO_SEL_MASK, NI_E_DMA_AO_SEL(bits));
606 /* negative channel means no channel */
607 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
614 bits = ni_stc_dma_channel_select_bitfield(channel);
616 ni_set_bitfield(dev, NI_E_DMA_G0_G1_SEL_REG,
617 NI_E_DMA_G0_G1_SEL_MASK(gpct_index),
618 NI_E_DMA_G0_G1_SEL(gpct_index, bits));
621 /* negative mite_channel means no channel */
622 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
625 struct ni_private *devpriv = dev->private;
629 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
630 devpriv->cdio_dma_select_reg &= ~NI_M_CDIO_DMA_SEL_CDO_MASK;
631 if (mite_channel >= 0) {
633 * XXX just guessing ni_stc_dma_channel_select_bitfield()
634 * returns the right bits, under the assumption the cdio dma
635 * selection works just like ai/ao/gpct.
636 * Definitely works for dma channels 0 and 1.
638 bits = ni_stc_dma_channel_select_bitfield(mite_channel);
639 devpriv->cdio_dma_select_reg |= NI_M_CDIO_DMA_SEL_CDO(bits);
641 ni_writeb(dev, devpriv->cdio_dma_select_reg, NI_M_CDIO_DMA_SEL_REG);
643 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
646 static int ni_request_ai_mite_channel(struct comedi_device *dev)
648 struct ni_private *devpriv = dev->private;
651 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
652 BUG_ON(devpriv->ai_mite_chan);
653 devpriv->ai_mite_chan =
654 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
655 if (!devpriv->ai_mite_chan) {
656 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
657 dev_err(dev->class_dev,
658 "failed to reserve mite dma channel for analog input\n");
661 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
662 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
663 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
667 static int ni_request_ao_mite_channel(struct comedi_device *dev)
669 struct ni_private *devpriv = dev->private;
672 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
673 BUG_ON(devpriv->ao_mite_chan);
674 devpriv->ao_mite_chan =
675 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
676 if (!devpriv->ao_mite_chan) {
677 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
678 dev_err(dev->class_dev,
679 "failed to reserve mite dma channel for analog outut\n");
682 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
683 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
684 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
688 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
690 enum comedi_io_direction direction)
692 struct ni_private *devpriv = dev->private;
694 struct mite_channel *mite_chan;
696 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
697 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
699 mite_request_channel(devpriv->mite,
700 devpriv->gpct_mite_ring[gpct_index]);
702 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
703 dev_err(dev->class_dev,
704 "failed to reserve mite dma channel for counter\n");
707 mite_chan->dir = direction;
708 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
710 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
711 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
717 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
720 struct ni_private *devpriv = dev->private;
723 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
724 BUG_ON(devpriv->cdo_mite_chan);
725 devpriv->cdo_mite_chan =
726 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
727 if (!devpriv->cdo_mite_chan) {
728 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
729 dev_err(dev->class_dev,
730 "failed to reserve mite dma channel for correlated digital output\n");
733 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
734 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
735 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
740 static void ni_release_ai_mite_channel(struct comedi_device *dev)
743 struct ni_private *devpriv = dev->private;
746 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
747 if (devpriv->ai_mite_chan) {
748 ni_set_ai_dma_channel(dev, -1);
749 mite_release_channel(devpriv->ai_mite_chan);
750 devpriv->ai_mite_chan = NULL;
752 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
756 static void ni_release_ao_mite_channel(struct comedi_device *dev)
759 struct ni_private *devpriv = dev->private;
762 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
763 if (devpriv->ao_mite_chan) {
764 ni_set_ao_dma_channel(dev, -1);
765 mite_release_channel(devpriv->ao_mite_chan);
766 devpriv->ao_mite_chan = NULL;
768 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
773 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
776 struct ni_private *devpriv = dev->private;
779 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
780 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
781 struct mite_channel *mite_chan =
782 devpriv->counter_dev->counters[gpct_index].mite_chan;
784 ni_set_gpct_dma_channel(dev, gpct_index, -1);
785 ni_tio_set_mite_channel(&devpriv->
786 counter_dev->counters[gpct_index],
788 mite_release_channel(mite_chan);
790 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
794 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
797 struct ni_private *devpriv = dev->private;
800 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
801 if (devpriv->cdo_mite_chan) {
802 ni_set_cdo_dma_channel(dev, -1);
803 mite_release_channel(devpriv->cdo_mite_chan);
804 devpriv->cdo_mite_chan = NULL;
806 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
811 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
812 unsigned gpct_index, short enable)
814 struct ni_private *devpriv = dev->private;
818 if (devpriv->is_m_series || gpct_index > 1)
822 * e-series boards use the second irq signals to generate
823 * dma requests for their counters
825 if (gpct_index == 0) {
826 reg = NISTC_INTA2_ENA_REG;
828 val = NISTC_INTA_ENA_G0_GATE;
830 reg = NISTC_INTB2_ENA_REG;
832 val = NISTC_INTB_ENA_G1_GATE;
834 ni_stc_writew(dev, val, reg);
838 static void ni_clear_ai_fifo(struct comedi_device *dev)
840 struct ni_private *devpriv = dev->private;
841 static const int timeout = 10000;
844 if (devpriv->is_6143) {
845 /* Flush the 6143 data FIFO */
846 ni_writel(dev, 0x10, NI6143_AI_FIFO_CTRL_REG);
847 ni_writel(dev, 0x00, NI6143_AI_FIFO_CTRL_REG);
848 /* Wait for complete */
849 for (i = 0; i < timeout; i++) {
850 if (!(ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x10))
855 dev_err(dev->class_dev, "FIFO flush timeout\n");
857 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
858 if (devpriv->is_625x) {
859 ni_writeb(dev, 0, NI_M_STATIC_AI_CTRL_REG(0));
860 ni_writeb(dev, 1, NI_M_STATIC_AI_CTRL_REG(0));
862 /* the NI example code does 3 convert pulses for 625x boards,
863 but that appears to be wrong in practice. */
864 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
866 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
868 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
875 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
878 struct ni_private *devpriv = dev->private;
881 spin_lock_irqsave(&devpriv->window_lock, flags);
882 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
883 ni_writew(dev, data, NI611X_AO_WINDOW_DATA_REG);
884 spin_unlock_irqrestore(&devpriv->window_lock, flags);
887 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
890 struct ni_private *devpriv = dev->private;
893 spin_lock_irqsave(&devpriv->window_lock, flags);
894 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
895 ni_writel(dev, data, NI611X_AO_WINDOW_DATA_REG);
896 spin_unlock_irqrestore(&devpriv->window_lock, flags);
899 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
901 struct ni_private *devpriv = dev->private;
905 spin_lock_irqsave(&devpriv->window_lock, flags);
906 ni_writew(dev, addr, NI611X_AO_WINDOW_ADDR_REG);
907 data = ni_readw(dev, NI611X_AO_WINDOW_DATA_REG);
908 spin_unlock_irqrestore(&devpriv->window_lock, flags);
912 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
913 * share registers (such as Interrupt_A_Register) without interfering with
916 * NOTE: the switch/case statements are optimized out for a constant argument
917 * so this is actually quite fast--- If you must wrap another function around this
918 * make it inline to avoid a large speed penalty.
920 * value should only be 1 or 0.
922 static inline void ni_set_bits(struct comedi_device *dev, int reg,
923 unsigned bits, unsigned value)
931 ni_set_bitfield(dev, reg, bits, bit_values);
935 static void ni_sync_ai_dma(struct comedi_device *dev)
937 struct ni_private *devpriv = dev->private;
938 struct comedi_subdevice *s = dev->read_subdev;
941 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
942 if (devpriv->ai_mite_chan)
943 mite_sync_input_dma(devpriv->ai_mite_chan, s);
944 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
947 static int ni_ai_drain_dma(struct comedi_device *dev)
949 struct ni_private *devpriv = dev->private;
951 static const int timeout = 10000;
955 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
956 if (devpriv->ai_mite_chan) {
957 for (i = 0; i < timeout; i++) {
958 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
959 NISTC_AI_STATUS1_FIFO_E)
960 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
966 dev_err(dev->class_dev, "timed out\n");
967 dev_err(dev->class_dev,
968 "mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
969 mite_bytes_in_transit(devpriv->ai_mite_chan),
970 ni_stc_readw(dev, NISTC_AI_STATUS1_REG));
974 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
981 static void mite_handle_b_linkc(struct mite_struct *mite,
982 struct comedi_device *dev)
984 struct ni_private *devpriv = dev->private;
985 struct comedi_subdevice *s = dev->write_subdev;
988 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
989 if (devpriv->ao_mite_chan)
990 mite_sync_output_dma(devpriv->ao_mite_chan, s);
991 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
994 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
996 static const int timeout = 10000;
999 for (i = 0; i < timeout; i++) {
1000 unsigned short b_status;
1002 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
1003 if (b_status & NISTC_AO_STATUS1_FIFO_HF)
1005 /* if we poll too often, the pci bus activity seems
1006 to slow the dma transfer down */
1010 dev_err(dev->class_dev, "timed out waiting for dma load\n");
1019 static void ni_ao_fifo_load(struct comedi_device *dev,
1020 struct comedi_subdevice *s, int n)
1022 struct ni_private *devpriv = dev->private;
1027 for (i = 0; i < n; i++) {
1028 comedi_buf_read_samples(s, &d, 1);
1030 if (devpriv->is_6xxx) {
1031 packed_data = d & 0xffff;
1032 /* 6711 only has 16 bit wide ao fifo */
1033 if (!devpriv->is_6711) {
1034 comedi_buf_read_samples(s, &d, 1);
1036 packed_data |= (d << 16) & 0xffff0000;
1038 ni_writel(dev, packed_data, NI611X_AO_FIFO_DATA_REG);
1040 ni_writew(dev, d, NI_E_AO_FIFO_DATA_REG);
1046 * There's a small problem if the FIFO gets really low and we
1047 * don't have the data to fill it. Basically, if after we fill
1048 * the FIFO with all the data available, the FIFO is _still_
1049 * less than half full, we never clear the interrupt. If the
1050 * IRQ is in edge mode, we never get another interrupt, because
1051 * this one wasn't cleared. If in level mode, we get flooded
1052 * with interrupts that we can't fulfill, because nothing ever
1053 * gets put into the buffer.
1055 * This kind of situation is recoverable, but it is easier to
1056 * just pretend we had a FIFO underrun, since there is a good
1057 * chance it will happen anyway. This is _not_ the case for
1058 * RT code, as RT code might purposely be running close to the
1059 * metal. Needs to be fixed eventually.
1061 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1062 struct comedi_subdevice *s)
1064 const struct ni_board_struct *board = dev->board_ptr;
1065 unsigned int nbytes;
1066 unsigned int nsamples;
1068 nbytes = comedi_buf_read_n_available(s);
1070 s->async->events |= COMEDI_CB_OVERFLOW;
1074 nsamples = comedi_bytes_to_samples(s, nbytes);
1075 if (nsamples > board->ao_fifo_depth / 2)
1076 nsamples = board->ao_fifo_depth / 2;
1078 ni_ao_fifo_load(dev, s, nsamples);
1083 static int ni_ao_prep_fifo(struct comedi_device *dev,
1084 struct comedi_subdevice *s)
1086 const struct ni_board_struct *board = dev->board_ptr;
1087 struct ni_private *devpriv = dev->private;
1088 unsigned int nbytes;
1089 unsigned int nsamples;
1092 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
1093 if (devpriv->is_6xxx)
1094 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
1096 /* load some data */
1097 nbytes = comedi_buf_read_n_available(s);
1101 nsamples = comedi_bytes_to_samples(s, nbytes);
1102 if (nsamples > board->ao_fifo_depth)
1103 nsamples = board->ao_fifo_depth;
1105 ni_ao_fifo_load(dev, s, nsamples);
1110 static void ni_ai_fifo_read(struct comedi_device *dev,
1111 struct comedi_subdevice *s, int n)
1113 struct ni_private *devpriv = dev->private;
1114 struct comedi_async *async = s->async;
1116 unsigned short data;
1119 if (devpriv->is_611x) {
1120 for (i = 0; i < n / 2; i++) {
1121 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1122 /* This may get the hi/lo data in the wrong order */
1123 data = (dl >> 16) & 0xffff;
1124 comedi_buf_write_samples(s, &data, 1);
1126 comedi_buf_write_samples(s, &data, 1);
1128 /* Check if there's a single sample stuck in the FIFO */
1130 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1132 comedi_buf_write_samples(s, &data, 1);
1134 } else if (devpriv->is_6143) {
1135 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1136 for (i = 0; i < n / 2; i++) {
1137 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1139 data = (dl >> 16) & 0xffff;
1140 comedi_buf_write_samples(s, &data, 1);
1142 comedi_buf_write_samples(s, &data, 1);
1145 /* Assume there is a single sample stuck in the FIFO */
1146 /* Get stranded sample into FIFO */
1147 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1148 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1149 data = (dl >> 16) & 0xffff;
1150 comedi_buf_write_samples(s, &data, 1);
1153 if (n > sizeof(devpriv->ai_fifo_buffer) /
1154 sizeof(devpriv->ai_fifo_buffer[0])) {
1155 dev_err(dev->class_dev,
1156 "bug! ai_fifo_buffer too small\n");
1157 async->events |= COMEDI_CB_ERROR;
1160 for (i = 0; i < n; i++) {
1161 devpriv->ai_fifo_buffer[i] =
1162 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1164 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n);
1168 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1170 const struct ni_board_struct *board = dev->board_ptr;
1171 struct comedi_subdevice *s = dev->read_subdev;
1174 n = board->ai_fifo_depth / 2;
1176 ni_ai_fifo_read(dev, s, n);
1183 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1185 struct ni_private *devpriv = dev->private;
1186 struct comedi_subdevice *s = dev->read_subdev;
1188 unsigned short data;
1189 unsigned short fifo_empty;
1192 if (devpriv->is_611x) {
1193 while ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1194 NISTC_AI_STATUS1_FIFO_E) == 0) {
1195 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1197 /* This may get the hi/lo data in the wrong order */
1199 comedi_buf_write_samples(s, &data, 1);
1201 comedi_buf_write_samples(s, &data, 1);
1203 } else if (devpriv->is_6143) {
1205 while (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x04) {
1206 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1208 /* This may get the hi/lo data in the wrong order */
1210 comedi_buf_write_samples(s, &data, 1);
1212 comedi_buf_write_samples(s, &data, 1);
1215 /* Check if stranded sample is present */
1216 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1217 /* Get stranded sample into FIFO */
1218 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1219 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1220 data = (dl >> 16) & 0xffff;
1221 comedi_buf_write_samples(s, &data, 1);
1225 fifo_empty = ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1226 NISTC_AI_STATUS1_FIFO_E;
1227 while (fifo_empty == 0) {
1230 sizeof(devpriv->ai_fifo_buffer) /
1231 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1232 fifo_empty = ni_stc_readw(dev,
1233 NISTC_AI_STATUS1_REG) &
1234 NISTC_AI_STATUS1_FIFO_E;
1237 devpriv->ai_fifo_buffer[i] =
1238 ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
1240 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i);
1245 static void get_last_sample_611x(struct comedi_device *dev)
1247 struct ni_private *devpriv = dev->private;
1248 struct comedi_subdevice *s = dev->read_subdev;
1249 unsigned short data;
1252 if (!devpriv->is_611x)
1255 /* Check if there's a single sample stuck in the FIFO */
1256 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1257 dl = ni_readl(dev, NI611X_AI_FIFO_DATA_REG);
1259 comedi_buf_write_samples(s, &data, 1);
1263 static void get_last_sample_6143(struct comedi_device *dev)
1265 struct ni_private *devpriv = dev->private;
1266 struct comedi_subdevice *s = dev->read_subdev;
1267 unsigned short data;
1270 if (!devpriv->is_6143)
1273 /* Check if there's a single sample stuck in the FIFO */
1274 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) & 0x01) {
1275 /* Get stranded sample into FIFO */
1276 ni_writel(dev, 0x01, NI6143_AI_FIFO_CTRL_REG);
1277 dl = ni_readl(dev, NI6143_AI_FIFO_DATA_REG);
1279 /* This may get the hi/lo data in the wrong order */
1280 data = (dl >> 16) & 0xffff;
1281 comedi_buf_write_samples(s, &data, 1);
1285 static void shutdown_ai_command(struct comedi_device *dev)
1287 struct comedi_subdevice *s = dev->read_subdev;
1290 ni_ai_drain_dma(dev);
1292 ni_handle_fifo_dregs(dev);
1293 get_last_sample_611x(dev);
1294 get_last_sample_6143(dev);
1296 s->async->events |= COMEDI_CB_EOA;
1299 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
1301 struct ni_private *devpriv = dev->private;
1303 if (devpriv->aimode == AIMODE_SCAN) {
1305 static const int timeout = 10;
1308 for (i = 0; i < timeout; i++) {
1309 ni_sync_ai_dma(dev);
1310 if ((s->async->events & COMEDI_CB_EOS))
1315 ni_handle_fifo_dregs(dev);
1316 s->async->events |= COMEDI_CB_EOS;
1319 /* handle special case of single scan */
1320 if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)
1321 shutdown_ai_command(dev);
1324 static void handle_gpct_interrupt(struct comedi_device *dev,
1325 unsigned short counter_index)
1328 struct ni_private *devpriv = dev->private;
1329 struct comedi_subdevice *s;
1331 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1333 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1335 comedi_handle_events(dev, s);
1339 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1341 unsigned short ack = 0;
1343 if (a_status & NISTC_AI_STATUS1_SC_TC)
1344 ack |= NISTC_INTA_ACK_AI_SC_TC;
1345 if (a_status & NISTC_AI_STATUS1_START1)
1346 ack |= NISTC_INTA_ACK_AI_START1;
1347 if (a_status & NISTC_AI_STATUS1_START)
1348 ack |= NISTC_INTA_ACK_AI_START;
1349 if (a_status & NISTC_AI_STATUS1_STOP)
1350 ack |= NISTC_INTA_ACK_AI_STOP;
1352 ni_stc_writew(dev, ack, NISTC_INTA_ACK_REG);
1355 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1356 unsigned ai_mite_status)
1358 struct comedi_subdevice *s = dev->read_subdev;
1359 struct comedi_cmd *cmd = &s->async->cmd;
1361 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1362 if (s->type == COMEDI_SUBD_UNUSED)
1366 if (ai_mite_status & CHSR_LINKC)
1367 ni_sync_ai_dma(dev);
1369 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1370 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1371 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1372 dev_err(dev->class_dev,
1373 "unknown mite interrupt (ai_mite_status=%08x)\n",
1375 s->async->events |= COMEDI_CB_ERROR;
1376 /* disable_irq(dev->irq); */
1380 /* test for all uncommon interrupt events at the same time */
1381 if (status & (NISTC_AI_STATUS1_ERR |
1382 NISTC_AI_STATUS1_SC_TC | NISTC_AI_STATUS1_START1)) {
1383 if (status == 0xffff) {
1384 dev_err(dev->class_dev, "Card removed?\n");
1385 /* we probably aren't even running a command now,
1386 * so it's a good idea to be careful. */
1387 if (comedi_is_subdevice_running(s)) {
1388 s->async->events |= COMEDI_CB_ERROR;
1389 comedi_handle_events(dev, s);
1393 if (status & NISTC_AI_STATUS1_ERR) {
1394 dev_err(dev->class_dev, "ai error a_status=%04x\n",
1397 shutdown_ai_command(dev);
1399 s->async->events |= COMEDI_CB_ERROR;
1400 if (status & NISTC_AI_STATUS1_OVER)
1401 s->async->events |= COMEDI_CB_OVERFLOW;
1403 comedi_handle_events(dev, s);
1406 if (status & NISTC_AI_STATUS1_SC_TC) {
1407 if (cmd->stop_src == TRIG_COUNT)
1408 shutdown_ai_command(dev);
1412 if (status & NISTC_AI_STATUS1_FIFO_HF) {
1414 static const int timeout = 10;
1415 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1416 *fail to get the fifo less than half full, so loop to be sure.*/
1417 for (i = 0; i < timeout; ++i) {
1418 ni_handle_fifo_half_full(dev);
1419 if ((ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1420 NISTC_AI_STATUS1_FIFO_HF) == 0)
1424 #endif /* !PCIDMA */
1426 if (status & NISTC_AI_STATUS1_STOP)
1427 ni_handle_eos(dev, s);
1429 comedi_handle_events(dev, s);
1432 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1434 unsigned short ack = 0;
1436 if (b_status & NISTC_AO_STATUS1_BC_TC)
1437 ack |= NISTC_INTB_ACK_AO_BC_TC;
1438 if (b_status & NISTC_AO_STATUS1_OVERRUN)
1439 ack |= NISTC_INTB_ACK_AO_ERR;
1440 if (b_status & NISTC_AO_STATUS1_START)
1441 ack |= NISTC_INTB_ACK_AO_START;
1442 if (b_status & NISTC_AO_STATUS1_START1)
1443 ack |= NISTC_INTB_ACK_AO_START1;
1444 if (b_status & NISTC_AO_STATUS1_UC_TC)
1445 ack |= NISTC_INTB_ACK_AO_UC_TC;
1446 if (b_status & NISTC_AO_STATUS1_UI2_TC)
1447 ack |= NISTC_INTB_ACK_AO_UI2_TC;
1448 if (b_status & NISTC_AO_STATUS1_UPDATE)
1449 ack |= NISTC_INTB_ACK_AO_UPDATE;
1451 ni_stc_writew(dev, ack, NISTC_INTB_ACK_REG);
1454 static void handle_b_interrupt(struct comedi_device *dev,
1455 unsigned short b_status, unsigned ao_mite_status)
1457 struct comedi_subdevice *s = dev->write_subdev;
1458 /* unsigned short ack=0; */
1461 /* Currently, mite.c requires us to handle LINKC */
1462 if (ao_mite_status & CHSR_LINKC) {
1463 struct ni_private *devpriv = dev->private;
1465 mite_handle_b_linkc(devpriv->mite, dev);
1468 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1469 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1470 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1471 dev_err(dev->class_dev,
1472 "unknown mite interrupt (ao_mite_status=%08x)\n",
1474 s->async->events |= COMEDI_CB_ERROR;
1478 if (b_status == 0xffff)
1480 if (b_status & NISTC_AO_STATUS1_OVERRUN) {
1481 dev_err(dev->class_dev,
1482 "AO FIFO underrun status=0x%04x status2=0x%04x\n",
1483 b_status, ni_stc_readw(dev, NISTC_AO_STATUS2_REG));
1484 s->async->events |= COMEDI_CB_OVERFLOW;
1487 if (b_status & NISTC_AO_STATUS1_BC_TC)
1488 s->async->events |= COMEDI_CB_EOA;
1491 if (b_status & NISTC_AO_STATUS1_FIFO_REQ) {
1494 ret = ni_ao_fifo_half_empty(dev, s);
1496 dev_err(dev->class_dev, "AO buffer underrun\n");
1497 ni_set_bits(dev, NISTC_INTB_ENA_REG,
1498 NISTC_INTB_ENA_AO_FIFO |
1499 NISTC_INTB_ENA_AO_ERR, 0);
1500 s->async->events |= COMEDI_CB_OVERFLOW;
1505 comedi_handle_events(dev, s);
1508 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1509 void *data, unsigned int num_bytes,
1510 unsigned int chan_index)
1512 struct ni_private *devpriv = dev->private;
1513 struct comedi_async *async = s->async;
1514 struct comedi_cmd *cmd = &async->cmd;
1515 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
1516 unsigned short *array = data;
1517 unsigned int *larray = data;
1520 for (i = 0; i < nsamples; i++) {
1522 if (s->subdev_flags & SDF_LSAMPL)
1523 larray[i] = le32_to_cpu(larray[i]);
1525 array[i] = le16_to_cpu(array[i]);
1527 if (s->subdev_flags & SDF_LSAMPL)
1528 larray[i] += devpriv->ai_offset[chan_index];
1530 array[i] += devpriv->ai_offset[chan_index];
1532 chan_index %= cmd->chanlist_len;
1538 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1540 struct ni_private *devpriv = dev->private;
1541 struct comedi_subdevice *s = dev->read_subdev;
1543 unsigned long flags;
1545 retval = ni_request_ai_mite_channel(dev);
1549 /* write alloc the entire buffer */
1550 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
1552 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1553 if (!devpriv->ai_mite_chan) {
1554 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1558 if (devpriv->is_611x || devpriv->is_6143)
1559 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1560 else if (devpriv->is_628x)
1561 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1563 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1566 mite_dma_arm(devpriv->ai_mite_chan);
1567 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1572 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1574 struct ni_private *devpriv = dev->private;
1575 struct comedi_subdevice *s = dev->write_subdev;
1577 unsigned long flags;
1579 retval = ni_request_ao_mite_channel(dev);
1583 /* read alloc the entire buffer */
1584 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
1586 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1587 if (devpriv->ao_mite_chan) {
1588 if (devpriv->is_611x || devpriv->is_6713) {
1589 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1591 /* doing 32 instead of 16 bit wide transfers from memory
1592 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1593 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1595 mite_dma_arm(devpriv->ao_mite_chan);
1599 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1607 used for both cancel ioctl and board initialization
1609 this is pretty harsh for a cancel, but it works...
1612 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1614 struct ni_private *devpriv = dev->private;
1615 unsigned ai_personal;
1616 unsigned ai_out_ctrl;
1618 ni_release_ai_mite_channel(dev);
1619 /* ai configuration */
1620 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START | NISTC_RESET_AI,
1623 ni_set_bits(dev, NISTC_INTA_ENA_REG, NISTC_INTA_ENA_AI_MASK, 0);
1625 ni_clear_ai_fifo(dev);
1627 if (!devpriv->is_6143)
1628 ni_writeb(dev, NI_E_MISC_CMD_EXT_ATRIG, NI_E_MISC_CMD_REG);
1630 ni_stc_writew(dev, NISTC_AI_CMD1_DISARM, NISTC_AI_CMD1_REG);
1631 ni_stc_writew(dev, NISTC_AI_MODE1_START_STOP |
1633 /*| NISTC_AI_MODE1_TRIGGER_ONCE */,
1634 NISTC_AI_MODE1_REG);
1635 ni_stc_writew(dev, 0, NISTC_AI_MODE2_REG);
1636 /* generate FIFO interrupts on non-empty */
1637 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
1638 NISTC_AI_MODE3_REG);
1640 ai_personal = NISTC_AI_PERSONAL_SHIFTIN_PW |
1641 NISTC_AI_PERSONAL_SOC_POLARITY |
1642 NISTC_AI_PERSONAL_LOCALMUX_CLK_PW;
1643 ai_out_ctrl = NISTC_AI_OUT_CTRL_SCAN_IN_PROG_SEL(3) |
1644 NISTC_AI_OUT_CTRL_EXTMUX_CLK_SEL(0) |
1645 NISTC_AI_OUT_CTRL_LOCALMUX_CLK_SEL(2) |
1646 NISTC_AI_OUT_CTRL_SC_TC_SEL(3);
1647 if (devpriv->is_611x) {
1648 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1649 } else if (devpriv->is_6143) {
1650 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1652 ai_personal |= NISTC_AI_PERSONAL_CONVERT_PW;
1653 if (devpriv->is_622x)
1654 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_HIGH;
1656 ai_out_ctrl |= NISTC_AI_OUT_CTRL_CONVERT_LOW;
1658 ni_stc_writew(dev, ai_personal, NISTC_AI_PERSONAL_REG);
1659 ni_stc_writew(dev, ai_out_ctrl, NISTC_AI_OUT_CTRL_REG);
1661 /* the following registers should not be changed, because there
1662 * are no backup registers in devpriv. If you want to change
1663 * any of these, add a backup register and other appropriate code:
1664 * NISTC_AI_MODE1_REG
1665 * NISTC_AI_MODE3_REG
1666 * NISTC_AI_PERSONAL_REG
1667 * NISTC_AI_OUT_CTRL_REG
1670 /* clear interrupts */
1671 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
1673 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
1678 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1680 unsigned long flags;
1683 /* lock to avoid race with interrupt handler */
1684 spin_lock_irqsave(&dev->spinlock, flags);
1686 ni_handle_fifo_dregs(dev);
1688 ni_sync_ai_dma(dev);
1690 count = comedi_buf_n_bytes_ready(s);
1691 spin_unlock_irqrestore(&dev->spinlock, flags);
1696 static void ni_prime_channelgain_list(struct comedi_device *dev)
1700 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE, NISTC_AI_CMD1_REG);
1701 for (i = 0; i < NI_TIMEOUT; ++i) {
1702 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1703 NISTC_AI_STATUS1_FIFO_E)) {
1704 ni_stc_writew(dev, 1, NISTC_ADC_FIFO_CLR_REG);
1709 dev_err(dev->class_dev, "timeout loading channel/gain list\n");
1712 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1713 unsigned int n_chan,
1716 const struct ni_board_struct *board = dev->board_ptr;
1717 struct ni_private *devpriv = dev->private;
1718 unsigned int chan, range, aref;
1720 unsigned int dither;
1721 unsigned range_code;
1723 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1725 if ((list[0] & CR_ALT_SOURCE)) {
1726 unsigned bypass_bits;
1728 chan = CR_CHAN(list[0]);
1729 range = CR_RANGE(list[0]);
1730 range_code = ni_gainlkup[board->gainlkup][range];
1731 dither = (list[0] & CR_ALT_FILTER) != 0;
1732 bypass_bits = NI_M_CFG_BYPASS_FIFO |
1733 NI_M_CFG_BYPASS_AI_CHAN(chan) |
1734 NI_M_CFG_BYPASS_AI_GAIN(range_code) |
1735 devpriv->ai_calib_source;
1737 bypass_bits |= NI_M_CFG_BYPASS_AI_DITHER;
1738 /* don't use 2's complement encoding */
1739 bypass_bits |= NI_M_CFG_BYPASS_AI_POLARITY;
1740 ni_writel(dev, bypass_bits, NI_M_CFG_BYPASS_FIFO_REG);
1742 ni_writel(dev, 0, NI_M_CFG_BYPASS_FIFO_REG);
1744 for (i = 0; i < n_chan; i++) {
1745 unsigned config_bits = 0;
1747 chan = CR_CHAN(list[i]);
1748 aref = CR_AREF(list[i]);
1749 range = CR_RANGE(list[i]);
1750 dither = (list[i] & CR_ALT_FILTER) != 0;
1752 range_code = ni_gainlkup[board->gainlkup][range];
1753 devpriv->ai_offset[i] = 0;
1756 config_bits |= NI_M_AI_CFG_CHAN_TYPE_DIFF;
1759 config_bits |= NI_M_AI_CFG_CHAN_TYPE_COMMON;
1762 config_bits |= NI_M_AI_CFG_CHAN_TYPE_GROUND;
1767 config_bits |= NI_M_AI_CFG_CHAN_SEL(chan);
1768 config_bits |= NI_M_AI_CFG_BANK_SEL(chan);
1769 config_bits |= NI_M_AI_CFG_GAIN(range_code);
1770 if (i == n_chan - 1)
1771 config_bits |= NI_M_AI_CFG_LAST_CHAN;
1773 config_bits |= NI_M_AI_CFG_DITHER;
1774 /* don't use 2's complement encoding */
1775 config_bits |= NI_M_AI_CFG_POLARITY;
1776 ni_writew(dev, config_bits, NI_M_AI_CFG_FIFO_DATA_REG);
1778 ni_prime_channelgain_list(dev);
1782 * Notes on the 6110 and 6111:
1783 * These boards a slightly different than the rest of the series, since
1784 * they have multiple A/D converters.
1785 * From the driver side, the configuration memory is a
1787 * Configuration Memory Low:
1789 * bit 8: unipolar/bipolar (should be 0 for bipolar)
1790 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1791 * 1001 gain=0.1 (+/- 50)
1800 * Configuration Memory High:
1801 * bits 12-14: Channel Type
1802 * 001 for differential
1803 * 000 for calibration
1804 * bit 11: coupling (this is not currently handled)
1808 * valid channels are 0-3
1810 static void ni_load_channelgain_list(struct comedi_device *dev,
1811 struct comedi_subdevice *s,
1812 unsigned int n_chan, unsigned int *list)
1814 const struct ni_board_struct *board = dev->board_ptr;
1815 struct ni_private *devpriv = dev->private;
1816 unsigned int offset = (s->maxdata + 1) >> 1;
1817 unsigned int chan, range, aref;
1819 unsigned int hi, lo;
1820 unsigned int dither;
1822 if (devpriv->is_m_series) {
1823 ni_m_series_load_channelgain_list(dev, n_chan, list);
1826 if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) {
1827 if (devpriv->changain_state
1828 && devpriv->changain_spec == list[0]) {
1832 devpriv->changain_state = 1;
1833 devpriv->changain_spec = list[0];
1835 devpriv->changain_state = 0;
1838 ni_stc_writew(dev, 1, NISTC_CFG_MEM_CLR_REG);
1840 /* Set up Calibration mode if required */
1841 if (devpriv->is_6143) {
1842 if ((list[0] & CR_ALT_SOURCE)
1843 && !devpriv->ai_calib_source_enabled) {
1844 /* Strobe Relay enable bit */
1845 ni_writew(dev, devpriv->ai_calib_source |
1846 NI6143_CALIB_CHAN_RELAY_ON,
1847 NI6143_CALIB_CHAN_REG);
1848 ni_writew(dev, devpriv->ai_calib_source,
1849 NI6143_CALIB_CHAN_REG);
1850 devpriv->ai_calib_source_enabled = 1;
1851 msleep_interruptible(100); /* Allow relays to change */
1852 } else if (!(list[0] & CR_ALT_SOURCE)
1853 && devpriv->ai_calib_source_enabled) {
1854 /* Strobe Relay disable bit */
1855 ni_writew(dev, devpriv->ai_calib_source |
1856 NI6143_CALIB_CHAN_RELAY_OFF,
1857 NI6143_CALIB_CHAN_REG);
1858 ni_writew(dev, devpriv->ai_calib_source,
1859 NI6143_CALIB_CHAN_REG);
1860 devpriv->ai_calib_source_enabled = 0;
1861 msleep_interruptible(100); /* Allow relays to change */
1865 for (i = 0; i < n_chan; i++) {
1866 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE))
1867 chan = devpriv->ai_calib_source;
1869 chan = CR_CHAN(list[i]);
1870 aref = CR_AREF(list[i]);
1871 range = CR_RANGE(list[i]);
1872 dither = (list[i] & CR_ALT_FILTER) != 0;
1874 /* fix the external/internal range differences */
1875 range = ni_gainlkup[board->gainlkup][range];
1876 if (devpriv->is_611x)
1877 devpriv->ai_offset[i] = offset;
1879 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
1882 if ((list[i] & CR_ALT_SOURCE)) {
1883 if (devpriv->is_611x)
1884 ni_writew(dev, CR_CHAN(list[i]) & 0x0003,
1885 NI611X_CALIB_CHAN_SEL_REG);
1887 if (devpriv->is_611x)
1889 else if (devpriv->is_6143)
1893 hi |= NI_E_AI_CFG_HI_TYPE_DIFF;
1896 hi |= NI_E_AI_CFG_HI_TYPE_COMMON;
1899 hi |= NI_E_AI_CFG_HI_TYPE_GROUND;
1905 hi |= NI_E_AI_CFG_HI_CHAN(chan);
1907 ni_writew(dev, hi, NI_E_AI_CFG_HI_REG);
1909 if (!devpriv->is_6143) {
1910 lo = NI_E_AI_CFG_LO_GAIN(range);
1912 if (i == n_chan - 1)
1913 lo |= NI_E_AI_CFG_LO_LAST_CHAN;
1915 lo |= NI_E_AI_CFG_LO_DITHER;
1917 ni_writew(dev, lo, NI_E_AI_CFG_LO_REG);
1921 /* prime the channel/gain list */
1922 if (!devpriv->is_611x && !devpriv->is_6143)
1923 ni_prime_channelgain_list(dev);
1926 static int ni_ai_insn_read(struct comedi_device *dev,
1927 struct comedi_subdevice *s,
1928 struct comedi_insn *insn,
1931 struct ni_private *devpriv = dev->private;
1932 unsigned int mask = (s->maxdata + 1) >> 1;
1938 ni_load_channelgain_list(dev, s, 1, &insn->chanspec);
1940 ni_clear_ai_fifo(dev);
1942 signbits = devpriv->ai_offset[0];
1943 if (devpriv->is_611x) {
1944 for (n = 0; n < num_adc_stages_611x; n++) {
1945 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1949 for (n = 0; n < insn->n; n++) {
1950 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1952 /* The 611x has screwy 32-bit FIFOs. */
1954 for (i = 0; i < NI_TIMEOUT; i++) {
1955 if (ni_readb(dev, NI_E_STATUS_REG) & 0x80) {
1957 NI611X_AI_FIFO_DATA_REG);
1962 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
1963 NISTC_AI_STATUS1_FIFO_E)) {
1965 NI611X_AI_FIFO_DATA_REG);
1970 if (i == NI_TIMEOUT) {
1971 dev_err(dev->class_dev, "timeout\n");
1977 } else if (devpriv->is_6143) {
1978 for (n = 0; n < insn->n; n++) {
1979 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
1982 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1984 for (i = 0; i < NI_TIMEOUT; i++) {
1985 if (ni_readl(dev, NI6143_AI_FIFO_STATUS_REG) &
1987 /* Get stranded sample into FIFO */
1988 ni_writel(dev, 0x01,
1989 NI6143_AI_FIFO_CTRL_REG);
1991 NI6143_AI_FIFO_DATA_REG);
1995 if (i == NI_TIMEOUT) {
1996 dev_err(dev->class_dev, "timeout\n");
1999 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
2002 for (n = 0; n < insn->n; n++) {
2003 ni_stc_writew(dev, NISTC_AI_CMD1_CONVERT_PULSE,
2005 for (i = 0; i < NI_TIMEOUT; i++) {
2006 if (!(ni_stc_readw(dev, NISTC_AI_STATUS1_REG) &
2007 NISTC_AI_STATUS1_FIFO_E))
2010 if (i == NI_TIMEOUT) {
2011 dev_err(dev->class_dev, "timeout\n");
2014 if (devpriv->is_m_series) {
2015 dl = ni_readl(dev, NI_M_AI_FIFO_DATA_REG);
2019 d = ni_readw(dev, NI_E_AI_FIFO_DATA_REG);
2020 d += signbits; /* subtle: needs to be short addition */
2028 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2031 struct ni_private *devpriv = dev->private;
2034 switch (flags & CMDF_ROUND_MASK) {
2035 case CMDF_ROUND_NEAREST:
2037 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2039 case CMDF_ROUND_DOWN:
2040 divider = (nanosec) / devpriv->clock_ns;
2043 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2049 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2051 struct ni_private *devpriv = dev->private;
2053 return devpriv->clock_ns * (timer + 1);
2056 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2057 unsigned num_channels)
2059 const struct ni_board_struct *board = dev->board_ptr;
2060 struct ni_private *devpriv = dev->private;
2062 /* simultaneously-sampled inputs */
2063 if (devpriv->is_611x || devpriv->is_6143)
2064 return board->ai_speed;
2066 /* multiplexed inputs */
2067 return board->ai_speed * num_channels;
2070 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2071 struct comedi_cmd *cmd)
2073 const struct ni_board_struct *board = dev->board_ptr;
2074 struct ni_private *devpriv = dev->private;
2077 unsigned int sources;
2079 /* Step 1 : check if triggers are trivially valid */
2081 err |= comedi_check_trigger_src(&cmd->start_src,
2082 TRIG_NOW | TRIG_INT | TRIG_EXT);
2083 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2084 TRIG_TIMER | TRIG_EXT);
2086 sources = TRIG_TIMER | TRIG_EXT;
2087 if (devpriv->is_611x || devpriv->is_6143)
2088 sources |= TRIG_NOW;
2089 err |= comedi_check_trigger_src(&cmd->convert_src, sources);
2091 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2092 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2097 /* Step 2a : make sure trigger sources are unique */
2099 err |= comedi_check_trigger_is_unique(cmd->start_src);
2100 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2101 err |= comedi_check_trigger_is_unique(cmd->convert_src);
2102 err |= comedi_check_trigger_is_unique(cmd->stop_src);
2104 /* Step 2b : and mutually compatible */
2109 /* Step 3: check if arguments are trivially valid */
2111 switch (cmd->start_src) {
2114 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2117 tmp = CR_CHAN(cmd->start_arg);
2121 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2122 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
2126 if (cmd->scan_begin_src == TRIG_TIMER) {
2127 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2128 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2129 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2132 } else if (cmd->scan_begin_src == TRIG_EXT) {
2133 /* external trigger */
2134 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2138 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2139 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2140 } else { /* TRIG_OTHER */
2141 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2144 if (cmd->convert_src == TRIG_TIMER) {
2145 if (devpriv->is_611x || devpriv->is_6143) {
2146 err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2149 err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2151 err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2155 } else if (cmd->convert_src == TRIG_EXT) {
2156 /* external trigger */
2157 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2161 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2162 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, tmp);
2163 } else if (cmd->convert_src == TRIG_NOW) {
2164 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
2167 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2170 if (cmd->stop_src == TRIG_COUNT) {
2171 unsigned int max_count = 0x01000000;
2173 if (devpriv->is_611x)
2174 max_count -= num_adc_stages_611x;
2175 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count);
2176 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2179 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2185 /* step 4: fix up any arguments */
2187 if (cmd->scan_begin_src == TRIG_TIMER) {
2188 tmp = cmd->scan_begin_arg;
2189 cmd->scan_begin_arg =
2190 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2191 cmd->scan_begin_arg,
2193 if (tmp != cmd->scan_begin_arg)
2196 if (cmd->convert_src == TRIG_TIMER) {
2197 if (!devpriv->is_611x && !devpriv->is_6143) {
2198 tmp = cmd->convert_arg;
2200 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2203 if (tmp != cmd->convert_arg)
2205 if (cmd->scan_begin_src == TRIG_TIMER &&
2206 cmd->scan_begin_arg <
2207 cmd->convert_arg * cmd->scan_end_arg) {
2208 cmd->scan_begin_arg =
2209 cmd->convert_arg * cmd->scan_end_arg;
2221 static int ni_ai_inttrig(struct comedi_device *dev,
2222 struct comedi_subdevice *s,
2223 unsigned int trig_num)
2225 struct ni_private *devpriv = dev->private;
2226 struct comedi_cmd *cmd = &s->async->cmd;
2228 if (trig_num != cmd->start_arg)
2231 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2,
2233 s->async->inttrig = NULL;
2238 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2240 struct ni_private *devpriv = dev->private;
2241 const struct comedi_cmd *cmd = &s->async->cmd;
2243 int mode1 = 0; /* mode1 is needed for both stop and convert */
2245 int start_stop_select = 0;
2246 unsigned int stop_count;
2247 int interrupt_a_enable = 0;
2250 if (dev->irq == 0) {
2251 dev_err(dev->class_dev, "cannot run command without an irq\n");
2254 ni_clear_ai_fifo(dev);
2256 ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist);
2258 /* start configuration */
2259 ni_stc_writew(dev, NISTC_RESET_AI_CFG_START, NISTC_RESET_REG);
2261 /* disable analog triggering for now, since it
2262 * interferes with the use of pfi0 */
2263 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
2264 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
2266 ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
2267 switch (cmd->start_src) {
2270 ai_trig |= NISTC_AI_TRIG_START1_EDGE |
2271 NISTC_AI_TRIG_START1_SEL(0);
2274 ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) +
2277 if (cmd->start_arg & CR_INVERT)
2278 ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
2279 if (cmd->start_arg & CR_EDGE)
2280 ai_trig |= NISTC_AI_TRIG_START1_EDGE;
2283 ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
2285 mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
2286 mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
2287 mode2 &= ~NISTC_AI_MODE2_SC_RELOAD_MODE;
2288 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2290 if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) {
2292 start_stop_select |= NISTC_AI_STOP_POLARITY |
2293 NISTC_AI_STOP_SEL(31) |
2296 /* ai configuration memory */
2297 start_stop_select |= NISTC_AI_STOP_SEL(19);
2299 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2301 devpriv->ai_cmd2 = 0;
2302 switch (cmd->stop_src) {
2304 stop_count = cmd->stop_arg - 1;
2306 if (devpriv->is_611x) {
2307 /* have to take 3 stage adc pipeline into account */
2308 stop_count += num_adc_stages_611x;
2310 /* stage number of scans */
2311 ni_stc_writel(dev, stop_count, NISTC_AI_SC_LOADA_REG);
2313 mode1 |= NISTC_AI_MODE1_START_STOP |
2314 NISTC_AI_MODE1_RSVD |
2315 NISTC_AI_MODE1_TRIGGER_ONCE;
2316 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2317 /* load SC (Scan Count) */
2318 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2320 if (stop_count == 0) {
2321 devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS;
2322 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2323 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2324 if (cmd->chanlist_len > 1)
2325 start_stop_select |= NISTC_AI_STOP_POLARITY |
2330 /* stage number of scans */
2331 ni_stc_writel(dev, 0, NISTC_AI_SC_LOADA_REG);
2333 mode1 |= NISTC_AI_MODE1_START_STOP |
2334 NISTC_AI_MODE1_RSVD |
2335 NISTC_AI_MODE1_CONTINUOUS;
2336 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2338 /* load SC (Scan Count) */
2339 ni_stc_writew(dev, NISTC_AI_CMD1_SC_LOAD, NISTC_AI_CMD1_REG);
2343 switch (cmd->scan_begin_src) {
2346 * stop bits for non 611x boards
2347 * NISTC_AI_MODE3_SI_TRIG_DELAY=0
2348 * NISTC_AI_MODE2_PRE_TRIGGER=0
2349 * NISTC_AI_START_STOP_REG:
2350 * NISTC_AI_START_POLARITY=0 (?) rising edge
2351 * NISTC_AI_START_EDGE=1 edge triggered
2352 * NISTC_AI_START_SYNC=1 (?)
2353 * NISTC_AI_START_SEL=0 SI_TC
2354 * NISTC_AI_STOP_POLARITY=0 rising edge
2355 * NISTC_AI_STOP_EDGE=0 level
2356 * NISTC_AI_STOP_SYNC=1
2357 * NISTC_AI_STOP_SEL=19 external pin (configuration mem)
2359 start_stop_select |= NISTC_AI_START_EDGE | NISTC_AI_START_SYNC;
2360 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2362 mode2 &= ~NISTC_AI_MODE2_SI_INIT_LOAD_SRC; /* A */
2363 mode2 |= NISTC_AI_MODE2_SI_RELOAD_MODE(0);
2364 /* mode2 |= NISTC_AI_MODE2_SC_RELOAD_MODE; */
2365 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2368 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2369 CMDF_ROUND_NEAREST);
2370 ni_stc_writel(dev, timer, NISTC_AI_SI_LOADA_REG);
2371 ni_stc_writew(dev, NISTC_AI_CMD1_SI_LOAD, NISTC_AI_CMD1_REG);
2374 if (cmd->scan_begin_arg & CR_EDGE)
2375 start_stop_select |= NISTC_AI_START_EDGE;
2376 if (cmd->scan_begin_arg & CR_INVERT) /* falling edge */
2377 start_stop_select |= NISTC_AI_START_POLARITY;
2378 if (cmd->scan_begin_src != cmd->convert_src ||
2379 (cmd->scan_begin_arg & ~CR_EDGE) !=
2380 (cmd->convert_arg & ~CR_EDGE))
2381 start_stop_select |= NISTC_AI_START_SYNC;
2382 start_stop_select |=
2383 NISTC_AI_START_SEL(1 + CR_CHAN(cmd->scan_begin_arg));
2384 ni_stc_writew(dev, start_stop_select, NISTC_AI_START_STOP_REG);
2388 switch (cmd->convert_src) {
2391 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2394 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2395 CMDF_ROUND_NEAREST);
2396 /* 0,0 does not work */
2397 ni_stc_writew(dev, 1, NISTC_AI_SI2_LOADA_REG);
2398 ni_stc_writew(dev, timer, NISTC_AI_SI2_LOADB_REG);
2400 mode2 &= ~NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* A */
2401 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2402 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2404 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_LOAD, NISTC_AI_CMD1_REG);
2406 mode2 |= NISTC_AI_MODE2_SI2_INIT_LOAD_SRC; /* B */
2407 mode2 |= NISTC_AI_MODE2_SI2_RELOAD_MODE; /* alternate */
2408 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2411 mode1 |= NISTC_AI_MODE1_CONVERT_SRC(1 + cmd->convert_arg);
2412 if ((cmd->convert_arg & CR_INVERT) == 0)
2413 mode1 |= NISTC_AI_MODE1_CONVERT_POLARITY;
2414 ni_stc_writew(dev, mode1, NISTC_AI_MODE1_REG);
2416 mode2 |= NISTC_AI_MODE2_SC_GATE_ENA |
2417 NISTC_AI_MODE2_START_STOP_GATE_ENA;
2418 ni_stc_writew(dev, mode2, NISTC_AI_MODE2_REG);
2424 /* interrupt on FIFO, errors, SC_TC */
2425 interrupt_a_enable |= NISTC_INTA_ENA_AI_ERR |
2426 NISTC_INTA_ENA_AI_SC_TC;
2429 interrupt_a_enable |= NISTC_INTA_ENA_AI_FIFO;
2432 if ((cmd->flags & CMDF_WAKE_EOS) ||
2433 (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) {
2434 /* wake on end-of-scan */
2435 devpriv->aimode = AIMODE_SCAN;
2437 devpriv->aimode = AIMODE_HALF_FULL;
2440 switch (devpriv->aimode) {
2441 case AIMODE_HALF_FULL:
2442 /*generate FIFO interrupts and DMA requests on half-full */
2444 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF_E,
2445 NISTC_AI_MODE3_REG);
2447 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2448 NISTC_AI_MODE3_REG);
2452 /*generate FIFO interrupts on non-empty */
2453 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2454 NISTC_AI_MODE3_REG);
2458 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_NE,
2459 NISTC_AI_MODE3_REG);
2461 ni_stc_writew(dev, NISTC_AI_MODE3_FIFO_MODE_HF,
2462 NISTC_AI_MODE3_REG);
2464 interrupt_a_enable |= NISTC_INTA_ENA_AI_STOP;
2470 /* clear interrupts */
2471 ni_stc_writew(dev, NISTC_INTA_ACK_AI_ALL, NISTC_INTA_ACK_REG);
2473 ni_set_bits(dev, NISTC_INTA_ENA_REG, interrupt_a_enable, 1);
2475 /* interrupt on nothing */
2476 ni_set_bits(dev, NISTC_INTA_ENA_REG, ~0, 0);
2478 /* XXX start polling if necessary */
2481 /* end configuration */
2482 ni_stc_writew(dev, NISTC_RESET_AI_CFG_END, NISTC_RESET_REG);
2484 switch (cmd->scan_begin_src) {
2486 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2487 NISTC_AI_CMD1_SI_ARM |
2488 NISTC_AI_CMD1_DIV_ARM |
2489 NISTC_AI_CMD1_SC_ARM,
2493 ni_stc_writew(dev, NISTC_AI_CMD1_SI2_ARM |
2494 NISTC_AI_CMD1_SI_ARM | /* XXX ? */
2495 NISTC_AI_CMD1_DIV_ARM |
2496 NISTC_AI_CMD1_SC_ARM,
2503 int retval = ni_ai_setup_MITE_dma(dev);
2510 if (cmd->start_src == TRIG_NOW) {
2511 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE |
2514 s->async->inttrig = NULL;
2515 } else if (cmd->start_src == TRIG_EXT) {
2516 s->async->inttrig = NULL;
2517 } else { /* TRIG_INT */
2518 s->async->inttrig = ni_ai_inttrig;
2524 static int ni_ai_insn_config(struct comedi_device *dev,
2525 struct comedi_subdevice *s,
2526 struct comedi_insn *insn, unsigned int *data)
2528 struct ni_private *devpriv = dev->private;
2534 case INSN_CONFIG_ALT_SOURCE:
2535 if (devpriv->is_m_series) {
2536 if (data[1] & ~NI_M_CFG_BYPASS_AI_CAL_MASK)
2538 devpriv->ai_calib_source = data[1];
2539 } else if (devpriv->is_6143) {
2540 unsigned int calib_source;
2542 calib_source = data[1] & 0xf;
2544 devpriv->ai_calib_source = calib_source;
2545 ni_writew(dev, calib_source, NI6143_CALIB_CHAN_REG);
2547 unsigned int calib_source;
2548 unsigned int calib_source_adjust;
2550 calib_source = data[1] & 0xf;
2551 calib_source_adjust = (data[1] >> 4) & 0xff;
2553 if (calib_source >= 8)
2555 devpriv->ai_calib_source = calib_source;
2556 if (devpriv->is_611x) {
2557 ni_writeb(dev, calib_source_adjust,
2558 NI611X_CAL_GAIN_SEL_REG);
2569 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2570 void *data, unsigned int num_bytes,
2571 unsigned int chan_index)
2573 struct comedi_cmd *cmd = &s->async->cmd;
2574 unsigned int nsamples = comedi_bytes_to_samples(s, num_bytes);
2575 unsigned short *array = data;
2578 for (i = 0; i < nsamples; i++) {
2579 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]);
2580 unsigned short val = array[i];
2583 * Munge data from unsigned to two's complement for
2586 if (comedi_range_is_bipolar(s, range))
2587 val = comedi_offset_munge(s, val);
2589 val = cpu_to_le16(val);
2594 chan_index %= cmd->chanlist_len;
2598 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2599 struct comedi_subdevice *s,
2600 unsigned int chanspec[],
2601 unsigned int n_chans, int timed)
2603 struct ni_private *devpriv = dev->private;
2611 for (i = 0; i < s->n_chan; ++i) {
2612 devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED;
2613 ni_writeb(dev, devpriv->ao_conf[i],
2614 NI_M_AO_CFG_BANK_REG(i));
2615 ni_writeb(dev, 0xf, NI_M_AO_WAVEFORM_ORDER_REG(i));
2618 for (i = 0; i < n_chans; i++) {
2619 const struct comedi_krange *krange;
2621 chan = CR_CHAN(chanspec[i]);
2622 range = CR_RANGE(chanspec[i]);
2623 krange = s->range_table->range + range;
2626 switch (krange->max - krange->min) {
2628 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2629 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2632 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2633 ni_writeb(dev, 0, NI_M_AO_REF_ATTENUATION_REG(chan));
2636 conf |= NI_M_AO_CFG_BANK_REF_INT_10V;
2637 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2638 NI_M_AO_REF_ATTENUATION_REG(chan));
2641 conf |= NI_M_AO_CFG_BANK_REF_INT_5V;
2642 ni_writeb(dev, NI_M_AO_REF_ATTENUATION_X5,
2643 NI_M_AO_REF_ATTENUATION_REG(chan));
2646 dev_err(dev->class_dev,
2647 "bug! unhandled ao reference voltage\n");
2650 switch (krange->max + krange->min) {
2652 conf |= NI_M_AO_CFG_BANK_OFFSET_0V;
2655 conf |= NI_M_AO_CFG_BANK_OFFSET_5V;
2658 dev_err(dev->class_dev,
2659 "bug! unhandled ao offset voltage\n");
2663 conf |= NI_M_AO_CFG_BANK_UPDATE_TIMED;
2664 ni_writeb(dev, conf, NI_M_AO_CFG_BANK_REG(chan));
2665 devpriv->ao_conf[chan] = conf;
2666 ni_writeb(dev, i, NI_M_AO_WAVEFORM_ORDER_REG(chan));
2671 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2672 struct comedi_subdevice *s,
2673 unsigned int chanspec[],
2674 unsigned int n_chans)
2676 struct ni_private *devpriv = dev->private;
2683 for (i = 0; i < n_chans; i++) {
2684 chan = CR_CHAN(chanspec[i]);
2685 range = CR_RANGE(chanspec[i]);
2686 conf = NI_E_AO_DACSEL(chan);
2688 if (comedi_range_is_bipolar(s, range)) {
2689 conf |= NI_E_AO_CFG_BIP;
2690 invert = (s->maxdata + 1) >> 1;
2694 if (comedi_range_is_external(s, range))
2695 conf |= NI_E_AO_EXT_REF;
2697 /* not all boards can deglitch, but this shouldn't hurt */
2698 if (chanspec[i] & CR_DEGLITCH)
2699 conf |= NI_E_AO_DEGLITCH;
2701 /* analog reference */
2702 /* AREF_OTHER connects AO ground to AI ground, i think */
2703 if (CR_AREF(chanspec[i]) == AREF_OTHER)
2704 conf |= NI_E_AO_GROUND_REF;
2706 ni_writew(dev, conf, NI_E_AO_CFG_REG);
2707 devpriv->ao_conf[chan] = conf;
2712 static int ni_ao_config_chanlist(struct comedi_device *dev,
2713 struct comedi_subdevice *s,
2714 unsigned int chanspec[], unsigned int n_chans,
2717 struct ni_private *devpriv = dev->private;
2719 if (devpriv->is_m_series)
2720 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
2723 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
2726 static int ni_ao_insn_write(struct comedi_device *dev,
2727 struct comedi_subdevice *s,
2728 struct comedi_insn *insn,
2731 struct ni_private *devpriv = dev->private;
2732 unsigned int chan = CR_CHAN(insn->chanspec);
2733 unsigned int range = CR_RANGE(insn->chanspec);
2737 if (devpriv->is_6xxx) {
2738 ni_ao_win_outw(dev, 1 << chan, NI671X_AO_IMMEDIATE_REG);
2740 reg = NI671X_DAC_DIRECT_DATA_REG(chan);
2741 } else if (devpriv->is_m_series) {
2742 reg = NI_M_DAC_DIRECT_DATA_REG(chan);
2744 reg = NI_E_DAC_DIRECT_DATA_REG(chan);
2747 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
2749 for (i = 0; i < insn->n; i++) {
2750 unsigned int val = data[i];
2752 s->readback[chan] = val;
2754 if (devpriv->is_6xxx) {
2756 * 6xxx boards have bipolar outputs, munge the
2757 * unsigned comedi values to 2's complement
2759 val = comedi_offset_munge(s, val);
2761 ni_ao_win_outw(dev, val, reg);
2762 } else if (devpriv->is_m_series) {
2764 * M-series boards use offset binary values for
2765 * bipolar and uinpolar outputs
2767 ni_writew(dev, val, reg);
2770 * Non-M series boards need two's complement values
2771 * for bipolar ranges.
2773 if (comedi_range_is_bipolar(s, range))
2774 val = comedi_offset_munge(s, val);
2776 ni_writew(dev, val, reg);
2783 static int ni_ao_insn_config(struct comedi_device *dev,
2784 struct comedi_subdevice *s,
2785 struct comedi_insn *insn, unsigned int *data)
2787 const struct ni_board_struct *board = dev->board_ptr;
2788 struct ni_private *devpriv = dev->private;
2789 unsigned int nbytes;
2792 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
2795 nbytes = comedi_samples_to_bytes(s,
2796 board->ao_fifo_depth);
2797 data[2] = 1 + nbytes;
2799 data[2] += devpriv->mite->fifo_size;
2815 static int ni_ao_inttrig(struct comedi_device *dev,
2816 struct comedi_subdevice *s,
2817 unsigned int trig_num)
2819 struct ni_private *devpriv = dev->private;
2820 struct comedi_cmd *cmd = &s->async->cmd;
2822 int interrupt_b_bits;
2824 static const int timeout = 1000;
2826 if (trig_num != cmd->start_arg)
2829 /* Null trig at beginning prevent ao start trigger from executing more than
2830 once per command (and doing things like trying to allocate the ao dma channel
2832 s->async->inttrig = NULL;
2834 ni_set_bits(dev, NISTC_INTB_ENA_REG,
2835 NISTC_INTB_ENA_AO_FIFO | NISTC_INTB_ENA_AO_ERR, 0);
2836 interrupt_b_bits = NISTC_INTB_ENA_AO_ERR;
2838 ni_stc_writew(dev, 1, NISTC_DAC_FIFO_CLR_REG);
2839 if (devpriv->is_6xxx)
2840 ni_ao_win_outl(dev, 0x6, NI611X_AO_FIFO_OFFSET_LOAD_REG);
2841 ret = ni_ao_setup_MITE_dma(dev);
2844 ret = ni_ao_wait_for_dma_load(dev);
2848 ret = ni_ao_prep_fifo(dev, s);
2852 interrupt_b_bits |= NISTC_INTB_ENA_AO_FIFO;
2855 ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE,
2856 NISTC_AO_MODE3_REG);
2857 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2858 /* wait for DACs to be loaded */
2859 for (i = 0; i < timeout; i++) {
2861 if ((ni_stc_readw(dev, NISTC_STATUS2_REG) &
2862 NISTC_STATUS2_AO_TMRDACWRS_IN_PROGRESS) == 0)
2866 dev_err(dev->class_dev,
2867 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear\n");
2871 * stc manual says we are need to clear error interrupt after
2872 * AO_TMRDACWRs_In_Progress_St clears
2874 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ERR, NISTC_INTB_ACK_REG);
2876 ni_set_bits(dev, NISTC_INTB_ENA_REG, interrupt_b_bits, 1);
2878 ni_stc_writew(dev, NISTC_AO_CMD1_UI_ARM |
2879 NISTC_AO_CMD1_UC_ARM |
2880 NISTC_AO_CMD1_BC_ARM |
2881 NISTC_AO_CMD1_DAC1_UPDATE_MODE |
2882 NISTC_AO_CMD1_DAC0_UPDATE_MODE |
2886 ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2,
2892 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2894 const struct ni_board_struct *board = dev->board_ptr;
2895 struct ni_private *devpriv = dev->private;
2896 const struct comedi_cmd *cmd = &s->async->cmd;
2902 if (dev->irq == 0) {
2903 dev_err(dev->class_dev, "cannot run command without an irq\n");
2907 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
2909 ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
2911 if (devpriv->is_6xxx) {
2912 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
2913 NI611X_AO_MISC_REG);
2916 for (i = 0; i < cmd->chanlist_len; i++) {
2919 chan = CR_CHAN(cmd->chanlist[i]);
2921 ni_ao_win_outw(dev, chan, NI611X_AO_WAVEFORM_GEN_REG);
2923 ni_ao_win_outw(dev, bits, NI611X_AO_TIMED_REG);
2926 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
2928 if (cmd->stop_src == TRIG_NONE) {
2929 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS;
2930 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE;
2932 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS;
2933 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE;
2935 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2937 val = devpriv->ao_trigger_select;
2938 switch (cmd->start_src) {
2941 val &= ~(NISTC_AO_TRIG_START1_POLARITY |
2942 NISTC_AO_TRIG_START1_SEL_MASK);
2943 val |= NISTC_AO_TRIG_START1_EDGE |
2944 NISTC_AO_TRIG_START1_SYNC;
2947 val = NISTC_AO_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) + 1);
2948 if (cmd->start_arg & CR_INVERT) {
2949 /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
2950 val |= NISTC_AO_TRIG_START1_POLARITY;
2952 if (cmd->start_arg & CR_EDGE) {
2953 /* 0=edge detection disabled, 1=enabled */
2954 val |= NISTC_AO_TRIG_START1_EDGE;
2956 ni_stc_writew(dev, devpriv->ao_trigger_select,
2957 NISTC_AO_TRIG_SEL_REG);
2963 devpriv->ao_trigger_select = val;
2964 ni_stc_writew(dev, devpriv->ao_trigger_select, NISTC_AO_TRIG_SEL_REG);
2966 devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN;
2967 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
2969 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
2970 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;
2971 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2972 if (cmd->stop_src == TRIG_NONE)
2973 ni_stc_writel(dev, 0xffffff, NISTC_AO_BC_LOADA_REG);
2975 ni_stc_writel(dev, 0, NISTC_AO_BC_LOADA_REG);
2976 ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);
2977 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;
2978 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
2979 switch (cmd->stop_src) {
2981 if (devpriv->is_m_series) {
2982 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
2983 ni_stc_writel(dev, cmd->stop_arg - 1,
2984 NISTC_AO_UC_LOADA_REG);
2985 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
2988 ni_stc_writel(dev, cmd->stop_arg,
2989 NISTC_AO_UC_LOADA_REG);
2990 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD,
2992 ni_stc_writel(dev, cmd->stop_arg - 1,
2993 NISTC_AO_UC_LOADA_REG);
2997 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
2998 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
2999 ni_stc_writel(dev, 0xffffff, NISTC_AO_UC_LOADA_REG);
3002 ni_stc_writel(dev, 0, NISTC_AO_UC_LOADA_REG);
3003 ni_stc_writew(dev, NISTC_AO_CMD1_UC_LOAD, NISTC_AO_CMD1_REG);
3004 ni_stc_writel(dev, cmd->stop_arg, NISTC_AO_UC_LOADA_REG);
3007 devpriv->ao_mode1 &= ~(NISTC_AO_MODE1_UPDATE_SRC_MASK |
3008 NISTC_AO_MODE1_UI_SRC_MASK |
3009 NISTC_AO_MODE1_UPDATE_SRC_POLARITY |
3010 NISTC_AO_MODE1_UI_SRC_POLARITY);
3011 switch (cmd->scan_begin_src) {
3013 devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA;
3015 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3016 CMDF_ROUND_NEAREST);
3017 ni_stc_writel(dev, 1, NISTC_AO_UI_LOADA_REG);
3018 ni_stc_writew(dev, NISTC_AO_CMD1_UI_LOAD, NISTC_AO_CMD1_REG);
3019 ni_stc_writel(dev, trigvar, NISTC_AO_UI_LOADA_REG);
3022 devpriv->ao_mode1 |=
3023 NISTC_AO_MODE1_UPDATE_SRC(cmd->scan_begin_arg);
3024 if (cmd->scan_begin_arg & CR_INVERT)
3025 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY;
3026 devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA;
3032 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3033 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3034 devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |
3035 NISTC_AO_MODE2_UI_INIT_LOAD_SRC);
3036 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3038 if (cmd->scan_end_arg > 1) {
3039 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
3041 NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1) |
3042 NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ,
3043 NISTC_AO_OUT_CTRL_REG);
3047 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN;
3048 bits = NISTC_AO_OUT_CTRL_UPDATE_SEL_HIGHZ;
3049 if (devpriv->is_m_series || devpriv->is_6xxx) {
3050 bits |= NISTC_AO_OUT_CTRL_CHANS(0);
3053 NISTC_AO_OUT_CTRL_CHANS(CR_CHAN(cmd->chanlist[0]));
3055 ni_stc_writew(dev, bits, NISTC_AO_OUT_CTRL_REG);
3057 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3059 ni_stc_writew(dev, NISTC_AO_CMD1_DAC1_UPDATE_MODE |
3060 NISTC_AO_CMD1_DAC0_UPDATE_MODE,
3063 devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR;
3064 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3066 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;
3068 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;
3070 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;
3072 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;
3073 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3075 bits = NISTC_AO_PERSONAL_BC_SRC_SEL |
3076 NISTC_AO_PERSONAL_UPDATE_PW |
3077 NISTC_AO_PERSONAL_TMRDACWR_PW;
3078 if (board->ao_fifo_depth)
3079 bits |= NISTC_AO_PERSONAL_FIFO_ENA;
3081 bits |= NISTC_AO_PERSONAL_DMA_PIO_CTRL;
3084 * F Hess: windows driver does not set NISTC_AO_PERSONAL_NUM_DAC bit
3085 * for 6281, verified with bus analyzer.
3087 if (devpriv->is_m_series)
3088 bits |= NISTC_AO_PERSONAL_NUM_DAC;
3090 ni_stc_writew(dev, bits, NISTC_AO_PERSONAL_REG);
3091 /* enable sending of ao dma requests */
3092 ni_stc_writew(dev, NISTC_AO_START_AOFREQ_ENA, NISTC_AO_START_SEL_REG);
3094 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3096 if (cmd->stop_src == TRIG_COUNT) {
3097 ni_stc_writew(dev, NISTC_INTB_ACK_AO_BC_TC,
3098 NISTC_INTB_ACK_REG);
3099 ni_set_bits(dev, NISTC_INTB_ENA_REG,
3100 NISTC_INTB_ENA_AO_BC_TC, 1);
3103 s->async->inttrig = ni_ao_inttrig;
3108 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3109 struct comedi_cmd *cmd)
3111 const struct ni_board_struct *board = dev->board_ptr;
3112 struct ni_private *devpriv = dev->private;
3116 /* Step 1 : check if triggers are trivially valid */
3118 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3119 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3120 TRIG_TIMER | TRIG_EXT);
3121 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3122 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3123 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3128 /* Step 2a : make sure trigger sources are unique */
3130 err |= comedi_check_trigger_is_unique(cmd->start_src);
3131 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3132 err |= comedi_check_trigger_is_unique(cmd->stop_src);
3134 /* Step 2b : and mutually compatible */
3139 /* Step 3: check if arguments are trivially valid */
3141 switch (cmd->start_src) {
3143 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3146 tmp = CR_CHAN(cmd->start_arg);
3150 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3151 err |= comedi_check_trigger_arg_is(&cmd->start_arg, tmp);
3155 if (cmd->scan_begin_src == TRIG_TIMER) {
3156 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3158 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
3163 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3164 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3167 if (cmd->stop_src == TRIG_COUNT)
3168 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3169 else /* TRIG_NONE */
3170 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3175 /* step 4: fix up any arguments */
3176 if (cmd->scan_begin_src == TRIG_TIMER) {
3177 tmp = cmd->scan_begin_arg;
3178 cmd->scan_begin_arg =
3179 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3180 cmd->scan_begin_arg,
3182 if (tmp != cmd->scan_begin_arg)
3191 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3193 struct ni_private *devpriv = dev->private;
3195 ni_release_ao_mite_channel(dev);
3197 ni_stc_writew(dev, NISTC_RESET_AO_CFG_START, NISTC_RESET_REG);
3198 ni_stc_writew(dev, NISTC_AO_CMD1_DISARM, NISTC_AO_CMD1_REG);
3199 ni_set_bits(dev, NISTC_INTB_ENA_REG, ~0, 0);
3200 ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL, NISTC_AO_PERSONAL_REG);
3201 ni_stc_writew(dev, NISTC_INTB_ACK_AO_ALL, NISTC_INTB_ACK_REG);
3202 ni_stc_writew(dev, NISTC_AO_PERSONAL_BC_SRC_SEL |
3203 NISTC_AO_PERSONAL_UPDATE_PW |
3204 NISTC_AO_PERSONAL_TMRDACWR_PW,
3205 NISTC_AO_PERSONAL_REG);
3206 ni_stc_writew(dev, 0, NISTC_AO_OUT_CTRL_REG);
3207 ni_stc_writew(dev, 0, NISTC_AO_START_SEL_REG);
3208 devpriv->ao_cmd1 = 0;
3209 ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG);
3210 devpriv->ao_cmd2 = 0;
3211 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);
3212 devpriv->ao_mode1 = 0;
3213 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);
3214 devpriv->ao_mode2 = 0;
3215 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);
3216 if (devpriv->is_m_series)
3217 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE;
3219 devpriv->ao_mode3 = 0;
3220 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG);
3221 devpriv->ao_trigger_select = 0;
3222 ni_stc_writew(dev, devpriv->ao_trigger_select,
3223 NISTC_AO_TRIG_SEL_REG);
3224 if (devpriv->is_6xxx) {
3225 unsigned immediate_bits = 0;
3228 for (i = 0; i < s->n_chan; ++i)
3229 immediate_bits |= 1 << i;
3230 ni_ao_win_outw(dev, immediate_bits, NI671X_AO_IMMEDIATE_REG);
3231 ni_ao_win_outw(dev, NI611X_AO_MISC_CLEAR_WG,
3232 NI611X_AO_MISC_REG);
3234 ni_stc_writew(dev, NISTC_RESET_AO_CFG_END, NISTC_RESET_REG);
3241 static int ni_dio_insn_config(struct comedi_device *dev,
3242 struct comedi_subdevice *s,
3243 struct comedi_insn *insn,
3246 struct ni_private *devpriv = dev->private;
3249 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3253 devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK;
3254 devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits);
3255 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3260 static int ni_dio_insn_bits(struct comedi_device *dev,
3261 struct comedi_subdevice *s,
3262 struct comedi_insn *insn,
3265 struct ni_private *devpriv = dev->private;
3267 /* Make sure we're not using the serial part of the dio */
3268 if ((data[0] & (NISTC_DIO_SDIN | NISTC_DIO_SDOUT)) &&
3269 devpriv->serial_interval_ns)
3272 if (comedi_dio_update_state(s, data)) {
3273 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK;
3274 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state);
3275 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3278 data[1] = ni_stc_readw(dev, NISTC_DIO_IN_REG);
3283 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3284 struct comedi_subdevice *s,
3285 struct comedi_insn *insn,
3290 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3294 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
3299 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3300 struct comedi_subdevice *s,
3301 struct comedi_insn *insn,
3304 if (comedi_dio_update_state(s, data))
3305 ni_writel(dev, s->state, NI_M_DIO_REG);
3307 data[1] = ni_readl(dev, NI_M_DIO_REG);
3312 static int ni_cdio_check_chanlist(struct comedi_device *dev,
3313 struct comedi_subdevice *s,
3314 struct comedi_cmd *cmd)
3318 for (i = 0; i < cmd->chanlist_len; ++i) {
3319 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3328 static int ni_cdio_cmdtest(struct comedi_device *dev,
3329 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3334 /* Step 1 : check if triggers are trivially valid */
3336 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT);
3337 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3338 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3339 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3340 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3345 /* Step 2a : make sure trigger sources are unique */
3346 /* Step 2b : and mutually compatible */
3348 /* Step 3: check if arguments are trivially valid */
3350 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3352 tmp = cmd->scan_begin_arg;
3353 tmp &= CR_PACK_FLAGS(NI_M_CDO_MODE_SAMPLE_SRC_MASK, 0, 0, CR_INVERT);
3354 if (tmp != cmd->scan_begin_arg)
3357 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
3358 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3360 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
3365 /* Step 4: fix up any arguments */
3367 /* Step 5: check channel list if it exists */
3369 if (cmd->chanlist && cmd->chanlist_len > 0)
3370 err |= ni_cdio_check_chanlist(dev, s, cmd);
3378 static int ni_cdo_inttrig(struct comedi_device *dev,
3379 struct comedi_subdevice *s,
3380 unsigned int trig_num)
3382 struct comedi_cmd *cmd = &s->async->cmd;
3383 const unsigned timeout = 1000;
3387 struct ni_private *devpriv = dev->private;
3388 unsigned long flags;
3391 if (trig_num != cmd->start_arg)
3394 s->async->inttrig = NULL;
3396 /* read alloc the entire buffer */
3397 comedi_buf_read_alloc(s, s->async->prealloc_bufsz);
3400 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3401 if (devpriv->cdo_mite_chan) {
3402 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3403 mite_dma_arm(devpriv->cdo_mite_chan);
3405 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n");
3408 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3413 * XXX not sure what interrupt C group does
3414 * wait for dma to fill output fifo
3415 * ni_writeb(dev, NI_M_INTC_ENA, NI_M_INTC_ENA_REG);
3417 for (i = 0; i < timeout; ++i) {
3418 if (ni_readl(dev, NI_M_CDIO_STATUS_REG) &
3419 NI_M_CDIO_STATUS_CDO_FIFO_FULL)
3424 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n");
3428 ni_writel(dev, NI_M_CDO_CMD_ARM |
3429 NI_M_CDO_CMD_ERR_INT_ENA_SET |
3430 NI_M_CDO_CMD_F_E_INT_ENA_SET,
3435 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3437 const struct comedi_cmd *cmd = &s->async->cmd;
3438 unsigned cdo_mode_bits;
3441 ni_writel(dev, NI_M_CDO_CMD_RESET, NI_M_CDIO_CMD_REG);
3442 cdo_mode_bits = NI_M_CDO_MODE_FIFO_MODE |
3443 NI_M_CDO_MODE_HALT_ON_ERROR |
3444 NI_M_CDO_MODE_SAMPLE_SRC(CR_CHAN(cmd->scan_begin_arg));
3445 if (cmd->scan_begin_arg & CR_INVERT)
3446 cdo_mode_bits |= NI_M_CDO_MODE_POLARITY;
3447 ni_writel(dev, cdo_mode_bits, NI_M_CDO_MODE_REG);
3449 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG);
3450 ni_writel(dev, NI_M_CDO_CMD_SW_UPDATE, NI_M_CDIO_CMD_REG);
3451 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG);
3453 dev_err(dev->class_dev,
3454 "attempted to run digital output command with no lines configured as outputs\n");
3457 retval = ni_request_cdo_mite_channel(dev);
3461 s->async->inttrig = ni_cdo_inttrig;
3466 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3468 ni_writel(dev, NI_M_CDO_CMD_DISARM |
3469 NI_M_CDO_CMD_ERR_INT_ENA_CLR |
3470 NI_M_CDO_CMD_F_E_INT_ENA_CLR |
3471 NI_M_CDO_CMD_F_REQ_INT_ENA_CLR,
3474 * XXX not sure what interrupt C group does
3475 * ni_writeb(dev, 0, NI_M_INTC_ENA_REG);
3477 ni_writel(dev, 0, NI_M_CDO_MASK_ENA_REG);
3478 ni_release_cdo_mite_channel(dev);
3482 static void handle_cdio_interrupt(struct comedi_device *dev)
3484 struct ni_private *devpriv = dev->private;
3485 unsigned cdio_status;
3486 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3488 unsigned long flags;
3491 if (!devpriv->is_m_series)
3494 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3495 if (devpriv->cdo_mite_chan) {
3496 unsigned cdo_mite_status =
3497 mite_get_status(devpriv->cdo_mite_chan);
3498 if (cdo_mite_status & CHSR_LINKC) {
3500 devpriv->mite->mite_io_addr +
3501 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3503 mite_sync_output_dma(devpriv->cdo_mite_chan, s);
3505 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3508 cdio_status = ni_readl(dev, NI_M_CDIO_STATUS_REG);
3509 if (cdio_status & NI_M_CDIO_STATUS_CDO_ERROR) {
3510 /* XXX just guessing this is needed and does something useful */
3511 ni_writel(dev, NI_M_CDO_CMD_ERR_INT_CONFIRM,
3513 s->async->events |= COMEDI_CB_OVERFLOW;
3515 if (cdio_status & NI_M_CDIO_STATUS_CDO_FIFO_EMPTY) {
3516 ni_writel(dev, NI_M_CDO_CMD_F_E_INT_ENA_CLR,
3518 /* s->async->events |= COMEDI_CB_EOA; */
3520 comedi_handle_events(dev, s);
3523 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3524 struct comedi_subdevice *s,
3525 unsigned char data_out,
3526 unsigned char *data_in)
3528 struct ni_private *devpriv = dev->private;
3529 unsigned int status1;
3530 int err = 0, count = 20;
3532 devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK;
3533 devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out);
3534 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3536 status1 = ni_stc_readw(dev, NISTC_STATUS1_REG);
3537 if (status1 & NISTC_STATUS1_SERIO_IN_PROG) {
3542 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START;
3543 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3544 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START;
3546 /* Wait until STC says we're done, but don't loop infinitely. */
3547 while ((status1 = ni_stc_readw(dev, NISTC_STATUS1_REG)) &
3548 NISTC_STATUS1_SERIO_IN_PROG) {
3549 /* Delay one bit per loop */
3550 udelay((devpriv->serial_interval_ns + 999) / 1000);
3552 dev_err(dev->class_dev,
3553 "SPI serial I/O didn't finish in time!\n");
3560 * Delay for last bit. This delay is absolutely necessary, because
3561 * NISTC_STATUS1_SERIO_IN_PROG goes high one bit too early.
3563 udelay((devpriv->serial_interval_ns + 999) / 1000);
3566 *data_in = ni_stc_readw(dev, NISTC_DIO_SERIAL_IN_REG);
3569 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3574 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
3575 struct comedi_subdevice *s,
3576 unsigned char data_out,
3577 unsigned char *data_in)
3579 struct ni_private *devpriv = dev->private;
3580 unsigned char mask, input = 0;
3582 /* Wait for one bit before transfer */
3583 udelay((devpriv->serial_interval_ns + 999) / 1000);
3585 for (mask = 0x80; mask; mask >>= 1) {
3586 /* Output current bit; note that we cannot touch s->state
3587 because it is a per-subdevice field, and serial is
3588 a separate subdevice from DIO. */
3589 devpriv->dio_output &= ~NISTC_DIO_SDOUT;
3590 if (data_out & mask)
3591 devpriv->dio_output |= NISTC_DIO_SDOUT;
3592 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG);
3594 /* Assert SDCLK (active low, inverted), wait for half of
3595 the delay, deassert SDCLK, and wait for the other half. */
3596 devpriv->dio_control |= NISTC_DIO_SDCLK;
3597 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3599 udelay((devpriv->serial_interval_ns + 999) / 2000);
3601 devpriv->dio_control &= ~NISTC_DIO_SDCLK;
3602 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3604 udelay((devpriv->serial_interval_ns + 999) / 2000);
3606 /* Input current bit */
3607 if (ni_stc_readw(dev, NISTC_DIO_IN_REG) & NISTC_DIO_SDIN)
3617 static int ni_serial_insn_config(struct comedi_device *dev,
3618 struct comedi_subdevice *s,
3619 struct comedi_insn *insn,
3622 struct ni_private *devpriv = dev->private;
3623 unsigned clk_fout = devpriv->clock_and_fout;
3625 unsigned char byte_out, byte_in = 0;
3631 case INSN_CONFIG_SERIAL_CLOCK:
3632 devpriv->serial_hw_mode = 1;
3633 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA;
3635 if (data[1] == SERIAL_DISABLED) {
3636 devpriv->serial_hw_mode = 0;
3637 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3639 data[1] = SERIAL_DISABLED;
3640 devpriv->serial_interval_ns = data[1];
3641 } else if (data[1] <= SERIAL_600NS) {
3642 /* Warning: this clock speed is too fast to reliably
3644 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3645 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE;
3646 clk_fout &= ~NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3647 data[1] = SERIAL_600NS;
3648 devpriv->serial_interval_ns = data[1];
3649 } else if (data[1] <= SERIAL_1_2US) {
3650 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3651 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3652 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3653 data[1] = SERIAL_1_2US;
3654 devpriv->serial_interval_ns = data[1];
3655 } else if (data[1] <= SERIAL_10US) {
3656 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE;
3657 clk_fout |= NISTC_CLK_FOUT_SLOW_TIMEBASE |
3658 NISTC_CLK_FOUT_DIO_SER_OUT_DIV2;
3659 /* Note: NISTC_CLK_FOUT_DIO_SER_OUT_DIV2 only affects
3660 600ns/1.2us. If you turn divide_by_2 off with the
3661 slow clock, you will still get 10us, except then
3662 all your delays are wrong. */
3663 data[1] = SERIAL_10US;
3664 devpriv->serial_interval_ns = data[1];
3666 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA |
3668 devpriv->serial_hw_mode = 0;
3669 data[1] = (data[1] / 1000) * 1000;
3670 devpriv->serial_interval_ns = data[1];
3672 devpriv->clock_and_fout = clk_fout;
3674 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
3675 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3678 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3680 if (devpriv->serial_interval_ns == 0)
3683 byte_out = data[1] & 0xFF;
3685 if (devpriv->serial_hw_mode) {
3686 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3688 } else if (devpriv->serial_interval_ns > 0) {
3689 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3692 dev_err(dev->class_dev, "serial disabled!\n");
3697 data[1] = byte_in & 0xFF;
3706 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
3710 for (i = 0; i < s->n_chan; i++) {
3711 ni_ao_win_outw(dev, NI_E_AO_DACSEL(i) | 0x0,
3712 NI67XX_AO_CFG2_REG);
3714 ni_ao_win_outw(dev, 0x0, NI67XX_AO_SP_UPDATES_REG);
3717 static const struct mio_regmap ni_gpct_to_stc_regmap[] = {
3718 [NITIO_G0_AUTO_INC] = { NISTC_G0_AUTOINC_REG, 2 },
3719 [NITIO_G1_AUTO_INC] = { NISTC_G1_AUTOINC_REG, 2 },
3720 [NITIO_G0_CMD] = { NISTC_G0_CMD_REG, 2 },
3721 [NITIO_G1_CMD] = { NISTC_G1_CMD_REG, 2 },
3722 [NITIO_G0_HW_SAVE] = { NISTC_G0_HW_SAVE_REG, 4 },
3723 [NITIO_G1_HW_SAVE] = { NISTC_G1_HW_SAVE_REG, 4 },
3724 [NITIO_G0_SW_SAVE] = { NISTC_G0_SAVE_REG, 4 },
3725 [NITIO_G1_SW_SAVE] = { NISTC_G1_SAVE_REG, 4 },
3726 [NITIO_G0_MODE] = { NISTC_G0_MODE_REG, 2 },
3727 [NITIO_G1_MODE] = { NISTC_G1_MODE_REG, 2 },
3728 [NITIO_G0_LOADA] = { NISTC_G0_LOADA_REG, 4 },
3729 [NITIO_G1_LOADA] = { NISTC_G1_LOADA_REG, 4 },
3730 [NITIO_G0_LOADB] = { NISTC_G0_LOADB_REG, 4 },
3731 [NITIO_G1_LOADB] = { NISTC_G1_LOADB_REG, 4 },
3732 [NITIO_G0_INPUT_SEL] = { NISTC_G0_INPUT_SEL_REG, 2 },
3733 [NITIO_G1_INPUT_SEL] = { NISTC_G1_INPUT_SEL_REG, 2 },
3734 [NITIO_G0_CNT_MODE] = { 0x1b0, 2 }, /* M-Series only */
3735 [NITIO_G1_CNT_MODE] = { 0x1b2, 2 }, /* M-Series only */
3736 [NITIO_G0_GATE2] = { 0x1b4, 2 }, /* M-Series only */
3737 [NITIO_G1_GATE2] = { 0x1b6, 2 }, /* M-Series only */
3738 [NITIO_G01_STATUS] = { NISTC_G01_STATUS_REG, 2 },
3739 [NITIO_G01_RESET] = { NISTC_RESET_REG, 2 },
3740 [NITIO_G01_STATUS1] = { NISTC_STATUS1_REG, 2 },
3741 [NITIO_G01_STATUS2] = { NISTC_STATUS2_REG, 2 },
3742 [NITIO_G0_DMA_CFG] = { 0x1b8, 2 }, /* M-Series only */
3743 [NITIO_G1_DMA_CFG] = { 0x1ba, 2 }, /* M-Series only */
3744 [NITIO_G0_DMA_STATUS] = { 0x1b8, 2 }, /* M-Series only */
3745 [NITIO_G1_DMA_STATUS] = { 0x1ba, 2 }, /* M-Series only */
3746 [NITIO_G0_ABZ] = { 0x1c0, 2 }, /* M-Series only */
3747 [NITIO_G1_ABZ] = { 0x1c2, 2 }, /* M-Series only */
3748 [NITIO_G0_INT_ACK] = { NISTC_INTA_ACK_REG, 2 },
3749 [NITIO_G1_INT_ACK] = { NISTC_INTB_ACK_REG, 2 },
3750 [NITIO_G0_STATUS] = { NISTC_AI_STATUS1_REG, 2 },
3751 [NITIO_G1_STATUS] = { NISTC_AO_STATUS1_REG, 2 },
3752 [NITIO_G0_INT_ENA] = { NISTC_INTA_ENA_REG, 2 },
3753 [NITIO_G1_INT_ENA] = { NISTC_INTB_ENA_REG, 2 },
3756 static unsigned int ni_gpct_to_stc_register(struct comedi_device *dev,
3757 enum ni_gpct_register reg)
3759 const struct mio_regmap *regmap;
3761 if (reg < ARRAY_SIZE(ni_gpct_to_stc_regmap)) {
3762 regmap = &ni_gpct_to_stc_regmap[reg];
3764 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n",
3769 return regmap->mio_reg;
3772 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
3773 enum ni_gpct_register reg)
3775 struct comedi_device *dev = counter->counter_dev->dev;
3776 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3777 static const unsigned gpct_interrupt_a_enable_mask =
3778 NISTC_INTA_ENA_G0_GATE | NISTC_INTA_ENA_G0_TC;
3779 static const unsigned gpct_interrupt_b_enable_mask =
3780 NISTC_INTB_ENA_G1_GATE | NISTC_INTB_ENA_G1_TC;
3782 if (stc_register == 0)
3786 /* m-series only registers */
3787 case NITIO_G0_CNT_MODE:
3788 case NITIO_G1_CNT_MODE:
3789 case NITIO_G0_GATE2:
3790 case NITIO_G1_GATE2:
3791 case NITIO_G0_DMA_CFG:
3792 case NITIO_G1_DMA_CFG:
3795 ni_writew(dev, bits, stc_register);
3798 /* 32 bit registers */
3799 case NITIO_G0_LOADA:
3800 case NITIO_G1_LOADA:
3801 case NITIO_G0_LOADB:
3802 case NITIO_G1_LOADB:
3803 ni_stc_writel(dev, bits, stc_register);
3806 /* 16 bit registers */
3807 case NITIO_G0_INT_ENA:
3808 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
3809 ni_set_bitfield(dev, stc_register,
3810 gpct_interrupt_a_enable_mask, bits);
3812 case NITIO_G1_INT_ENA:
3813 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
3814 ni_set_bitfield(dev, stc_register,
3815 gpct_interrupt_b_enable_mask, bits);
3817 case NITIO_G01_RESET:
3818 BUG_ON(bits & ~(NISTC_RESET_G0 | NISTC_RESET_G1));
3821 ni_stc_writew(dev, bits, stc_register);
3825 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
3826 enum ni_gpct_register reg)
3828 struct comedi_device *dev = counter->counter_dev->dev;
3829 unsigned int stc_register = ni_gpct_to_stc_register(dev, reg);
3831 if (stc_register == 0)
3835 /* m-series only registers */
3836 case NITIO_G0_DMA_STATUS:
3837 case NITIO_G1_DMA_STATUS:
3838 return ni_readw(dev, stc_register);
3840 /* 32 bit registers */
3841 case NITIO_G0_HW_SAVE:
3842 case NITIO_G1_HW_SAVE:
3843 case NITIO_G0_SW_SAVE:
3844 case NITIO_G1_SW_SAVE:
3845 return ni_stc_readl(dev, stc_register);
3847 /* 16 bit registers */
3849 return ni_stc_readw(dev, stc_register);
3853 static int ni_freq_out_insn_read(struct comedi_device *dev,
3854 struct comedi_subdevice *s,
3855 struct comedi_insn *insn,
3858 struct ni_private *devpriv = dev->private;
3859 unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout);
3862 for (i = 0; i < insn->n; i++)
3868 static int ni_freq_out_insn_write(struct comedi_device *dev,
3869 struct comedi_subdevice *s,
3870 struct comedi_insn *insn,
3873 struct ni_private *devpriv = dev->private;
3876 unsigned int val = data[insn->n - 1];
3878 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA;
3879 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3880 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK;
3882 /* use the last data value to set the fout divider */
3883 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val);
3885 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA;
3886 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3891 static int ni_freq_out_insn_config(struct comedi_device *dev,
3892 struct comedi_subdevice *s,
3893 struct comedi_insn *insn,
3896 struct ni_private *devpriv = dev->private;
3899 case INSN_CONFIG_SET_CLOCK_SRC:
3901 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
3902 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL;
3904 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
3905 devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL;
3910 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
3912 case INSN_CONFIG_GET_CLOCK_SRC:
3913 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) {
3914 data[1] = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
3915 data[2] = TIMEBASE_2_NS;
3917 data[1] = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
3918 data[2] = TIMEBASE_1_NS * 2;
3927 static int ni_8255_callback(struct comedi_device *dev,
3928 int dir, int port, int data, unsigned long iobase)
3931 ni_writeb(dev, data, iobase + 2 * port);
3935 return ni_readb(dev, iobase + 2 * port);
3938 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
3940 struct ni_private *devpriv = dev->private;
3942 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
3943 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
3947 static int ni_m_series_pwm_config(struct comedi_device *dev,
3948 struct comedi_subdevice *s,
3949 struct comedi_insn *insn,
3952 struct ni_private *devpriv = dev->private;
3953 unsigned up_count, down_count;
3956 case INSN_CONFIG_PWM_OUTPUT:
3958 case CMDF_ROUND_NEAREST:
3961 devpriv->clock_ns / 2) / devpriv->clock_ns;
3963 case CMDF_ROUND_DOWN:
3964 up_count = data[2] / devpriv->clock_ns;
3968 (data[2] + devpriv->clock_ns -
3969 1) / devpriv->clock_ns;
3975 case CMDF_ROUND_NEAREST:
3978 devpriv->clock_ns / 2) / devpriv->clock_ns;
3980 case CMDF_ROUND_DOWN:
3981 down_count = data[4] / devpriv->clock_ns;
3985 (data[4] + devpriv->clock_ns -
3986 1) / devpriv->clock_ns;
3991 if (up_count * devpriv->clock_ns != data[2] ||
3992 down_count * devpriv->clock_ns != data[4]) {
3993 data[2] = up_count * devpriv->clock_ns;
3994 data[4] = down_count * devpriv->clock_ns;
3997 ni_writel(dev, NI_M_CAL_PWM_HIGH_TIME(up_count) |
3998 NI_M_CAL_PWM_LOW_TIME(down_count),
4000 devpriv->pwm_up_count = up_count;
4001 devpriv->pwm_down_count = down_count;
4003 case INSN_CONFIG_GET_PWM_OUTPUT:
4004 return ni_get_pwm_config(dev, data);
4011 static int ni_6143_pwm_config(struct comedi_device *dev,
4012 struct comedi_subdevice *s,
4013 struct comedi_insn *insn,
4016 struct ni_private *devpriv = dev->private;
4017 unsigned up_count, down_count;
4020 case INSN_CONFIG_PWM_OUTPUT:
4022 case CMDF_ROUND_NEAREST:
4025 devpriv->clock_ns / 2) / devpriv->clock_ns;
4027 case CMDF_ROUND_DOWN:
4028 up_count = data[2] / devpriv->clock_ns;
4032 (data[2] + devpriv->clock_ns -
4033 1) / devpriv->clock_ns;
4039 case CMDF_ROUND_NEAREST:
4042 devpriv->clock_ns / 2) / devpriv->clock_ns;
4044 case CMDF_ROUND_DOWN:
4045 down_count = data[4] / devpriv->clock_ns;
4049 (data[4] + devpriv->clock_ns -
4050 1) / devpriv->clock_ns;
4055 if (up_count * devpriv->clock_ns != data[2] ||
4056 down_count * devpriv->clock_ns != data[4]) {
4057 data[2] = up_count * devpriv->clock_ns;
4058 data[4] = down_count * devpriv->clock_ns;
4061 ni_writel(dev, up_count, NI6143_CALIB_HI_TIME_REG);
4062 devpriv->pwm_up_count = up_count;
4063 ni_writel(dev, down_count, NI6143_CALIB_LO_TIME_REG);
4064 devpriv->pwm_down_count = down_count;
4066 case INSN_CONFIG_GET_PWM_OUTPUT:
4067 return ni_get_pwm_config(dev, data);
4074 static int pack_mb88341(int addr, int val, int *bitstring)
4078 Note that address bits are reversed. Thanks to
4079 Ingo Keen for noticing this.
4081 Note also that the 88341 expects address values from
4082 1-12, whereas we use channel numbers 0-11. The NI
4083 docs use 1-12, also, so be careful here.
4086 *bitstring = ((addr & 0x1) << 11) |
4087 ((addr & 0x2) << 9) |
4088 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
4092 static int pack_dac8800(int addr, int val, int *bitstring)
4094 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
4098 static int pack_dac8043(int addr, int val, int *bitstring)
4100 *bitstring = val & 0xfff;
4104 static int pack_ad8522(int addr, int val, int *bitstring)
4106 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
4110 static int pack_ad8804(int addr, int val, int *bitstring)
4112 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
4116 static int pack_ad8842(int addr, int val, int *bitstring)
4118 *bitstring = ((addr + 1) << 8) | (val & 0xff);
4122 struct caldac_struct {
4125 int (*packbits)(int, int, int *);
4128 static struct caldac_struct caldacs[] = {
4129 [mb88341] = {12, 8, pack_mb88341},
4130 [dac8800] = {8, 8, pack_dac8800},
4131 [dac8043] = {1, 12, pack_dac8043},
4132 [ad8522] = {2, 12, pack_ad8522},
4133 [ad8804] = {12, 8, pack_ad8804},
4134 [ad8842] = {8, 8, pack_ad8842},
4135 [ad8804_debug] = {16, 8, pack_ad8804},
4138 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
4140 const struct ni_board_struct *board = dev->board_ptr;
4141 struct ni_private *devpriv = dev->private;
4142 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
4147 if (devpriv->caldacs[addr] == val)
4149 devpriv->caldacs[addr] = val;
4151 for (i = 0; i < 3; i++) {
4152 type = board->caldac[i];
4153 if (type == caldac_none)
4155 if (addr < caldacs[type].n_chans) {
4156 bits = caldacs[type].packbits(addr, val, &bitstring);
4157 loadbit = NI_E_SERIAL_CMD_DAC_LD(i);
4160 addr -= caldacs[type].n_chans;
4163 /* bits will be 0 if there is no caldac for the given addr */
4167 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
4168 cmd = (bit & bitstring) ? NI_E_SERIAL_CMD_SDATA : 0;
4169 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4171 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4174 ni_writeb(dev, loadbit, NI_E_SERIAL_CMD_REG);
4176 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4179 static int ni_calib_insn_write(struct comedi_device *dev,
4180 struct comedi_subdevice *s,
4181 struct comedi_insn *insn,
4184 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4189 static int ni_calib_insn_read(struct comedi_device *dev,
4190 struct comedi_subdevice *s,
4191 struct comedi_insn *insn,
4194 struct ni_private *devpriv = dev->private;
4196 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4201 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4203 const struct ni_board_struct *board = dev->board_ptr;
4204 struct ni_private *devpriv = dev->private;
4213 type = board->caldac[0];
4214 if (type == caldac_none)
4216 n_bits = caldacs[type].n_bits;
4217 for (i = 0; i < 3; i++) {
4218 type = board->caldac[i];
4219 if (type == caldac_none)
4221 if (caldacs[type].n_bits != n_bits)
4223 n_chans += caldacs[type].n_chans;
4226 s->n_chan = n_chans;
4229 unsigned int *maxdata_list;
4231 if (n_chans > MAX_N_CALDACS)
4232 dev_err(dev->class_dev,
4233 "BUG! MAX_N_CALDACS too small\n");
4234 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
4236 for (i = 0; i < n_dacs; i++) {
4237 type = board->caldac[i];
4238 for (j = 0; j < caldacs[type].n_chans; j++) {
4239 maxdata_list[chan] =
4240 (1 << caldacs[type].n_bits) - 1;
4245 for (chan = 0; chan < s->n_chan; chan++)
4246 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
4248 type = board->caldac[0];
4249 s->maxdata = (1 << caldacs[type].n_bits) - 1;
4251 for (chan = 0; chan < s->n_chan; chan++)
4252 ni_write_caldac(dev, i, s->maxdata / 2);
4256 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4258 unsigned int cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4262 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4263 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4264 for (bit = 0x8000; bit; bit >>= 1) {
4265 if (bit & bitstring)
4266 cmd |= NI_E_SERIAL_CMD_SDATA;
4268 cmd &= ~NI_E_SERIAL_CMD_SDATA;
4270 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4271 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4273 cmd = NI_E_SERIAL_CMD_EEPROM_CS;
4275 for (bit = 0x80; bit; bit >>= 1) {
4276 ni_writeb(dev, cmd, NI_E_SERIAL_CMD_REG);
4277 ni_writeb(dev, NI_E_SERIAL_CMD_SCLK | cmd, NI_E_SERIAL_CMD_REG);
4278 if (ni_readb(dev, NI_E_STATUS_REG) & NI_E_STATUS_PROMOUT)
4281 ni_writeb(dev, 0, NI_E_SERIAL_CMD_REG);
4286 static int ni_eeprom_insn_read(struct comedi_device *dev,
4287 struct comedi_subdevice *s,
4288 struct comedi_insn *insn,
4291 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4296 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4297 struct comedi_subdevice *s,
4298 struct comedi_insn *insn,
4301 struct ni_private *devpriv = dev->private;
4303 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4308 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
4311 /* pre-m-series boards have fixed signals on pfi pins */
4314 return NI_PFI_OUTPUT_AI_START1;
4316 return NI_PFI_OUTPUT_AI_START2;
4318 return NI_PFI_OUTPUT_AI_CONVERT;
4320 return NI_PFI_OUTPUT_G_SRC1;
4322 return NI_PFI_OUTPUT_G_GATE1;
4324 return NI_PFI_OUTPUT_AO_UPDATE_N;
4326 return NI_PFI_OUTPUT_AO_START1;
4328 return NI_PFI_OUTPUT_AI_START_PULSE;
4330 return NI_PFI_OUTPUT_G_SRC0;
4332 return NI_PFI_OUTPUT_G_GATE0;
4334 dev_err(dev->class_dev, "bug, unhandled case in switch.\n");
4340 static int ni_old_set_pfi_routing(struct comedi_device *dev,
4341 unsigned chan, unsigned source)
4343 /* pre-m-series boards have fixed signals on pfi pins */
4344 if (source != ni_old_get_pfi_routing(dev, chan))
4349 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
4352 struct ni_private *devpriv = dev->private;
4353 const unsigned array_offset = chan / 3;
4355 return NI_M_PFI_OUT_SEL_TO_SRC(chan,
4356 devpriv->pfi_output_select_reg[array_offset]);
4359 static int ni_m_series_set_pfi_routing(struct comedi_device *dev,
4360 unsigned chan, unsigned source)
4362 struct ni_private *devpriv = dev->private;
4363 unsigned index = chan / 3;
4364 unsigned short val = devpriv->pfi_output_select_reg[index];
4366 if ((source & 0x1f) != source)
4369 val &= ~NI_M_PFI_OUT_SEL_MASK(chan);
4370 val |= NI_M_PFI_OUT_SEL(chan, source);
4371 ni_writew(dev, val, NI_M_PFI_OUT_SEL_REG(index));
4372 devpriv->pfi_output_select_reg[index] = val;
4377 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
4379 struct ni_private *devpriv = dev->private;
4381 return (devpriv->is_m_series)
4382 ? ni_m_series_get_pfi_routing(dev, chan)
4383 : ni_old_get_pfi_routing(dev, chan);
4386 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
4389 struct ni_private *devpriv = dev->private;
4391 return (devpriv->is_m_series)
4392 ? ni_m_series_set_pfi_routing(dev, chan, source)
4393 : ni_old_set_pfi_routing(dev, chan, source);
4396 static int ni_config_filter(struct comedi_device *dev,
4397 unsigned pfi_channel,
4398 enum ni_pfi_filter_select filter)
4400 struct ni_private *devpriv = dev->private;
4403 if (!devpriv->is_m_series)
4406 bits = ni_readl(dev, NI_M_PFI_FILTER_REG);
4407 bits &= ~NI_M_PFI_FILTER_SEL_MASK(pfi_channel);
4408 bits |= NI_M_PFI_FILTER_SEL(pfi_channel, filter);
4409 ni_writel(dev, bits, NI_M_PFI_FILTER_REG);
4413 static int ni_pfi_insn_config(struct comedi_device *dev,
4414 struct comedi_subdevice *s,
4415 struct comedi_insn *insn,
4418 struct ni_private *devpriv = dev->private;
4424 chan = CR_CHAN(insn->chanspec);
4428 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 1);
4431 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, 1 << chan, 0);
4433 case INSN_CONFIG_DIO_QUERY:
4435 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
4436 COMEDI_OUTPUT : COMEDI_INPUT;
4438 case INSN_CONFIG_SET_ROUTING:
4439 return ni_set_pfi_routing(dev, chan, data[1]);
4440 case INSN_CONFIG_GET_ROUTING:
4441 data[1] = ni_get_pfi_routing(dev, chan);
4443 case INSN_CONFIG_FILTER:
4444 return ni_config_filter(dev, chan, data[1]);
4451 static int ni_pfi_insn_bits(struct comedi_device *dev,
4452 struct comedi_subdevice *s,
4453 struct comedi_insn *insn,
4456 struct ni_private *devpriv = dev->private;
4458 if (!devpriv->is_m_series)
4461 if (comedi_dio_update_state(s, data))
4462 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
4464 data[1] = ni_readw(dev, NI_M_PFI_DI_REG);
4469 static int cs5529_wait_for_idle(struct comedi_device *dev)
4471 unsigned short status;
4472 const int timeout = HZ;
4475 for (i = 0; i < timeout; i++) {
4476 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4477 if ((status & NI67XX_CAL_STATUS_BUSY) == 0)
4479 set_current_state(TASK_INTERRUPTIBLE);
4480 if (schedule_timeout(1))
4484 dev_err(dev->class_dev, "timeout\n");
4490 static void cs5529_command(struct comedi_device *dev, unsigned short value)
4492 static const int timeout = 100;
4495 ni_ao_win_outw(dev, value, NI67XX_CAL_CMD_REG);
4496 /* give time for command to start being serially clocked into cs5529.
4497 * this insures that the NI67XX_CAL_STATUS_BUSY bit will get properly
4498 * set before we exit this function.
4500 for (i = 0; i < timeout; i++) {
4501 if (ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG) &
4502 NI67XX_CAL_STATUS_BUSY)
4507 dev_err(dev->class_dev,
4508 "possible problem - never saw adc go busy?\n");
4511 static int cs5529_do_conversion(struct comedi_device *dev,
4512 unsigned short *data)
4515 unsigned short status;
4517 cs5529_command(dev, CS5529_CMD_CB | CS5529_CMD_SINGLE_CONV);
4518 retval = cs5529_wait_for_idle(dev);
4520 dev_err(dev->class_dev,
4521 "timeout or signal in cs5529_do_conversion()\n");
4524 status = ni_ao_win_inw(dev, NI67XX_CAL_STATUS_REG);
4525 if (status & NI67XX_CAL_STATUS_OSC_DETECT) {
4526 dev_err(dev->class_dev,
4527 "cs5529 conversion error, status CSS_OSC_DETECT\n");
4530 if (status & NI67XX_CAL_STATUS_OVERRANGE) {
4531 dev_err(dev->class_dev,
4532 "cs5529 conversion error, overrange (ignoring)\n");
4535 *data = ni_ao_win_inw(dev, NI67XX_CAL_DATA_REG);
4536 /* cs5529 returns 16 bit signed data in bipolar mode */
4542 static int cs5529_ai_insn_read(struct comedi_device *dev,
4543 struct comedi_subdevice *s,
4544 struct comedi_insn *insn,
4548 unsigned short sample;
4549 unsigned int channel_select;
4550 const unsigned int INTERNAL_REF = 0x1000;
4552 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
4553 * do nothing. bit 12 seems to chooses internal reference voltage, bit
4554 * 13 causes the adc input to go overrange (maybe reads external reference?) */
4555 if (insn->chanspec & CR_ALT_SOURCE)
4556 channel_select = INTERNAL_REF;
4558 channel_select = CR_CHAN(insn->chanspec);
4559 ni_ao_win_outw(dev, channel_select, NI67XX_AO_CAL_CHAN_SEL_REG);
4561 for (n = 0; n < insn->n; n++) {
4562 retval = cs5529_do_conversion(dev, &sample);
4570 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
4571 unsigned int reg_select_bits)
4573 ni_ao_win_outw(dev, (value >> 16) & 0xff, NI67XX_CAL_CFG_HI_REG);
4574 ni_ao_win_outw(dev, value & 0xffff, NI67XX_CAL_CFG_LO_REG);
4575 reg_select_bits &= CS5529_CMD_REG_MASK;
4576 cs5529_command(dev, CS5529_CMD_CB | reg_select_bits);
4577 if (cs5529_wait_for_idle(dev))
4578 dev_err(dev->class_dev,
4579 "timeout or signal in %s\n", __func__);
4582 static int init_cs5529(struct comedi_device *dev)
4584 unsigned int config_bits = CS5529_CFG_PORT_FLAG |
4585 CS5529_CFG_WORD_RATE_2180;
4588 /* do self-calibration */
4589 cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_BOTH_SELF,
4591 /* need to force a conversion for calibration to run */
4592 cs5529_do_conversion(dev, NULL);
4594 /* force gain calibration to 1 */
4595 cs5529_config_write(dev, 0x400000, CS5529_GAIN_REG);
4596 cs5529_config_write(dev, config_bits | CS5529_CFG_CALIB_OFFSET_SELF,
4598 if (cs5529_wait_for_idle(dev))
4599 dev_err(dev->class_dev,
4600 "timeout or signal in %s\n", __func__);
4606 * Find best multiplier/divider to try and get the PLL running at 80 MHz
4607 * given an arbitrary frequency input clock.
4609 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
4610 unsigned *freq_divider,
4611 unsigned *freq_multiplier,
4612 unsigned *actual_period_ns)
4615 unsigned best_div = 1;
4617 unsigned best_mult = 1;
4618 static const unsigned pico_per_nano = 1000;
4620 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
4621 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
4622 * 20 MHz for most timing clocks */
4623 static const unsigned target_picosec = 12500;
4624 static const unsigned fudge_factor_80_to_20Mhz = 4;
4625 int best_period_picosec = 0;
4627 for (div = 1; div <= NI_M_PLL_MAX_DIVISOR; ++div) {
4628 for (mult = 1; mult <= NI_M_PLL_MAX_MULTIPLIER; ++mult) {
4629 unsigned new_period_ps =
4630 (reference_picosec * div) / mult;
4631 if (abs(new_period_ps - target_picosec) <
4632 abs(best_period_picosec - target_picosec)) {
4633 best_period_picosec = new_period_ps;
4639 if (best_period_picosec == 0)
4642 *freq_divider = best_div;
4643 *freq_multiplier = best_mult;
4645 (best_period_picosec * fudge_factor_80_to_20Mhz +
4646 (pico_per_nano / 2)) / pico_per_nano;
4650 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
4651 unsigned source, unsigned period_ns)
4653 struct ni_private *devpriv = dev->private;
4654 static const unsigned min_period_ns = 50;
4655 static const unsigned max_period_ns = 1000;
4656 static const unsigned timeout = 1000;
4657 unsigned pll_control_bits;
4658 unsigned freq_divider;
4659 unsigned freq_multiplier;
4664 if (source == NI_MIO_PLL_PXI10_CLOCK)
4666 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
4667 if (period_ns < min_period_ns || period_ns > max_period_ns) {
4668 dev_err(dev->class_dev,
4669 "%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\n",
4670 __func__, min_period_ns, max_period_ns);
4673 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4674 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4675 NISTC_RTSI_TRIG_DIR_REG);
4676 pll_control_bits = NI_M_PLL_CTRL_ENA | NI_M_PLL_CTRL_VCO_MODE_75_150MHZ;
4677 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4678 NI_M_CLK_FOUT2_TIMEBASE3_PLL;
4679 devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK;
4681 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
4682 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR;
4684 case NI_MIO_PLL_PXI10_CLOCK:
4685 /* pxi clock is 10MHz */
4686 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10;
4689 for (rtsi = 0; rtsi <= NI_M_MAX_RTSI_CHAN; ++rtsi) {
4690 if (source == NI_MIO_PLL_RTSI_CLOCK(rtsi)) {
4691 devpriv->clock_and_fout2 |=
4692 NI_M_CLK_FOUT2_PLL_SRC_RTSI(rtsi);
4696 if (rtsi > NI_M_MAX_RTSI_CHAN)
4700 retval = ni_mseries_get_pll_parameters(period_ns,
4703 &devpriv->clock_ns);
4705 dev_err(dev->class_dev,
4706 "bug, failed to find pll parameters\n");
4710 ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG);
4711 pll_control_bits |= NI_M_PLL_CTRL_DIVISOR(freq_divider) |
4712 NI_M_PLL_CTRL_MULTIPLIER(freq_multiplier);
4714 ni_writew(dev, pll_control_bits, NI_M_PLL_CTRL_REG);
4715 devpriv->clock_source = source;
4716 /* it seems to typically take a few hundred microseconds for PLL to lock */
4717 for (i = 0; i < timeout; ++i) {
4718 if (ni_readw(dev, NI_M_PLL_STATUS_REG) & NI_M_PLL_STATUS_LOCKED)
4723 dev_err(dev->class_dev,
4724 "%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns\n",
4725 __func__, source, period_ns);
4731 static int ni_set_master_clock(struct comedi_device *dev,
4732 unsigned source, unsigned period_ns)
4734 struct ni_private *devpriv = dev->private;
4736 if (source == NI_MIO_INTERNAL_CLOCK) {
4737 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK;
4738 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4739 NISTC_RTSI_TRIG_DIR_REG);
4740 devpriv->clock_ns = TIMEBASE_1_NS;
4741 if (devpriv->is_m_series) {
4742 devpriv->clock_and_fout2 &=
4743 ~(NI_M_CLK_FOUT2_TIMEBASE1_PLL |
4744 NI_M_CLK_FOUT2_TIMEBASE3_PLL);
4745 ni_writew(dev, devpriv->clock_and_fout2,
4746 NI_M_CLK_FOUT2_REG);
4747 ni_writew(dev, 0, NI_M_PLL_CTRL_REG);
4749 devpriv->clock_source = source;
4751 if (devpriv->is_m_series) {
4752 return ni_mseries_set_pll_master_clock(dev, source,
4755 if (source == NI_MIO_RTSI_CLOCK) {
4756 devpriv->rtsi_trig_direction_reg |=
4757 NISTC_RTSI_TRIG_USE_CLK;
4759 devpriv->rtsi_trig_direction_reg,
4760 NISTC_RTSI_TRIG_DIR_REG);
4761 if (period_ns == 0) {
4762 dev_err(dev->class_dev,
4763 "we don't handle an unspecified clock period correctly yet, returning error\n");
4766 devpriv->clock_ns = period_ns;
4767 devpriv->clock_source = source;
4776 static int ni_valid_rtsi_output_source(struct comedi_device *dev,
4777 unsigned chan, unsigned source)
4779 struct ni_private *devpriv = dev->private;
4781 if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4782 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4783 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
4786 dev_err(dev->class_dev,
4787 "%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n",
4788 __func__, chan, NISTC_RTSI_TRIG_OLD_CLK_CHAN);
4794 case NI_RTSI_OUTPUT_ADR_START1:
4795 case NI_RTSI_OUTPUT_ADR_START2:
4796 case NI_RTSI_OUTPUT_SCLKG:
4797 case NI_RTSI_OUTPUT_DACUPDN:
4798 case NI_RTSI_OUTPUT_DA_START1:
4799 case NI_RTSI_OUTPUT_G_SRC0:
4800 case NI_RTSI_OUTPUT_G_GATE0:
4801 case NI_RTSI_OUTPUT_RGOUT0:
4802 case NI_RTSI_OUTPUT_RTSI_BRD_0:
4804 case NI_RTSI_OUTPUT_RTSI_OSC:
4805 return (devpriv->is_m_series) ? 1 : 0;
4811 static int ni_set_rtsi_routing(struct comedi_device *dev,
4812 unsigned chan, unsigned src)
4814 struct ni_private *devpriv = dev->private;
4816 if (ni_valid_rtsi_output_source(dev, chan, src) == 0)
4819 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4820 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src);
4821 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4822 NISTC_RTSI_TRIGA_OUT_REG);
4823 } else if (chan < 8) {
4824 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan);
4825 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src);
4826 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4827 NISTC_RTSI_TRIGB_OUT_REG);
4832 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
4834 struct ni_private *devpriv = dev->private;
4837 return NISTC_RTSI_TRIG_TO_SRC(chan,
4838 devpriv->rtsi_trig_a_output_reg);
4839 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) {
4840 return NISTC_RTSI_TRIG_TO_SRC(chan,
4841 devpriv->rtsi_trig_b_output_reg);
4843 if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN)
4844 return NI_RTSI_OUTPUT_RTSI_OSC;
4845 dev_err(dev->class_dev, "bug! should never get here?\n");
4850 static int ni_rtsi_insn_config(struct comedi_device *dev,
4851 struct comedi_subdevice *s,
4852 struct comedi_insn *insn,
4855 struct ni_private *devpriv = dev->private;
4856 unsigned int chan = CR_CHAN(insn->chanspec);
4857 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series);
4860 case INSN_CONFIG_DIO_OUTPUT:
4861 if (chan < max_chan) {
4862 devpriv->rtsi_trig_direction_reg |=
4863 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
4864 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4865 devpriv->rtsi_trig_direction_reg |=
4866 NISTC_RTSI_TRIG_DRV_CLK;
4868 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4869 NISTC_RTSI_TRIG_DIR_REG);
4871 case INSN_CONFIG_DIO_INPUT:
4872 if (chan < max_chan) {
4873 devpriv->rtsi_trig_direction_reg &=
4874 ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series);
4875 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4876 devpriv->rtsi_trig_direction_reg &=
4877 ~NISTC_RTSI_TRIG_DRV_CLK;
4879 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg,
4880 NISTC_RTSI_TRIG_DIR_REG);
4882 case INSN_CONFIG_DIO_QUERY:
4883 if (chan < max_chan) {
4885 (devpriv->rtsi_trig_direction_reg &
4886 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series))
4887 ? INSN_CONFIG_DIO_OUTPUT
4888 : INSN_CONFIG_DIO_INPUT;
4889 } else if (chan == NISTC_RTSI_TRIG_OLD_CLK_CHAN) {
4890 data[1] = (devpriv->rtsi_trig_direction_reg &
4891 NISTC_RTSI_TRIG_DRV_CLK)
4892 ? INSN_CONFIG_DIO_OUTPUT
4893 : INSN_CONFIG_DIO_INPUT;
4896 case INSN_CONFIG_SET_CLOCK_SRC:
4897 return ni_set_master_clock(dev, data[1], data[2]);
4898 case INSN_CONFIG_GET_CLOCK_SRC:
4899 data[1] = devpriv->clock_source;
4900 data[2] = devpriv->clock_ns;
4902 case INSN_CONFIG_SET_ROUTING:
4903 return ni_set_rtsi_routing(dev, chan, data[1]);
4904 case INSN_CONFIG_GET_ROUTING:
4905 data[1] = ni_get_rtsi_routing(dev, chan);
4913 static int ni_rtsi_insn_bits(struct comedi_device *dev,
4914 struct comedi_subdevice *s,
4915 struct comedi_insn *insn,
4923 static void ni_rtsi_init(struct comedi_device *dev)
4925 struct ni_private *devpriv = dev->private;
4927 /* Initialises the RTSI bus signal switch to a default state */
4930 * Use 10MHz instead of 20MHz for RTSI clock frequency. Appears
4931 * to have no effect, at least on pxi-6281, which always uses
4932 * 20MHz rtsi clock frequency
4934 devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ;
4935 /* Set clock mode to internal */
4936 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0)
4937 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n");
4938 /* default internal lines routing to RTSI bus lines */
4939 devpriv->rtsi_trig_a_output_reg =
4940 NISTC_RTSI_TRIG(0, NI_RTSI_OUTPUT_ADR_START1) |
4941 NISTC_RTSI_TRIG(1, NI_RTSI_OUTPUT_ADR_START2) |
4942 NISTC_RTSI_TRIG(2, NI_RTSI_OUTPUT_SCLKG) |
4943 NISTC_RTSI_TRIG(3, NI_RTSI_OUTPUT_DACUPDN);
4944 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
4945 NISTC_RTSI_TRIGA_OUT_REG);
4946 devpriv->rtsi_trig_b_output_reg =
4947 NISTC_RTSI_TRIG(4, NI_RTSI_OUTPUT_DA_START1) |
4948 NISTC_RTSI_TRIG(5, NI_RTSI_OUTPUT_G_SRC0) |
4949 NISTC_RTSI_TRIG(6, NI_RTSI_OUTPUT_G_GATE0);
4950 if (devpriv->is_m_series)
4951 devpriv->rtsi_trig_b_output_reg |=
4952 NISTC_RTSI_TRIG(7, NI_RTSI_OUTPUT_RTSI_OSC);
4953 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
4954 NISTC_RTSI_TRIGB_OUT_REG);
4957 * Sets the source and direction of the 4 on board lines
4958 * ni_stc_writew(dev, 0, NISTC_RTSI_BOARD_REG);
4963 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
4965 struct ni_gpct *counter = s->private;
4968 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
4971 dev_err(dev->class_dev,
4972 "no dma channel available for use by counter\n");
4975 ni_tio_acknowledge(counter);
4976 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
4978 return ni_tio_cmd(dev, s);
4981 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
4983 struct ni_gpct *counter = s->private;
4986 retval = ni_tio_cancel(counter);
4987 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
4988 ni_release_gpct_mite_channel(dev, counter->counter_index);
4993 static irqreturn_t ni_E_interrupt(int irq, void *d)
4995 struct comedi_device *dev = d;
4996 unsigned short a_status;
4997 unsigned short b_status;
4998 unsigned int ai_mite_status = 0;
4999 unsigned int ao_mite_status = 0;
5000 unsigned long flags;
5002 struct ni_private *devpriv = dev->private;
5003 struct mite_struct *mite = devpriv->mite;
5008 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
5010 /* lock to avoid race with comedi_poll */
5011 spin_lock_irqsave(&dev->spinlock, flags);
5012 a_status = ni_stc_readw(dev, NISTC_AI_STATUS1_REG);
5013 b_status = ni_stc_readw(dev, NISTC_AO_STATUS1_REG);
5016 struct ni_private *devpriv = dev->private;
5017 unsigned long flags_too;
5019 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
5020 if (devpriv->ai_mite_chan) {
5021 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
5022 if (ai_mite_status & CHSR_LINKC)
5024 devpriv->mite->mite_io_addr +
5026 ai_mite_chan->channel));
5028 if (devpriv->ao_mite_chan) {
5029 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
5030 if (ao_mite_status & CHSR_LINKC)
5032 mite->mite_io_addr +
5034 ao_mite_chan->channel));
5036 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
5039 ack_a_interrupt(dev, a_status);
5040 ack_b_interrupt(dev, b_status);
5041 if ((a_status & NISTC_AI_STATUS1_INTA) || (ai_mite_status & CHSR_INT))
5042 handle_a_interrupt(dev, a_status, ai_mite_status);
5043 if ((b_status & NISTC_AO_STATUS1_INTB) || (ao_mite_status & CHSR_INT))
5044 handle_b_interrupt(dev, b_status, ao_mite_status);
5045 handle_gpct_interrupt(dev, 0);
5046 handle_gpct_interrupt(dev, 1);
5047 handle_cdio_interrupt(dev);
5049 spin_unlock_irqrestore(&dev->spinlock, flags);
5053 static int ni_alloc_private(struct comedi_device *dev)
5055 struct ni_private *devpriv;
5057 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
5061 spin_lock_init(&devpriv->window_lock);
5062 spin_lock_init(&devpriv->soft_reg_copy_lock);
5063 spin_lock_init(&devpriv->mite_channel_lock);
5068 static int ni_E_init(struct comedi_device *dev,
5069 unsigned interrupt_pin, unsigned irq_polarity)
5071 const struct ni_board_struct *board = dev->board_ptr;
5072 struct ni_private *devpriv = dev->private;
5073 struct comedi_subdevice *s;
5077 if (board->n_aochan > MAX_N_AO_CHAN) {
5078 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n");
5082 /* initialize clock dividers */
5083 devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 |
5084 NISTC_CLK_FOUT_SLOW_TIMEBASE |
5085 NISTC_CLK_FOUT_TO_BOARD_DIV2 |
5086 NISTC_CLK_FOUT_TO_BOARD;
5087 if (!devpriv->is_6xxx) {
5088 /* BEAM is this needed for PCI-6143 ?? */
5089 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 |
5090 NISTC_CLK_FOUT_AO_OUT_DIV2);
5092 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG);
5094 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
5098 /* Analog Input subdevice */
5099 s = &dev->subdevices[NI_AI_SUBDEV];
5100 if (board->n_adchan) {
5101 s->type = COMEDI_SUBD_AI;
5102 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER;
5103 if (!devpriv->is_611x)
5104 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
5105 if (board->ai_maxdata > 0xffff)
5106 s->subdev_flags |= SDF_LSAMPL;
5107 if (devpriv->is_m_series)
5108 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5109 s->n_chan = board->n_adchan;
5110 s->maxdata = board->ai_maxdata;
5111 s->range_table = ni_range_lkup[board->gainlkup];
5112 s->insn_read = ni_ai_insn_read;
5113 s->insn_config = ni_ai_insn_config;
5115 dev->read_subdev = s;
5116 s->subdev_flags |= SDF_CMD_READ;
5117 s->len_chanlist = 512;
5118 s->do_cmdtest = ni_ai_cmdtest;
5119 s->do_cmd = ni_ai_cmd;
5120 s->cancel = ni_ai_reset;
5121 s->poll = ni_ai_poll;
5122 s->munge = ni_ai_munge;
5125 s->async_dma_dir = DMA_FROM_DEVICE;
5128 /* reset the analog input configuration */
5129 ni_ai_reset(dev, s);
5131 s->type = COMEDI_SUBD_UNUSED;
5134 /* Analog Output subdevice */
5135 s = &dev->subdevices[NI_AO_SUBDEV];
5136 if (board->n_aochan) {
5137 s->type = COMEDI_SUBD_AO;
5138 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
5139 if (devpriv->is_m_series)
5140 s->subdev_flags |= SDF_SOFT_CALIBRATED;
5141 s->n_chan = board->n_aochan;
5142 s->maxdata = board->ao_maxdata;
5143 s->range_table = board->ao_range_table;
5144 s->insn_config = ni_ao_insn_config;
5145 s->insn_write = ni_ao_insn_write;
5147 ret = comedi_alloc_subdev_readback(s);
5152 * Along with the IRQ we need either a FIFO or DMA for
5153 * async command support.
5155 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) {
5156 dev->write_subdev = s;
5157 s->subdev_flags |= SDF_CMD_WRITE;
5158 s->len_chanlist = s->n_chan;
5159 s->do_cmdtest = ni_ao_cmdtest;
5160 s->do_cmd = ni_ao_cmd;
5161 s->cancel = ni_ao_reset;
5162 if (!devpriv->is_m_series)
5163 s->munge = ni_ao_munge;
5166 s->async_dma_dir = DMA_TO_DEVICE;
5169 if (devpriv->is_67xx)
5170 init_ao_67xx(dev, s);
5172 /* reset the analog output configuration */
5173 ni_ao_reset(dev, s);
5175 s->type = COMEDI_SUBD_UNUSED;
5178 /* Digital I/O subdevice */
5179 s = &dev->subdevices[NI_DIO_SUBDEV];
5180 s->type = COMEDI_SUBD_DIO;
5181 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
5182 s->n_chan = board->has_32dio_chan ? 32 : 8;
5184 s->range_table = &range_digital;
5185 if (devpriv->is_m_series) {
5186 s->subdev_flags |= SDF_LSAMPL;
5187 s->insn_bits = ni_m_series_dio_insn_bits;
5188 s->insn_config = ni_m_series_dio_insn_config;
5190 s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */;
5191 s->len_chanlist = s->n_chan;
5192 s->do_cmdtest = ni_cdio_cmdtest;
5193 s->do_cmd = ni_cdio_cmd;
5194 s->cancel = ni_cdio_cancel;
5196 /* M-series boards use DMA */
5197 s->async_dma_dir = DMA_BIDIRECTIONAL;
5200 /* reset DIO and set all channels to inputs */
5201 ni_writel(dev, NI_M_CDO_CMD_RESET |
5204 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG);
5206 s->insn_bits = ni_dio_insn_bits;
5207 s->insn_config = ni_dio_insn_config;
5209 /* set all channels to inputs */
5210 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits);
5211 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG);
5215 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
5216 if (board->has_8255) {
5217 ret = subdev_8255_init(dev, s, ni_8255_callback,
5222 s->type = COMEDI_SUBD_UNUSED;
5225 /* formerly general purpose counter/timer device, but no longer used */
5226 s = &dev->subdevices[NI_UNUSED_SUBDEV];
5227 s->type = COMEDI_SUBD_UNUSED;
5229 /* Calibration subdevice */
5230 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
5231 s->type = COMEDI_SUBD_CALIB;
5232 s->subdev_flags = SDF_INTERNAL;
5235 if (devpriv->is_m_series) {
5236 /* internal PWM output used for AI nonlinearity calibration */
5237 s->insn_config = ni_m_series_pwm_config;
5239 ni_writel(dev, 0x0, NI_M_CAL_PWM_REG);
5240 } else if (devpriv->is_6143) {
5241 /* internal PWM output used for AI nonlinearity calibration */
5242 s->insn_config = ni_6143_pwm_config;
5244 s->subdev_flags |= SDF_WRITABLE;
5245 s->insn_read = ni_calib_insn_read;
5246 s->insn_write = ni_calib_insn_write;
5248 /* setup the caldacs and find the real n_chan and maxdata */
5249 caldac_setup(dev, s);
5252 /* EEPROM subdevice */
5253 s = &dev->subdevices[NI_EEPROM_SUBDEV];
5254 s->type = COMEDI_SUBD_MEMORY;
5255 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
5257 if (devpriv->is_m_series) {
5258 s->n_chan = M_SERIES_EEPROM_SIZE;
5259 s->insn_read = ni_m_series_eeprom_insn_read;
5262 s->insn_read = ni_eeprom_insn_read;
5265 /* Digital I/O (PFI) subdevice */
5266 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
5267 s->type = COMEDI_SUBD_DIO;
5268 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5270 if (devpriv->is_m_series) {
5272 s->insn_bits = ni_pfi_insn_bits;
5274 ni_writew(dev, s->state, NI_M_PFI_DO_REG);
5275 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
5276 ni_writew(dev, devpriv->pfi_output_select_reg[i],
5277 NI_M_PFI_OUT_SEL_REG(i));
5282 s->insn_config = ni_pfi_insn_config;
5284 ni_set_bits(dev, NISTC_IO_BIDIR_PIN_REG, ~0, 0);
5286 /* cs5529 calibration adc */
5287 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
5288 if (devpriv->is_67xx) {
5289 s->type = COMEDI_SUBD_AI;
5290 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
5291 /* one channel for each analog output channel */
5292 s->n_chan = board->n_aochan;
5293 s->maxdata = (1 << 16) - 1;
5294 s->range_table = &range_unknown; /* XXX */
5295 s->insn_read = cs5529_ai_insn_read;
5296 s->insn_config = NULL;
5299 s->type = COMEDI_SUBD_UNUSED;
5303 s = &dev->subdevices[NI_SERIAL_SUBDEV];
5304 s->type = COMEDI_SUBD_SERIAL;
5305 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5308 s->insn_config = ni_serial_insn_config;
5309 devpriv->serial_interval_ns = 0;
5310 devpriv->serial_hw_mode = 0;
5313 s = &dev->subdevices[NI_RTSI_SUBDEV];
5314 s->type = COMEDI_SUBD_DIO;
5315 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
5318 s->insn_bits = ni_rtsi_insn_bits;
5319 s->insn_config = ni_rtsi_insn_config;
5322 /* allocate and initialize the gpct counter device */
5323 devpriv->counter_dev = ni_gpct_device_construct(dev,
5324 ni_gpct_write_register,
5325 ni_gpct_read_register,
5326 (devpriv->is_m_series)
5327 ? ni_gpct_variant_m_series
5328 : ni_gpct_variant_e_series,
5330 if (!devpriv->counter_dev)
5333 /* Counter (gpct) subdevices */
5334 for (i = 0; i < NUM_GPCT; ++i) {
5335 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i];
5337 /* setup and initialize the counter */
5338 gpct->chip_index = 0;
5339 gpct->counter_index = i;
5340 ni_tio_init_counter(gpct);
5342 s = &dev->subdevices[NI_GPCT_SUBDEV(i)];
5343 s->type = COMEDI_SUBD_COUNTER;
5344 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
5346 s->maxdata = (devpriv->is_m_series) ? 0xffffffff
5348 s->insn_read = ni_tio_insn_read;
5349 s->insn_write = ni_tio_insn_read;
5350 s->insn_config = ni_tio_insn_config;
5352 if (dev->irq && devpriv->mite) {
5353 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
5354 s->len_chanlist = 1;
5355 s->do_cmdtest = ni_tio_cmdtest;
5356 s->do_cmd = ni_gpct_cmd;
5357 s->cancel = ni_gpct_cancel;
5359 s->async_dma_dir = DMA_BIDIRECTIONAL;
5365 /* Frequency output subdevice */
5366 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
5367 s->type = COMEDI_SUBD_COUNTER;
5368 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
5371 s->insn_read = ni_freq_out_insn_read;
5372 s->insn_write = ni_freq_out_insn_write;
5373 s->insn_config = ni_freq_out_insn_config;
5377 (irq_polarity ? NISTC_INT_CTRL_INT_POL : 0) |
5378 (NISTC_INT_CTRL_3PIN_INT & 0) |
5379 NISTC_INT_CTRL_INTA_ENA |
5380 NISTC_INT_CTRL_INTB_ENA |
5381 NISTC_INT_CTRL_INTA_SEL(interrupt_pin) |
5382 NISTC_INT_CTRL_INTB_SEL(interrupt_pin),
5383 NISTC_INT_CTRL_REG);
5387 ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG);
5388 ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG);
5390 if (devpriv->is_6xxx) {
5391 ni_writeb(dev, 0, NI611X_MAGIC_REG);
5392 } else if (devpriv->is_m_series) {
5395 for (channel = 0; channel < board->n_aochan; ++channel) {
5397 NI_M_AO_WAVEFORM_ORDER_REG(channel));
5399 NI_M_AO_REF_ATTENUATION_REG(channel));
5401 ni_writeb(dev, 0x0, NI_M_AO_CALIB_REG);
5407 static void mio_common_detach(struct comedi_device *dev)
5409 struct ni_private *devpriv = dev->private;
5412 if (devpriv->counter_dev)
5413 ni_gpct_device_destroy(devpriv->counter_dev);