2 comedi/drivers/ni_atmio16d.c
3 Hardware driver for National Instruments AT-MIO16D board
4 Copyright (C) 2000 Chris R. Baugher <baugher@enteract.com>
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
18 Description: National Instruments AT-MIO-16D
19 Author: Chris R. Baugher <baugher@enteract.com>
21 Devices: [National Instruments] AT-MIO-16 (atmio16), AT-MIO-16D (atmio16d)
24 * I must give credit here to Michal Dobes <dobes@tesnet.cz> who
25 * wrote the driver for Advantec's pcl812 boards. I used the interrupt
26 * handling code from his driver as an example for this one.
33 #include <linux/module.h>
34 #include <linux/interrupt.h>
35 #include "../comedidev.h"
37 #include "comedi_fc.h"
40 /* Configuration and Status Registers */
41 #define COM_REG_1 0x00 /* wo 16 */
42 #define STAT_REG 0x00 /* ro 16 */
43 #define COM_REG_2 0x02 /* wo 16 */
44 /* Event Strobe Registers */
45 #define START_CONVERT_REG 0x08 /* wo 16 */
46 #define START_DAQ_REG 0x0A /* wo 16 */
47 #define AD_CLEAR_REG 0x0C /* wo 16 */
48 #define EXT_STROBE_REG 0x0E /* wo 16 */
49 /* Analog Output Registers */
50 #define DAC0_REG 0x10 /* wo 16 */
51 #define DAC1_REG 0x12 /* wo 16 */
52 #define INT2CLR_REG 0x14 /* wo 16 */
53 /* Analog Input Registers */
54 #define MUX_CNTR_REG 0x04 /* wo 16 */
55 #define MUX_GAIN_REG 0x06 /* wo 16 */
56 #define AD_FIFO_REG 0x16 /* ro 16 */
57 #define DMA_TC_INT_CLR_REG 0x16 /* wo 16 */
58 /* AM9513A Counter/Timer Registers */
59 #define AM9513A_DATA_REG 0x18 /* rw 16 */
60 #define AM9513A_COM_REG 0x1A /* wo 16 */
61 #define AM9513A_STAT_REG 0x1A /* ro 16 */
62 /* MIO-16 Digital I/O Registers */
63 #define MIO_16_DIG_IN_REG 0x1C /* ro 16 */
64 #define MIO_16_DIG_OUT_REG 0x1C /* wo 16 */
65 /* RTSI Switch Registers */
66 #define RTSI_SW_SHIFT_REG 0x1E /* wo 8 */
67 #define RTSI_SW_STROBE_REG 0x1F /* wo 8 */
68 /* DIO-24 Registers */
69 #define DIO_24_PORTA_REG 0x00 /* rw 8 */
70 #define DIO_24_PORTB_REG 0x01 /* rw 8 */
71 #define DIO_24_PORTC_REG 0x02 /* rw 8 */
72 #define DIO_24_CNFG_REG 0x03 /* wo 8 */
74 /* Command Register bits */
75 #define COMREG1_2SCADC 0x0001
76 #define COMREG1_1632CNT 0x0002
77 #define COMREG1_SCANEN 0x0008
78 #define COMREG1_DAQEN 0x0010
79 #define COMREG1_DMAEN 0x0020
80 #define COMREG1_CONVINTEN 0x0080
81 #define COMREG2_SCN2 0x0010
82 #define COMREG2_INTEN 0x0080
83 #define COMREG2_DOUTEN0 0x0100
84 #define COMREG2_DOUTEN1 0x0200
85 /* Status Register bits */
86 #define STAT_AD_OVERRUN 0x0100
87 #define STAT_AD_OVERFLOW 0x0200
88 #define STAT_AD_DAQPROG 0x0800
89 #define STAT_AD_CONVAVAIL 0x2000
90 #define STAT_AD_DAQSTOPINT 0x4000
91 /* AM9513A Counter/Timer defines */
92 #define CLOCK_1_MHZ 0x8B25
93 #define CLOCK_100_KHZ 0x8C25
94 #define CLOCK_10_KHZ 0x8D25
95 #define CLOCK_1_KHZ 0x8E25
96 #define CLOCK_100_HZ 0x8F25
98 struct atmio16_board_t {
105 static const struct comedi_lrange range_atmio16d_ai_10_bipolar = {
114 static const struct comedi_lrange range_atmio16d_ai_5_bipolar = {
123 static const struct comedi_lrange range_atmio16d_ai_unipolar = {
132 /* private data struct */
133 struct atmio16d_private {
134 enum { adc_diff, adc_singleended } adc_mux;
135 enum { adc_bipolar10, adc_bipolar5, adc_unipolar10 } adc_range;
136 enum { adc_2comp, adc_straight } adc_coding;
137 enum { dac_bipolar, dac_unipolar } dac0_range, dac1_range;
138 enum { dac_internal, dac_external } dac0_reference, dac1_reference;
139 enum { dac_2comp, dac_straight } dac0_coding, dac1_coding;
140 const struct comedi_lrange *ao_range_type_list[2];
141 unsigned int com_reg_1_state; /* current state of command register 1 */
142 unsigned int com_reg_2_state; /* current state of command register 2 */
145 static void reset_counters(struct comedi_device *dev)
148 outw(0xFFC2, dev->iobase + AM9513A_COM_REG);
149 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
150 outw(0x4, dev->iobase + AM9513A_DATA_REG);
151 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
152 outw(0x3, dev->iobase + AM9513A_DATA_REG);
153 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
154 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
156 outw(0xFFC4, dev->iobase + AM9513A_COM_REG);
157 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
158 outw(0x4, dev->iobase + AM9513A_DATA_REG);
159 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
160 outw(0x3, dev->iobase + AM9513A_DATA_REG);
161 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
162 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
164 outw(0xFFC8, dev->iobase + AM9513A_COM_REG);
165 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
166 outw(0x4, dev->iobase + AM9513A_DATA_REG);
167 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
168 outw(0x3, dev->iobase + AM9513A_DATA_REG);
169 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
170 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
172 outw(0xFFD0, dev->iobase + AM9513A_COM_REG);
173 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
174 outw(0x4, dev->iobase + AM9513A_DATA_REG);
175 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
176 outw(0x3, dev->iobase + AM9513A_DATA_REG);
177 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
178 outw(0xFF50, dev->iobase + AM9513A_COM_REG);
180 outw(0, dev->iobase + AD_CLEAR_REG);
183 static void reset_atmio16d(struct comedi_device *dev)
185 struct atmio16d_private *devpriv = dev->private;
188 /* now we need to initialize the board */
189 outw(0, dev->iobase + COM_REG_1);
190 outw(0, dev->iobase + COM_REG_2);
191 outw(0, dev->iobase + MUX_GAIN_REG);
192 /* init AM9513A timer */
193 outw(0xFFFF, dev->iobase + AM9513A_COM_REG);
194 outw(0xFFEF, dev->iobase + AM9513A_COM_REG);
195 outw(0xFF17, dev->iobase + AM9513A_COM_REG);
196 outw(0xF000, dev->iobase + AM9513A_DATA_REG);
197 for (i = 1; i <= 5; ++i) {
198 outw(0xFF00 + i, dev->iobase + AM9513A_COM_REG);
199 outw(0x0004, dev->iobase + AM9513A_DATA_REG);
200 outw(0xFF08 + i, dev->iobase + AM9513A_COM_REG);
201 outw(0x3, dev->iobase + AM9513A_DATA_REG);
203 outw(0xFF5F, dev->iobase + AM9513A_COM_REG);
204 /* timer init done */
205 outw(0, dev->iobase + AD_CLEAR_REG);
206 outw(0, dev->iobase + INT2CLR_REG);
207 /* select straight binary mode for Analog Input */
208 devpriv->com_reg_1_state |= 1;
209 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
210 devpriv->adc_coding = adc_straight;
211 /* zero the analog outputs */
212 outw(2048, dev->iobase + DAC0_REG);
213 outw(2048, dev->iobase + DAC1_REG);
216 static irqreturn_t atmio16d_interrupt(int irq, void *d)
218 struct comedi_device *dev = d;
219 struct comedi_subdevice *s = dev->read_subdev;
222 val = inw(dev->iobase + AD_FIFO_REG);
223 comedi_buf_write_samples(s, &val, 1);
224 comedi_handle_events(dev, s);
229 static int atmio16d_ai_cmdtest(struct comedi_device *dev,
230 struct comedi_subdevice *s,
231 struct comedi_cmd *cmd)
235 /* Step 1 : check if triggers are trivially valid */
237 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
238 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
239 TRIG_FOLLOW | TRIG_TIMER);
240 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER);
241 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
242 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
247 /* Step 2a : make sure trigger sources are unique */
249 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
250 err |= cfc_check_trigger_is_unique(cmd->stop_src);
252 /* Step 2b : and mutually compatible */
257 /* Step 3: check if arguments are trivially valid */
259 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
261 if (cmd->scan_begin_src == TRIG_FOLLOW) {
262 /* internal trigger */
263 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
266 /* external trigger */
267 /* should be level/edge, hi/lo specification here */
268 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
272 err |= cfc_check_trigger_arg_min(&cmd->convert_arg, 10000);
274 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, SLOWEST_TIMER);
277 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
279 if (cmd->stop_src == TRIG_COUNT)
280 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
282 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
290 static int atmio16d_ai_cmd(struct comedi_device *dev,
291 struct comedi_subdevice *s)
293 struct atmio16d_private *devpriv = dev->private;
294 struct comedi_cmd *cmd = &s->async->cmd;
295 unsigned int timer, base_clock;
296 unsigned int sample_count, tmp, chan, gain;
299 /* This is slowly becoming a working command interface. *
300 * It is still uber-experimental */
304 /* check if scanning multiple channels */
305 if (cmd->chanlist_len < 2) {
306 devpriv->com_reg_1_state &= ~COMREG1_SCANEN;
307 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
309 devpriv->com_reg_1_state |= COMREG1_SCANEN;
310 devpriv->com_reg_2_state |= COMREG2_SCN2;
311 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
312 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
315 /* Setup the Mux-Gain Counter */
316 for (i = 0; i < cmd->chanlist_len; ++i) {
317 chan = CR_CHAN(cmd->chanlist[i]);
318 gain = CR_RANGE(cmd->chanlist[i]);
319 outw(i, dev->iobase + MUX_CNTR_REG);
320 tmp = chan | (gain << 6);
321 if (i == cmd->scan_end_arg - 1)
322 tmp |= 0x0010; /* set LASTONE bit */
323 outw(tmp, dev->iobase + MUX_GAIN_REG);
326 /* Now program the sample interval timer */
327 /* Figure out which clock to use then get an
328 * appropriate timer value */
329 if (cmd->convert_arg < 65536000) {
330 base_clock = CLOCK_1_MHZ;
331 timer = cmd->convert_arg / 1000;
332 } else if (cmd->convert_arg < 655360000) {
333 base_clock = CLOCK_100_KHZ;
334 timer = cmd->convert_arg / 10000;
335 } else /* cmd->convert_arg < 6553600000 */ {
336 base_clock = CLOCK_10_KHZ;
337 timer = cmd->convert_arg / 100000;
339 outw(0xFF03, dev->iobase + AM9513A_COM_REG);
340 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
341 outw(0xFF0B, dev->iobase + AM9513A_COM_REG);
342 outw(0x2, dev->iobase + AM9513A_DATA_REG);
343 outw(0xFF44, dev->iobase + AM9513A_COM_REG);
344 outw(0xFFF3, dev->iobase + AM9513A_COM_REG);
345 outw(timer, dev->iobase + AM9513A_DATA_REG);
346 outw(0xFF24, dev->iobase + AM9513A_COM_REG);
348 /* Now figure out how many samples to get */
349 /* and program the sample counter */
350 sample_count = cmd->stop_arg * cmd->scan_end_arg;
351 outw(0xFF04, dev->iobase + AM9513A_COM_REG);
352 outw(0x1025, dev->iobase + AM9513A_DATA_REG);
353 outw(0xFF0C, dev->iobase + AM9513A_COM_REG);
354 if (sample_count < 65536) {
355 /* use only Counter 4 */
356 outw(sample_count, dev->iobase + AM9513A_DATA_REG);
357 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
358 outw(0xFFF4, dev->iobase + AM9513A_COM_REG);
359 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
360 devpriv->com_reg_1_state &= ~COMREG1_1632CNT;
361 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
363 /* Counter 4 and 5 are needed */
365 tmp = sample_count & 0xFFFF;
367 outw(tmp - 1, dev->iobase + AM9513A_DATA_REG);
369 outw(0xFFFF, dev->iobase + AM9513A_DATA_REG);
371 outw(0xFF48, dev->iobase + AM9513A_COM_REG);
372 outw(0, dev->iobase + AM9513A_DATA_REG);
373 outw(0xFF28, dev->iobase + AM9513A_COM_REG);
374 outw(0xFF05, dev->iobase + AM9513A_COM_REG);
375 outw(0x25, dev->iobase + AM9513A_DATA_REG);
376 outw(0xFF0D, dev->iobase + AM9513A_COM_REG);
377 tmp = sample_count & 0xFFFF;
378 if ((tmp == 0) || (tmp == 1)) {
379 outw((sample_count >> 16) & 0xFFFF,
380 dev->iobase + AM9513A_DATA_REG);
382 outw(((sample_count >> 16) & 0xFFFF) + 1,
383 dev->iobase + AM9513A_DATA_REG);
385 outw(0xFF70, dev->iobase + AM9513A_COM_REG);
386 devpriv->com_reg_1_state |= COMREG1_1632CNT;
387 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
390 /* Program the scan interval timer ONLY IF SCANNING IS ENABLED */
391 /* Figure out which clock to use then get an
392 * appropriate timer value */
393 if (cmd->chanlist_len > 1) {
394 if (cmd->scan_begin_arg < 65536000) {
395 base_clock = CLOCK_1_MHZ;
396 timer = cmd->scan_begin_arg / 1000;
397 } else if (cmd->scan_begin_arg < 655360000) {
398 base_clock = CLOCK_100_KHZ;
399 timer = cmd->scan_begin_arg / 10000;
400 } else /* cmd->scan_begin_arg < 6553600000 */ {
401 base_clock = CLOCK_10_KHZ;
402 timer = cmd->scan_begin_arg / 100000;
404 outw(0xFF02, dev->iobase + AM9513A_COM_REG);
405 outw(base_clock, dev->iobase + AM9513A_DATA_REG);
406 outw(0xFF0A, dev->iobase + AM9513A_COM_REG);
407 outw(0x2, dev->iobase + AM9513A_DATA_REG);
408 outw(0xFF42, dev->iobase + AM9513A_COM_REG);
409 outw(0xFFF2, dev->iobase + AM9513A_COM_REG);
410 outw(timer, dev->iobase + AM9513A_DATA_REG);
411 outw(0xFF22, dev->iobase + AM9513A_COM_REG);
414 /* Clear the A/D FIFO and reset the MUX counter */
415 outw(0, dev->iobase + AD_CLEAR_REG);
416 outw(0, dev->iobase + MUX_CNTR_REG);
417 outw(0, dev->iobase + INT2CLR_REG);
418 /* enable this acquisition operation */
419 devpriv->com_reg_1_state |= COMREG1_DAQEN;
420 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
421 /* enable interrupts for conversion completion */
422 devpriv->com_reg_1_state |= COMREG1_CONVINTEN;
423 devpriv->com_reg_2_state |= COMREG2_INTEN;
424 outw(devpriv->com_reg_1_state, dev->iobase + COM_REG_1);
425 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
426 /* apply a trigger. this starts the counters! */
427 outw(0, dev->iobase + START_DAQ_REG);
432 /* This will cancel a running acquisition operation */
433 static int atmio16d_ai_cancel(struct comedi_device *dev,
434 struct comedi_subdevice *s)
441 static int atmio16d_ai_eoc(struct comedi_device *dev,
442 struct comedi_subdevice *s,
443 struct comedi_insn *insn,
444 unsigned long context)
448 status = inw(dev->iobase + STAT_REG);
449 if (status & STAT_AD_CONVAVAIL)
451 if (status & STAT_AD_OVERFLOW) {
452 outw(0, dev->iobase + AD_CLEAR_REG);
458 static int atmio16d_ai_insn_read(struct comedi_device *dev,
459 struct comedi_subdevice *s,
460 struct comedi_insn *insn, unsigned int *data)
462 struct atmio16d_private *devpriv = dev->private;
468 chan = CR_CHAN(insn->chanspec);
469 gain = CR_RANGE(insn->chanspec);
471 /* reset the Analog input circuitry */
472 /* outw( 0, dev->iobase+AD_CLEAR_REG ); */
473 /* reset the Analog Input MUX Counter to 0 */
474 /* outw( 0, dev->iobase+MUX_CNTR_REG ); */
476 /* set the Input MUX gain */
477 outw(chan | (gain << 6), dev->iobase + MUX_GAIN_REG);
479 for (i = 0; i < insn->n; i++) {
480 /* start the conversion */
481 outw(0, dev->iobase + START_CONVERT_REG);
483 /* wait for it to finish */
484 ret = comedi_timeout(dev, s, insn, atmio16d_ai_eoc, 0);
488 /* read the data now */
489 data[i] = inw(dev->iobase + AD_FIFO_REG);
490 /* change to two's complement if need be */
491 if (devpriv->adc_coding == adc_2comp)
498 static int atmio16d_ao_insn_write(struct comedi_device *dev,
499 struct comedi_subdevice *s,
500 struct comedi_insn *insn,
503 struct atmio16d_private *devpriv = dev->private;
504 unsigned int chan = CR_CHAN(insn->chanspec);
505 unsigned int reg = (chan) ? DAC1_REG : DAC0_REG;
509 if (chan == 0 && devpriv->dac0_coding == dac_2comp)
511 if (chan == 1 && devpriv->dac1_coding == dac_2comp)
514 for (i = 0; i < insn->n; i++) {
515 unsigned int val = data[i];
517 s->readback[chan] = val;
522 outw(val, dev->iobase + reg);
528 static int atmio16d_dio_insn_bits(struct comedi_device *dev,
529 struct comedi_subdevice *s,
530 struct comedi_insn *insn,
533 if (comedi_dio_update_state(s, data))
534 outw(s->state, dev->iobase + MIO_16_DIG_OUT_REG);
536 data[1] = inw(dev->iobase + MIO_16_DIG_IN_REG);
541 static int atmio16d_dio_insn_config(struct comedi_device *dev,
542 struct comedi_subdevice *s,
543 struct comedi_insn *insn,
546 struct atmio16d_private *devpriv = dev->private;
547 unsigned int chan = CR_CHAN(insn->chanspec);
556 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
560 devpriv->com_reg_2_state &= ~(COMREG2_DOUTEN0 | COMREG2_DOUTEN1);
561 if (s->io_bits & 0x0f)
562 devpriv->com_reg_2_state |= COMREG2_DOUTEN0;
563 if (s->io_bits & 0xf0)
564 devpriv->com_reg_2_state |= COMREG2_DOUTEN1;
565 outw(devpriv->com_reg_2_state, dev->iobase + COM_REG_2);
571 options[0] - I/O port
574 N == irq N {3,4,5,6,7,9,10,11,12,14,15}
577 N == irq N {3,4,5,6,7,9}
578 options[3] - DMA1 channel
581 options[4] - DMA2 channel
586 0=differential, 1=single
587 options[6] - a/d range
588 0=bipolar10, 1=bipolar5, 2=unipolar10
590 options[7] - dac0 range
591 0=bipolar, 1=unipolar
592 options[8] - dac0 reference
593 0=internal, 1=external
594 options[9] - dac0 coding
595 0=2's comp, 1=straight binary
597 options[10] - dac1 range
598 options[11] - dac1 reference
599 options[12] - dac1 coding
602 static int atmio16d_attach(struct comedi_device *dev,
603 struct comedi_devconfig *it)
605 const struct atmio16_board_t *board = dev->board_ptr;
606 struct atmio16d_private *devpriv;
607 struct comedi_subdevice *s;
610 ret = comedi_request_region(dev, it->options[0], 0x20);
614 ret = comedi_alloc_subdevices(dev, 4);
618 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
622 /* reset the atmio16d hardware */
625 if (it->options[1]) {
626 ret = request_irq(it->options[1], atmio16d_interrupt, 0,
627 dev->board_name, dev);
629 dev->irq = it->options[1];
632 /* set device options */
633 devpriv->adc_mux = it->options[5];
634 devpriv->adc_range = it->options[6];
636 devpriv->dac0_range = it->options[7];
637 devpriv->dac0_reference = it->options[8];
638 devpriv->dac0_coding = it->options[9];
639 devpriv->dac1_range = it->options[10];
640 devpriv->dac1_reference = it->options[11];
641 devpriv->dac1_coding = it->options[12];
643 /* setup sub-devices */
644 s = &dev->subdevices[0];
646 s->type = COMEDI_SUBD_AI;
647 s->subdev_flags = SDF_READABLE | SDF_GROUND;
648 s->n_chan = (devpriv->adc_mux ? 16 : 8);
649 s->insn_read = atmio16d_ai_insn_read;
650 s->maxdata = 0xfff; /* 4095 decimal */
651 switch (devpriv->adc_range) {
653 s->range_table = &range_atmio16d_ai_10_bipolar;
656 s->range_table = &range_atmio16d_ai_5_bipolar;
659 s->range_table = &range_atmio16d_ai_unipolar;
663 dev->read_subdev = s;
664 s->subdev_flags |= SDF_CMD_READ;
665 s->len_chanlist = 16;
666 s->do_cmdtest = atmio16d_ai_cmdtest;
667 s->do_cmd = atmio16d_ai_cmd;
668 s->cancel = atmio16d_ai_cancel;
672 s = &dev->subdevices[1];
673 s->type = COMEDI_SUBD_AO;
674 s->subdev_flags = SDF_WRITABLE;
676 s->maxdata = 0xfff; /* 4095 decimal */
677 s->range_table_list = devpriv->ao_range_type_list;
678 switch (devpriv->dac0_range) {
680 devpriv->ao_range_type_list[0] = &range_bipolar10;
683 devpriv->ao_range_type_list[0] = &range_unipolar10;
686 switch (devpriv->dac1_range) {
688 devpriv->ao_range_type_list[1] = &range_bipolar10;
691 devpriv->ao_range_type_list[1] = &range_unipolar10;
694 s->insn_write = atmio16d_ao_insn_write;
696 ret = comedi_alloc_subdev_readback(s);
701 s = &dev->subdevices[2];
702 s->type = COMEDI_SUBD_DIO;
703 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
705 s->insn_bits = atmio16d_dio_insn_bits;
706 s->insn_config = atmio16d_dio_insn_config;
708 s->range_table = &range_digital;
711 s = &dev->subdevices[3];
712 if (board->has_8255) {
713 ret = subdev_8255_init(dev, s, NULL, 0x00);
717 s->type = COMEDI_SUBD_UNUSED;
720 /* don't yet know how to deal with counter/timers */
722 s = &dev->subdevices[4];
724 s->type = COMEDI_SUBD_TIMER;
732 static void atmio16d_detach(struct comedi_device *dev)
735 comedi_legacy_detach(dev);
738 static const struct atmio16_board_t atmio16_boards[] = {
748 static struct comedi_driver atmio16d_driver = {
749 .driver_name = "atmio16",
750 .module = THIS_MODULE,
751 .attach = atmio16d_attach,
752 .detach = atmio16d_detach,
753 .board_name = &atmio16_boards[0].name,
754 .num_names = ARRAY_SIZE(atmio16_boards),
755 .offset = sizeof(struct atmio16_board_t),
757 module_comedi_driver(atmio16d_driver);
759 MODULE_AUTHOR("Comedi http://www.comedi.org");
760 MODULE_DESCRIPTION("Comedi low-level driver");
761 MODULE_LICENSE("GPL");