drivers/staging/comedi/drivers/ni_660x.c

   1 /*
   2   comedi/drivers/ni_660x.c
   3   Hardware driver for NI 660x devices
   4
   5   This program is free software; you can redistribute it and/or modify
   6   it under the terms of the GNU General Public License as published by
   7   the Free Software Foundation; either version 2 of the License, or
   8   (at your option) any later version.
   9
  10   This program is distributed in the hope that it will be useful,
  11   but WITHOUT ANY WARRANTY; without even the implied warranty of
  12   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13   GNU General Public License for more details.
  14
  15   You should have received a copy of the GNU General Public License
  16   along with this program; if not, write to the Free Software
  17   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18 */
  19
  20 /*
  21  * Driver: ni_660x
  22  * Description: National Instruments 660x counter/timer boards
  23  * Devices: [National Instruments] PCI-6601 (ni_660x), PCI-6602, PXI-6602,
  24  *   PXI-6608, PXI-6624
  25  * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
  26  *   Herman.Bruyninckx@mech.kuleuven.ac.be,
  27  *   Wim.Meeussen@mech.kuleuven.ac.be,
  28  *   Klaas.Gadeyne@mech.kuleuven.ac.be,
  29  *   Frank Mori Hess <fmhess@users.sourceforge.net>
  30  * Updated: Fri, 15 Mar 2013 10:47:56 +0000
  31  * Status: experimental
  32  *
  33  * Encoders work.  PulseGeneration (both single pulse and pulse train)
  34  * works.  Buffered commands work for input but not output.
  35  *
  36  * References:
  37  * DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
  38  * DAQ 6601/6602 User Manual (NI 322137B-01)
  39  */
  40
  41 #include <linux/pci.h>
  42 #include <linux/interrupt.h>
  43
  44 #include "../comedidev.h"
  45
  46 #include "mite.h"
  47 #include "ni_tio.h"
  48
  49 enum ni_660x_constants {
  50         min_counter_pfi_chan = 8,
  51         max_dio_pfi_chan = 31,
  52         counters_per_chip = 4
  53 };
  54
  55 #define NUM_PFI_CHANNELS 40
  56 /* really there are only up to 3 dma channels, but the register layout allows
  57 for 4 */
  58 #define MAX_DMA_CHANNEL 4
  59
  60 /* See Register-Level Programmer Manual page 3.1 */
  61 enum NI_660x_Register {
  62         G0InterruptAcknowledge,
  63         G0StatusRegister,
  64         G1InterruptAcknowledge,
  65         G1StatusRegister,
  66         G01StatusRegister,
  67         G0CommandRegister,
  68         STCDIOParallelInput,
  69         G1CommandRegister,
  70         G0HWSaveRegister,
  71         G1HWSaveRegister,
  72         STCDIOOutput,
  73         STCDIOControl,
  74         G0SWSaveRegister,
  75         G1SWSaveRegister,
  76         G0ModeRegister,
  77         G01JointStatus1Register,
  78         G1ModeRegister,
  79         STCDIOSerialInput,
  80         G0LoadARegister,
  81         G01JointStatus2Register,
  82         G0LoadBRegister,
  83         G1LoadARegister,
  84         G1LoadBRegister,
  85         G0InputSelectRegister,
  86         G1InputSelectRegister,
  87         G0AutoincrementRegister,
  88         G1AutoincrementRegister,
  89         G01JointResetRegister,
  90         G0InterruptEnable,
  91         G1InterruptEnable,
  92         G0CountingModeRegister,
  93         G1CountingModeRegister,
  94         G0SecondGateRegister,
  95         G1SecondGateRegister,
  96         G0DMAConfigRegister,
  97         G0DMAStatusRegister,
  98         G1DMAConfigRegister,
  99         G1DMAStatusRegister,
 100         G2InterruptAcknowledge,
 101         G2StatusRegister,
 102         G3InterruptAcknowledge,
 103         G3StatusRegister,
 104         G23StatusRegister,
 105         G2CommandRegister,
 106         G3CommandRegister,
 107         G2HWSaveRegister,
 108         G3HWSaveRegister,
 109         G2SWSaveRegister,
 110         G3SWSaveRegister,
 111         G2ModeRegister,
 112         G23JointStatus1Register,
 113         G3ModeRegister,
 114         G2LoadARegister,
 115         G23JointStatus2Register,
 116         G2LoadBRegister,
 117         G3LoadARegister,
 118         G3LoadBRegister,
 119         G2InputSelectRegister,
 120         G3InputSelectRegister,
 121         G2AutoincrementRegister,
 122         G3AutoincrementRegister,
 123         G23JointResetRegister,
 124         G2InterruptEnable,
 125         G3InterruptEnable,
 126         G2CountingModeRegister,
 127         G3CountingModeRegister,
 128         G3SecondGateRegister,
 129         G2SecondGateRegister,
 130         G2DMAConfigRegister,
 131         G2DMAStatusRegister,
 132         G3DMAConfigRegister,
 133         G3DMAStatusRegister,
 134         DIO32Input,
 135         DIO32Output,
 136         ClockConfigRegister,
 137         GlobalInterruptStatusRegister,
 138         DMAConfigRegister,
 139         GlobalInterruptConfigRegister,
 140         IOConfigReg0_1,
 141         IOConfigReg2_3,
 142         IOConfigReg4_5,
 143         IOConfigReg6_7,
 144         IOConfigReg8_9,
 145         IOConfigReg10_11,
 146         IOConfigReg12_13,
 147         IOConfigReg14_15,
 148         IOConfigReg16_17,
 149         IOConfigReg18_19,
 150         IOConfigReg20_21,
 151         IOConfigReg22_23,
 152         IOConfigReg24_25,
 153         IOConfigReg26_27,
 154         IOConfigReg28_29,
 155         IOConfigReg30_31,
 156         IOConfigReg32_33,
 157         IOConfigReg34_35,
 158         IOConfigReg36_37,
 159         IOConfigReg38_39,
 160         NumRegisters,
 161 };
 162
 163 static inline unsigned IOConfigReg(unsigned pfi_channel)
 164 {
 165         unsigned reg = IOConfigReg0_1 + pfi_channel / 2;
 166         BUG_ON(reg > IOConfigReg38_39);
 167         return reg;
 168 }
 169
 170 enum ni_660x_register_width {
 171         DATA_1B,
 172         DATA_2B,
 173         DATA_4B
 174 };
 175
 176 enum ni_660x_register_direction {
 177         NI_660x_READ,
 178         NI_660x_WRITE,
 179         NI_660x_READ_WRITE
 180 };
 181
 182 enum ni_660x_pfi_output_select {
 183         pfi_output_select_high_Z = 0,
 184         pfi_output_select_counter = 1,
 185         pfi_output_select_do = 2,
 186         num_pfi_output_selects
 187 };
 188
 189 enum ni_660x_subdevices {
 190         NI_660X_DIO_SUBDEV = 1,
 191         NI_660X_GPCT_SUBDEV_0 = 2
 192 };
 193 static inline unsigned NI_660X_GPCT_SUBDEV(unsigned index)
 194 {
 195         return NI_660X_GPCT_SUBDEV_0 + index;
 196 }
 197
 198 struct NI_660xRegisterData {
 199
 200         const char *name;       /*  Register Name */
 201         int offset;             /*  Offset from base address from GPCT chip */
 202         enum ni_660x_register_direction direction;
 203         enum ni_660x_register_width size; /* 1 byte, 2 bytes, or 4 bytes */
 204 };
 205
 206 static const struct NI_660xRegisterData registerData[NumRegisters] = {
 207         {"G0 Interrupt Acknowledge", 0x004, NI_660x_WRITE, DATA_2B},
 208         {"G0 Status Register", 0x004, NI_660x_READ, DATA_2B},
 209         {"G1 Interrupt Acknowledge", 0x006, NI_660x_WRITE, DATA_2B},
 210         {"G1 Status Register", 0x006, NI_660x_READ, DATA_2B},
 211         {"G01 Status Register ", 0x008, NI_660x_READ, DATA_2B},
 212         {"G0 Command Register", 0x00C, NI_660x_WRITE, DATA_2B},
 213         {"STC DIO Parallel Input", 0x00E, NI_660x_READ, DATA_2B},
 214         {"G1 Command Register", 0x00E, NI_660x_WRITE, DATA_2B},
 215         {"G0 HW Save Register", 0x010, NI_660x_READ, DATA_4B},
 216         {"G1 HW Save Register", 0x014, NI_660x_READ, DATA_4B},
 217         {"STC DIO Output", 0x014, NI_660x_WRITE, DATA_2B},
 218         {"STC DIO Control", 0x016, NI_660x_WRITE, DATA_2B},
 219         {"G0 SW Save Register", 0x018, NI_660x_READ, DATA_4B},
 220         {"G1 SW Save Register", 0x01C, NI_660x_READ, DATA_4B},
 221         {"G0 Mode Register", 0x034, NI_660x_WRITE, DATA_2B},
 222         {"G01 Joint Status 1 Register", 0x036, NI_660x_READ, DATA_2B},
 223         {"G1 Mode Register", 0x036, NI_660x_WRITE, DATA_2B},
 224         {"STC DIO Serial Input", 0x038, NI_660x_READ, DATA_2B},
 225         {"G0 Load A Register", 0x038, NI_660x_WRITE, DATA_4B},
 226         {"G01 Joint Status 2 Register", 0x03A, NI_660x_READ, DATA_2B},
 227         {"G0 Load B Register", 0x03C, NI_660x_WRITE, DATA_4B},
 228         {"G1 Load A Register", 0x040, NI_660x_WRITE, DATA_4B},
 229         {"G1 Load B Register", 0x044, NI_660x_WRITE, DATA_4B},
 230         {"G0 Input Select Register", 0x048, NI_660x_WRITE, DATA_2B},
 231         {"G1 Input Select Register", 0x04A, NI_660x_WRITE, DATA_2B},
 232         {"G0 Autoincrement Register", 0x088, NI_660x_WRITE, DATA_2B},
 233         {"G1 Autoincrement Register", 0x08A, NI_660x_WRITE, DATA_2B},
 234         {"G01 Joint Reset Register", 0x090, NI_660x_WRITE, DATA_2B},
 235         {"G0 Interrupt Enable", 0x092, NI_660x_WRITE, DATA_2B},
 236         {"G1 Interrupt Enable", 0x096, NI_660x_WRITE, DATA_2B},
 237         {"G0 Counting Mode Register", 0x0B0, NI_660x_WRITE, DATA_2B},
 238         {"G1 Counting Mode Register", 0x0B2, NI_660x_WRITE, DATA_2B},
 239         {"G0 Second Gate Register", 0x0B4, NI_660x_WRITE, DATA_2B},
 240         {"G1 Second Gate Register", 0x0B6, NI_660x_WRITE, DATA_2B},
 241         {"G0 DMA Config Register", 0x0B8, NI_660x_WRITE, DATA_2B},
 242         {"G0 DMA Status Register", 0x0B8, NI_660x_READ, DATA_2B},
 243         {"G1 DMA Config Register", 0x0BA, NI_660x_WRITE, DATA_2B},
 244         {"G1 DMA Status Register", 0x0BA, NI_660x_READ, DATA_2B},
 245         {"G2 Interrupt Acknowledge", 0x104, NI_660x_WRITE, DATA_2B},
 246         {"G2 Status Register", 0x104, NI_660x_READ, DATA_2B},
 247         {"G3 Interrupt Acknowledge", 0x106, NI_660x_WRITE, DATA_2B},
 248         {"G3 Status Register", 0x106, NI_660x_READ, DATA_2B},
 249         {"G23 Status Register", 0x108, NI_660x_READ, DATA_2B},
 250         {"G2 Command Register", 0x10C, NI_660x_WRITE, DATA_2B},
 251         {"G3 Command Register", 0x10E, NI_660x_WRITE, DATA_2B},
 252         {"G2 HW Save Register", 0x110, NI_660x_READ, DATA_4B},
 253         {"G3 HW Save Register", 0x114, NI_660x_READ, DATA_4B},
 254         {"G2 SW Save Register", 0x118, NI_660x_READ, DATA_4B},
 255         {"G3 SW Save Register", 0x11C, NI_660x_READ, DATA_4B},
 256         {"G2 Mode Register", 0x134, NI_660x_WRITE, DATA_2B},
 257         {"G23 Joint Status 1 Register", 0x136, NI_660x_READ, DATA_2B},
 258         {"G3 Mode Register", 0x136, NI_660x_WRITE, DATA_2B},
 259         {"G2 Load A Register", 0x138, NI_660x_WRITE, DATA_4B},
 260         {"G23 Joint Status 2 Register", 0x13A, NI_660x_READ, DATA_2B},
 261         {"G2 Load B Register", 0x13C, NI_660x_WRITE, DATA_4B},
 262         {"G3 Load A Register", 0x140, NI_660x_WRITE, DATA_4B},
 263         {"G3 Load B Register", 0x144, NI_660x_WRITE, DATA_4B},
 264         {"G2 Input Select Register", 0x148, NI_660x_WRITE, DATA_2B},
 265         {"G3 Input Select Register", 0x14A, NI_660x_WRITE, DATA_2B},
 266         {"G2 Autoincrement Register", 0x188, NI_660x_WRITE, DATA_2B},
 267         {"G3 Autoincrement Register", 0x18A, NI_660x_WRITE, DATA_2B},
 268         {"G23 Joint Reset Register", 0x190, NI_660x_WRITE, DATA_2B},
 269         {"G2 Interrupt Enable", 0x192, NI_660x_WRITE, DATA_2B},
 270         {"G3 Interrupt Enable", 0x196, NI_660x_WRITE, DATA_2B},
 271         {"G2 Counting Mode Register", 0x1B0, NI_660x_WRITE, DATA_2B},
 272         {"G3 Counting Mode Register", 0x1B2, NI_660x_WRITE, DATA_2B},
 273         {"G3 Second Gate Register", 0x1B6, NI_660x_WRITE, DATA_2B},
 274         {"G2 Second Gate Register", 0x1B4, NI_660x_WRITE, DATA_2B},
 275         {"G2 DMA Config Register", 0x1B8, NI_660x_WRITE, DATA_2B},
 276         {"G2 DMA Status Register", 0x1B8, NI_660x_READ, DATA_2B},
 277         {"G3 DMA Config Register", 0x1BA, NI_660x_WRITE, DATA_2B},
 278         {"G3 DMA Status Register", 0x1BA, NI_660x_READ, DATA_2B},
 279         {"32 bit Digital Input", 0x414, NI_660x_READ, DATA_4B},
 280         {"32 bit Digital Output", 0x510, NI_660x_WRITE, DATA_4B},
 281         {"Clock Config Register", 0x73C, NI_660x_WRITE, DATA_4B},
 282         {"Global Interrupt Status Register", 0x754, NI_660x_READ, DATA_4B},
 283         {"DMA Configuration Register", 0x76C, NI_660x_WRITE, DATA_4B},
 284         {"Global Interrupt Config Register", 0x770, NI_660x_WRITE, DATA_4B},
 285         {"IO Config Register 0-1", 0x77C, NI_660x_READ_WRITE, DATA_2B},
 286         {"IO Config Register 2-3", 0x77E, NI_660x_READ_WRITE, DATA_2B},
 287         {"IO Config Register 4-5", 0x780, NI_660x_READ_WRITE, DATA_2B},
 288         {"IO Config Register 6-7", 0x782, NI_660x_READ_WRITE, DATA_2B},
 289         {"IO Config Register 8-9", 0x784, NI_660x_READ_WRITE, DATA_2B},
 290         {"IO Config Register 10-11", 0x786, NI_660x_READ_WRITE, DATA_2B},
 291         {"IO Config Register 12-13", 0x788, NI_660x_READ_WRITE, DATA_2B},
 292         {"IO Config Register 14-15", 0x78A, NI_660x_READ_WRITE, DATA_2B},
 293         {"IO Config Register 16-17", 0x78C, NI_660x_READ_WRITE, DATA_2B},
 294         {"IO Config Register 18-19", 0x78E, NI_660x_READ_WRITE, DATA_2B},
 295         {"IO Config Register 20-21", 0x790, NI_660x_READ_WRITE, DATA_2B},
 296         {"IO Config Register 22-23", 0x792, NI_660x_READ_WRITE, DATA_2B},
 297         {"IO Config Register 24-25", 0x794, NI_660x_READ_WRITE, DATA_2B},
 298         {"IO Config Register 26-27", 0x796, NI_660x_READ_WRITE, DATA_2B},
 299         {"IO Config Register 28-29", 0x798, NI_660x_READ_WRITE, DATA_2B},
 300         {"IO Config Register 30-31", 0x79A, NI_660x_READ_WRITE, DATA_2B},
 301         {"IO Config Register 32-33", 0x79C, NI_660x_READ_WRITE, DATA_2B},
 302         {"IO Config Register 34-35", 0x79E, NI_660x_READ_WRITE, DATA_2B},
 303         {"IO Config Register 36-37", 0x7A0, NI_660x_READ_WRITE, DATA_2B},
 304         {"IO Config Register 38-39", 0x7A2, NI_660x_READ_WRITE, DATA_2B}
 305 };
 306
 307 /* kind of ENABLE for the second counter */
 308 enum clock_config_register_bits {
 309         CounterSwap = 0x1 << 21
 310 };
 311
 312 /* ioconfigreg */
 313 static inline unsigned ioconfig_bitshift(unsigned pfi_channel)
 314 {
 315         if (pfi_channel % 2)
 316                 return 0;
 317         else
 318                 return 8;
 319 }
 320
 321 static inline unsigned pfi_output_select_mask(unsigned pfi_channel)
 322 {
 323         return 0x3 << ioconfig_bitshift(pfi_channel);
 324 }
 325
 326 static inline unsigned pfi_output_select_bits(unsigned pfi_channel,
 327                                               unsigned output_select)
 328 {
 329         return (output_select & 0x3) << ioconfig_bitshift(pfi_channel);
 330 }
 331
 332 static inline unsigned pfi_input_select_mask(unsigned pfi_channel)
 333 {
 334         return 0x7 << (4 + ioconfig_bitshift(pfi_channel));
 335 }
 336
 337 static inline unsigned pfi_input_select_bits(unsigned pfi_channel,
 338                                              unsigned input_select)
 339 {
 340         return (input_select & 0x7) << (4 + ioconfig_bitshift(pfi_channel));
 341 }
 342
 343 /* dma configuration register bits */
 344 static inline unsigned dma_select_mask(unsigned dma_channel)
 345 {
 346         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
 347         return 0x1f << (8 * dma_channel);
 348 }
 349
 350 enum dma_selection {
 351         dma_selection_none = 0x1f,
 352 };
 353 static inline unsigned dma_selection_counter(unsigned counter_index)
 354 {
 355         BUG_ON(counter_index >= counters_per_chip);
 356         return counter_index;
 357 }
 358
 359 static inline unsigned dma_select_bits(unsigned dma_channel, unsigned selection)
 360 {
 361         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
 362         return (selection << (8 * dma_channel)) & dma_select_mask(dma_channel);
 363 }
 364
 365 static inline unsigned dma_reset_bit(unsigned dma_channel)
 366 {
 367         BUG_ON(dma_channel >= MAX_DMA_CHANNEL);
 368         return 0x80 << (8 * dma_channel);
 369 }
 370
 371 enum global_interrupt_status_register_bits {
 372         Counter_0_Int_Bit = 0x100,
 373         Counter_1_Int_Bit = 0x200,
 374         Counter_2_Int_Bit = 0x400,
 375         Counter_3_Int_Bit = 0x800,
 376         Cascade_Int_Bit = 0x20000000,
 377         Global_Int_Bit = 0x80000000
 378 };
 379
 380 enum global_interrupt_config_register_bits {
 381         Cascade_Int_Enable_Bit = 0x20000000,
 382         Global_Int_Polarity_Bit = 0x40000000,
 383         Global_Int_Enable_Bit = 0x80000000
 384 };
 385
 386 /* Offset of the GPCT chips from the base-address of the card */
 387 /* First chip is at base-address + 0x00, etc. */
 388 static const unsigned GPCT_OFFSET[2] = { 0x0, 0x800 };
 389
 390 enum ni_660x_boardid {
 391         BOARD_PCI6601,
 392         BOARD_PCI6602,
 393         BOARD_PXI6602,
 394         BOARD_PXI6608,
 395         BOARD_PXI6624
 396 };
 397
 398 struct ni_660x_board {
 399         const char *name;
 400         unsigned n_chips;       /* total number of TIO chips */
 401 };
 402
 403 static const struct ni_660x_board ni_660x_boards[] = {
 404         [BOARD_PCI6601] = {
 405                 .name           = "PCI-6601",
 406                 .n_chips        = 1,
 407         },
 408         [BOARD_PCI6602] = {
 409                 .name           = "PCI-6602",
 410                 .n_chips        = 2,
 411         },
 412         [BOARD_PXI6602] = {
 413                 .name           = "PXI-6602",
 414                 .n_chips        = 2,
 415         },
 416         [BOARD_PXI6608] = {
 417                 .name           = "PXI-6608",
 418                 .n_chips        = 2,
 419         },
 420         [BOARD_PXI6624] = {
 421                 .name           = "PXI-6624",
 422                 .n_chips        = 2,
 423         },
 424 };
 425
 426 #define NI_660X_MAX_NUM_CHIPS 2
 427 #define NI_660X_MAX_NUM_COUNTERS (NI_660X_MAX_NUM_CHIPS * counters_per_chip)
 428
 429 struct ni_660x_private {
 430         struct mite_struct *mite;
 431         struct ni_gpct_device *counter_dev;
 432         uint64_t pfi_direction_bits;
 433         struct mite_dma_descriptor_ring
 434         *mite_rings[NI_660X_MAX_NUM_CHIPS][counters_per_chip];
 435         spinlock_t mite_channel_lock;
 436         /* interrupt_lock prevents races between interrupt and comedi_poll */
 437         spinlock_t interrupt_lock;
 438         unsigned dma_configuration_soft_copies[NI_660X_MAX_NUM_CHIPS];
 439         spinlock_t soft_reg_copy_lock;
 440         unsigned short pfi_output_selects[NUM_PFI_CHANNELS];
 441 };
 442
 443 static inline unsigned ni_660x_num_counters(struct comedi_device *dev)
 444 {
 445         const struct ni_660x_board *board = comedi_board(dev);
 446
 447         return board->n_chips * counters_per_chip;
 448 }
 449
 450 static enum NI_660x_Register ni_gpct_to_660x_register(enum ni_gpct_register reg)
 451 {
 452         enum NI_660x_Register ni_660x_register;
 453         switch (reg) {
 454         case NITIO_G0_Autoincrement_Reg:
 455                 ni_660x_register = G0AutoincrementRegister;
 456                 break;
 457         case NITIO_G1_Autoincrement_Reg:
 458                 ni_660x_register = G1AutoincrementRegister;
 459                 break;
 460         case NITIO_G2_Autoincrement_Reg:
 461                 ni_660x_register = G2AutoincrementRegister;
 462                 break;
 463         case NITIO_G3_Autoincrement_Reg:
 464                 ni_660x_register = G3AutoincrementRegister;
 465                 break;
 466         case NITIO_G0_Command_Reg:
 467                 ni_660x_register = G0CommandRegister;
 468                 break;
 469         case NITIO_G1_Command_Reg:
 470                 ni_660x_register = G1CommandRegister;
 471                 break;
 472         case NITIO_G2_Command_Reg:
 473                 ni_660x_register = G2CommandRegister;
 474                 break;
 475         case NITIO_G3_Command_Reg:
 476                 ni_660x_register = G3CommandRegister;
 477                 break;
 478         case NITIO_G0_HW_Save_Reg:
 479                 ni_660x_register = G0HWSaveRegister;
 480                 break;
 481         case NITIO_G1_HW_Save_Reg:
 482                 ni_660x_register = G1HWSaveRegister;
 483                 break;
 484         case NITIO_G2_HW_Save_Reg:
 485                 ni_660x_register = G2HWSaveRegister;
 486                 break;
 487         case NITIO_G3_HW_Save_Reg:
 488                 ni_660x_register = G3HWSaveRegister;
 489                 break;
 490         case NITIO_G0_SW_Save_Reg:
 491                 ni_660x_register = G0SWSaveRegister;
 492                 break;
 493         case NITIO_G1_SW_Save_Reg:
 494                 ni_660x_register = G1SWSaveRegister;
 495                 break;
 496         case NITIO_G2_SW_Save_Reg:
 497                 ni_660x_register = G2SWSaveRegister;
 498                 break;
 499         case NITIO_G3_SW_Save_Reg:
 500                 ni_660x_register = G3SWSaveRegister;
 501                 break;
 502         case NITIO_G0_Mode_Reg:
 503                 ni_660x_register = G0ModeRegister;
 504                 break;
 505         case NITIO_G1_Mode_Reg:
 506                 ni_660x_register = G1ModeRegister;
 507                 break;
 508         case NITIO_G2_Mode_Reg:
 509                 ni_660x_register = G2ModeRegister;
 510                 break;
 511         case NITIO_G3_Mode_Reg:
 512                 ni_660x_register = G3ModeRegister;
 513                 break;
 514         case NITIO_G0_LoadA_Reg:
 515                 ni_660x_register = G0LoadARegister;
 516                 break;
 517         case NITIO_G1_LoadA_Reg:
 518                 ni_660x_register = G1LoadARegister;
 519                 break;
 520         case NITIO_G2_LoadA_Reg:
 521                 ni_660x_register = G2LoadARegister;
 522                 break;
 523         case NITIO_G3_LoadA_Reg:
 524                 ni_660x_register = G3LoadARegister;
 525                 break;
 526         case NITIO_G0_LoadB_Reg:
 527                 ni_660x_register = G0LoadBRegister;
 528                 break;
 529         case NITIO_G1_LoadB_Reg:
 530                 ni_660x_register = G1LoadBRegister;
 531                 break;
 532         case NITIO_G2_LoadB_Reg:
 533                 ni_660x_register = G2LoadBRegister;
 534                 break;
 535         case NITIO_G3_LoadB_Reg:
 536                 ni_660x_register = G3LoadBRegister;
 537                 break;
 538         case NITIO_G0_Input_Select_Reg:
 539                 ni_660x_register = G0InputSelectRegister;
 540                 break;
 541         case NITIO_G1_Input_Select_Reg:
 542                 ni_660x_register = G1InputSelectRegister;
 543                 break;
 544         case NITIO_G2_Input_Select_Reg:
 545                 ni_660x_register = G2InputSelectRegister;
 546                 break;
 547         case NITIO_G3_Input_Select_Reg:
 548                 ni_660x_register = G3InputSelectRegister;
 549                 break;
 550         case NITIO_G01_Status_Reg:
 551                 ni_660x_register = G01StatusRegister;
 552                 break;
 553         case NITIO_G23_Status_Reg:
 554                 ni_660x_register = G23StatusRegister;
 555                 break;
 556         case NITIO_G01_Joint_Reset_Reg:
 557                 ni_660x_register = G01JointResetRegister;
 558                 break;
 559         case NITIO_G23_Joint_Reset_Reg:
 560                 ni_660x_register = G23JointResetRegister;
 561                 break;
 562         case NITIO_G01_Joint_Status1_Reg:
 563                 ni_660x_register = G01JointStatus1Register;
 564                 break;
 565         case NITIO_G23_Joint_Status1_Reg:
 566                 ni_660x_register = G23JointStatus1Register;
 567                 break;
 568         case NITIO_G01_Joint_Status2_Reg:
 569                 ni_660x_register = G01JointStatus2Register;
 570                 break;
 571         case NITIO_G23_Joint_Status2_Reg:
 572                 ni_660x_register = G23JointStatus2Register;
 573                 break;
 574         case NITIO_G0_Counting_Mode_Reg:
 575                 ni_660x_register = G0CountingModeRegister;
 576                 break;
 577         case NITIO_G1_Counting_Mode_Reg:
 578                 ni_660x_register = G1CountingModeRegister;
 579                 break;
 580         case NITIO_G2_Counting_Mode_Reg:
 581                 ni_660x_register = G2CountingModeRegister;
 582                 break;
 583         case NITIO_G3_Counting_Mode_Reg:
 584                 ni_660x_register = G3CountingModeRegister;
 585                 break;
 586         case NITIO_G0_Second_Gate_Reg:
 587                 ni_660x_register = G0SecondGateRegister;
 588                 break;
 589         case NITIO_G1_Second_Gate_Reg:
 590                 ni_660x_register = G1SecondGateRegister;
 591                 break;
 592         case NITIO_G2_Second_Gate_Reg:
 593                 ni_660x_register = G2SecondGateRegister;
 594                 break;
 595         case NITIO_G3_Second_Gate_Reg:
 596                 ni_660x_register = G3SecondGateRegister;
 597                 break;
 598         case NITIO_G0_DMA_Config_Reg:
 599                 ni_660x_register = G0DMAConfigRegister;
 600                 break;
 601         case NITIO_G0_DMA_Status_Reg:
 602                 ni_660x_register = G0DMAStatusRegister;
 603                 break;
 604         case NITIO_G1_DMA_Config_Reg:
 605                 ni_660x_register = G1DMAConfigRegister;
 606                 break;
 607         case NITIO_G1_DMA_Status_Reg:
 608                 ni_660x_register = G1DMAStatusRegister;
 609                 break;
 610         case NITIO_G2_DMA_Config_Reg:
 611                 ni_660x_register = G2DMAConfigRegister;
 612                 break;
 613         case NITIO_G2_DMA_Status_Reg:
 614                 ni_660x_register = G2DMAStatusRegister;
 615                 break;
 616         case NITIO_G3_DMA_Config_Reg:
 617                 ni_660x_register = G3DMAConfigRegister;
 618                 break;
 619         case NITIO_G3_DMA_Status_Reg:
 620                 ni_660x_register = G3DMAStatusRegister;
 621                 break;
 622         case NITIO_G0_Interrupt_Acknowledge_Reg:
 623                 ni_660x_register = G0InterruptAcknowledge;
 624                 break;
 625         case NITIO_G1_Interrupt_Acknowledge_Reg:
 626                 ni_660x_register = G1InterruptAcknowledge;
 627                 break;
 628         case NITIO_G2_Interrupt_Acknowledge_Reg:
 629                 ni_660x_register = G2InterruptAcknowledge;
 630                 break;
 631         case NITIO_G3_Interrupt_Acknowledge_Reg:
 632                 ni_660x_register = G3InterruptAcknowledge;
 633                 break;
 634         case NITIO_G0_Status_Reg:
 635                 ni_660x_register = G0StatusRegister;
 636                 break;
 637         case NITIO_G1_Status_Reg:
 638                 ni_660x_register = G1StatusRegister;
 639                 break;
 640         case NITIO_G2_Status_Reg:
 641                 ni_660x_register = G2StatusRegister;
 642                 break;
 643         case NITIO_G3_Status_Reg:
 644                 ni_660x_register = G3StatusRegister;
 645                 break;
 646         case NITIO_G0_Interrupt_Enable_Reg:
 647                 ni_660x_register = G0InterruptEnable;
 648                 break;
 649         case NITIO_G1_Interrupt_Enable_Reg:
 650                 ni_660x_register = G1InterruptEnable;
 651                 break;
 652         case NITIO_G2_Interrupt_Enable_Reg:
 653                 ni_660x_register = G2InterruptEnable;
 654                 break;
 655         case NITIO_G3_Interrupt_Enable_Reg:
 656                 ni_660x_register = G3InterruptEnable;
 657                 break;
 658         default:
 659                 BUG();
 660                 return 0;
 661                 break;
 662         }
 663         return ni_660x_register;
 664 }
 665
 666 static inline void ni_660x_write_register(struct comedi_device *dev,
 667                                           unsigned chip_index, unsigned bits,
 668                                           enum NI_660x_Register reg)
 669 {
 670         struct ni_660x_private *devpriv = dev->private;
 671         void __iomem *write_address =
 672             devpriv->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
 673             registerData[reg].offset;
 674
 675         switch (registerData[reg].size) {
 676         case DATA_2B:
 677                 writew(bits, write_address);
 678                 break;
 679         case DATA_4B:
 680                 writel(bits, write_address);
 681                 break;
 682         default:
 683                 BUG();
 684                 break;
 685         }
 686 }
 687
 688 static inline unsigned ni_660x_read_register(struct comedi_device *dev,
 689                                              unsigned chip_index,
 690                                              enum NI_660x_Register reg)
 691 {
 692         struct ni_660x_private *devpriv = dev->private;
 693         void __iomem *read_address =
 694             devpriv->mite->daq_io_addr + GPCT_OFFSET[chip_index] +
 695             registerData[reg].offset;
 696
 697         switch (registerData[reg].size) {
 698         case DATA_2B:
 699                 return readw(read_address);
 700                 break;
 701         case DATA_4B:
 702                 return readl(read_address);
 703                 break;
 704         default:
 705                 BUG();
 706                 break;
 707         }
 708         return 0;
 709 }
 710
 711 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
 712                                    enum ni_gpct_register reg)
 713 {
 714         struct comedi_device *dev = counter->counter_dev->dev;
 715         enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
 716         ni_660x_write_register(dev, counter->chip_index, bits,
 717                                ni_660x_register);
 718 }
 719
 720 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
 721                                       enum ni_gpct_register reg)
 722 {
 723         struct comedi_device *dev = counter->counter_dev->dev;
 724         enum NI_660x_Register ni_660x_register = ni_gpct_to_660x_register(reg);
 725         return ni_660x_read_register(dev, counter->chip_index,
 726                                      ni_660x_register);
 727 }
 728
 729 static inline struct mite_dma_descriptor_ring *mite_ring(struct ni_660x_private
 730                                                          *priv,
 731                                                          struct ni_gpct
 732                                                          *counter)
 733 {
 734         return priv->mite_rings[counter->chip_index][counter->counter_index];
 735 }
 736
 737 static inline void ni_660x_set_dma_channel(struct comedi_device *dev,
 738                                            unsigned mite_channel,
 739                                            struct ni_gpct *counter)
 740 {
 741         struct ni_660x_private *devpriv = dev->private;
 742         unsigned long flags;
 743
 744         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 745         devpriv->dma_configuration_soft_copies[counter->chip_index] &=
 746             ~dma_select_mask(mite_channel);
 747         devpriv->dma_configuration_soft_copies[counter->chip_index] |=
 748             dma_select_bits(mite_channel,
 749                             dma_selection_counter(counter->counter_index));
 750         ni_660x_write_register(dev, counter->chip_index,
 751                                devpriv->dma_configuration_soft_copies
 752                                [counter->chip_index] |
 753                                dma_reset_bit(mite_channel), DMAConfigRegister);
 754         mmiowb();
 755         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 756 }
 757
 758 static inline void ni_660x_unset_dma_channel(struct comedi_device *dev,
 759                                              unsigned mite_channel,
 760                                              struct ni_gpct *counter)
 761 {
 762         struct ni_660x_private *devpriv = dev->private;
 763         unsigned long flags;
 764
 765         spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
 766         devpriv->dma_configuration_soft_copies[counter->chip_index] &=
 767             ~dma_select_mask(mite_channel);
 768         devpriv->dma_configuration_soft_copies[counter->chip_index] |=
 769             dma_select_bits(mite_channel, dma_selection_none);
 770         ni_660x_write_register(dev, counter->chip_index,
 771                                devpriv->dma_configuration_soft_copies
 772                                [counter->chip_index], DMAConfigRegister);
 773         mmiowb();
 774         spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
 775 }
 776
 777 static int ni_660x_request_mite_channel(struct comedi_device *dev,
 778                                         struct ni_gpct *counter,
 779                                         enum comedi_io_direction direction)
 780 {
 781         struct ni_660x_private *devpriv = dev->private;
 782         unsigned long flags;
 783         struct mite_channel *mite_chan;
 784
 785         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 786         BUG_ON(counter->mite_chan);
 787         mite_chan = mite_request_channel(devpriv->mite,
 788                                          mite_ring(devpriv, counter));
 789         if (mite_chan == NULL) {
 790                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 791                 comedi_error(dev,
 792                              "failed to reserve mite dma channel for counter.");
 793                 return -EBUSY;
 794         }
 795         mite_chan->dir = direction;
 796         ni_tio_set_mite_channel(counter, mite_chan);
 797         ni_660x_set_dma_channel(dev, mite_chan->channel, counter);
 798         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 799         return 0;
 800 }
 801
 802 static void ni_660x_release_mite_channel(struct comedi_device *dev,
 803                                          struct ni_gpct *counter)
 804 {
 805         struct ni_660x_private *devpriv = dev->private;
 806         unsigned long flags;
 807
 808         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 809         if (counter->mite_chan) {
 810                 struct mite_channel *mite_chan = counter->mite_chan;
 811
 812                 ni_660x_unset_dma_channel(dev, mite_chan->channel, counter);
 813                 ni_tio_set_mite_channel(counter, NULL);
 814                 mite_release_channel(mite_chan);
 815         }
 816         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 817 }
 818
 819 static int ni_660x_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
 820 {
 821         int retval;
 822
 823         struct ni_gpct *counter = subdev_to_counter(s);
 824 /* const struct comedi_cmd *cmd = &s->async->cmd; */
 825
 826         retval = ni_660x_request_mite_channel(dev, counter, COMEDI_INPUT);
 827         if (retval) {
 828                 comedi_error(dev,
 829                              "no dma channel available for use by counter");
 830                 return retval;
 831         }
 832         ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
 833         retval = ni_tio_cmd(counter, s->async);
 834
 835         return retval;
 836 }
 837
 838 static int ni_660x_cmdtest(struct comedi_device *dev,
 839                            struct comedi_subdevice *s, struct comedi_cmd *cmd)
 840 {
 841         struct ni_gpct *counter = subdev_to_counter(s);
 842
 843         return ni_tio_cmdtest(counter, cmd);
 844 }
 845
 846 static int ni_660x_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
 847 {
 848         struct ni_gpct *counter = subdev_to_counter(s);
 849         int retval;
 850
 851         retval = ni_tio_cancel(counter);
 852         ni_660x_release_mite_channel(dev, counter);
 853         return retval;
 854 }
 855
 856 static void set_tio_counterswap(struct comedi_device *dev, int chipset)
 857 {
 858         /* See P. 3.5 of the Register-Level Programming manual.  The
 859            CounterSwap bit has to be set on the second chip, otherwise
 860            it will try to use the same pins as the first chip.
 861          */
 862         if (chipset)
 863                 ni_660x_write_register(dev, chipset, CounterSwap,
 864                                        ClockConfigRegister);
 865         else
 866                 ni_660x_write_register(dev, chipset, 0, ClockConfigRegister);
 867 }
 868
 869 static void ni_660x_handle_gpct_interrupt(struct comedi_device *dev,
 870                                           struct comedi_subdevice *s)
 871 {
 872         ni_tio_handle_interrupt(subdev_to_counter(s), s);
 873         if (s->async->events) {
 874                 if (s->async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR |
 875                                         COMEDI_CB_OVERFLOW)) {
 876                         ni_660x_cancel(dev, s);
 877                 }
 878                 comedi_event(dev, s);
 879         }
 880 }
 881
 882 static irqreturn_t ni_660x_interrupt(int irq, void *d)
 883 {
 884         struct comedi_device *dev = d;
 885         struct ni_660x_private *devpriv = dev->private;
 886         struct comedi_subdevice *s;
 887         unsigned i;
 888         unsigned long flags;
 889
 890         if (!dev->attached)
 891                 return IRQ_NONE;
 892         /* lock to avoid race with comedi_poll */
 893         spin_lock_irqsave(&devpriv->interrupt_lock, flags);
 894         smp_mb();
 895         for (i = 0; i < ni_660x_num_counters(dev); ++i) {
 896                 s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)];
 897                 ni_660x_handle_gpct_interrupt(dev, s);
 898         }
 899         spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
 900         return IRQ_HANDLED;
 901 }
 902
 903 static int ni_660x_input_poll(struct comedi_device *dev,
 904                               struct comedi_subdevice *s)
 905 {
 906         struct ni_660x_private *devpriv = dev->private;
 907         unsigned long flags;
 908
 909         /* lock to avoid race with comedi_poll */
 910         spin_lock_irqsave(&devpriv->interrupt_lock, flags);
 911         mite_sync_input_dma(subdev_to_counter(s)->mite_chan, s->async);
 912         spin_unlock_irqrestore(&devpriv->interrupt_lock, flags);
 913         return comedi_buf_read_n_available(s->async);
 914 }
 915
 916 static int ni_660x_buf_change(struct comedi_device *dev,
 917                               struct comedi_subdevice *s,
 918                               unsigned long new_size)
 919 {
 920         struct ni_660x_private *devpriv = dev->private;
 921         int ret;
 922
 923         ret = mite_buf_change(mite_ring(devpriv, subdev_to_counter(s)),
 924                               s->async);
 925         if (ret < 0)
 926                 return ret;
 927
 928         return 0;
 929 }
 930
 931 static int ni_660x_allocate_private(struct comedi_device *dev)
 932 {
 933         struct ni_660x_private *devpriv;
 934         unsigned i;
 935
 936         devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
 937         if (!devpriv)
 938                 return -ENOMEM;
 939         dev->private = devpriv;
 940
 941         spin_lock_init(&devpriv->mite_channel_lock);
 942         spin_lock_init(&devpriv->interrupt_lock);
 943         spin_lock_init(&devpriv->soft_reg_copy_lock);
 944         for (i = 0; i < NUM_PFI_CHANNELS; ++i)
 945                 devpriv->pfi_output_selects[i] = pfi_output_select_counter;
 946
 947         return 0;
 948 }
 949
 950 static int ni_660x_alloc_mite_rings(struct comedi_device *dev)
 951 {
 952         const struct ni_660x_board *board = comedi_board(dev);
 953         struct ni_660x_private *devpriv = dev->private;
 954         unsigned i;
 955         unsigned j;
 956
 957         for (i = 0; i < board->n_chips; ++i) {
 958                 for (j = 0; j < counters_per_chip; ++j) {
 959                         devpriv->mite_rings[i][j] =
 960                             mite_alloc_ring(devpriv->mite);
 961                         if (devpriv->mite_rings[i][j] == NULL)
 962                                 return -ENOMEM;
 963                 }
 964         }
 965         return 0;
 966 }
 967
 968 static void ni_660x_free_mite_rings(struct comedi_device *dev)
 969 {
 970         const struct ni_660x_board *board = comedi_board(dev);
 971         struct ni_660x_private *devpriv = dev->private;
 972         unsigned i;
 973         unsigned j;
 974
 975         for (i = 0; i < board->n_chips; ++i) {
 976                 for (j = 0; j < counters_per_chip; ++j)
 977                         mite_free_ring(devpriv->mite_rings[i][j]);
 978         }
 979 }
 980
 981 static int
 982 ni_660x_GPCT_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
 983                    struct comedi_insn *insn, unsigned int *data)
 984 {
 985         return ni_tio_rinsn(subdev_to_counter(s), insn, data);
 986 }
 987
 988 static void init_tio_chip(struct comedi_device *dev, int chipset)
 989 {
 990         struct ni_660x_private *devpriv = dev->private;
 991         unsigned i;
 992
 993         /*  init dma configuration register */
 994         devpriv->dma_configuration_soft_copies[chipset] = 0;
 995         for (i = 0; i < MAX_DMA_CHANNEL; ++i) {
 996                 devpriv->dma_configuration_soft_copies[chipset] |=
 997                     dma_select_bits(i, dma_selection_none) & dma_select_mask(i);
 998         }
 999         ni_660x_write_register(dev, chipset,
1000                                devpriv->dma_configuration_soft_copies[chipset],
1001                                DMAConfigRegister);
1002         for (i = 0; i < NUM_PFI_CHANNELS; ++i)
1003                 ni_660x_write_register(dev, chipset, 0, IOConfigReg(i));
1004 }
1005
1006 static int
1007 ni_660x_GPCT_insn_config(struct comedi_device *dev, struct comedi_subdevice *s,
1008                          struct comedi_insn *insn, unsigned int *data)
1009 {
1010         return ni_tio_insn_config(subdev_to_counter(s), insn, data);
1011 }
1012
1013 static int ni_660x_GPCT_winsn(struct comedi_device *dev,
1014                               struct comedi_subdevice *s,
1015                               struct comedi_insn *insn, unsigned int *data)
1016 {
1017         return ni_tio_winsn(subdev_to_counter(s), insn, data);
1018 }
1019
1020 static int ni_660x_dio_insn_bits(struct comedi_device *dev,
1021                                  struct comedi_subdevice *s,
1022                                  struct comedi_insn *insn, unsigned int *data)
1023 {
1024         unsigned base_bitfield_channel = CR_CHAN(insn->chanspec);
1025
1026         /*  Check if we have to write some bits */
1027         if (data[0]) {
1028                 s->state &= ~(data[0] << base_bitfield_channel);
1029                 s->state |= (data[0] & data[1]) << base_bitfield_channel;
1030                 /* Write out the new digital output lines */
1031                 ni_660x_write_register(dev, 0, s->state, DIO32Output);
1032         }
1033         /* on return, data[1] contains the value of the digital
1034          * input and output lines. */
1035         data[1] =
1036             (ni_660x_read_register(dev, 0,
1037                                    DIO32Input) >> base_bitfield_channel);
1038         return insn->n;
1039 }
1040
1041 static void ni_660x_select_pfi_output(struct comedi_device *dev,
1042                                       unsigned pfi_channel,
1043                                       unsigned output_select)
1044 {
1045         const struct ni_660x_board *board = comedi_board(dev);
1046         static const unsigned counter_4_7_first_pfi = 8;
1047         static const unsigned counter_4_7_last_pfi = 23;
1048         unsigned active_chipset = 0;
1049         unsigned idle_chipset = 0;
1050         unsigned active_bits;
1051         unsigned idle_bits;
1052
1053         if (board->n_chips > 1) {
1054                 if (output_select == pfi_output_select_counter &&
1055                     pfi_channel >= counter_4_7_first_pfi &&
1056                     pfi_channel <= counter_4_7_last_pfi) {
1057                         active_chipset = 1;
1058                         idle_chipset = 0;
1059                 } else {
1060                         active_chipset = 0;
1061                         idle_chipset = 1;
1062                 }
1063         }
1064
1065         if (idle_chipset != active_chipset) {
1066                 idle_bits =
1067                     ni_660x_read_register(dev, idle_chipset,
1068                                           IOConfigReg(pfi_channel));
1069                 idle_bits &= ~pfi_output_select_mask(pfi_channel);
1070                 idle_bits |=
1071                     pfi_output_select_bits(pfi_channel,
1072                                            pfi_output_select_high_Z);
1073                 ni_660x_write_register(dev, idle_chipset, idle_bits,
1074                                        IOConfigReg(pfi_channel));
1075         }
1076
1077         active_bits =
1078             ni_660x_read_register(dev, active_chipset,
1079                                   IOConfigReg(pfi_channel));
1080         active_bits &= ~pfi_output_select_mask(pfi_channel);
1081         active_bits |= pfi_output_select_bits(pfi_channel, output_select);
1082         ni_660x_write_register(dev, active_chipset, active_bits,
1083                                IOConfigReg(pfi_channel));
1084 }
1085
1086 static int ni_660x_set_pfi_routing(struct comedi_device *dev, unsigned chan,
1087                                    unsigned source)
1088 {
1089         struct ni_660x_private *devpriv = dev->private;
1090
1091         if (source > num_pfi_output_selects)
1092                 return -EINVAL;
1093         if (source == pfi_output_select_high_Z)
1094                 return -EINVAL;
1095         if (chan < min_counter_pfi_chan) {
1096                 if (source == pfi_output_select_counter)
1097                         return -EINVAL;
1098         } else if (chan > max_dio_pfi_chan) {
1099                 if (source == pfi_output_select_do)
1100                         return -EINVAL;
1101         }
1102
1103         devpriv->pfi_output_selects[chan] = source;
1104         if (devpriv->pfi_direction_bits & (((uint64_t) 1) << chan))
1105                 ni_660x_select_pfi_output(dev, chan,
1106                                           devpriv->pfi_output_selects[chan]);
1107         return 0;
1108 }
1109
1110 static int ni_660x_dio_insn_config(struct comedi_device *dev,
1111                                    struct comedi_subdevice *s,
1112                                    struct comedi_insn *insn,
1113                                    unsigned int *data)
1114 {
1115         struct ni_660x_private *devpriv = dev->private;
1116         unsigned int chan = CR_CHAN(insn->chanspec);
1117         uint64_t bit = 1ULL << chan;
1118         unsigned int val;
1119         int ret;
1120
1121         switch (data[0]) {
1122         case INSN_CONFIG_DIO_OUTPUT:
1123                 devpriv->pfi_direction_bits |= bit;
1124                 ni_660x_select_pfi_output(dev, chan,
1125                                           devpriv->pfi_output_selects[chan]);
1126                 break;
1127
1128         case INSN_CONFIG_DIO_INPUT:
1129                 devpriv->pfi_direction_bits &= ~bit;
1130                 ni_660x_select_pfi_output(dev, chan, pfi_output_select_high_Z);
1131                 break;
1132
1133         case INSN_CONFIG_DIO_QUERY:
1134                 data[1] = (devpriv->pfi_direction_bits & bit) ? COMEDI_OUTPUT
1135                                                               : COMEDI_INPUT;
1136                 break;
1137
1138         case INSN_CONFIG_SET_ROUTING:
1139                 ret = ni_660x_set_pfi_routing(dev, chan, data[1]);
1140                 if (ret)
1141                         return ret;
1142                 break;
1143
1144         case INSN_CONFIG_GET_ROUTING:
1145                 data[1] = devpriv->pfi_output_selects[chan];
1146                 break;
1147
1148         case INSN_CONFIG_FILTER:
1149                 val = ni_660x_read_register(dev, 0, IOConfigReg(chan));
1150                 val &= ~pfi_input_select_mask(chan);
1151                 val |= pfi_input_select_bits(chan, data[1]);
1152                 ni_660x_write_register(dev, 0, val, IOConfigReg(chan));
1153                 break;
1154
1155         default:
1156                 return -EINVAL;
1157         }
1158
1159         return insn->n;
1160 }
1161
1162 static int ni_660x_auto_attach(struct comedi_device *dev,
1163                                unsigned long context)
1164 {
1165         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1166         const struct ni_660x_board *board = NULL;
1167         struct ni_660x_private *devpriv;
1168         struct comedi_subdevice *s;
1169         int ret;
1170         unsigned i;
1171         unsigned global_interrupt_config_bits;
1172
1173         if (context < ARRAY_SIZE(ni_660x_boards))
1174                 board = &ni_660x_boards[context];
1175         if (!board)
1176                 return -ENODEV;
1177         dev->board_ptr = board;
1178         dev->board_name = board->name;
1179
1180         ret = comedi_pci_enable(dev);
1181         if (ret)
1182                 return ret;
1183
1184         ret = ni_660x_allocate_private(dev);
1185         if (ret < 0)
1186                 return ret;
1187         devpriv = dev->private;
1188
1189         devpriv->mite = mite_alloc(pcidev);
1190         if (!devpriv->mite)
1191                 return -ENOMEM;
1192
1193         ret = mite_setup2(devpriv->mite, 1);
1194         if (ret < 0) {
1195                 dev_warn(dev->class_dev, "error setting up mite\n");
1196                 return ret;
1197         }
1198
1199         ret = ni_660x_alloc_mite_rings(dev);
1200         if (ret < 0)
1201                 return ret;
1202
1203         ret = comedi_alloc_subdevices(dev, 2 + NI_660X_MAX_NUM_COUNTERS);
1204         if (ret)
1205                 return ret;
1206
1207         s = &dev->subdevices[0];
1208         /* Old GENERAL-PURPOSE COUNTER/TIME (GPCT) subdevice, no longer used */
1209         s->type = COMEDI_SUBD_UNUSED;
1210
1211         s = &dev->subdevices[NI_660X_DIO_SUBDEV];
1212         /* DIGITAL I/O SUBDEVICE */
1213         s->type = COMEDI_SUBD_DIO;
1214         s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1215         s->n_chan = NUM_PFI_CHANNELS;
1216         s->maxdata = 1;
1217         s->range_table = &range_digital;
1218         s->insn_bits = ni_660x_dio_insn_bits;
1219         s->insn_config = ni_660x_dio_insn_config;
1220         s->io_bits = 0;         /* all bits default to input */
1221         /*  we use the ioconfig registers to control dio direction, so zero
1222         output enables in stc dio control reg */
1223         ni_660x_write_register(dev, 0, 0, STCDIOControl);
1224
1225         devpriv->counter_dev = ni_gpct_device_construct(dev,
1226                                                      &ni_gpct_write_register,
1227                                                      &ni_gpct_read_register,
1228                                                      ni_gpct_variant_660x,
1229                                                      ni_660x_num_counters
1230                                                      (dev));
1231         if (devpriv->counter_dev == NULL)
1232                 return -ENOMEM;
1233         for (i = 0; i < NI_660X_MAX_NUM_COUNTERS; ++i) {
1234                 s = &dev->subdevices[NI_660X_GPCT_SUBDEV(i)];
1235                 if (i < ni_660x_num_counters(dev)) {
1236                         s->type = COMEDI_SUBD_COUNTER;
1237                         s->subdev_flags =
1238                             SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL |
1239                             SDF_CMD_READ /* | SDF_CMD_WRITE */ ;
1240                         s->n_chan = 3;
1241                         s->maxdata = 0xffffffff;
1242                         s->insn_read = ni_660x_GPCT_rinsn;
1243                         s->insn_write = ni_660x_GPCT_winsn;
1244                         s->insn_config = ni_660x_GPCT_insn_config;
1245                         s->do_cmd = &ni_660x_cmd;
1246                         s->len_chanlist = 1;
1247                         s->do_cmdtest = &ni_660x_cmdtest;
1248                         s->cancel = &ni_660x_cancel;
1249                         s->poll = &ni_660x_input_poll;
1250                         s->async_dma_dir = DMA_BIDIRECTIONAL;
1251                         s->buf_change = &ni_660x_buf_change;
1252                         s->private = &devpriv->counter_dev->counters[i];
1253
1254                         devpriv->counter_dev->counters[i].chip_index =
1255                             i / counters_per_chip;
1256                         devpriv->counter_dev->counters[i].counter_index =
1257                             i % counters_per_chip;
1258                 } else {
1259                         s->type = COMEDI_SUBD_UNUSED;
1260                 }
1261         }
1262         for (i = 0; i < board->n_chips; ++i)
1263                 init_tio_chip(dev, i);
1264
1265         for (i = 0; i < ni_660x_num_counters(dev); ++i)
1266                 ni_tio_init_counter(&devpriv->counter_dev->counters[i]);
1267
1268         for (i = 0; i < NUM_PFI_CHANNELS; ++i) {
1269                 if (i < min_counter_pfi_chan)
1270                         ni_660x_set_pfi_routing(dev, i, pfi_output_select_do);
1271                 else
1272                         ni_660x_set_pfi_routing(dev, i,
1273                                                 pfi_output_select_counter);
1274                 ni_660x_select_pfi_output(dev, i, pfi_output_select_high_Z);
1275         }
1276         /* to be safe, set counterswap bits on tio chips after all the counter
1277            outputs have been set to high impedance mode */
1278         for (i = 0; i < board->n_chips; ++i)
1279                 set_tio_counterswap(dev, i);
1280
1281         ret = request_irq(mite_irq(devpriv->mite), ni_660x_interrupt,
1282                           IRQF_SHARED, "ni_660x", dev);
1283         if (ret < 0) {
1284                 dev_warn(dev->class_dev, " irq not available\n");
1285                 return ret;
1286         }
1287         dev->irq = mite_irq(devpriv->mite);
1288         global_interrupt_config_bits = Global_Int_Enable_Bit;
1289         if (board->n_chips > 1)
1290                 global_interrupt_config_bits |= Cascade_Int_Enable_Bit;
1291         ni_660x_write_register(dev, 0, global_interrupt_config_bits,
1292                                GlobalInterruptConfigRegister);
1293         dev_info(dev->class_dev, "ni_660x: %s attached\n", dev->board_name);
1294         return 0;
1295 }
1296
1297 static void ni_660x_detach(struct comedi_device *dev)
1298 {
1299         struct ni_660x_private *devpriv = dev->private;
1300
1301         if (dev->irq)
1302                 free_irq(dev->irq, dev);
1303         if (devpriv) {
1304                 if (devpriv->counter_dev)
1305                         ni_gpct_device_destroy(devpriv->counter_dev);
1306                 if (devpriv->mite) {
1307                         ni_660x_free_mite_rings(dev);
1308                         mite_unsetup(devpriv->mite);
1309                         mite_free(devpriv->mite);
1310                 }
1311         }
1312         comedi_pci_disable(dev);
1313 }
1314
1315 static struct comedi_driver ni_660x_driver = {
1316         .driver_name    = "ni_660x",
1317         .module         = THIS_MODULE,
1318         .auto_attach    = ni_660x_auto_attach,
1319         .detach         = ni_660x_detach,
1320 };
1321
1322 static int ni_660x_pci_probe(struct pci_dev *dev,
1323                              const struct pci_device_id *id)
1324 {
1325         return comedi_pci_auto_config(dev, &ni_660x_driver, id->driver_data);
1326 }
1327
1328 static DEFINE_PCI_DEVICE_TABLE(ni_660x_pci_table) = {
1329         { PCI_VDEVICE(NI, 0x1310), BOARD_PCI6602 },
1330         { PCI_VDEVICE(NI, 0x1360), BOARD_PXI6602 },
1331         { PCI_VDEVICE(NI, 0x2c60), BOARD_PCI6601 },
1332         { PCI_VDEVICE(NI, 0x2cc0), BOARD_PXI6608 },
1333         { PCI_VDEVICE(NI, 0x1e40), BOARD_PXI6624 },
1334         { 0 }
1335 };
1336 MODULE_DEVICE_TABLE(pci, ni_660x_pci_table);
1337
1338 static struct pci_driver ni_660x_pci_driver = {
1339         .name           = "ni_660x",
1340         .id_table       = ni_660x_pci_table,
1341         .probe          = ni_660x_pci_probe,
1342         .remove         = comedi_pci_auto_unconfig,
1343 };
1344 module_comedi_pci_driver(ni_660x_driver, ni_660x_pci_driver);
1345
1346 MODULE_AUTHOR("Comedi http://www.comedi.org");
1347 MODULE_DESCRIPTION("Comedi low-level driver");
1348 MODULE_LICENSE("GPL");