2 * comedi/drivers/me_daq.c
3 * Hardware driver for Meilhaus data acquisition cards:
4 * ME-2000i, ME-2600i, ME-3000vm1
6 * Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
21 * Description: Meilhaus PCI data acquisition cards
22 * Devices: [Meilhaus] ME-2600i (me-2600i), ME-2000i (me-2000i)
23 * Author: Michael Hillmann <hillmann@syscongroup.de>
24 * Status: experimental
26 * Configuration options: not applicable, uses PCI auto config
29 * Analog Input, Analog Output, Digital I/O
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
37 #include "../comedidev.h"
41 #define ME2600_FIRMWARE "me2600_firmware.bin"
43 #define XILINX_DOWNLOAD_RESET 0x42 /* Xilinx registers */
45 #define ME_CONTROL_1 0x0000 /* - | W */
46 #define INTERRUPT_ENABLE (1<<15)
47 #define COUNTER_B_IRQ (1<<12)
48 #define COUNTER_A_IRQ (1<<11)
49 #define CHANLIST_READY_IRQ (1<<10)
50 #define EXT_IRQ (1<<9)
51 #define ADFIFO_HALFFULL_IRQ (1<<8)
52 #define SCAN_COUNT_ENABLE (1<<5)
53 #define SIMULTANEOUS_ENABLE (1<<4)
54 #define TRIGGER_FALLING_EDGE (1<<3)
55 #define CONTINUOUS_MODE (1<<2)
56 #define DISABLE_ADC (0<<0)
57 #define SOFTWARE_TRIGGERED_ADC (1<<0)
58 #define SCAN_TRIGGERED_ADC (2<<0)
59 #define EXT_TRIGGERED_ADC (3<<0)
60 #define ME_ADC_START 0x0000 /* R | - */
61 #define ME_CONTROL_2 0x0002 /* - | W */
62 #define ENABLE_ADFIFO (1<<10)
63 #define ENABLE_CHANLIST (1<<9)
64 #define ENABLE_PORT_B (1<<7)
65 #define ENABLE_PORT_A (1<<6)
66 #define ENABLE_COUNTER_B (1<<4)
67 #define ENABLE_COUNTER_A (1<<3)
68 #define ENABLE_DAC (1<<1)
69 #define BUFFERED_DAC (1<<0)
70 #define ME_DAC_UPDATE 0x0002 /* R | - */
71 #define ME_STATUS 0x0004 /* R | - */
72 #define COUNTER_B_IRQ_PENDING (1<<12)
73 #define COUNTER_A_IRQ_PENDING (1<<11)
74 #define CHANLIST_READY_IRQ_PENDING (1<<10)
75 #define EXT_IRQ_PENDING (1<<9)
76 #define ADFIFO_HALFFULL_IRQ_PENDING (1<<8)
77 #define ADFIFO_FULL (1<<4)
78 #define ADFIFO_HALFFULL (1<<3)
79 #define ADFIFO_EMPTY (1<<2)
80 #define CHANLIST_FULL (1<<1)
81 #define FST_ACTIVE (1<<0)
82 #define ME_RESET_INTERRUPT 0x0004 /* - | W */
83 #define ME_DIO_PORT_A 0x0006 /* R | W */
84 #define ME_DIO_PORT_B 0x0008 /* R | W */
85 #define ME_TIMER_DATA_0 0x000A /* - | W */
86 #define ME_TIMER_DATA_1 0x000C /* - | W */
87 #define ME_TIMER_DATA_2 0x000E /* - | W */
88 #define ME_CHANNEL_LIST 0x0010 /* - | W */
89 #define ADC_UNIPOLAR (1<<6)
90 #define ADC_GAIN_0 (0<<4)
91 #define ADC_GAIN_1 (1<<4)
92 #define ADC_GAIN_2 (2<<4)
93 #define ADC_GAIN_3 (3<<4)
94 #define ME_READ_AD_FIFO 0x0010 /* R | - */
95 #define ME_DAC_CONTROL 0x0012 /* - | W */
96 #define DAC_UNIPOLAR_D (0<<4)
97 #define DAC_BIPOLAR_D (1<<4)
98 #define DAC_UNIPOLAR_C (0<<5)
99 #define DAC_BIPOLAR_C (1<<5)
100 #define DAC_UNIPOLAR_B (0<<6)
101 #define DAC_BIPOLAR_B (1<<6)
102 #define DAC_UNIPOLAR_A (0<<7)
103 #define DAC_BIPOLAR_A (1<<7)
104 #define DAC_GAIN_0_D (0<<8)
105 #define DAC_GAIN_1_D (1<<8)
106 #define DAC_GAIN_0_C (0<<9)
107 #define DAC_GAIN_1_C (1<<9)
108 #define DAC_GAIN_0_B (0<<10)
109 #define DAC_GAIN_1_B (1<<10)
110 #define DAC_GAIN_0_A (0<<11)
111 #define DAC_GAIN_1_A (1<<11)
112 #define ME_DAC_CONTROL_UPDATE 0x0012 /* R | - */
113 #define ME_DAC_DATA_A 0x0014 /* - | W */
114 #define ME_DAC_DATA_B 0x0016 /* - | W */
115 #define ME_DAC_DATA_C 0x0018 /* - | W */
116 #define ME_DAC_DATA_D 0x001A /* - | W */
117 #define ME_COUNTER_ENDDATA_A 0x001C /* - | W */
118 #define ME_COUNTER_ENDDATA_B 0x001E /* - | W */
119 #define ME_COUNTER_STARTDATA_A 0x0020 /* - | W */
120 #define ME_COUNTER_VALUE_A 0x0020 /* R | - */
121 #define ME_COUNTER_STARTDATA_B 0x0022 /* - | W */
122 #define ME_COUNTER_VALUE_B 0x0022 /* R | - */
124 static const struct comedi_lrange me_ai_range = {
137 static const struct comedi_lrange me_ao_range = {
156 static const struct me_board me_boards[] = {
167 struct me_private_data {
168 void __iomem *plx_regbase; /* PLX configuration base address */
170 unsigned short control_1; /* Mirror of CONTROL_1 register */
171 unsigned short control_2; /* Mirror of CONTROL_2 register */
172 unsigned short dac_control; /* Mirror of the DAC_CONTROL register */
175 static inline void sleep(unsigned sec)
177 __set_current_state(TASK_INTERRUPTIBLE);
178 schedule_timeout(sec * HZ);
181 static int me_dio_insn_config(struct comedi_device *dev,
182 struct comedi_subdevice *s,
183 struct comedi_insn *insn,
186 struct me_private_data *devpriv = dev->private;
187 unsigned int chan = CR_CHAN(insn->chanspec);
196 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
200 if (s->io_bits & 0x0000ffff)
201 devpriv->control_2 |= ENABLE_PORT_A;
203 devpriv->control_2 &= ~ENABLE_PORT_A;
204 if (s->io_bits & 0xffff0000)
205 devpriv->control_2 |= ENABLE_PORT_B;
207 devpriv->control_2 &= ~ENABLE_PORT_B;
209 writew(devpriv->control_2, dev->mmio + ME_CONTROL_2);
214 static int me_dio_insn_bits(struct comedi_device *dev,
215 struct comedi_subdevice *s,
216 struct comedi_insn *insn,
219 void __iomem *mmio_porta = dev->mmio + ME_DIO_PORT_A;
220 void __iomem *mmio_portb = dev->mmio + ME_DIO_PORT_B;
224 mask = comedi_dio_update_state(s, data);
226 if (mask & 0x0000ffff)
227 writew((s->state & 0xffff), mmio_porta);
228 if (mask & 0xffff0000)
229 writew(((s->state >> 16) & 0xffff), mmio_portb);
232 if (s->io_bits & 0x0000ffff)
233 val = s->state & 0xffff;
235 val = readw(mmio_porta);
237 if (s->io_bits & 0xffff0000)
238 val |= (s->state & 0xffff0000);
240 val |= (readw(mmio_portb) << 16);
247 static int me_ai_eoc(struct comedi_device *dev,
248 struct comedi_subdevice *s,
249 struct comedi_insn *insn,
250 unsigned long context)
254 status = readw(dev->mmio + ME_STATUS);
255 if ((status & 0x0004) == 0)
260 static int me_ai_insn_read(struct comedi_device *dev,
261 struct comedi_subdevice *s,
262 struct comedi_insn *insn,
265 struct me_private_data *dev_private = dev->private;
266 unsigned int chan = CR_CHAN(insn->chanspec);
267 unsigned int rang = CR_RANGE(insn->chanspec);
268 unsigned int aref = CR_AREF(insn->chanspec);
272 /* stop any running conversion */
273 dev_private->control_1 &= 0xFFFC;
274 writew(dev_private->control_1, dev->mmio + ME_CONTROL_1);
276 /* clear chanlist and ad fifo */
277 dev_private->control_2 &= ~(ENABLE_ADFIFO | ENABLE_CHANLIST);
278 writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
280 /* reset any pending interrupt */
281 writew(0x00, dev->mmio + ME_RESET_INTERRUPT);
283 /* enable the chanlist and ADC fifo */
284 dev_private->control_2 |= (ENABLE_ADFIFO | ENABLE_CHANLIST);
285 writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
287 /* write to channel list fifo */
288 val = chan & 0x0f; /* b3:b0 channel */
289 val |= (rang & 0x03) << 4; /* b5:b4 gain */
290 val |= (rang & 0x04) << 4; /* b6 polarity */
291 val |= ((aref & AREF_DIFF) ? 0x80 : 0); /* b7 differential */
292 writew(val & 0xff, dev->mmio + ME_CHANNEL_LIST);
294 /* set ADC mode to software trigger */
295 dev_private->control_1 |= SOFTWARE_TRIGGERED_ADC;
296 writew(dev_private->control_1, dev->mmio + ME_CONTROL_1);
298 /* start conversion by reading from ADC_START */
299 readw(dev->mmio + ME_ADC_START);
301 /* wait for ADC fifo not empty flag */
302 ret = comedi_timeout(dev, s, insn, me_ai_eoc, 0);
306 /* get value from ADC fifo */
307 val = readw(dev->mmio + ME_READ_AD_FIFO);
308 val = (val ^ 0x800) & 0x0fff;
311 /* stop any running conversion */
312 dev_private->control_1 &= 0xFFFC;
313 writew(dev_private->control_1, dev->mmio + ME_CONTROL_1);
318 static int me_ao_insn_write(struct comedi_device *dev,
319 struct comedi_subdevice *s,
320 struct comedi_insn *insn,
323 struct me_private_data *dev_private = dev->private;
324 unsigned int chan = CR_CHAN(insn->chanspec);
325 unsigned int rang = CR_RANGE(insn->chanspec);
326 unsigned int val = s->readback[chan];
330 dev_private->control_2 |= ENABLE_DAC;
331 writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
333 /* and set DAC to "buffered" mode */
334 dev_private->control_2 |= BUFFERED_DAC;
335 writew(dev_private->control_2, dev->mmio + ME_CONTROL_2);
337 /* Set dac-control register */
338 for (i = 0; i < insn->n; i++) {
339 /* clear bits for this channel */
340 dev_private->dac_control &= ~(0x0880 >> chan);
342 dev_private->dac_control |=
343 ((DAC_BIPOLAR_A | DAC_GAIN_1_A) >> chan);
345 dev_private->dac_control |=
346 ((DAC_BIPOLAR_A | DAC_GAIN_0_A) >> chan);
348 writew(dev_private->dac_control, dev->mmio + ME_DAC_CONTROL);
350 /* Update dac-control register */
351 readw(dev->mmio + ME_DAC_CONTROL_UPDATE);
353 /* Set data register */
354 for (i = 0; i < insn->n; i++) {
357 writew(val, dev->mmio + ME_DAC_DATA_A + (chan << 1));
359 s->readback[chan] = val;
361 /* Update dac with data registers */
362 readw(dev->mmio + ME_DAC_UPDATE);
367 static int me2600_xilinx_download(struct comedi_device *dev,
368 const u8 *data, size_t size,
369 unsigned long context)
371 struct me_private_data *dev_private = dev->private;
373 unsigned int file_length;
376 /* disable irq's on PLX */
377 writel(0x00, dev_private->plx_regbase + PLX9052_INTCSR);
379 /* First, make a dummy read to reset xilinx */
380 value = readw(dev->mmio + XILINX_DOWNLOAD_RESET);
382 /* Wait until reset is over */
385 /* Write a dummy value to Xilinx */
386 writeb(0x00, dev->mmio + 0x0);
390 * Format of the firmware
391 * Build longs from the byte-wise coded header
392 * Byte 1-3: length of the array
395 * Byte 12-15: reserved
400 file_length = (((unsigned int)data[0] & 0xff) << 24) +
401 (((unsigned int)data[1] & 0xff) << 16) +
402 (((unsigned int)data[2] & 0xff) << 8) +
403 ((unsigned int)data[3] & 0xff);
406 * Loop for writing firmware byte by byte to xilinx
407 * Firmware data start at offset 16
409 for (i = 0; i < file_length; i++)
410 writeb((data[16 + i] & 0xff), dev->mmio + 0x0);
412 /* Write 5 dummy values to xilinx */
413 for (i = 0; i < 5; i++)
414 writeb(0x00, dev->mmio + 0x0);
416 /* Test if there was an error during download -> INTB was thrown */
417 value = readl(dev_private->plx_regbase + PLX9052_INTCSR);
418 if (value & PLX9052_INTCSR_LI2STAT) {
419 /* Disable interrupt */
420 writel(0x00, dev_private->plx_regbase + PLX9052_INTCSR);
421 dev_err(dev->class_dev, "Xilinx download failed\n");
425 /* Wait until the Xilinx is ready for real work */
428 /* Enable PLX-Interrupts */
429 writel(PLX9052_INTCSR_LI1ENAB |
430 PLX9052_INTCSR_LI1POL |
431 PLX9052_INTCSR_PCIENAB,
432 dev_private->plx_regbase + PLX9052_INTCSR);
437 static int me_reset(struct comedi_device *dev)
439 struct me_private_data *dev_private = dev->private;
442 writew(0x00, dev->mmio + ME_CONTROL_1);
443 writew(0x00, dev->mmio + ME_CONTROL_2);
444 writew(0x00, dev->mmio + ME_RESET_INTERRUPT);
445 writew(0x00, dev->mmio + ME_DAC_CONTROL);
447 /* Save values in the board context */
448 dev_private->dac_control = 0;
449 dev_private->control_1 = 0;
450 dev_private->control_2 = 0;
455 static int me_auto_attach(struct comedi_device *dev,
456 unsigned long context)
458 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
459 const struct me_board *board = NULL;
460 struct me_private_data *dev_private;
461 struct comedi_subdevice *s;
464 if (context < ARRAY_SIZE(me_boards))
465 board = &me_boards[context];
468 dev->board_ptr = board;
469 dev->board_name = board->name;
471 dev_private = comedi_alloc_devpriv(dev, sizeof(*dev_private));
475 ret = comedi_pci_enable(dev);
479 dev_private->plx_regbase = pci_ioremap_bar(pcidev, 0);
480 if (!dev_private->plx_regbase)
483 dev->mmio = pci_ioremap_bar(pcidev, 2);
487 /* Download firmware and reset card */
488 if (board->needs_firmware) {
489 ret = comedi_load_firmware(dev, &comedi_to_pci_dev(dev)->dev,
491 me2600_xilinx_download, 0);
497 ret = comedi_alloc_subdevices(dev, 3);
501 s = &dev->subdevices[0];
502 s->type = COMEDI_SUBD_AI;
503 s->subdev_flags = SDF_READABLE | SDF_COMMON;
506 s->len_chanlist = 16;
507 s->range_table = &me_ai_range;
508 s->insn_read = me_ai_insn_read;
510 s = &dev->subdevices[1];
512 s->type = COMEDI_SUBD_AO;
513 s->subdev_flags = SDF_WRITABLE | SDF_COMMON;
517 s->range_table = &me_ao_range;
518 s->insn_write = me_ao_insn_write;
520 ret = comedi_alloc_subdev_readback(s);
524 s->type = COMEDI_SUBD_UNUSED;
527 s = &dev->subdevices[2];
528 s->type = COMEDI_SUBD_DIO;
529 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
532 s->len_chanlist = 32;
533 s->range_table = &range_digital;
534 s->insn_bits = me_dio_insn_bits;
535 s->insn_config = me_dio_insn_config;
540 static void me_detach(struct comedi_device *dev)
542 struct me_private_data *dev_private = dev->private;
547 if (dev_private->plx_regbase)
548 iounmap(dev_private->plx_regbase);
550 comedi_pci_detach(dev);
553 static struct comedi_driver me_daq_driver = {
554 .driver_name = "me_daq",
555 .module = THIS_MODULE,
556 .auto_attach = me_auto_attach,
560 static int me_daq_pci_probe(struct pci_dev *dev,
561 const struct pci_device_id *id)
563 return comedi_pci_auto_config(dev, &me_daq_driver, id->driver_data);
566 static const struct pci_device_id me_daq_pci_table[] = {
567 { PCI_VDEVICE(MEILHAUS, 0x2600), BOARD_ME2600 },
568 { PCI_VDEVICE(MEILHAUS, 0x2000), BOARD_ME2000 },
571 MODULE_DEVICE_TABLE(pci, me_daq_pci_table);
573 static struct pci_driver me_daq_pci_driver = {
575 .id_table = me_daq_pci_table,
576 .probe = me_daq_pci_probe,
577 .remove = comedi_pci_auto_unconfig,
579 module_comedi_pci_driver(me_daq_driver, me_daq_pci_driver);
581 MODULE_AUTHOR("Comedi http://www.comedi.org");
582 MODULE_DESCRIPTION("Comedi low-level driver");
583 MODULE_LICENSE("GPL");
584 MODULE_FIRMWARE(ME2600_FIRMWARE);