2 comedi/drivers/dmm32at.c
3 Diamond Systems mm32at code for a Comedi driver
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
20 Description: Diamond Systems mm32at driver.
22 Author: Perry J. Piplani <perry.j.piplani@nasa.gov>
23 Updated: Fri Jun 4 09:13:24 CDT 2004
26 This driver is for the Diamond Systems MM-32-AT board
27 http://www.diamondsystems.com/products/diamondmm32at It is being used
28 on serveral projects inside NASA, without problems so far. For analog
29 input commands, TRIG_EXT is not yet supported at all..
31 Configuration Options:
32 comedi_config /dev/comedi0 dmm32at baseaddr,irq
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/interrupt.h>
38 #include "../comedidev.h"
40 #include "comedi_fc.h"
42 /* Board register addresses */
44 #define DMM32AT_MEMSIZE 0x10
46 #define DMM32AT_CONV 0x00
47 #define DMM32AT_AILSB 0x00
48 #define DMM32AT_AUXDOUT 0x01
49 #define DMM32AT_AIMSB 0x01
50 #define DMM32AT_AILOW 0x02
51 #define DMM32AT_AIHIGH 0x03
53 #define DMM32AT_DACLSB 0x04
54 #define DMM32AT_DACSTAT 0x04
55 #define DMM32AT_DACMSB 0x05
57 #define DMM32AT_FIFOCNTRL 0x07
58 #define DMM32AT_FIFOSTAT 0x07
60 #define DMM32AT_CNTRL 0x08
61 #define DMM32AT_AISTAT 0x08
63 #define DMM32AT_INTCLOCK 0x09
65 #define DMM32AT_CNTRDIO 0x0a
67 #define DMM32AT_AICONF 0x0b
68 #define DMM32AT_AIRBACK 0x0b
70 #define DMM32AT_CLK1 0x0d
71 #define DMM32AT_CLK2 0x0e
72 #define DMM32AT_CLKCT 0x0f
74 #define DMM32AT_DIOA 0x0c
75 #define DMM32AT_DIOB 0x0d
76 #define DMM32AT_DIOC 0x0e
77 #define DMM32AT_DIOCONF 0x0f
79 /* Board register values. */
81 /* DMM32AT_DACSTAT 0x04 */
82 #define DMM32AT_DACBUSY 0x80
84 /* DMM32AT_FIFOCNTRL 0x07 */
85 #define DMM32AT_FIFORESET 0x02
86 #define DMM32AT_SCANENABLE 0x04
88 /* DMM32AT_CNTRL 0x08 */
89 #define DMM32AT_RESET 0x20
90 #define DMM32AT_INTRESET 0x08
91 #define DMM32AT_CLKACC 0x00
92 #define DMM32AT_DIOACC 0x01
94 /* DMM32AT_AISTAT 0x08 */
95 #define DMM32AT_STATUS 0x80
97 /* DMM32AT_INTCLOCK 0x09 */
98 #define DMM32AT_ADINT 0x80
99 #define DMM32AT_CLKSEL 0x03
101 /* DMM32AT_CNTRDIO 0x0a */
102 #define DMM32AT_FREQ12 0x80
104 /* DMM32AT_AICONF 0x0b */
105 #define DMM32AT_RANGE_U10 0x0c
106 #define DMM32AT_RANGE_U5 0x0d
107 #define DMM32AT_RANGE_B10 0x08
108 #define DMM32AT_RANGE_B5 0x00
109 #define DMM32AT_SCINT_20 0x00
110 #define DMM32AT_SCINT_15 0x10
111 #define DMM32AT_SCINT_10 0x20
112 #define DMM32AT_SCINT_5 0x30
114 /* DMM32AT_CLKCT 0x0f */
115 #define DMM32AT_CLKCT1 0x56 /* mode3 counter 1 - write low byte only */
116 #define DMM32AT_CLKCT2 0xb6 /* mode3 counter 2 - write high and low byte */
118 /* DMM32AT_DIOCONF 0x0f */
119 #define DMM32AT_DIENABLE 0x80
120 #define DMM32AT_DIRA 0x10
121 #define DMM32AT_DIRB 0x02
122 #define DMM32AT_DIRCL 0x01
123 #define DMM32AT_DIRCH 0x08
125 /* board AI ranges in comedi structure */
126 static const struct comedi_lrange dmm32at_airanges = {
136 /* register values for above ranges */
137 static const unsigned char dmm32at_rangebits[] = {
144 /* only one of these ranges is valid, as set by a jumper on the
145 * board. The application should only use the range set by the jumper
147 static const struct comedi_lrange dmm32at_aoranges = {
157 struct dmm32at_private {
161 unsigned int ai_scans_left;
163 /* Used for AO readback */
164 unsigned int ao_readback[4];
165 unsigned char dio_config;
169 static int dmm32at_ai_rinsn(struct comedi_device *dev,
170 struct comedi_subdevice *s,
171 struct comedi_insn *insn, unsigned int *data)
175 unsigned char status;
176 unsigned short msb, lsb;
180 /* get the channel and range number */
182 chan = CR_CHAN(insn->chanspec) & (s->n_chan - 1);
183 range = CR_RANGE(insn->chanspec);
185 /* printk("channel=0x%02x, range=%d\n",chan,range); */
187 /* zero scan and fifo control and reset fifo */
188 outb(DMM32AT_FIFORESET, dev->iobase + DMM32AT_FIFOCNTRL);
190 /* write the ai channel range regs */
191 outb(chan, dev->iobase + DMM32AT_AILOW);
192 outb(chan, dev->iobase + DMM32AT_AIHIGH);
193 /* set the range bits */
194 outb(dmm32at_rangebits[range], dev->iobase + DMM32AT_AICONF);
196 /* wait for circuit to settle */
197 for (i = 0; i < 40000; i++) {
198 status = inb(dev->iobase + DMM32AT_AIRBACK);
199 if ((status & DMM32AT_STATUS) == 0)
203 printk(KERN_WARNING "dmm32at: timeout\n");
207 /* convert n samples */
208 for (n = 0; n < insn->n; n++) {
209 /* trigger conversion */
210 outb(0xff, dev->iobase + DMM32AT_CONV);
211 /* wait for conversion to end */
212 for (i = 0; i < 40000; i++) {
213 status = inb(dev->iobase + DMM32AT_AISTAT);
214 if ((status & DMM32AT_STATUS) == 0)
218 printk(KERN_WARNING "dmm32at: timeout\n");
223 lsb = inb(dev->iobase + DMM32AT_AILSB);
224 msb = inb(dev->iobase + DMM32AT_AIMSB);
226 /* invert sign bit to make range unsigned, this is an
227 idiosyncrasy of the diamond board, it return
228 conversions as a signed value, i.e. -32768 to
229 32767, flipping the bit and interpreting it as
230 signed gives you a range of 0 to 65535 which is
232 d = ((msb ^ 0x0080) << 8) + lsb;
237 /* return the number of samples read/written */
241 static int dmm32at_ns_to_timer(unsigned int *ns, int round)
247 static int dmm32at_ai_cmdtest(struct comedi_device *dev,
248 struct comedi_subdevice *s,
249 struct comedi_cmd *cmd)
253 int start_chan, gain, i;
255 /* Step 1 : check if triggers are trivially valid */
257 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
258 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
259 TRIG_TIMER /*| TRIG_EXT */);
260 err |= cfc_check_trigger_src(&cmd->convert_src,
261 TRIG_TIMER /*| TRIG_EXT */);
262 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
263 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
268 /* Step 2a : make sure trigger sources are unique */
270 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
271 err |= cfc_check_trigger_is_unique(cmd->convert_src);
272 err |= cfc_check_trigger_is_unique(cmd->stop_src);
274 /* Step 2b : and mutually compatible */
279 /* Step 3: check if arguments are trivially valid */
281 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
283 #define MAX_SCAN_SPEED 1000000 /* in nanoseconds */
284 #define MIN_SCAN_SPEED 1000000000 /* in nanoseconds */
286 if (cmd->scan_begin_src == TRIG_TIMER) {
287 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
289 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
292 /* external trigger */
293 /* should be level/edge, hi/lo specification here */
294 /* should specify multiple external triggers */
295 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg, 9);
298 if (cmd->convert_src == TRIG_TIMER) {
299 if (cmd->convert_arg >= 17500)
300 cmd->convert_arg = 20000;
301 else if (cmd->convert_arg >= 12500)
302 cmd->convert_arg = 15000;
303 else if (cmd->convert_arg >= 7500)
304 cmd->convert_arg = 10000;
306 cmd->convert_arg = 5000;
308 /* external trigger */
310 err |= cfc_check_trigger_arg_max(&cmd->convert_arg, 9);
313 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
315 if (cmd->stop_src == TRIG_COUNT) {
316 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0xfffffff0);
317 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
320 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
326 /* step 4: fix up any arguments */
328 if (cmd->scan_begin_src == TRIG_TIMER) {
329 tmp = cmd->scan_begin_arg;
330 dmm32at_ns_to_timer(&cmd->scan_begin_arg,
331 cmd->flags & TRIG_ROUND_MASK);
332 if (tmp != cmd->scan_begin_arg)
335 if (cmd->convert_src == TRIG_TIMER) {
336 tmp = cmd->convert_arg;
337 dmm32at_ns_to_timer(&cmd->convert_arg,
338 cmd->flags & TRIG_ROUND_MASK);
339 if (tmp != cmd->convert_arg)
341 if (cmd->scan_begin_src == TRIG_TIMER &&
342 cmd->scan_begin_arg <
343 cmd->convert_arg * cmd->scan_end_arg) {
344 cmd->scan_begin_arg =
345 cmd->convert_arg * cmd->scan_end_arg;
353 /* step 5 check the channel list, the channel list for this
354 board must be consecutive and gains must be the same */
357 gain = CR_RANGE(cmd->chanlist[0]);
358 start_chan = CR_CHAN(cmd->chanlist[0]);
359 for (i = 1; i < cmd->chanlist_len; i++) {
360 if (CR_CHAN(cmd->chanlist[i]) !=
361 (start_chan + i) % s->n_chan) {
363 "entries in chanlist must be consecutive channels, counting upwards\n");
366 if (CR_RANGE(cmd->chanlist[i]) != gain) {
368 "entries in chanlist must all have the same gain\n");
380 static void dmm32at_setaitimer(struct comedi_device *dev, unsigned int nansec)
382 unsigned char lo1, lo2, hi2;
383 unsigned short both2;
385 /* based on 10mhz clock */
387 both2 = nansec / 20000;
388 hi2 = (both2 & 0xff00) >> 8;
389 lo2 = both2 & 0x00ff;
391 /* set the counter frequency to 10mhz */
392 outb(0, dev->iobase + DMM32AT_CNTRDIO);
394 /* get access to the clock regs */
395 outb(DMM32AT_CLKACC, dev->iobase + DMM32AT_CNTRL);
397 /* write the counter 1 control word and low byte to counter */
398 outb(DMM32AT_CLKCT1, dev->iobase + DMM32AT_CLKCT);
399 outb(lo1, dev->iobase + DMM32AT_CLK1);
401 /* write the counter 2 control word and low byte then to counter */
402 outb(DMM32AT_CLKCT2, dev->iobase + DMM32AT_CLKCT);
403 outb(lo2, dev->iobase + DMM32AT_CLK2);
404 outb(hi2, dev->iobase + DMM32AT_CLK2);
406 /* enable the ai conversion interrupt and the clock to start scans */
407 outb(DMM32AT_ADINT | DMM32AT_CLKSEL, dev->iobase + DMM32AT_INTCLOCK);
410 static int dmm32at_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
412 struct dmm32at_private *devpriv = dev->private;
413 struct comedi_cmd *cmd = &s->async->cmd;
415 unsigned char chanlo, chanhi, status;
420 /* get the channel list and range */
421 chanlo = CR_CHAN(cmd->chanlist[0]) & (s->n_chan - 1);
422 chanhi = chanlo + cmd->chanlist_len - 1;
423 if (chanhi >= s->n_chan)
425 range = CR_RANGE(cmd->chanlist[0]);
428 outb(DMM32AT_FIFORESET, dev->iobase + DMM32AT_FIFOCNTRL);
430 /* set scan enable */
431 outb(DMM32AT_SCANENABLE, dev->iobase + DMM32AT_FIFOCNTRL);
433 /* write the ai channel range regs */
434 outb(chanlo, dev->iobase + DMM32AT_AILOW);
435 outb(chanhi, dev->iobase + DMM32AT_AIHIGH);
437 /* set the range bits */
438 outb(dmm32at_rangebits[range], dev->iobase + DMM32AT_AICONF);
440 /* reset the interrupt just in case */
441 outb(DMM32AT_INTRESET, dev->iobase + DMM32AT_CNTRL);
443 if (cmd->stop_src == TRIG_COUNT)
444 devpriv->ai_scans_left = cmd->stop_arg;
445 else { /* TRIG_NONE */
446 devpriv->ai_scans_left = 0xffffffff; /* indicates TRIG_NONE to
450 /* wait for circuit to settle */
451 for (i = 0; i < 40000; i++) {
452 status = inb(dev->iobase + DMM32AT_AIRBACK);
453 if ((status & DMM32AT_STATUS) == 0)
457 printk(KERN_WARNING "dmm32at: timeout\n");
461 if (devpriv->ai_scans_left > 1) {
462 /* start the clock and enable the interrupts */
463 dmm32at_setaitimer(dev, cmd->scan_begin_arg);
465 /* start the interrups and initiate a single scan */
466 outb(DMM32AT_ADINT, dev->iobase + DMM32AT_INTCLOCK);
467 outb(0xff, dev->iobase + DMM32AT_CONV);
470 /* printk("dmmat32 in command\n"); */
472 /* for(i=0;i<cmd->chanlist_len;i++) */
473 /* comedi_buf_put(s->async,i*100); */
475 /* s->async->events |= COMEDI_CB_EOA; */
476 /* comedi_event(dev, s); */
482 static int dmm32at_ai_cancel(struct comedi_device *dev,
483 struct comedi_subdevice *s)
485 struct dmm32at_private *devpriv = dev->private;
487 devpriv->ai_scans_left = 1;
491 static irqreturn_t dmm32at_isr(int irq, void *d)
493 struct comedi_device *dev = d;
494 struct dmm32at_private *devpriv = dev->private;
495 unsigned char intstat;
497 unsigned short msb, lsb;
500 if (!dev->attached) {
501 comedi_error(dev, "spurious interrupt");
505 intstat = inb(dev->iobase + DMM32AT_INTCLOCK);
507 if (intstat & DMM32AT_ADINT) {
508 struct comedi_subdevice *s = dev->read_subdev;
509 struct comedi_cmd *cmd = &s->async->cmd;
511 for (i = 0; i < cmd->chanlist_len; i++) {
513 lsb = inb(dev->iobase + DMM32AT_AILSB);
514 msb = inb(dev->iobase + DMM32AT_AIMSB);
516 /* invert sign bit to make range unsigned */
517 samp = ((msb ^ 0x0080) << 8) + lsb;
518 comedi_buf_put(s->async, samp);
521 if (devpriv->ai_scans_left != 0xffffffff) { /* TRIG_COUNT */
522 devpriv->ai_scans_left--;
523 if (devpriv->ai_scans_left == 0) {
524 /* disable further interrupts and clocks */
525 outb(0x0, dev->iobase + DMM32AT_INTCLOCK);
526 /* set the buffer to be flushed with an EOF */
527 s->async->events |= COMEDI_CB_EOA;
531 /* flush the buffer */
532 comedi_event(dev, s);
535 /* reset the interrupt */
536 outb(DMM32AT_INTRESET, dev->iobase + DMM32AT_CNTRL);
540 static int dmm32at_ao_winsn(struct comedi_device *dev,
541 struct comedi_subdevice *s,
542 struct comedi_insn *insn, unsigned int *data)
544 struct dmm32at_private *devpriv = dev->private;
546 int chan = CR_CHAN(insn->chanspec);
547 unsigned char hi, lo, status;
549 /* Writing a list of values to an AO channel is probably not
550 * very useful, but that's how the interface is defined. */
551 for (i = 0; i < insn->n; i++) {
553 devpriv->ao_readback[chan] = data[i];
555 /* get the low byte */
556 lo = data[i] & 0x00ff;
557 /* high byte also contains channel number */
558 hi = (data[i] >> 8) + chan * (1 << 6);
559 /* printk("writing 0x%02x 0x%02x\n",hi,lo); */
560 /* write the low and high values to the board */
561 outb(lo, dev->iobase + DMM32AT_DACLSB);
562 outb(hi, dev->iobase + DMM32AT_DACMSB);
564 /* wait for circuit to settle */
565 for (i = 0; i < 40000; i++) {
566 status = inb(dev->iobase + DMM32AT_DACSTAT);
567 if ((status & DMM32AT_DACBUSY) == 0)
571 printk(KERN_WARNING "dmm32at: timeout\n");
574 /* dummy read to update trigger the output */
575 status = inb(dev->iobase + DMM32AT_DACMSB);
579 /* return the number of samples read/written */
583 static int dmm32at_ao_rinsn(struct comedi_device *dev,
584 struct comedi_subdevice *s,
585 struct comedi_insn *insn, unsigned int *data)
587 struct dmm32at_private *devpriv = dev->private;
589 int chan = CR_CHAN(insn->chanspec);
591 for (i = 0; i < insn->n; i++)
592 data[i] = devpriv->ao_readback[chan];
597 static int dmm32at_dio_insn_bits(struct comedi_device *dev,
598 struct comedi_subdevice *s,
599 struct comedi_insn *insn,
602 struct dmm32at_private *devpriv = dev->private;
606 mask = comedi_dio_update_state(s, data);
608 /* get access to the DIO regs */
609 outb(DMM32AT_DIOACC, dev->iobase + DMM32AT_CNTRL);
611 /* if either part of dio is set for output */
612 if (((devpriv->dio_config & DMM32AT_DIRCL) == 0) ||
613 ((devpriv->dio_config & DMM32AT_DIRCH) == 0)) {
614 val = (s->state & 0x00ff0000) >> 16;
615 outb(val, dev->iobase + DMM32AT_DIOC);
617 if ((devpriv->dio_config & DMM32AT_DIRB) == 0) {
618 val = (s->state & 0x0000ff00) >> 8;
619 outb(val, dev->iobase + DMM32AT_DIOB);
621 if ((devpriv->dio_config & DMM32AT_DIRA) == 0) {
622 val = (s->state & 0x000000ff);
623 outb(val, dev->iobase + DMM32AT_DIOA);
627 val = inb(dev->iobase + DMM32AT_DIOA);
628 val |= inb(dev->iobase + DMM32AT_DIOB) << 8;
629 val |= inb(dev->iobase + DMM32AT_DIOC) << 16;
637 static int dmm32at_dio_insn_config(struct comedi_device *dev,
638 struct comedi_subdevice *s,
639 struct comedi_insn *insn,
642 struct dmm32at_private *devpriv = dev->private;
643 unsigned int chan = CR_CHAN(insn->chanspec);
645 unsigned char chanbit;
650 chanbit = DMM32AT_DIRA;
651 } else if (chan < 16) {
653 chanbit = DMM32AT_DIRB;
654 } else if (chan < 20) {
656 chanbit = DMM32AT_DIRCL;
659 chanbit = DMM32AT_DIRCH;
662 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
666 if (data[0] == INSN_CONFIG_DIO_OUTPUT)
667 devpriv->dio_config &= ~chanbit;
669 devpriv->dio_config |= chanbit;
670 /* get access to the DIO regs */
671 outb(DMM32AT_DIOACC, dev->iobase + DMM32AT_CNTRL);
672 /* set the DIO's to the new configuration setting */
673 outb(devpriv->dio_config, dev->iobase + DMM32AT_DIOCONF);
678 static int dmm32at_attach(struct comedi_device *dev,
679 struct comedi_devconfig *it)
681 struct dmm32at_private *devpriv;
683 struct comedi_subdevice *s;
684 unsigned char aihi, ailo, fifostat, aistat, intstat, airback;
687 irq = it->options[1];
689 ret = comedi_request_region(dev, it->options[0], DMM32AT_MEMSIZE);
693 /* the following just makes sure the board is there and gets
694 it to a known state */
696 /* reset the board */
697 outb(DMM32AT_RESET, dev->iobase + DMM32AT_CNTRL);
699 /* allow a millisecond to reset */
702 /* zero scan and fifo control */
703 outb(0x0, dev->iobase + DMM32AT_FIFOCNTRL);
705 /* zero interrupt and clock control */
706 outb(0x0, dev->iobase + DMM32AT_INTCLOCK);
708 /* write a test channel range, the high 3 bits should drop */
709 outb(0x80, dev->iobase + DMM32AT_AILOW);
710 outb(0xff, dev->iobase + DMM32AT_AIHIGH);
712 /* set the range at 10v unipolar */
713 outb(DMM32AT_RANGE_U10, dev->iobase + DMM32AT_AICONF);
715 /* should take 10 us to settle, here's a hundred */
718 /* read back the values */
719 ailo = inb(dev->iobase + DMM32AT_AILOW);
720 aihi = inb(dev->iobase + DMM32AT_AIHIGH);
721 fifostat = inb(dev->iobase + DMM32AT_FIFOSTAT);
722 aistat = inb(dev->iobase + DMM32AT_AISTAT);
723 intstat = inb(dev->iobase + DMM32AT_INTCLOCK);
724 airback = inb(dev->iobase + DMM32AT_AIRBACK);
726 if ((ailo != 0x00) || (aihi != 0x1f) || (fifostat != 0x80) ||
727 (aistat != 0x60 || (intstat != 0x00) || airback != 0x0c)) {
728 printk(KERN_ERR "dmmat32: board detection failed\n");
732 /* board is there, register interrupt */
734 ret = request_irq(irq, dmm32at_isr, 0, dev->board_name, dev);
736 printk(KERN_ERR "dmm32at: irq conflict\n");
742 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
746 ret = comedi_alloc_subdevices(dev, 3);
750 s = &dev->subdevices[0];
751 dev->read_subdev = s;
752 /* analog input subdevice */
753 s->type = COMEDI_SUBD_AI;
754 /* we support single-ended (ground) and differential */
755 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF | SDF_CMD_READ;
758 s->range_table = &dmm32at_airanges;
759 s->len_chanlist = 32; /* This is the maximum chanlist length that
760 the board can handle */
761 s->insn_read = dmm32at_ai_rinsn;
762 s->do_cmd = dmm32at_ai_cmd;
763 s->do_cmdtest = dmm32at_ai_cmdtest;
764 s->cancel = dmm32at_ai_cancel;
766 s = &dev->subdevices[1];
767 /* analog output subdevice */
768 s->type = COMEDI_SUBD_AO;
769 s->subdev_flags = SDF_WRITABLE;
772 s->range_table = &dmm32at_aoranges;
773 s->insn_write = dmm32at_ao_winsn;
774 s->insn_read = dmm32at_ao_rinsn;
776 s = &dev->subdevices[2];
777 /* digital i/o subdevice */
779 /* get access to the DIO regs */
780 outb(DMM32AT_DIOACC, dev->iobase + DMM32AT_CNTRL);
781 /* set the DIO's to the defualt input setting */
782 devpriv->dio_config = DMM32AT_DIRA | DMM32AT_DIRB |
783 DMM32AT_DIRCL | DMM32AT_DIRCH | DMM32AT_DIENABLE;
784 outb(devpriv->dio_config, dev->iobase + DMM32AT_DIOCONF);
786 /* set up the subdevice */
787 s->type = COMEDI_SUBD_DIO;
788 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
792 s->range_table = &range_digital;
793 s->insn_bits = dmm32at_dio_insn_bits;
794 s->insn_config = dmm32at_dio_insn_config;
797 printk(KERN_INFO "comedi%d: dmm32at: attached\n", dev->minor);
803 static struct comedi_driver dmm32at_driver = {
804 .driver_name = "dmm32at",
805 .module = THIS_MODULE,
806 .attach = dmm32at_attach,
807 .detach = comedi_legacy_detach,
809 module_comedi_driver(dmm32at_driver);
811 MODULE_AUTHOR("Comedi http://www.comedi.org");
812 MODULE_DESCRIPTION("Comedi low-level driver");
813 MODULE_LICENSE("GPL");