2 comedi/drivers/amplc_dio200_common.c
4 Common support code for "amplc_dio200" and "amplc_dio200_pci".
6 Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/>
8 COMEDI - Linux Control and Measurement Device Interface
9 Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
22 #include <linux/module.h>
23 #include <linux/interrupt.h>
25 #include "../comedidev.h"
27 #include "amplc_dio200.h"
28 #include "comedi_fc.h"
30 #include "8255.h" /* only for register defines */
32 /* 200 series registers */
33 #define DIO200_IO_SIZE 0x20
34 #define DIO200_PCIE_IO_SIZE 0x4000
35 #define DIO200_XCLK_SCE 0x18 /* Group X clock selection register */
36 #define DIO200_YCLK_SCE 0x19 /* Group Y clock selection register */
37 #define DIO200_ZCLK_SCE 0x1a /* Group Z clock selection register */
38 #define DIO200_XGAT_SCE 0x1b /* Group X gate selection register */
39 #define DIO200_YGAT_SCE 0x1c /* Group Y gate selection register */
40 #define DIO200_ZGAT_SCE 0x1d /* Group Z gate selection register */
41 #define DIO200_INT_SCE 0x1e /* Interrupt enable/status register */
42 /* Extra registers for new PCIe boards */
43 #define DIO200_ENHANCE 0x20 /* 1 to enable enhanced features */
44 #define DIO200_VERSION 0x24 /* Hardware version register */
45 #define DIO200_TS_CONFIG 0x600 /* Timestamp timer config register */
46 #define DIO200_TS_COUNT 0x602 /* Timestamp timer count register */
49 * Functions for constructing value for DIO_200_?CLK_SCE and
50 * DIO_200_?GAT_SCE registers:
52 * 'which' is: 0 for CTR-X1, CTR-Y1, CTR-Z1; 1 for CTR-X2, CTR-Y2 or CTR-Z2.
53 * 'chan' is the channel: 0, 1 or 2.
54 * 'source' is the signal source: 0 to 7, or 0 to 31 for "enhanced" boards.
56 static unsigned char clk_gat_sce(unsigned int which, unsigned int chan,
59 return (which << 5) | (chan << 3) |
60 ((source & 030) << 3) | (source & 007);
63 static unsigned char clk_sce(unsigned int which, unsigned int chan,
66 return clk_gat_sce(which, chan, source);
69 static unsigned char gat_sce(unsigned int which, unsigned int chan,
72 return clk_gat_sce(which, chan, source);
76 * Periods of the internal clock sources in nanoseconds.
78 static const unsigned int clock_period[32] = {
79 [1] = 100, /* 10 MHz */
80 [2] = 1000, /* 1 MHz */
81 [3] = 10000, /* 100 kHz */
82 [4] = 100000, /* 10 kHz */
83 [5] = 1000000, /* 1 kHz */
84 [11] = 50, /* 20 MHz (enhanced boards) */
85 /* clock sources 12 and later reserved for enhanced boards */
89 * Timestamp timer configuration register (for new PCIe boards).
91 #define TS_CONFIG_RESET 0x100 /* Reset counter to zero. */
92 #define TS_CONFIG_CLK_SRC_MASK 0x0FF /* Clock source. */
93 #define TS_CONFIG_MAX_CLK_SRC 2 /* Maximum clock source value. */
96 * Periods of the timestamp timer clock sources in nanoseconds.
98 static const unsigned int ts_clock_period[TS_CONFIG_MAX_CLK_SRC + 1] = {
99 1, /* 1 nanosecond (but with 20 ns granularity). */
100 1000, /* 1 microsecond. */
101 1000000, /* 1 millisecond. */
104 struct dio200_subdev_8254 {
105 unsigned int ofs; /* Counter base offset */
106 unsigned int clk_sce_ofs; /* CLK_SCE base address */
107 unsigned int gat_sce_ofs; /* GAT_SCE base address */
108 int which; /* Bit 5 of CLK_SCE or GAT_SCE */
109 unsigned int clock_src[3]; /* Current clock sources */
110 unsigned int gate_src[3]; /* Current gate sources */
114 struct dio200_subdev_8255 {
115 unsigned int ofs; /* DIO base offset */
118 struct dio200_subdev_intr {
121 unsigned int valid_isns;
122 unsigned int enabled_isns;
126 static unsigned char dio200_read8(struct comedi_device *dev,
129 const struct dio200_board *board = dev->board_ptr;
135 return readb(dev->mmio + offset);
136 return inb(dev->iobase + offset);
139 static void dio200_write8(struct comedi_device *dev,
140 unsigned int offset, unsigned char val)
142 const struct dio200_board *board = dev->board_ptr;
148 writeb(val, dev->mmio + offset);
150 outb(val, dev->iobase + offset);
153 static unsigned int dio200_read32(struct comedi_device *dev,
156 const struct dio200_board *board = dev->board_ptr;
162 return readl(dev->mmio + offset);
163 return inl(dev->iobase + offset);
166 static void dio200_write32(struct comedi_device *dev,
167 unsigned int offset, unsigned int val)
169 const struct dio200_board *board = dev->board_ptr;
175 writel(val, dev->mmio + offset);
177 outl(val, dev->iobase + offset);
180 static int dio200_subdev_intr_insn_bits(struct comedi_device *dev,
181 struct comedi_subdevice *s,
182 struct comedi_insn *insn,
185 const struct dio200_board *board = dev->board_ptr;
186 struct dio200_subdev_intr *subpriv = s->private;
188 if (board->has_int_sce) {
189 /* Just read the interrupt status register. */
190 data[1] = dio200_read8(dev, subpriv->ofs) & subpriv->valid_isns;
192 /* No interrupt status register. */
199 static void dio200_stop_intr(struct comedi_device *dev,
200 struct comedi_subdevice *s)
202 const struct dio200_board *board = dev->board_ptr;
203 struct dio200_subdev_intr *subpriv = s->private;
205 subpriv->active = false;
206 subpriv->enabled_isns = 0;
207 if (board->has_int_sce)
208 dio200_write8(dev, subpriv->ofs, 0);
211 static void dio200_start_intr(struct comedi_device *dev,
212 struct comedi_subdevice *s)
214 const struct dio200_board *board = dev->board_ptr;
215 struct dio200_subdev_intr *subpriv = s->private;
216 struct comedi_cmd *cmd = &s->async->cmd;
220 /* Determine interrupt sources to enable. */
223 for (n = 0; n < cmd->chanlist_len; n++)
224 isn_bits |= (1U << CR_CHAN(cmd->chanlist[n]));
226 isn_bits &= subpriv->valid_isns;
227 /* Enable interrupt sources. */
228 subpriv->enabled_isns = isn_bits;
229 if (board->has_int_sce)
230 dio200_write8(dev, subpriv->ofs, isn_bits);
233 static int dio200_inttrig_start_intr(struct comedi_device *dev,
234 struct comedi_subdevice *s,
235 unsigned int trig_num)
237 struct dio200_subdev_intr *subpriv = s->private;
238 struct comedi_cmd *cmd = &s->async->cmd;
241 if (trig_num != cmd->start_arg)
244 spin_lock_irqsave(&subpriv->spinlock, flags);
245 s->async->inttrig = NULL;
247 dio200_start_intr(dev, s);
249 spin_unlock_irqrestore(&subpriv->spinlock, flags);
254 static void dio200_read_scan_intr(struct comedi_device *dev,
255 struct comedi_subdevice *s,
256 unsigned int triggered)
258 struct comedi_cmd *cmd = &s->async->cmd;
263 for (n = 0; n < cmd->chanlist_len; n++) {
264 ch = CR_CHAN(cmd->chanlist[n]);
265 if (triggered & (1U << ch))
269 comedi_buf_write_samples(s, &val, 1);
271 if (cmd->stop_src == TRIG_COUNT &&
272 s->async->scans_done >= cmd->stop_arg)
273 s->async->events |= COMEDI_CB_EOA;
276 static int dio200_handle_read_intr(struct comedi_device *dev,
277 struct comedi_subdevice *s)
279 const struct dio200_board *board = dev->board_ptr;
280 struct dio200_subdev_intr *subpriv = s->private;
283 unsigned cur_enabled;
288 spin_lock_irqsave(&subpriv->spinlock, flags);
289 if (board->has_int_sce) {
291 * Collect interrupt sources that have triggered and disable
292 * them temporarily. Loop around until no extra interrupt
293 * sources have triggered, at which point, the valid part of
294 * the interrupt status register will read zero, clearing the
295 * cause of the interrupt.
297 * Mask off interrupt sources already seen to avoid infinite
298 * loop in case of misconfiguration.
300 cur_enabled = subpriv->enabled_isns;
301 while ((intstat = (dio200_read8(dev, subpriv->ofs) &
302 subpriv->valid_isns & ~triggered)) != 0) {
303 triggered |= intstat;
304 cur_enabled &= ~triggered;
305 dio200_write8(dev, subpriv->ofs, cur_enabled);
309 * No interrupt status register. Assume the single interrupt
310 * source has triggered.
312 triggered = subpriv->enabled_isns;
317 * Some interrupt sources have triggered and have been
318 * temporarily disabled to clear the cause of the interrupt.
320 * Reenable them NOW to minimize the time they are disabled.
322 cur_enabled = subpriv->enabled_isns;
323 if (board->has_int_sce)
324 dio200_write8(dev, subpriv->ofs, cur_enabled);
326 if (subpriv->active) {
328 * The command is still active.
330 * Ignore interrupt sources that the command isn't
331 * interested in (just in case there's a race
334 if (triggered & subpriv->enabled_isns)
335 /* Collect scan data. */
336 dio200_read_scan_intr(dev, s, triggered);
339 spin_unlock_irqrestore(&subpriv->spinlock, flags);
341 comedi_handle_events(dev, s);
343 return (triggered != 0);
346 static int dio200_subdev_intr_cancel(struct comedi_device *dev,
347 struct comedi_subdevice *s)
349 struct dio200_subdev_intr *subpriv = s->private;
352 spin_lock_irqsave(&subpriv->spinlock, flags);
354 dio200_stop_intr(dev, s);
356 spin_unlock_irqrestore(&subpriv->spinlock, flags);
361 static int dio200_subdev_intr_cmdtest(struct comedi_device *dev,
362 struct comedi_subdevice *s,
363 struct comedi_cmd *cmd)
367 /* Step 1 : check if triggers are trivially valid */
369 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
370 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
371 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
372 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
373 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
378 /* Step 2a : make sure trigger sources are unique */
380 err |= cfc_check_trigger_is_unique(cmd->start_src);
381 err |= cfc_check_trigger_is_unique(cmd->stop_src);
383 /* Step 2b : and mutually compatible */
388 /* Step 3: check if arguments are trivially valid */
390 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
391 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
392 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
393 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
395 if (cmd->stop_src == TRIG_COUNT)
396 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
398 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
403 /* step 4: fix up any arguments */
405 /* if (err) return 4; */
410 static int dio200_subdev_intr_cmd(struct comedi_device *dev,
411 struct comedi_subdevice *s)
413 struct comedi_cmd *cmd = &s->async->cmd;
414 struct dio200_subdev_intr *subpriv = s->private;
417 spin_lock_irqsave(&subpriv->spinlock, flags);
419 subpriv->active = true;
421 if (cmd->start_src == TRIG_INT)
422 s->async->inttrig = dio200_inttrig_start_intr;
424 dio200_start_intr(dev, s);
426 spin_unlock_irqrestore(&subpriv->spinlock, flags);
431 static int dio200_subdev_intr_init(struct comedi_device *dev,
432 struct comedi_subdevice *s,
436 const struct dio200_board *board = dev->board_ptr;
437 struct dio200_subdev_intr *subpriv;
439 subpriv = comedi_alloc_spriv(s, sizeof(*subpriv));
443 subpriv->ofs = offset;
444 subpriv->valid_isns = valid_isns;
445 spin_lock_init(&subpriv->spinlock);
447 if (board->has_int_sce)
448 /* Disable interrupt sources. */
449 dio200_write8(dev, subpriv->ofs, 0);
451 s->type = COMEDI_SUBD_DI;
452 s->subdev_flags = SDF_READABLE | SDF_CMD_READ | SDF_PACKED;
453 if (board->has_int_sce) {
454 s->n_chan = DIO200_MAX_ISNS;
455 s->len_chanlist = DIO200_MAX_ISNS;
457 /* No interrupt source register. Support single channel. */
461 s->range_table = &range_digital;
463 s->insn_bits = dio200_subdev_intr_insn_bits;
464 s->do_cmdtest = dio200_subdev_intr_cmdtest;
465 s->do_cmd = dio200_subdev_intr_cmd;
466 s->cancel = dio200_subdev_intr_cancel;
471 static irqreturn_t dio200_interrupt(int irq, void *d)
473 struct comedi_device *dev = d;
474 struct comedi_subdevice *s = dev->read_subdev;
480 handled = dio200_handle_read_intr(dev, s);
482 return IRQ_RETVAL(handled);
485 static unsigned int dio200_subdev_8254_read_chan(struct comedi_device *dev,
486 struct comedi_subdevice *s,
489 struct dio200_subdev_8254 *subpriv = s->private;
494 dio200_write8(dev, subpriv->ofs + i8254_control_reg, val);
496 val = dio200_read8(dev, subpriv->ofs + chan);
497 val += dio200_read8(dev, subpriv->ofs + chan) << 8;
501 static void dio200_subdev_8254_write_chan(struct comedi_device *dev,
502 struct comedi_subdevice *s,
506 struct dio200_subdev_8254 *subpriv = s->private;
509 dio200_write8(dev, subpriv->ofs + chan, count & 0xff);
510 dio200_write8(dev, subpriv->ofs + chan, (count >> 8) & 0xff);
513 static void dio200_subdev_8254_set_mode(struct comedi_device *dev,
514 struct comedi_subdevice *s,
518 struct dio200_subdev_8254 *subpriv = s->private;
522 byte |= 0x30; /* access order: lsb, msb */
523 byte |= (mode & 0xf); /* counter mode and BCD|binary */
524 dio200_write8(dev, subpriv->ofs + i8254_control_reg, byte);
527 static unsigned int dio200_subdev_8254_status(struct comedi_device *dev,
528 struct comedi_subdevice *s,
531 struct dio200_subdev_8254 *subpriv = s->private;
534 dio200_write8(dev, subpriv->ofs + i8254_control_reg,
537 return dio200_read8(dev, subpriv->ofs + chan);
540 static int dio200_subdev_8254_read(struct comedi_device *dev,
541 struct comedi_subdevice *s,
542 struct comedi_insn *insn,
545 struct dio200_subdev_8254 *subpriv = s->private;
546 int chan = CR_CHAN(insn->chanspec);
550 for (n = 0; n < insn->n; n++) {
551 spin_lock_irqsave(&subpriv->spinlock, flags);
552 data[n] = dio200_subdev_8254_read_chan(dev, s, chan);
553 spin_unlock_irqrestore(&subpriv->spinlock, flags);
558 static int dio200_subdev_8254_write(struct comedi_device *dev,
559 struct comedi_subdevice *s,
560 struct comedi_insn *insn,
563 struct dio200_subdev_8254 *subpriv = s->private;
564 int chan = CR_CHAN(insn->chanspec);
568 for (n = 0; n < insn->n; n++) {
569 spin_lock_irqsave(&subpriv->spinlock, flags);
570 dio200_subdev_8254_write_chan(dev, s, chan, data[n]);
571 spin_unlock_irqrestore(&subpriv->spinlock, flags);
576 static int dio200_subdev_8254_set_gate_src(struct comedi_device *dev,
577 struct comedi_subdevice *s,
578 unsigned int counter_number,
579 unsigned int gate_src)
581 const struct dio200_board *board = dev->board_ptr;
582 struct dio200_subdev_8254 *subpriv = s->private;
585 if (!board->has_clk_gat_sce)
587 if (counter_number > 2)
589 if (gate_src > (board->is_pcie ? 31 : 7))
592 subpriv->gate_src[counter_number] = gate_src;
593 byte = gat_sce(subpriv->which, counter_number, gate_src);
594 dio200_write8(dev, subpriv->gat_sce_ofs, byte);
599 static int dio200_subdev_8254_get_gate_src(struct comedi_device *dev,
600 struct comedi_subdevice *s,
601 unsigned int counter_number)
603 const struct dio200_board *board = dev->board_ptr;
604 struct dio200_subdev_8254 *subpriv = s->private;
606 if (!board->has_clk_gat_sce)
608 if (counter_number > 2)
611 return subpriv->gate_src[counter_number];
614 static int dio200_subdev_8254_set_clock_src(struct comedi_device *dev,
615 struct comedi_subdevice *s,
616 unsigned int counter_number,
617 unsigned int clock_src)
619 const struct dio200_board *board = dev->board_ptr;
620 struct dio200_subdev_8254 *subpriv = s->private;
623 if (!board->has_clk_gat_sce)
625 if (counter_number > 2)
627 if (clock_src > (board->is_pcie ? 31 : 7))
630 subpriv->clock_src[counter_number] = clock_src;
631 byte = clk_sce(subpriv->which, counter_number, clock_src);
632 dio200_write8(dev, subpriv->clk_sce_ofs, byte);
637 static int dio200_subdev_8254_get_clock_src(struct comedi_device *dev,
638 struct comedi_subdevice *s,
639 unsigned int counter_number,
640 unsigned int *period_ns)
642 const struct dio200_board *board = dev->board_ptr;
643 struct dio200_subdev_8254 *subpriv = s->private;
646 if (!board->has_clk_gat_sce)
648 if (counter_number > 2)
651 clock_src = subpriv->clock_src[counter_number];
652 *period_ns = clock_period[clock_src];
656 static int dio200_subdev_8254_config(struct comedi_device *dev,
657 struct comedi_subdevice *s,
658 struct comedi_insn *insn,
661 struct dio200_subdev_8254 *subpriv = s->private;
663 int chan = CR_CHAN(insn->chanspec);
666 spin_lock_irqsave(&subpriv->spinlock, flags);
668 case INSN_CONFIG_SET_COUNTER_MODE:
669 if (data[1] > (I8254_MODE5 | I8254_BCD))
672 dio200_subdev_8254_set_mode(dev, s, chan, data[1]);
674 case INSN_CONFIG_8254_READ_STATUS:
675 data[1] = dio200_subdev_8254_status(dev, s, chan);
677 case INSN_CONFIG_SET_GATE_SRC:
678 ret = dio200_subdev_8254_set_gate_src(dev, s, chan, data[2]);
682 case INSN_CONFIG_GET_GATE_SRC:
683 ret = dio200_subdev_8254_get_gate_src(dev, s, chan);
690 case INSN_CONFIG_SET_CLOCK_SRC:
691 ret = dio200_subdev_8254_set_clock_src(dev, s, chan, data[1]);
695 case INSN_CONFIG_GET_CLOCK_SRC:
696 ret = dio200_subdev_8254_get_clock_src(dev, s, chan, &data[2]);
707 spin_unlock_irqrestore(&subpriv->spinlock, flags);
708 return ret < 0 ? ret : insn->n;
711 static int dio200_subdev_8254_init(struct comedi_device *dev,
712 struct comedi_subdevice *s,
715 const struct dio200_board *board = dev->board_ptr;
716 struct dio200_subdev_8254 *subpriv;
719 subpriv = comedi_alloc_spriv(s, sizeof(*subpriv));
723 s->type = COMEDI_SUBD_COUNTER;
724 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
727 s->insn_read = dio200_subdev_8254_read;
728 s->insn_write = dio200_subdev_8254_write;
729 s->insn_config = dio200_subdev_8254_config;
731 spin_lock_init(&subpriv->spinlock);
732 subpriv->ofs = offset;
733 if (board->has_clk_gat_sce) {
734 /* Derive CLK_SCE and GAT_SCE register offsets from
736 subpriv->clk_sce_ofs = DIO200_XCLK_SCE + (offset >> 3);
737 subpriv->gat_sce_ofs = DIO200_XGAT_SCE + (offset >> 3);
738 subpriv->which = (offset >> 2) & 1;
741 /* Initialize channels. */
742 for (chan = 0; chan < 3; chan++) {
743 dio200_subdev_8254_set_mode(dev, s, chan,
744 I8254_MODE0 | I8254_BINARY);
745 if (board->has_clk_gat_sce) {
746 /* Gate source 0 is VCC (logic 1). */
747 dio200_subdev_8254_set_gate_src(dev, s, chan, 0);
748 /* Clock source 0 is the dedicated clock input. */
749 dio200_subdev_8254_set_clock_src(dev, s, chan, 0);
756 static void dio200_subdev_8255_set_dir(struct comedi_device *dev,
757 struct comedi_subdevice *s)
759 struct dio200_subdev_8255 *subpriv = s->private;
762 config = I8255_CTRL_CW;
763 /* 1 in io_bits indicates output, 1 in config indicates input */
764 if (!(s->io_bits & 0x0000ff))
765 config |= I8255_CTRL_A_IO;
766 if (!(s->io_bits & 0x00ff00))
767 config |= I8255_CTRL_B_IO;
768 if (!(s->io_bits & 0x0f0000))
769 config |= I8255_CTRL_C_LO_IO;
770 if (!(s->io_bits & 0xf00000))
771 config |= I8255_CTRL_C_HI_IO;
772 dio200_write8(dev, subpriv->ofs + I8255_CTRL_REG, config);
775 static int dio200_subdev_8255_bits(struct comedi_device *dev,
776 struct comedi_subdevice *s,
777 struct comedi_insn *insn,
780 struct dio200_subdev_8255 *subpriv = s->private;
784 mask = comedi_dio_update_state(s, data);
787 dio200_write8(dev, subpriv->ofs + I8255_DATA_A_REG,
790 dio200_write8(dev, subpriv->ofs + I8255_DATA_B_REG,
791 (s->state >> 8) & 0xff);
793 dio200_write8(dev, subpriv->ofs + I8255_DATA_C_REG,
794 (s->state >> 16) & 0xff);
797 val = dio200_read8(dev, subpriv->ofs + I8255_DATA_A_REG);
798 val |= dio200_read8(dev, subpriv->ofs + I8255_DATA_B_REG) << 8;
799 val |= dio200_read8(dev, subpriv->ofs + I8255_DATA_C_REG) << 16;
806 static int dio200_subdev_8255_config(struct comedi_device *dev,
807 struct comedi_subdevice *s,
808 struct comedi_insn *insn,
811 unsigned int chan = CR_CHAN(insn->chanspec);
824 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
828 dio200_subdev_8255_set_dir(dev, s);
833 static int dio200_subdev_8255_init(struct comedi_device *dev,
834 struct comedi_subdevice *s,
837 struct dio200_subdev_8255 *subpriv;
839 subpriv = comedi_alloc_spriv(s, sizeof(*subpriv));
843 subpriv->ofs = offset;
845 s->type = COMEDI_SUBD_DIO;
846 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
848 s->range_table = &range_digital;
850 s->insn_bits = dio200_subdev_8255_bits;
851 s->insn_config = dio200_subdev_8255_config;
852 dio200_subdev_8255_set_dir(dev, s);
856 static int dio200_subdev_timer_read(struct comedi_device *dev,
857 struct comedi_subdevice *s,
858 struct comedi_insn *insn,
863 for (n = 0; n < insn->n; n++)
864 data[n] = dio200_read32(dev, DIO200_TS_COUNT);
868 static void dio200_subdev_timer_reset(struct comedi_device *dev,
869 struct comedi_subdevice *s)
873 clock = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
874 dio200_write32(dev, DIO200_TS_CONFIG, clock | TS_CONFIG_RESET);
875 dio200_write32(dev, DIO200_TS_CONFIG, clock);
878 static void dio200_subdev_timer_get_clock_src(struct comedi_device *dev,
879 struct comedi_subdevice *s,
881 unsigned int *period)
885 clk = dio200_read32(dev, DIO200_TS_CONFIG) & TS_CONFIG_CLK_SRC_MASK;
887 *period = (clk < ARRAY_SIZE(ts_clock_period)) ?
888 ts_clock_period[clk] : 0;
891 static int dio200_subdev_timer_set_clock_src(struct comedi_device *dev,
892 struct comedi_subdevice *s,
895 if (src > TS_CONFIG_MAX_CLK_SRC)
897 dio200_write32(dev, DIO200_TS_CONFIG, src);
901 static int dio200_subdev_timer_config(struct comedi_device *dev,
902 struct comedi_subdevice *s,
903 struct comedi_insn *insn,
909 case INSN_CONFIG_RESET:
910 dio200_subdev_timer_reset(dev, s);
912 case INSN_CONFIG_SET_CLOCK_SRC:
913 ret = dio200_subdev_timer_set_clock_src(dev, s, data[1]);
917 case INSN_CONFIG_GET_CLOCK_SRC:
918 dio200_subdev_timer_get_clock_src(dev, s, &data[1], &data[2]);
924 return ret < 0 ? ret : insn->n;
927 void amplc_dio200_set_enhance(struct comedi_device *dev, unsigned char val)
929 dio200_write8(dev, DIO200_ENHANCE, val);
931 EXPORT_SYMBOL_GPL(amplc_dio200_set_enhance);
933 int amplc_dio200_common_attach(struct comedi_device *dev, unsigned int irq,
934 unsigned long req_irq_flags)
936 const struct dio200_board *board = dev->board_ptr;
937 struct comedi_subdevice *s;
941 ret = comedi_alloc_subdevices(dev, board->n_subdevs);
945 for (n = 0; n < dev->n_subdevices; n++) {
946 s = &dev->subdevices[n];
947 switch (board->sdtype[n]) {
949 /* counter subdevice (8254) */
950 ret = dio200_subdev_8254_init(dev, s,
956 /* digital i/o subdevice (8255) */
957 ret = dio200_subdev_8255_init(dev, s,
963 /* 'INTERRUPT' subdevice */
964 if (irq && !dev->read_subdev) {
965 ret = dio200_subdev_intr_init(dev, s,
970 dev->read_subdev = s;
972 s->type = COMEDI_SUBD_UNUSED;
976 s->type = COMEDI_SUBD_TIMER;
977 s->subdev_flags = SDF_READABLE | SDF_LSAMPL;
979 s->maxdata = 0xffffffff;
980 s->insn_read = dio200_subdev_timer_read;
981 s->insn_config = dio200_subdev_timer_config;
984 s->type = COMEDI_SUBD_UNUSED;
989 if (irq && dev->read_subdev) {
990 if (request_irq(irq, dio200_interrupt, req_irq_flags,
991 dev->board_name, dev) >= 0) {
994 dev_warn(dev->class_dev,
995 "warning! irq %u unavailable!\n", irq);
1001 EXPORT_SYMBOL_GPL(amplc_dio200_common_attach);
1003 static int __init amplc_dio200_common_init(void)
1007 module_init(amplc_dio200_common_init);
1009 static void __exit amplc_dio200_common_exit(void)
1012 module_exit(amplc_dio200_common_exit);
1014 MODULE_AUTHOR("Comedi http://www.comedi.org");
1015 MODULE_DESCRIPTION("Comedi helper for amplc_dio200 and amplc_dio200_pci");
1016 MODULE_LICENSE("GPL");