1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 * Copyright (c) 2010, Google Inc.
4 * Original authors: Code Aurora Forum
6 * Author: Dima Zavin <dima@android.com>
7 * - Largely rewritten from original to not be an i2c driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 and
11 * only version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #define pr_fmt(fmt) "%s: " fmt, __func__
21 #include <linux/delay.h>
22 #include <linux/err.h>
24 #include <linux/kernel.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/msm_ssbi.h>
28 #include <linux/module.h>
30 #include <linux/of_device.h>
32 /* SSBI 2.0 controller registers */
33 #define SSBI2_CMD 0x0008
34 #define SSBI2_RD 0x0010
35 #define SSBI2_STATUS 0x0014
36 #define SSBI2_MODE2 0x001C
39 #define SSBI_CMD_RDWRN (1 << 24)
41 /* SSBI_STATUS fields */
42 #define SSBI_STATUS_RD_READY (1 << 2)
43 #define SSBI_STATUS_READY (1 << 1)
44 #define SSBI_STATUS_MCHN_BUSY (1 << 0)
46 /* SSBI_MODE2 fields */
47 #define SSBI_MODE2_REG_ADDR_15_8_SHFT 0x04
48 #define SSBI_MODE2_REG_ADDR_15_8_MASK (0x7f << SSBI_MODE2_REG_ADDR_15_8_SHFT)
50 #define SET_SSBI_MODE2_REG_ADDR_15_8(MD, AD) \
51 (((MD) & 0x0F) | ((((AD) >> 8) << SSBI_MODE2_REG_ADDR_15_8_SHFT) & \
52 SSBI_MODE2_REG_ADDR_15_8_MASK))
54 /* SSBI PMIC Arbiter command registers */
55 #define SSBI_PA_CMD 0x0000
56 #define SSBI_PA_RD_STATUS 0x0004
58 /* SSBI_PA_CMD fields */
59 #define SSBI_PA_CMD_RDWRN (1 << 24)
60 #define SSBI_PA_CMD_ADDR_MASK 0x7fff /* REG_ADDR_7_0, REG_ADDR_8_14*/
62 /* SSBI_PA_RD_STATUS fields */
63 #define SSBI_PA_RD_STATUS_TRANS_DONE (1 << 27)
64 #define SSBI_PA_RD_STATUS_TRANS_DENIED (1 << 26)
66 #define SSBI_TIMEOUT_US 100
73 enum msm_ssbi_controller_type controller_type;
74 int (*read)(struct msm_ssbi *, u16 addr, u8 *buf, int len);
75 int (*write)(struct msm_ssbi *, u16 addr, u8 *buf, int len);
78 #define to_msm_ssbi(dev) platform_get_drvdata(to_platform_device(dev))
80 static inline u32 ssbi_readl(struct msm_ssbi *ssbi, u32 reg)
82 return readl(ssbi->base + reg);
85 static inline void ssbi_writel(struct msm_ssbi *ssbi, u32 val, u32 reg)
87 writel(val, ssbi->base + reg);
90 static int ssbi_wait_mask(struct msm_ssbi *ssbi, u32 set_mask, u32 clr_mask)
92 u32 timeout = SSBI_TIMEOUT_US;
96 val = ssbi_readl(ssbi, SSBI2_STATUS);
97 if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0))
102 dev_err(ssbi->dev, "%s: timeout (status %x set_mask %x clr_mask %x)\n",
103 __func__, ssbi_readl(ssbi, SSBI2_STATUS), set_mask, clr_mask);
108 msm_ssbi_read_bytes(struct msm_ssbi *ssbi, u16 addr, u8 *buf, int len)
110 u32 cmd = SSBI_CMD_RDWRN | ((addr & 0xff) << 16);
113 if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
114 u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
115 mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
116 ssbi_writel(ssbi, mode2, SSBI2_MODE2);
120 ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
124 ssbi_writel(ssbi, cmd, SSBI2_CMD);
125 ret = ssbi_wait_mask(ssbi, SSBI_STATUS_RD_READY, 0);
128 *buf++ = ssbi_readl(ssbi, SSBI2_RD) & 0xff;
137 msm_ssbi_write_bytes(struct msm_ssbi *ssbi, u16 addr, u8 *buf, int len)
141 if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) {
142 u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2);
143 mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr);
144 ssbi_writel(ssbi, mode2, SSBI2_MODE2);
148 ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0);
152 ssbi_writel(ssbi, ((addr & 0xff) << 16) | *buf, SSBI2_CMD);
153 ret = ssbi_wait_mask(ssbi, 0, SSBI_STATUS_MCHN_BUSY);
165 msm_ssbi_pa_transfer(struct msm_ssbi *ssbi, u32 cmd, u8 *data)
167 u32 timeout = SSBI_TIMEOUT_US;
170 ssbi_writel(ssbi, cmd, SSBI_PA_CMD);
173 rd_status = ssbi_readl(ssbi, SSBI_PA_RD_STATUS);
175 if (rd_status & SSBI_PA_RD_STATUS_TRANS_DENIED) {
176 dev_err(ssbi->dev, "%s: transaction denied (0x%x)\n",
177 __func__, rd_status);
181 if (rd_status & SSBI_PA_RD_STATUS_TRANS_DONE) {
183 *data = rd_status & 0xff;
189 dev_err(ssbi->dev, "%s: timeout, status 0x%x\n", __func__, rd_status);
194 msm_ssbi_pa_read_bytes(struct msm_ssbi *ssbi, u16 addr, u8 *buf, int len)
199 cmd = SSBI_PA_CMD_RDWRN | (addr & SSBI_PA_CMD_ADDR_MASK) << 8;
202 ret = msm_ssbi_pa_transfer(ssbi, cmd, buf);
214 msm_ssbi_pa_write_bytes(struct msm_ssbi *ssbi, u16 addr, u8 *buf, int len)
220 cmd = (addr & SSBI_PA_CMD_ADDR_MASK) << 8 | *buf;
221 ret = msm_ssbi_pa_transfer(ssbi, cmd, NULL);
232 int msm_ssbi_read(struct device *dev, u16 addr, u8 *buf, int len)
234 struct msm_ssbi *ssbi = to_msm_ssbi(dev);
238 if (ssbi->dev != dev)
241 spin_lock_irqsave(&ssbi->lock, flags);
242 ret = ssbi->read(ssbi, addr, buf, len);
243 spin_unlock_irqrestore(&ssbi->lock, flags);
247 EXPORT_SYMBOL_GPL(msm_ssbi_read);
249 int msm_ssbi_write(struct device *dev, u16 addr, u8 *buf, int len)
251 struct msm_ssbi *ssbi = to_msm_ssbi(dev);
255 if (ssbi->dev != dev)
258 spin_lock_irqsave(&ssbi->lock, flags);
259 ret = ssbi->write(ssbi, addr, buf, len);
260 spin_unlock_irqrestore(&ssbi->lock, flags);
264 EXPORT_SYMBOL_GPL(msm_ssbi_write);
266 static int msm_ssbi_probe(struct platform_device *pdev)
268 struct device_node *np = pdev->dev.of_node;
269 struct resource *mem_res;
270 struct msm_ssbi *ssbi;
274 ssbi = kzalloc(sizeof(struct msm_ssbi), GFP_KERNEL);
276 pr_err("can not allocate ssbi_data\n");
280 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
282 pr_err("missing mem resource\n");
284 goto err_get_mem_res;
287 ssbi->base = ioremap(mem_res->start, resource_size(mem_res));
289 pr_err("ioremap of 0x%p failed\n", (void *)mem_res->start);
293 ssbi->dev = &pdev->dev;
294 platform_set_drvdata(pdev, ssbi);
296 type = of_get_property(np, "qcom,controller-type", NULL);
298 pr_err("Missing qcom,controller-type property\n");
300 goto err_ssbi_controller;
302 dev_info(&pdev->dev, "SSBI controller type: '%s'\n", type);
303 if (strcmp(type, "ssbi") == 0)
304 ssbi->controller_type = MSM_SBI_CTRL_SSBI;
305 else if (strcmp(type, "ssbi2") == 0)
306 ssbi->controller_type = MSM_SBI_CTRL_SSBI2;
307 else if (strcmp(type, "pmic-arbiter") == 0)
308 ssbi->controller_type = MSM_SBI_CTRL_PMIC_ARBITER;
310 pr_err("Unknown qcom,controller-type\n");
312 goto err_ssbi_controller;
315 if (ssbi->controller_type == MSM_SBI_CTRL_PMIC_ARBITER) {
316 ssbi->read = msm_ssbi_pa_read_bytes;
317 ssbi->write = msm_ssbi_pa_write_bytes;
319 ssbi->read = msm_ssbi_read_bytes;
320 ssbi->write = msm_ssbi_write_bytes;
323 spin_lock_init(&ssbi->lock);
325 ret = of_platform_populate(np, NULL, NULL, &pdev->dev);
327 goto err_ssbi_controller;
332 platform_set_drvdata(pdev, NULL);
340 static int msm_ssbi_remove(struct platform_device *pdev)
342 struct msm_ssbi *ssbi = platform_get_drvdata(pdev);
344 platform_set_drvdata(pdev, NULL);
350 static struct of_device_id ssbi_match_table[] = {
351 { .compatible = "qcom,ssbi" },
355 static struct platform_driver msm_ssbi_driver = {
356 .probe = msm_ssbi_probe,
357 .remove = msm_ssbi_remove,
360 .owner = THIS_MODULE,
361 .of_match_table = ssbi_match_table,
365 static int __init msm_ssbi_init(void)
367 return platform_driver_register(&msm_ssbi_driver);
369 postcore_initcall(msm_ssbi_init);
371 static void __exit msm_ssbi_exit(void)
373 platform_driver_unregister(&msm_ssbi_driver);
375 module_exit(msm_ssbi_exit)
377 MODULE_LICENSE("GPL v2");
378 MODULE_VERSION("1.0");
379 MODULE_ALIAS("platform:msm_ssbi");
380 MODULE_AUTHOR("Dima Zavin <dima@android.com>");