2 * Xilinx SPI controller driver (master mode only)
4 * Author: MontaVista Software, Inc.
7 * Copyright (c) 2010 Secret Lab Technologies, Ltd.
8 * Copyright (c) 2009 Intel Corporation
9 * 2002-2007 (c) MontaVista Software, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
19 #include <linux/platform_device.h>
20 #include <linux/spi/spi.h>
21 #include <linux/spi/spi_bitbang.h>
22 #include <linux/spi/xilinx_spi.h>
25 #define XILINX_SPI_NAME "xilinx_spi"
27 /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
28 * Product Specification", DS464
30 #define XSPI_CR_OFFSET 0x60 /* Control Register */
32 #define XSPI_CR_LOOP 0x01
33 #define XSPI_CR_ENABLE 0x02
34 #define XSPI_CR_MASTER_MODE 0x04
35 #define XSPI_CR_CPOL 0x08
36 #define XSPI_CR_CPHA 0x10
37 #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \
38 XSPI_CR_LSB_FIRST | XSPI_CR_LOOP)
39 #define XSPI_CR_TXFIFO_RESET 0x20
40 #define XSPI_CR_RXFIFO_RESET 0x40
41 #define XSPI_CR_MANUAL_SSELECT 0x80
42 #define XSPI_CR_TRANS_INHIBIT 0x100
43 #define XSPI_CR_LSB_FIRST 0x200
45 #define XSPI_SR_OFFSET 0x64 /* Status Register */
47 #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
48 #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
49 #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
50 #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
51 #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
53 #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
54 #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
56 #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
58 /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
59 * IPIF registers are 32 bit
61 #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
62 #define XIPIF_V123B_GINTR_ENABLE 0x80000000
64 #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
65 #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
67 #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
68 #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
70 #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
71 #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
72 #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
73 #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
74 #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
76 #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
77 #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
80 /* bitbang has to be first */
81 struct spi_bitbang bitbang;
82 struct completion done;
83 void __iomem *regs; /* virt. address of the control registers */
87 u8 *rx_ptr; /* pointer in the Tx buffer */
88 const u8 *tx_ptr; /* pointer in the Rx buffer */
89 int remaining_words; /* the number of words left to transfer */
91 int buffer_size; /* buffer size in words */
92 u32 cs_inactive; /* Level of the CS pins when inactive*/
93 unsigned int (*read_fn)(void __iomem *);
94 void (*write_fn)(u32, void __iomem *);
97 static void xspi_write32(u32 val, void __iomem *addr)
102 static unsigned int xspi_read32(void __iomem *addr)
104 return ioread32(addr);
107 static void xspi_write32_be(u32 val, void __iomem *addr)
109 iowrite32be(val, addr);
112 static unsigned int xspi_read32_be(void __iomem *addr)
114 return ioread32be(addr);
117 static void xilinx_spi_tx(struct xilinx_spi *xspi)
120 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
123 xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
124 xspi->tx_ptr += xspi->bits_per_word / 8;
127 static void xilinx_spi_rx(struct xilinx_spi *xspi)
129 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
134 switch (xspi->bits_per_word) {
136 *(u8 *)(xspi->rx_ptr) = data;
139 *(u16 *)(xspi->rx_ptr) = data;
142 *(u32 *)(xspi->rx_ptr) = data;
146 xspi->rx_ptr += xspi->bits_per_word / 8;
149 static void xspi_init_hw(struct xilinx_spi *xspi)
151 void __iomem *regs_base = xspi->regs;
154 /* Reset the SPI device */
155 xspi->write_fn(XIPIF_V123B_RESET_MASK,
156 regs_base + XIPIF_V123B_RESETR_OFFSET);
157 /* Enable the transmit empty interrupt, which we use to determine
158 * progress on the transmission.
160 xspi->write_fn(XSPI_INTR_TX_EMPTY,
161 regs_base + XIPIF_V123B_IIER_OFFSET);
162 /* Enable the global IPIF interrupt */
163 if (xspi->irq >= 0) {
164 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
165 regs_base + XIPIF_V123B_DGIER_OFFSET);
166 inhibit = XSPI_CR_TRANS_INHIBIT;
168 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
171 /* Deselect the slave on the SPI bus */
172 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
173 /* Disable the transmitter, enable Manual Slave Select Assertion,
174 * put SPI controller into master mode, and enable it */
175 xspi->write_fn(inhibit | XSPI_CR_MANUAL_SSELECT |
176 XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |
177 XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
180 static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
182 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
186 if (is_on == BITBANG_CS_INACTIVE) {
187 /* Deselect the slave on the SPI bus */
188 xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET);
192 /* Set the SPI clock phase and polarity */
193 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK;
194 if (spi->mode & SPI_CPHA)
196 if (spi->mode & SPI_CPOL)
198 if (spi->mode & SPI_LSB_FIRST)
199 cr |= XSPI_CR_LSB_FIRST;
200 if (spi->mode & SPI_LOOP)
202 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
204 /* We do not check spi->max_speed_hz here as the SPI clock
205 * frequency is not software programmable (the IP block design
209 cs = xspi->cs_inactive;
210 cs ^= BIT(spi->chip_select);
212 /* Activate the chip select */
213 xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET);
216 /* spi_bitbang requires custom setup_transfer() to be defined if there is a
217 * custom txrx_bufs().
219 static int xilinx_spi_setup_transfer(struct spi_device *spi,
220 struct spi_transfer *t)
222 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
224 if (spi->mode & SPI_CS_HIGH)
225 xspi->cs_inactive &= ~BIT(spi->chip_select);
227 xspi->cs_inactive |= BIT(spi->chip_select);
232 static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi, int n_words)
234 xspi->remaining_words -= n_words;
241 static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
243 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
245 /* We get here with transmitter inhibited */
247 xspi->tx_ptr = t->tx_buf;
248 xspi->rx_ptr = t->rx_buf;
249 xspi->remaining_words = (t->len * 8) / xspi->bits_per_word;
250 reinit_completion(&xspi->done);
252 while (xspi->remaining_words) {
256 n_words = min(xspi->remaining_words, xspi->buffer_size);
258 xilinx_spi_fill_tx_fifo(xspi, n_words);
260 /* Start the transfer by not inhibiting the transmitter any
264 if (xspi->irq >= 0) {
265 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
266 ~XSPI_CR_TRANS_INHIBIT;
267 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
268 wait_for_completion(&xspi->done);
270 while (!(xspi->read_fn(xspi->regs + XSPI_SR_OFFSET) &
271 XSPI_SR_TX_EMPTY_MASK))
274 /* A transmit has just completed. Process received data and
275 * check for more data to transmit. Always inhibit the
276 * transmitter while the Isr refills the transmit register/FIFO,
277 * or make sure it is stopped if we're done.
280 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
281 xspi->regs + XSPI_CR_OFFSET);
283 /* Read out all the data from the Rx FIFO */
292 /* This driver supports single master mode only. Hence Tx FIFO Empty
293 * is the only interrupt we care about.
294 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
295 * Fault are not to happen.
297 static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
299 struct xilinx_spi *xspi = dev_id;
302 /* Get the IPIF interrupts, and clear them immediately */
303 ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
304 xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
306 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
307 complete(&xspi->done);
313 static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi)
319 * Before the buffer_size detection we reset the core
320 * to make sure we start with a clean state.
322 xspi->write_fn(XIPIF_V123B_RESET_MASK,
323 xspi->regs + XIPIF_V123B_RESETR_OFFSET);
325 /* Fill the Tx FIFO with as many words as possible */
327 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
328 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
330 } while (!(sr & XSPI_SR_TX_FULL_MASK));
335 static const struct of_device_id xilinx_spi_of_match[] = {
336 { .compatible = "xlnx,xps-spi-2.00.a", },
337 { .compatible = "xlnx,xps-spi-2.00.b", },
340 MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
342 static int xilinx_spi_probe(struct platform_device *pdev)
344 struct xilinx_spi *xspi;
345 struct xspi_platform_data *pdata;
346 struct resource *res;
347 int ret, num_cs = 0, bits_per_word = 8;
348 struct spi_master *master;
352 pdata = dev_get_platdata(&pdev->dev);
354 num_cs = pdata->num_chipselect;
355 bits_per_word = pdata->bits_per_word;
357 of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
363 "Missing slave select configuration data\n");
367 master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
371 /* the spi->mode bits understood by this driver: */
372 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP |
375 xspi = spi_master_get_devdata(master);
376 xspi->cs_inactive = 0xffffffff;
377 xspi->bitbang.master = master;
378 xspi->bitbang.chipselect = xilinx_spi_chipselect;
379 xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
380 xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
381 init_completion(&xspi->done);
383 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
384 xspi->regs = devm_ioremap_resource(&pdev->dev, res);
385 if (IS_ERR(xspi->regs)) {
386 ret = PTR_ERR(xspi->regs);
390 master->bus_num = pdev->id;
391 master->num_chipselect = num_cs;
392 master->dev.of_node = pdev->dev.of_node;
395 * Detect endianess on the IP via loop bit in CR. Detection
396 * must be done before reset is sent because incorrect reset
397 * value generates error interrupt.
398 * Setup little endian helper functions first and try to use them
399 * and check if bit was correctly setup or not.
401 xspi->read_fn = xspi_read32;
402 xspi->write_fn = xspi_write32;
404 xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
405 tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
407 if (tmp != XSPI_CR_LOOP) {
408 xspi->read_fn = xspi_read32_be;
409 xspi->write_fn = xspi_write32_be;
412 master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word);
413 xspi->bits_per_word = bits_per_word;
414 xspi->buffer_size = xilinx_spi_find_buffer_size(xspi);
416 xspi->irq = platform_get_irq(pdev, 0);
417 if (xspi->irq >= 0) {
418 /* Register for SPI Interrupt */
419 ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
420 dev_name(&pdev->dev), xspi);
425 /* SPI controller initializations */
428 ret = spi_bitbang_start(&xspi->bitbang);
430 dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
434 dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
435 (unsigned long long)res->start, xspi->regs, xspi->irq);
438 for (i = 0; i < pdata->num_devices; i++)
439 spi_new_device(master, pdata->devices + i);
442 platform_set_drvdata(pdev, master);
446 spi_master_put(master);
451 static int xilinx_spi_remove(struct platform_device *pdev)
453 struct spi_master *master = platform_get_drvdata(pdev);
454 struct xilinx_spi *xspi = spi_master_get_devdata(master);
455 void __iomem *regs_base = xspi->regs;
457 spi_bitbang_stop(&xspi->bitbang);
459 /* Disable all the interrupts just in case */
460 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
461 /* Disable the global IPIF interrupt */
462 xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
464 spi_master_put(xspi->bitbang.master);
469 /* work with hotplug and coldplug */
470 MODULE_ALIAS("platform:" XILINX_SPI_NAME);
472 static struct platform_driver xilinx_spi_driver = {
473 .probe = xilinx_spi_probe,
474 .remove = xilinx_spi_remove,
476 .name = XILINX_SPI_NAME,
477 .of_match_table = xilinx_spi_of_match,
480 module_platform_driver(xilinx_spi_driver);
482 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
483 MODULE_DESCRIPTION("Xilinx SPI driver");
484 MODULE_LICENSE("GPL");