2 * SuperH MSIOF SPI Master Interface
4 * Copyright (c) 2009 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/bitmap.h>
13 #include <linux/clk.h>
14 #include <linux/completion.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/spi/sh_msiof.h>
27 #include <linux/spi/spi.h>
28 #include <linux/spi/spi_bitbang.h>
30 #include <asm/unaligned.h>
32 struct sh_msiof_spi_priv {
33 struct spi_bitbang bitbang; /* must be first for spi_bitbang.c */
34 void __iomem *mapbase;
36 struct platform_device *pdev;
37 struct sh_msiof_spi_info *info;
38 struct completion done;
63 #define CTR_TSCKE (1 << 15)
64 #define CTR_TFSE (1 << 14)
65 #define CTR_TXE (1 << 9)
66 #define CTR_RXE (1 << 8)
68 #define STR_TEOF (1 << 23)
69 #define STR_REOF (1 << 7)
71 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
76 return ioread16(p->mapbase + reg_offs);
78 return ioread32(p->mapbase + reg_offs);
82 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
88 iowrite16(value, p->mapbase + reg_offs);
91 iowrite32(value, p->mapbase + reg_offs);
96 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
103 data = sh_msiof_read(p, CTR);
106 sh_msiof_write(p, CTR, data);
108 for (k = 100; k > 0; k--) {
109 if ((sh_msiof_read(p, CTR) & mask) == set)
115 return k > 0 ? 0 : -ETIMEDOUT;
118 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
120 struct sh_msiof_spi_priv *p = data;
122 /* just disable the interrupt and wake up */
123 sh_msiof_write(p, IER, 0);
132 } const sh_msiof_spi_clk_table[] = {
146 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
147 unsigned long parent_rate,
148 unsigned long spi_hz)
150 unsigned long div = 1024;
153 if (!WARN_ON(!spi_hz || !parent_rate))
154 div = parent_rate / spi_hz;
156 /* TODO: make more fine grained */
158 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_clk_table); k++) {
159 if (sh_msiof_spi_clk_table[k].div >= div)
163 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1);
165 sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr);
166 sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr);
169 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
171 u32 tx_hi_z, u32 lsb_first)
177 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
183 sh_msiof_write(p, FCTR, 0);
184 sh_msiof_write(p, TMDR1, 0xe2000005 | (lsb_first << 24));
185 sh_msiof_write(p, RMDR1, 0x22000005 | (lsb_first << 24));
188 tmp |= cpol << 30; /* TSCKIZ */
189 tmp |= cpol << 28; /* RSCKIZ */
193 tmp |= edge << 27; /* TEDG */
194 tmp |= edge << 26; /* REDG */
195 tmp |= (tx_hi_z ? 2 : 0) << 22; /* TXDIZ */
196 sh_msiof_write(p, CTR, tmp);
199 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
200 const void *tx_buf, void *rx_buf,
203 u32 dr2 = ((bits - 1) << 24) | ((words - 1) << 16);
206 sh_msiof_write(p, TMDR2, dr2);
208 sh_msiof_write(p, TMDR2, dr2 | 1);
211 sh_msiof_write(p, RMDR2, dr2);
213 sh_msiof_write(p, IER, STR_TEOF | STR_REOF);
216 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
218 sh_msiof_write(p, STR, sh_msiof_read(p, STR));
221 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
222 const void *tx_buf, int words, int fs)
224 const u8 *buf_8 = tx_buf;
227 for (k = 0; k < words; k++)
228 sh_msiof_write(p, TFDR, buf_8[k] << fs);
231 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
232 const void *tx_buf, int words, int fs)
234 const u16 *buf_16 = tx_buf;
237 for (k = 0; k < words; k++)
238 sh_msiof_write(p, TFDR, buf_16[k] << fs);
241 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
242 const void *tx_buf, int words, int fs)
244 const u16 *buf_16 = tx_buf;
247 for (k = 0; k < words; k++)
248 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
251 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
252 const void *tx_buf, int words, int fs)
254 const u32 *buf_32 = tx_buf;
257 for (k = 0; k < words; k++)
258 sh_msiof_write(p, TFDR, buf_32[k] << fs);
261 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
262 const void *tx_buf, int words, int fs)
264 const u32 *buf_32 = tx_buf;
267 for (k = 0; k < words; k++)
268 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
271 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
272 const void *tx_buf, int words, int fs)
274 const u32 *buf_32 = tx_buf;
277 for (k = 0; k < words; k++)
278 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
281 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
282 const void *tx_buf, int words, int fs)
284 const u32 *buf_32 = tx_buf;
287 for (k = 0; k < words; k++)
288 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
291 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
292 void *rx_buf, int words, int fs)
297 for (k = 0; k < words; k++)
298 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
301 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
302 void *rx_buf, int words, int fs)
304 u16 *buf_16 = rx_buf;
307 for (k = 0; k < words; k++)
308 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
311 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
312 void *rx_buf, int words, int fs)
314 u16 *buf_16 = rx_buf;
317 for (k = 0; k < words; k++)
318 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
321 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
322 void *rx_buf, int words, int fs)
324 u32 *buf_32 = rx_buf;
327 for (k = 0; k < words; k++)
328 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
331 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
332 void *rx_buf, int words, int fs)
334 u32 *buf_32 = rx_buf;
337 for (k = 0; k < words; k++)
338 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
341 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
342 void *rx_buf, int words, int fs)
344 u32 *buf_32 = rx_buf;
347 for (k = 0; k < words; k++)
348 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
351 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
352 void *rx_buf, int words, int fs)
354 u32 *buf_32 = rx_buf;
357 for (k = 0; k < words; k++)
358 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
361 static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t)
365 bits = t ? t->bits_per_word : 0;
367 bits = spi->bits_per_word;
371 static unsigned long sh_msiof_spi_hz(struct spi_device *spi,
372 struct spi_transfer *t)
376 hz = t ? t->speed_hz : 0;
378 hz = spi->max_speed_hz;
382 static int sh_msiof_spi_setup_transfer(struct spi_device *spi,
383 struct spi_transfer *t)
387 /* noting to check hz values against since parent clock is disabled */
389 bits = sh_msiof_spi_bits(spi, t);
395 return spi_bitbang_setup_transfer(spi, t);
398 static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on)
400 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
403 /* chip select is active low unless SPI_CS_HIGH is set */
404 if (spi->mode & SPI_CS_HIGH)
405 value = (is_on == BITBANG_CS_ACTIVE) ? 1 : 0;
407 value = (is_on == BITBANG_CS_ACTIVE) ? 0 : 1;
409 if (is_on == BITBANG_CS_ACTIVE) {
410 if (!test_and_set_bit(0, &p->flags)) {
411 pm_runtime_get_sync(&p->pdev->dev);
415 /* Configure pins before asserting CS */
416 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
417 !!(spi->mode & SPI_CPHA),
418 !!(spi->mode & SPI_3WIRE),
419 !!(spi->mode & SPI_LSB_FIRST));
422 /* use spi->controller data for CS (same strategy as spi_gpio) */
423 gpio_set_value((unsigned)spi->controller_data, value);
425 if (is_on == BITBANG_CS_INACTIVE) {
426 if (test_and_clear_bit(0, &p->flags)) {
428 pm_runtime_put(&p->pdev->dev);
433 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
434 void (*tx_fifo)(struct sh_msiof_spi_priv *,
435 const void *, int, int),
436 void (*rx_fifo)(struct sh_msiof_spi_priv *,
438 const void *tx_buf, void *rx_buf,
444 /* limit maximum word transfer to rx/tx fifo size */
446 words = min_t(int, words, p->tx_fifo_size);
448 words = min_t(int, words, p->rx_fifo_size);
450 /* the fifo contents need shifting */
451 fifo_shift = 32 - bits;
453 /* setup msiof transfer mode registers */
454 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
458 tx_fifo(p, tx_buf, words, fifo_shift);
460 /* setup clock and rx/tx signals */
461 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
463 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
464 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
466 /* start by setting frame bit */
467 INIT_COMPLETION(p->done);
468 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
470 dev_err(&p->pdev->dev, "failed to start hardware\n");
474 /* wait for tx fifo to be emptied / rx fifo to be filled */
475 wait_for_completion(&p->done);
479 rx_fifo(p, rx_buf, words, fifo_shift);
481 /* clear status bits */
482 sh_msiof_reset_str(p);
484 /* shut down frame, tx/tx and clock signals */
485 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
486 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
488 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
489 ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
491 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
498 sh_msiof_write(p, IER, 0);
502 static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
504 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
505 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
506 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
514 bits = sh_msiof_spi_bits(spi, t);
516 if (bits <= 8 && t->len > 15 && !(t->len & 3)) {
523 /* setup bytes per word and fifo read/write functions */
526 tx_fifo = sh_msiof_spi_write_fifo_8;
527 rx_fifo = sh_msiof_spi_read_fifo_8;
528 } else if (bits <= 16) {
530 if ((unsigned long)t->tx_buf & 0x01)
531 tx_fifo = sh_msiof_spi_write_fifo_16u;
533 tx_fifo = sh_msiof_spi_write_fifo_16;
535 if ((unsigned long)t->rx_buf & 0x01)
536 rx_fifo = sh_msiof_spi_read_fifo_16u;
538 rx_fifo = sh_msiof_spi_read_fifo_16;
541 if ((unsigned long)t->tx_buf & 0x03)
542 tx_fifo = sh_msiof_spi_write_fifo_s32u;
544 tx_fifo = sh_msiof_spi_write_fifo_s32;
546 if ((unsigned long)t->rx_buf & 0x03)
547 rx_fifo = sh_msiof_spi_read_fifo_s32u;
549 rx_fifo = sh_msiof_spi_read_fifo_s32;
552 if ((unsigned long)t->tx_buf & 0x03)
553 tx_fifo = sh_msiof_spi_write_fifo_32u;
555 tx_fifo = sh_msiof_spi_write_fifo_32;
557 if ((unsigned long)t->rx_buf & 0x03)
558 rx_fifo = sh_msiof_spi_read_fifo_32u;
560 rx_fifo = sh_msiof_spi_read_fifo_32;
563 /* setup clocks (clock already enabled in chipselect()) */
564 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk),
565 sh_msiof_spi_hz(spi, t));
567 /* transfer in fifo sized chunks */
568 words = t->len / bytes_per_word;
571 while (bytes_done < t->len) {
572 void *rx_buf = t->rx_buf ? t->rx_buf + bytes_done : NULL;
573 const void *tx_buf = t->tx_buf ? t->tx_buf + bytes_done : NULL;
574 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo,
581 bytes_done += n * bytes_per_word;
588 static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs,
591 BUG(); /* unused but needed by bitbang code */
595 static int sh_msiof_spi_probe(struct platform_device *pdev)
598 struct spi_master *master;
599 struct sh_msiof_spi_priv *p;
604 master = spi_alloc_master(&pdev->dev, sizeof(struct sh_msiof_spi_priv));
605 if (master == NULL) {
606 dev_err(&pdev->dev, "failed to allocate spi master\n");
611 p = spi_master_get_devdata(master);
613 platform_set_drvdata(pdev, p);
614 p->info = pdev->dev.platform_data;
615 init_completion(&p->done);
617 snprintf(clk_name, sizeof(clk_name), "msiof%d", pdev->id);
618 p->clk = clk_get(&pdev->dev, clk_name);
619 if (IS_ERR(p->clk)) {
620 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
621 ret = PTR_ERR(p->clk);
625 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
626 i = platform_get_irq(pdev, 0);
628 dev_err(&pdev->dev, "cannot get platform resources\n");
632 p->mapbase = ioremap_nocache(r->start, resource_size(r));
634 dev_err(&pdev->dev, "unable to ioremap\n");
639 ret = request_irq(i, sh_msiof_spi_irq, 0,
640 dev_name(&pdev->dev), p);
642 dev_err(&pdev->dev, "unable to request irq\n");
647 pm_runtime_enable(&pdev->dev);
649 /* The standard version of MSIOF use 64 word FIFOs */
650 p->tx_fifo_size = 64;
651 p->rx_fifo_size = 64;
653 /* Platform data may override FIFO sizes */
654 if (p->info->tx_fifo_override)
655 p->tx_fifo_size = p->info->tx_fifo_override;
656 if (p->info->rx_fifo_override)
657 p->rx_fifo_size = p->info->rx_fifo_override;
659 /* init master and bitbang code */
660 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
661 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
663 master->bus_num = pdev->id;
664 master->num_chipselect = p->info->num_chipselect;
665 master->setup = spi_bitbang_setup;
666 master->cleanup = spi_bitbang_cleanup;
668 p->bitbang.master = master;
669 p->bitbang.chipselect = sh_msiof_spi_chipselect;
670 p->bitbang.setup_transfer = sh_msiof_spi_setup_transfer;
671 p->bitbang.txrx_bufs = sh_msiof_spi_txrx;
672 p->bitbang.txrx_word[SPI_MODE_0] = sh_msiof_spi_txrx_word;
673 p->bitbang.txrx_word[SPI_MODE_1] = sh_msiof_spi_txrx_word;
674 p->bitbang.txrx_word[SPI_MODE_2] = sh_msiof_spi_txrx_word;
675 p->bitbang.txrx_word[SPI_MODE_3] = sh_msiof_spi_txrx_word;
677 ret = spi_bitbang_start(&p->bitbang);
681 pm_runtime_disable(&pdev->dev);
687 spi_master_put(master);
692 static int sh_msiof_spi_remove(struct platform_device *pdev)
694 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
697 ret = spi_bitbang_stop(&p->bitbang);
699 pm_runtime_disable(&pdev->dev);
700 free_irq(platform_get_irq(pdev, 0), p);
703 spi_master_put(p->bitbang.master);
708 static int sh_msiof_spi_runtime_nop(struct device *dev)
710 /* Runtime PM callback shared between ->runtime_suspend()
711 * and ->runtime_resume(). Simply returns success.
713 * This driver re-initializes all registers after
714 * pm_runtime_get_sync() anyway so there is no need
715 * to save and restore registers here.
720 static struct dev_pm_ops sh_msiof_spi_dev_pm_ops = {
721 .runtime_suspend = sh_msiof_spi_runtime_nop,
722 .runtime_resume = sh_msiof_spi_runtime_nop,
725 static struct platform_driver sh_msiof_spi_drv = {
726 .probe = sh_msiof_spi_probe,
727 .remove = sh_msiof_spi_remove,
729 .name = "spi_sh_msiof",
730 .owner = THIS_MODULE,
731 .pm = &sh_msiof_spi_dev_pm_ops,
734 module_platform_driver(sh_msiof_spi_drv);
736 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
737 MODULE_AUTHOR("Magnus Damm");
738 MODULE_LICENSE("GPL v2");
739 MODULE_ALIAS("platform:spi_sh_msiof");