2 * SuperH HSPI bus driver
4 * Copyright (C) 2011 Kuninori Morimoto
7 * Based on pxa2xx_spi.c:
8 * Copyright (C) 2011 Renesas Solutions Corp.
9 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include <linux/clk.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/timer.h>
25 #include <linux/delay.h>
26 #include <linux/list.h>
27 #include <linux/interrupt.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
31 #include <linux/spi/spi.h>
32 #include <linux/spi/sh_hspi.h>
46 struct spi_master *master;
54 static void hspi_write(struct hspi_priv *hspi, int reg, u32 val)
56 iowrite32(val, hspi->addr + reg);
59 static u32 hspi_read(struct hspi_priv *hspi, int reg)
61 return ioread32(hspi->addr + reg);
64 static void hspi_bit_set(struct hspi_priv *hspi, int reg, u32 mask, u32 set)
66 u32 val = hspi_read(hspi, reg);
71 hspi_write(hspi, reg, val);
77 static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val)
82 if ((mask & hspi_read(hspi, SPSR)) == val)
88 dev_err(hspi->dev, "timeout\n");
96 #define hspi_hw_cs_enable(hspi) hspi_hw_cs_ctrl(hspi, 0)
97 #define hspi_hw_cs_disable(hspi) hspi_hw_cs_ctrl(hspi, 1)
98 static void hspi_hw_cs_ctrl(struct hspi_priv *hspi, int hi)
100 hspi_bit_set(hspi, SPSCR, (1 << 6), (hi) << 6);
103 static void hspi_hw_setup(struct hspi_priv *hspi,
104 struct spi_message *msg,
105 struct spi_transfer *t)
107 struct spi_device *spi = msg->spi;
108 struct device *dev = hspi->dev;
110 u32 rate, best_rate, min, tmp;
113 * find best IDIV/CLKCx settings
118 for (idiv_clk = 0x00; idiv_clk <= 0x3F; idiv_clk++) {
119 rate = clk_get_rate(hspi->clk);
121 /* IDIV calculation */
122 if (idiv_clk & (1 << 5))
127 /* CLKCx calculation */
128 rate /= (((idiv_clk & 0x1F) + 1) * 2);
130 /* save best settings */
131 tmp = abs(t->speed_hz - rate);
139 if (spi->mode & SPI_CPHA)
141 if (spi->mode & SPI_CPOL)
144 dev_dbg(dev, "speed %d/%d\n", t->speed_hz, best_rate);
146 hspi_write(hspi, SPCR, spcr);
147 hspi_write(hspi, SPSR, 0x0);
148 hspi_write(hspi, SPSCR, 0x21); /* master mode / CS control */
151 static int hspi_transfer_one_message(struct spi_master *master,
152 struct spi_message *msg)
154 struct hspi_priv *hspi = spi_master_get_devdata(master);
155 struct spi_transfer *t;
159 unsigned int cs_change;
160 const int nsecs = 50;
162 dev_dbg(hspi->dev, "%s\n", __func__);
166 list_for_each_entry(t, &msg->transfers, transfer_list) {
169 hspi_hw_setup(hspi, msg, t);
170 hspi_hw_cs_enable(hspi);
173 cs_change = t->cs_change;
175 for (i = 0; i < t->len; i++) {
178 ret = hspi_status_check_timeout(hspi, 0x1, 0);
184 tx = (u32)((u8 *)t->tx_buf)[i];
186 hspi_write(hspi, SPTBR, tx);
189 ret = hspi_status_check_timeout(hspi, 0x4, 0x4);
193 rx = hspi_read(hspi, SPRBR);
195 ((u8 *)t->rx_buf)[i] = (u8)rx;
199 msg->actual_length += t->len;
202 udelay(t->delay_usecs);
206 hspi_hw_cs_disable(hspi);
214 hspi_hw_cs_disable(hspi);
216 spi_finalize_current_message(master);
221 static int hspi_probe(struct platform_device *pdev)
223 struct resource *res;
224 struct spi_master *master;
225 struct hspi_priv *hspi;
230 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
232 dev_err(&pdev->dev, "invalid resource\n");
236 master = spi_alloc_master(&pdev->dev, sizeof(*hspi));
238 dev_err(&pdev->dev, "spi_alloc_master error.\n");
242 clk = clk_get(&pdev->dev, NULL);
244 dev_err(&pdev->dev, "couldn't get clock\n");
249 hspi = spi_master_get_devdata(master);
250 platform_set_drvdata(pdev, hspi);
253 hspi->master = master;
254 hspi->dev = &pdev->dev;
256 hspi->addr = devm_ioremap(hspi->dev,
257 res->start, resource_size(res));
259 dev_err(&pdev->dev, "ioremap error.\n");
264 pm_runtime_enable(&pdev->dev);
266 master->bus_num = pdev->id;
267 master->mode_bits = SPI_CPOL | SPI_CPHA;
268 master->dev.of_node = pdev->dev.of_node;
269 master->auto_runtime_pm = true;
270 master->transfer_one_message = hspi_transfer_one_message;
271 master->bits_per_word_mask = SPI_BPW_MASK(8);
273 ret = devm_spi_register_master(&pdev->dev, master);
275 dev_err(&pdev->dev, "spi_register_master error.\n");
282 pm_runtime_disable(&pdev->dev);
286 spi_master_put(master);
291 static int hspi_remove(struct platform_device *pdev)
293 struct hspi_priv *hspi = platform_get_drvdata(pdev);
295 pm_runtime_disable(&pdev->dev);
302 static const struct of_device_id hspi_of_match[] = {
303 { .compatible = "renesas,hspi", },
306 MODULE_DEVICE_TABLE(of, hspi_of_match);
308 static struct platform_driver hspi_driver = {
310 .remove = hspi_remove,
313 .of_match_table = hspi_of_match,
316 module_platform_driver(hspi_driver);
318 MODULE_DESCRIPTION("SuperH HSPI bus driver");
319 MODULE_LICENSE("GPL");
320 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
321 MODULE_ALIAS("platform:sh-hspi");