2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
3 * Author: Addy Ke <addy.ke@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/clk.h>
19 #include <linux/err.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
24 #include <linux/spi/spi.h>
25 #include <linux/scatterlist.h>
27 #include <linux/pm_runtime.h>
29 #include <linux/dmaengine.h>
31 #define DRIVER_NAME "rockchip-spi"
33 /* SPI register offsets */
34 #define ROCKCHIP_SPI_CTRLR0 0x0000
35 #define ROCKCHIP_SPI_CTRLR1 0x0004
36 #define ROCKCHIP_SPI_SSIENR 0x0008
37 #define ROCKCHIP_SPI_SER 0x000c
38 #define ROCKCHIP_SPI_BAUDR 0x0010
39 #define ROCKCHIP_SPI_TXFTLR 0x0014
40 #define ROCKCHIP_SPI_RXFTLR 0x0018
41 #define ROCKCHIP_SPI_TXFLR 0x001c
42 #define ROCKCHIP_SPI_RXFLR 0x0020
43 #define ROCKCHIP_SPI_SR 0x0024
44 #define ROCKCHIP_SPI_IPR 0x0028
45 #define ROCKCHIP_SPI_IMR 0x002c
46 #define ROCKCHIP_SPI_ISR 0x0030
47 #define ROCKCHIP_SPI_RISR 0x0034
48 #define ROCKCHIP_SPI_ICR 0x0038
49 #define ROCKCHIP_SPI_DMACR 0x003c
50 #define ROCKCHIP_SPI_DMATDLR 0x0040
51 #define ROCKCHIP_SPI_DMARDLR 0x0044
52 #define ROCKCHIP_SPI_TXDR 0x0400
53 #define ROCKCHIP_SPI_RXDR 0x0800
55 /* Bit fields in CTRLR0 */
56 #define CR0_DFS_OFFSET 0
58 #define CR0_CFS_OFFSET 2
60 #define CR0_SCPH_OFFSET 6
62 #define CR0_SCPOL_OFFSET 7
64 #define CR0_CSM_OFFSET 8
65 #define CR0_CSM_KEEP 0x0
66 /* ss_n be high for half sclk_out cycles */
67 #define CR0_CSM_HALF 0X1
68 /* ss_n be high for one sclk_out cycle */
69 #define CR0_CSM_ONE 0x2
71 /* ss_n to sclk_out delay */
72 #define CR0_SSD_OFFSET 10
74 * The period between ss_n active and
75 * sclk_out active is half sclk_out cycles
77 #define CR0_SSD_HALF 0x0
79 * The period between ss_n active and
80 * sclk_out active is one sclk_out cycle
82 #define CR0_SSD_ONE 0x1
84 #define CR0_EM_OFFSET 11
85 #define CR0_EM_LITTLE 0x0
86 #define CR0_EM_BIG 0x1
88 #define CR0_FBM_OFFSET 12
89 #define CR0_FBM_MSB 0x0
90 #define CR0_FBM_LSB 0x1
92 #define CR0_BHT_OFFSET 13
93 #define CR0_BHT_16BIT 0x0
94 #define CR0_BHT_8BIT 0x1
96 #define CR0_RSD_OFFSET 14
98 #define CR0_FRF_OFFSET 16
99 #define CR0_FRF_SPI 0x0
100 #define CR0_FRF_SSP 0x1
101 #define CR0_FRF_MICROWIRE 0x2
103 #define CR0_XFM_OFFSET 18
104 #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
105 #define CR0_XFM_TR 0x0
106 #define CR0_XFM_TO 0x1
107 #define CR0_XFM_RO 0x2
109 #define CR0_OPM_OFFSET 20
110 #define CR0_OPM_MASTER 0x0
111 #define CR0_OPM_SLAVE 0x1
113 #define CR0_MTM_OFFSET 0x21
115 /* Bit fields in SER, 2bit */
118 /* Bit fields in SR, 5bit */
120 #define SR_BUSY (1 << 0)
121 #define SR_TF_FULL (1 << 1)
122 #define SR_TF_EMPTY (1 << 2)
123 #define SR_RF_EMPTY (1 << 3)
124 #define SR_RF_FULL (1 << 4)
126 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
127 #define INT_MASK 0x1f
128 #define INT_TF_EMPTY (1 << 0)
129 #define INT_TF_OVERFLOW (1 << 1)
130 #define INT_RF_UNDERFLOW (1 << 2)
131 #define INT_RF_OVERFLOW (1 << 3)
132 #define INT_RF_FULL (1 << 4)
134 /* Bit fields in ICR, 4bit */
135 #define ICR_MASK 0x0f
136 #define ICR_ALL (1 << 0)
137 #define ICR_RF_UNDERFLOW (1 << 1)
138 #define ICR_RF_OVERFLOW (1 << 2)
139 #define ICR_TF_OVERFLOW (1 << 3)
141 /* Bit fields in DMACR */
142 #define RF_DMA_EN (1 << 0)
143 #define TF_DMA_EN (1 << 1)
145 #define RXBUSY (1 << 0)
146 #define TXBUSY (1 << 1)
148 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
149 #define MAX_SCLK_OUT 50000000
151 enum rockchip_ssi_type {
157 struct rockchip_spi_dma_data {
159 enum dma_transfer_direction direction;
163 struct rockchip_spi {
165 struct spi_master *master;
168 struct clk *apb_pclk;
171 /*depth of the FIFO buffer */
173 /* max bus freq supported */
175 /* supported slave numbers */
176 enum rockchip_ssi_type type;
196 struct sg_table tx_sg;
197 struct sg_table rx_sg;
198 struct rockchip_spi_dma_data dma_rx;
199 struct rockchip_spi_dma_data dma_tx;
202 static inline void spi_enable_chip(struct rockchip_spi *rs, int enable)
204 writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR);
207 static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
209 writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR);
212 static inline void flush_fifo(struct rockchip_spi *rs)
214 while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR))
215 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
218 static inline void wait_for_idle(struct rockchip_spi *rs)
220 unsigned long timeout = jiffies + msecs_to_jiffies(5);
223 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
225 } while (!time_after(jiffies, timeout));
227 dev_warn(rs->dev, "spi controller is in busy state!\n");
230 static u32 get_fifo_len(struct rockchip_spi *rs)
234 for (fifo = 2; fifo < 32; fifo++) {
235 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
236 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
240 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
242 return (fifo == 31) ? 0 : fifo;
245 static inline u32 tx_max(struct rockchip_spi *rs)
247 u32 tx_left, tx_room;
249 tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
250 tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
252 return min(tx_left, tx_room);
255 static inline u32 rx_max(struct rockchip_spi *rs)
257 u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
258 u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
260 return min(rx_left, rx_room);
263 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
266 struct spi_master *master = spi->master;
267 struct rockchip_spi *rs = spi_master_get_devdata(master);
269 pm_runtime_get_sync(rs->dev);
271 ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK;
275 * static void spi_set_cs(struct spi_device *spi, bool enable)
277 * if (spi->mode & SPI_CS_HIGH)
280 * if (spi->cs_gpio >= 0)
281 * gpio_set_value(spi->cs_gpio, !enable);
282 * else if (spi->master->set_cs)
283 * spi->master->set_cs(spi, !enable);
286 * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs)
289 ser |= 1 << spi->chip_select;
291 ser &= ~(1 << spi->chip_select);
293 writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER);
295 pm_runtime_put_sync(rs->dev);
298 static int rockchip_spi_prepare_message(struct spi_master *master,
299 struct spi_message *msg)
301 struct rockchip_spi *rs = spi_master_get_devdata(master);
302 struct spi_device *spi = msg->spi;
304 rs->mode = spi->mode;
309 static void rockchip_spi_handle_err(struct spi_master *master,
310 struct spi_message *msg)
313 struct rockchip_spi *rs = spi_master_get_devdata(master);
315 spin_lock_irqsave(&rs->lock, flags);
318 * For DMA mode, we need terminate DMA channel and flush
319 * fifo for the next transfer if DMA thansfer timeout.
320 * handle_err() was called by core if transfer failed.
321 * Maybe it is reasonable for error handling here.
324 if (rs->state & RXBUSY) {
325 dmaengine_terminate_async(rs->dma_rx.ch);
329 if (rs->state & TXBUSY)
330 dmaengine_terminate_async(rs->dma_tx.ch);
333 spin_unlock_irqrestore(&rs->lock, flags);
336 static int rockchip_spi_unprepare_message(struct spi_master *master,
337 struct spi_message *msg)
339 struct rockchip_spi *rs = spi_master_get_devdata(master);
341 spi_enable_chip(rs, 0);
346 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
348 u32 max = tx_max(rs);
352 if (rs->n_bytes == 1)
353 txw = *(u8 *)(rs->tx);
355 txw = *(u16 *)(rs->tx);
357 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
358 rs->tx += rs->n_bytes;
362 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
364 u32 max = rx_max(rs);
368 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
369 if (rs->n_bytes == 1)
370 *(u8 *)(rs->rx) = (u8)rxw;
372 *(u16 *)(rs->rx) = (u16)rxw;
373 rs->rx += rs->n_bytes;
377 static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
383 remain = rs->tx_end - rs->tx;
384 rockchip_spi_pio_writer(rs);
388 remain = rs->rx_end - rs->rx;
389 rockchip_spi_pio_reader(rs);
395 /* If tx, wait until the FIFO data completely. */
399 spi_enable_chip(rs, 0);
404 static void rockchip_spi_dma_rxcb(void *data)
407 struct rockchip_spi *rs = data;
409 spin_lock_irqsave(&rs->lock, flags);
411 rs->state &= ~RXBUSY;
412 if (!(rs->state & TXBUSY)) {
413 spi_enable_chip(rs, 0);
414 spi_finalize_current_transfer(rs->master);
417 spin_unlock_irqrestore(&rs->lock, flags);
420 static void rockchip_spi_dma_txcb(void *data)
423 struct rockchip_spi *rs = data;
425 /* Wait until the FIFO data completely. */
428 spin_lock_irqsave(&rs->lock, flags);
430 rs->state &= ~TXBUSY;
431 if (!(rs->state & RXBUSY)) {
432 spi_enable_chip(rs, 0);
433 spi_finalize_current_transfer(rs->master);
436 spin_unlock_irqrestore(&rs->lock, flags);
439 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs)
442 struct dma_slave_config rxconf, txconf;
443 struct dma_async_tx_descriptor *rxdesc, *txdesc;
445 spin_lock_irqsave(&rs->lock, flags);
446 rs->state &= ~RXBUSY;
447 rs->state &= ~TXBUSY;
448 spin_unlock_irqrestore(&rs->lock, flags);
452 rxconf.direction = rs->dma_rx.direction;
453 rxconf.src_addr = rs->dma_rx.addr;
454 rxconf.src_addr_width = rs->n_bytes;
455 rxconf.src_maxburst = rs->n_bytes;
456 dmaengine_slave_config(rs->dma_rx.ch, &rxconf);
458 rxdesc = dmaengine_prep_slave_sg(
460 rs->rx_sg.sgl, rs->rx_sg.nents,
461 rs->dma_rx.direction, DMA_PREP_INTERRUPT);
465 rxdesc->callback = rockchip_spi_dma_rxcb;
466 rxdesc->callback_param = rs;
471 txconf.direction = rs->dma_tx.direction;
472 txconf.dst_addr = rs->dma_tx.addr;
473 txconf.dst_addr_width = rs->n_bytes;
474 txconf.dst_maxburst = rs->n_bytes;
475 dmaengine_slave_config(rs->dma_tx.ch, &txconf);
477 txdesc = dmaengine_prep_slave_sg(
479 rs->tx_sg.sgl, rs->tx_sg.nents,
480 rs->dma_tx.direction, DMA_PREP_INTERRUPT);
483 dmaengine_terminate_sync(rs->dma_rx.ch);
487 txdesc->callback = rockchip_spi_dma_txcb;
488 txdesc->callback_param = rs;
491 /* rx must be started before tx due to spi instinct */
493 spin_lock_irqsave(&rs->lock, flags);
495 spin_unlock_irqrestore(&rs->lock, flags);
496 dmaengine_submit(rxdesc);
497 dma_async_issue_pending(rs->dma_rx.ch);
501 spin_lock_irqsave(&rs->lock, flags);
503 spin_unlock_irqrestore(&rs->lock, flags);
504 dmaengine_submit(txdesc);
505 dma_async_issue_pending(rs->dma_tx.ch);
511 static void rockchip_spi_config(struct rockchip_spi *rs)
517 u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
518 | (CR0_SSD_ONE << CR0_SSD_OFFSET)
519 | (CR0_EM_BIG << CR0_EM_OFFSET);
521 cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
522 cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
523 cr0 |= (rs->tmode << CR0_XFM_OFFSET);
524 cr0 |= (rs->type << CR0_FRF_OFFSET);
533 if (WARN_ON(rs->speed > MAX_SCLK_OUT))
534 rs->speed = MAX_SCLK_OUT;
536 /* the minimum divsor is 2 */
537 if (rs->max_freq < 2 * rs->speed) {
538 clk_set_rate(rs->spiclk, 2 * rs->speed);
539 rs->max_freq = clk_get_rate(rs->spiclk);
542 /* div doesn't support odd number */
543 div = DIV_ROUND_UP(rs->max_freq, rs->speed);
544 div = (div + 1) & 0xfffe;
546 /* Rx sample delay is expressed in parent clock cycles (max 3) */
547 rsd = DIV_ROUND_CLOSEST(rs->rsd_nsecs * (rs->max_freq >> 8),
549 if (!rsd && rs->rsd_nsecs) {
550 pr_warn_once("rockchip-spi: %u Hz are too slow to express %u ns delay\n",
551 rs->max_freq, rs->rsd_nsecs);
552 } else if (rsd > 3) {
554 pr_warn_once("rockchip-spi: %u Hz are too fast to express %u ns delay, clamping at %u ns\n",
555 rs->max_freq, rs->rsd_nsecs,
556 rsd * 1000000000U / rs->max_freq);
558 cr0 |= rsd << CR0_RSD_OFFSET;
560 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
562 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
563 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
564 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
566 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR);
567 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
568 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
570 spi_set_clk(rs, div);
572 dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
575 static int rockchip_spi_transfer_one(
576 struct spi_master *master,
577 struct spi_device *spi,
578 struct spi_transfer *xfer)
581 struct rockchip_spi *rs = spi_master_get_devdata(master);
583 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
584 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
586 if (!xfer->tx_buf && !xfer->rx_buf) {
587 dev_err(rs->dev, "No buffer for transfer\n");
591 rs->speed = xfer->speed_hz;
592 rs->bpw = xfer->bits_per_word;
593 rs->n_bytes = rs->bpw >> 3;
595 rs->tx = xfer->tx_buf;
596 rs->tx_end = rs->tx + xfer->len;
597 rs->rx = xfer->rx_buf;
598 rs->rx_end = rs->rx + xfer->len;
601 rs->tx_sg = xfer->tx_sg;
602 rs->rx_sg = xfer->rx_sg;
604 if (rs->tx && rs->rx)
605 rs->tmode = CR0_XFM_TR;
607 rs->tmode = CR0_XFM_TO;
609 rs->tmode = CR0_XFM_RO;
611 /* we need prepare dma before spi was enabled */
612 if (master->can_dma && master->can_dma(master, spi, xfer))
617 rockchip_spi_config(rs);
620 if (rs->tmode == CR0_XFM_RO) {
621 /* rx: dma must be prepared first */
622 ret = rockchip_spi_prepare_dma(rs);
623 spi_enable_chip(rs, 1);
625 /* tx or tr: spi must be enabled first */
626 spi_enable_chip(rs, 1);
627 ret = rockchip_spi_prepare_dma(rs);
630 spi_enable_chip(rs, 1);
631 ret = rockchip_spi_pio_transfer(rs);
637 static bool rockchip_spi_can_dma(struct spi_master *master,
638 struct spi_device *spi,
639 struct spi_transfer *xfer)
641 struct rockchip_spi *rs = spi_master_get_devdata(master);
643 return (xfer->len > rs->fifo_len);
646 static int rockchip_spi_probe(struct platform_device *pdev)
649 struct rockchip_spi *rs;
650 struct spi_master *master;
651 struct resource *mem;
654 master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
658 platform_set_drvdata(pdev, master);
660 rs = spi_master_get_devdata(master);
662 /* Get basic io resource and map it */
663 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
664 rs->regs = devm_ioremap_resource(&pdev->dev, mem);
665 if (IS_ERR(rs->regs)) {
666 ret = PTR_ERR(rs->regs);
667 goto err_ioremap_resource;
670 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
671 if (IS_ERR(rs->apb_pclk)) {
672 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
673 ret = PTR_ERR(rs->apb_pclk);
674 goto err_ioremap_resource;
677 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
678 if (IS_ERR(rs->spiclk)) {
679 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
680 ret = PTR_ERR(rs->spiclk);
681 goto err_ioremap_resource;
684 ret = clk_prepare_enable(rs->apb_pclk);
686 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
687 goto err_ioremap_resource;
690 ret = clk_prepare_enable(rs->spiclk);
692 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
693 goto err_spiclk_enable;
696 spi_enable_chip(rs, 0);
698 rs->type = SSI_MOTO_SPI;
700 rs->dev = &pdev->dev;
701 rs->max_freq = clk_get_rate(rs->spiclk);
703 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns",
705 rs->rsd_nsecs = rsd_nsecs;
707 rs->fifo_len = get_fifo_len(rs);
709 dev_err(&pdev->dev, "Failed to get fifo length\n");
711 goto err_get_fifo_len;
714 spin_lock_init(&rs->lock);
716 pm_runtime_set_active(&pdev->dev);
717 pm_runtime_enable(&pdev->dev);
719 master->auto_runtime_pm = true;
720 master->bus_num = pdev->id;
721 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
722 master->num_chipselect = 2;
723 master->dev.of_node = pdev->dev.of_node;
724 master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
726 master->set_cs = rockchip_spi_set_cs;
727 master->prepare_message = rockchip_spi_prepare_message;
728 master->unprepare_message = rockchip_spi_unprepare_message;
729 master->transfer_one = rockchip_spi_transfer_one;
730 master->handle_err = rockchip_spi_handle_err;
732 rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx");
734 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
736 rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx");
737 if (!rs->dma_rx.ch) {
739 dma_release_channel(rs->dma_tx.ch);
740 rs->dma_tx.ch = NULL;
742 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
745 if (rs->dma_tx.ch && rs->dma_rx.ch) {
746 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
747 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
748 rs->dma_tx.direction = DMA_MEM_TO_DEV;
749 rs->dma_rx.direction = DMA_DEV_TO_MEM;
751 master->can_dma = rockchip_spi_can_dma;
752 master->dma_tx = rs->dma_tx.ch;
753 master->dma_rx = rs->dma_rx.ch;
756 ret = devm_spi_register_master(&pdev->dev, master);
758 dev_err(&pdev->dev, "Failed to register master\n");
759 goto err_register_master;
765 pm_runtime_disable(&pdev->dev);
767 dma_release_channel(rs->dma_tx.ch);
769 dma_release_channel(rs->dma_rx.ch);
771 clk_disable_unprepare(rs->spiclk);
773 clk_disable_unprepare(rs->apb_pclk);
774 err_ioremap_resource:
775 spi_master_put(master);
780 static int rockchip_spi_remove(struct platform_device *pdev)
782 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
783 struct rockchip_spi *rs = spi_master_get_devdata(master);
785 pm_runtime_disable(&pdev->dev);
787 clk_disable_unprepare(rs->spiclk);
788 clk_disable_unprepare(rs->apb_pclk);
791 dma_release_channel(rs->dma_tx.ch);
793 dma_release_channel(rs->dma_rx.ch);
795 spi_master_put(master);
800 #ifdef CONFIG_PM_SLEEP
801 static int rockchip_spi_suspend(struct device *dev)
804 struct spi_master *master = dev_get_drvdata(dev);
805 struct rockchip_spi *rs = spi_master_get_devdata(master);
807 ret = spi_master_suspend(rs->master);
811 if (!pm_runtime_suspended(dev)) {
812 clk_disable_unprepare(rs->spiclk);
813 clk_disable_unprepare(rs->apb_pclk);
819 static int rockchip_spi_resume(struct device *dev)
822 struct spi_master *master = dev_get_drvdata(dev);
823 struct rockchip_spi *rs = spi_master_get_devdata(master);
825 if (!pm_runtime_suspended(dev)) {
826 ret = clk_prepare_enable(rs->apb_pclk);
830 ret = clk_prepare_enable(rs->spiclk);
832 clk_disable_unprepare(rs->apb_pclk);
837 ret = spi_master_resume(rs->master);
839 clk_disable_unprepare(rs->spiclk);
840 clk_disable_unprepare(rs->apb_pclk);
845 #endif /* CONFIG_PM_SLEEP */
848 static int rockchip_spi_runtime_suspend(struct device *dev)
850 struct spi_master *master = dev_get_drvdata(dev);
851 struct rockchip_spi *rs = spi_master_get_devdata(master);
853 clk_disable_unprepare(rs->spiclk);
854 clk_disable_unprepare(rs->apb_pclk);
859 static int rockchip_spi_runtime_resume(struct device *dev)
862 struct spi_master *master = dev_get_drvdata(dev);
863 struct rockchip_spi *rs = spi_master_get_devdata(master);
865 ret = clk_prepare_enable(rs->apb_pclk);
869 ret = clk_prepare_enable(rs->spiclk);
871 clk_disable_unprepare(rs->apb_pclk);
875 #endif /* CONFIG_PM */
877 static const struct dev_pm_ops rockchip_spi_pm = {
878 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
879 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
880 rockchip_spi_runtime_resume, NULL)
883 static const struct of_device_id rockchip_spi_dt_match[] = {
884 { .compatible = "rockchip,rk3066-spi", },
885 { .compatible = "rockchip,rk3188-spi", },
886 { .compatible = "rockchip,rk3288-spi", },
887 { .compatible = "rockchip,rk3399-spi", },
890 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
892 static struct platform_driver rockchip_spi_driver = {
895 .pm = &rockchip_spi_pm,
896 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
898 .probe = rockchip_spi_probe,
899 .remove = rockchip_spi_remove,
902 module_platform_driver(rockchip_spi_driver);
904 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
905 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
906 MODULE_LICENSE("GPL v2");