2 * Special handling for DW core on Intel MID platform
4 * Copyright (c) 2009, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/interrupt.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/workqueue.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/clk.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/dmaengine.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/spi/spi.h>
33 #include <linux/gpio.h>
35 #include <linux/of_gpio.h>
36 #include <linux/platform_data/spi-rockchip.h>
39 #include "spi-rockchip-core.h"
41 #ifdef CONFIG_SPI_ROCKCHIP_DMA
42 #define DMA_BUFFER_SIZE (PAGE_SIZE<<4)
45 struct spi_dma_slave {
47 enum dma_transfer_direction direction;
53 struct spi_dma_slave dmas_tx;
54 struct spi_dma_slave dmas_rx;
57 static void printk_transfer_data(struct dw_spi *dws, char *buf, int len)
61 DBG_SPI("0x%02x,",*buf++);
67 static int mid_spi_dma_init(struct dw_spi *dws)
69 struct spi_dma *dw_dma = dws->dma_priv;
70 struct spi_dma_slave *rxs, *txs;
73 DBG_SPI("%s:start\n",__func__);
75 /* 1. Init rx channel */
76 dws->rxchan = dma_request_slave_channel(dws->parent_dev, "rx");
79 dev_err(dws->parent_dev, "Failed to get RX DMA channel\n");
83 DBG_SPI("%s:rx_chan_id=%d\n",__func__,dws->rxchan->chan_id);
85 rxs = &dw_dma->dmas_rx;
86 dws->rxchan->private = rxs;
88 /* 2. Init tx channel */
89 dws->txchan = dma_request_slave_channel(dws->parent_dev, "tx");
92 dev_err(dws->parent_dev, "Failed to get RX DMA channel\n");
95 txs = &dw_dma->dmas_tx;
96 dws->txchan->private = txs;
98 DBG_SPI("%s:tx_chan_id=%d\n",__func__,dws->txchan->chan_id);
102 DBG_SPI("%s:line=%d\n",__func__,__LINE__);
106 dma_release_channel(dws->rxchan);
112 static void mid_spi_dma_exit(struct dw_spi *dws)
114 DBG_SPI("%s:start\n",__func__);
115 dma_release_channel(dws->txchan);
116 dma_release_channel(dws->rxchan);
120 static void dw_spi_dma_rxcb(void *arg)
122 struct dw_spi *dws = arg;
124 struct dma_tx_state state;
127 dma_sync_single_for_device(dws->rxchan->device->dev, dws->rx_dma,
128 dws->len, DMA_FROM_DEVICE);
130 dma_status = dmaengine_tx_status(dws->rxchan, dws->rx_cookie, &state);
132 DBG_SPI("%s:dma_status=0x%x\n", __FUNCTION__, dma_status);
134 spin_lock_irqsave(&dws->lock, flags);
135 if (dma_status == DMA_SUCCESS)
136 dws->state &= ~RXBUSY;
138 dev_err(&dws->master->dev, "error:rx dma_status=%x\n", dma_status);
140 //copy data from dma to transfer buf
141 if(dws->cur_transfer && (dws->cur_transfer->rx_buf != NULL))
143 memcpy(dws->cur_transfer->rx_buf, dws->rx_buffer, dws->cur_transfer->len);
146 printk_transfer_data(dws, dws->cur_transfer->rx_buf, dws->cur_transfer->len);
149 spin_unlock_irqrestore(&dws->lock, flags);
151 /* If the other done */
152 if (!(dws->state & TXBUSY))
154 complete(&dws->xfer_completion);
155 DBG_SPI("%s:complete\n", __FUNCTION__);
156 //DMA could not lose intterupt
157 dw_spi_xfer_done(dws);
162 static void dw_spi_dma_txcb(void *arg)
164 struct dw_spi *dws = arg;
166 struct dma_tx_state state;
169 dma_sync_single_for_device(dws->txchan->device->dev, dws->tx_dma,
170 dws->len, DMA_TO_DEVICE);
172 dma_status = dmaengine_tx_status(dws->txchan, dws->tx_cookie, &state);
174 DBG_SPI("%s:dma_status=0x%x\n", __FUNCTION__, dma_status);
176 printk_transfer_data(dws, (char *)dws->cur_transfer->tx_buf, dws->cur_transfer->len);
178 spin_lock_irqsave(&dws->lock, flags);
180 if (dma_status == DMA_SUCCESS)
181 dws->state &= ~TXBUSY;
183 dev_err(&dws->master->dev, "error:tx dma_status=%x\n", dma_status);
185 spin_unlock_irqrestore(&dws->lock, flags);
187 /* If the other done */
188 if (!(dws->state & RXBUSY))
190 complete(&dws->xfer_completion);
191 DBG_SPI("%s:complete\n", __FUNCTION__);
193 //DMA could not lose intterupt
194 dw_spi_xfer_done(dws);
200 static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
202 struct dma_async_tx_descriptor *txdesc = NULL, *rxdesc = NULL;
203 struct dma_chan *txchan, *rxchan;
204 struct dma_slave_config txconf, rxconf;
208 enum dma_slave_buswidth width;
210 DBG_SPI("%s:cs_change=%d\n",__func__,cs_change);
212 //alloc dma buffer default while cur_transfer->tx_dma or cur_transfer->rx_dma is null
213 if((dws->cur_transfer->tx_buf) && dws->dma_mapped && (!dws->cur_transfer->tx_dma))
215 //printk("%s:warning tx_dma is %p\n",__func__, (int *)dws->tx_dma);
216 memcpy(dws->tx_buffer, dws->cur_transfer->tx_buf, dws->cur_transfer->len);
217 dws->tx_dma = dws->tx_dma_init;
220 if((dws->cur_transfer->rx_buf) && dws->dma_mapped && (!dws->cur_transfer->rx_dma))
222 //printk("%s:warning rx_dma is %p\n",__func__, (int *)dws->rx_dma);
223 dws->rx_dma = dws->rx_dma_init;
228 dws->state |= TXBUSY;
230 dws->state |= RXBUSY;
233 switch (dws->n_bytes) {
235 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
238 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
241 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
245 dws->dma_chan_done = 0;
248 txchan = dws->txchan;
251 rxchan = dws->rxchan;
255 /* 2. Prepare the TX dma transfer */
256 txconf.direction = DMA_MEM_TO_DEV;
257 txconf.dst_addr = dws->tx_dma_addr;
258 txconf.dst_maxburst = dws->dma_width;
259 //txconf.src_addr_width = width;
260 txconf.dst_addr_width = width;
261 //txconf.device_fc = false;
263 ret = dmaengine_slave_config(txchan, &txconf);
265 dev_warn(dws->parent_dev, "TX DMA slave config failed\n");
269 memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
270 dws->tx_sgl.dma_address = dws->tx_dma;
271 dws->tx_sgl.length = dws->len;
273 txdesc = dmaengine_prep_slave_sg(txchan,
279 txdesc->callback = dw_spi_dma_txcb;
280 txdesc->callback_param = dws;
282 DBG_SPI("%s:dst_addr=0x%p,tx_dma=0x%p,len=%d,burst=%d,width=%d\n",__func__,(int *)dws->tx_dma_addr, (int *)dws->tx_dma, dws->len,dws->dma_width, width);
287 /* 3. Prepare the RX dma transfer */
288 rxconf.direction = DMA_DEV_TO_MEM;
289 rxconf.src_addr = dws->rx_dma_addr;
290 rxconf.src_maxburst = dws->dma_width;
291 //rxconf.dst_addr_width = width;
292 rxconf.src_addr_width = width;
293 //rxconf.device_fc = false;
295 ret = dmaengine_slave_config(rxchan, &rxconf);
297 dev_warn(dws->parent_dev, "RX DMA slave config failed\n");
301 memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
302 dws->rx_sgl.dma_address = dws->rx_dma;
303 dws->rx_sgl.length = dws->len;
305 rxdesc = dmaengine_prep_slave_sg(rxchan,
310 rxdesc->callback = dw_spi_dma_rxcb;
311 rxdesc->callback_param = dws;
313 DBG_SPI("%s:src_addr=0x%p,rx_dma=0x%p,len=%d,burst=%d,width=%d\n",__func__, (int *)dws->rx_dma_addr, (int *)dws->rx_dma, dws->len, dws->dma_width, width);
316 /* rx must be started before tx due to spi instinct */
319 dws->rx_cookie = dmaengine_submit(rxdesc);
320 dma_sync_single_for_device(rxchan->device->dev, dws->rx_dma,
321 dws->len, DMA_FROM_DEVICE);
322 dma_async_issue_pending(rxchan);
324 DBG_SPI("%s:rx end\n",__func__);
329 dws->tx_cookie = dmaengine_submit(txdesc);
330 dma_sync_single_for_device(txchan->device->dev, dws->tx_dma,
331 dws->len, DMA_TO_DEVICE);
332 dma_async_issue_pending(txchan);
334 DBG_SPI("%s:tx end\n",__func__);
340 static struct dw_spi_dma_ops spi_dma_ops = {
341 .dma_init = mid_spi_dma_init,
342 .dma_exit = mid_spi_dma_exit,
343 .dma_transfer = mid_spi_dma_transfer,
346 int dw_spi_dma_init(struct dw_spi *dws)
348 DBG_SPI("%s:start\n",__func__);
349 dws->dma_priv = kzalloc(sizeof(struct spi_dma), GFP_KERNEL);
352 dws->dma_ops = &spi_dma_ops;
354 dws->tx_buffer = dma_alloc_coherent(dws->parent_dev, DMA_BUFFER_SIZE, &dws->tx_dma_init, GFP_KERNEL | GFP_DMA);
357 dev_err(dws->parent_dev, "fail to dma tx buffer alloc\n");
361 dws->rx_buffer = dma_alloc_coherent(dws->parent_dev, DMA_BUFFER_SIZE, &dws->rx_dma_init, GFP_KERNEL | GFP_DMA);
364 dev_err(dws->parent_dev, "fail to dma rx buffer alloc\n");
368 memset(dws->tx_buffer, 0, DMA_BUFFER_SIZE);
369 memset(dws->rx_buffer, 0, DMA_BUFFER_SIZE);
373 init_completion(&dws->xfer_completion);