drivers/spi/spi-rockchip-dma.c

   1 /*
   2  * Special handling for DW core on Intel MID platform
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #include <linux/interrupt.h>
  21 #include <linux/slab.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/workqueue.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/clk.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/dmaengine.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/spi/spi.h>
  33 #include <linux/gpio.h>
  34 #include <linux/of.h>
  35 #include <linux/of_gpio.h>
  36 #include <linux/platform_data/spi-rockchip.h>
  37
  38
  39 #include "spi-rockchip-core.h"
  40
  41 #ifdef CONFIG_SPI_ROCKCHIP_DMA
  42
  43 struct spi_dma_slave {
  44         struct dma_chan *ch;
  45         enum dma_transfer_direction direction;
  46         unsigned int dmach;
  47 };
  48
  49
  50 struct spi_dma {
  51         struct spi_dma_slave    dmas_tx;
  52         struct spi_dma_slave    dmas_rx;
  53 };
  54
  55 static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
  56 {
  57         struct dw_spi *dws = param;
  58         int ret = 0;
  59         ret = dws->parent_dev && (&dws->parent_dev == chan->device->dev);
  60
  61         printk("%s:ret=%d\n",__func__, ret);
  62         return ret;
  63 }
  64
  65
  66 static int mid_spi_dma_init(struct dw_spi *dws)
  67 {
  68         struct spi_dma *dw_dma = dws->dma_priv;
  69         struct spi_dma_slave *rxs, *txs;
  70         dma_cap_mask_t mask;
  71
  72         /*
  73          * Get pci device for DMA controller, currently it could only
  74          * be the DMA controller of either Moorestown or Medfield
  75          */
  76         //dws->dmac = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0813, NULL);
  77         //if (!dws->dmac)
  78         //      dws->dmac = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
  79
  80         dma_cap_zero(mask);
  81         dma_cap_set(DMA_SLAVE, mask);
  82
  83         /* 1. Init rx channel */
  84         dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
  85         if (!dws->rxchan)
  86                 goto err_exit;
  87         rxs = &dw_dma->dmas_rx;
  88         //rxs->hs_mode = LNW_DMA_HW_HS;
  89         //rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
  90         dws->rxchan->private = rxs;
  91
  92         /* 2. Init tx channel */
  93         dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
  94         if (!dws->txchan)
  95                 goto free_rxchan;
  96         txs = &dw_dma->dmas_tx;
  97         //txs->hs_mode = LNW_DMA_HW_HS;
  98         //txs->cfg_mode = LNW_DMA_MEM_TO_PER;
  99         dws->txchan->private = txs;
 100
 101         dws->dma_inited = 1;
 102         return 0;
 103
 104         free_rxchan:
 105         dma_release_channel(dws->rxchan);
 106         err_exit:
 107         return -1;
 108
 109 }
 110
 111 static void mid_spi_dma_exit(struct dw_spi *dws)
 112 {
 113         dma_release_channel(dws->txchan);
 114         dma_release_channel(dws->rxchan);
 115 }
 116
 117 /*
 118  * dws->dma_chan_done is cleared before the dma transfer starts,
 119  * callback for rx/tx channel will each increment it by 1.
 120  * Reaching 2 means the whole spi transaction is done.
 121  */
 122 static void dw_spi_dma_done(void *arg)
 123 {
 124         struct dw_spi *dws = arg;
 125
 126         if (++dws->dma_chan_done != 2)
 127                 return;
 128         dw_spi_xfer_done(dws);
 129 }
 130
 131 static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
 132 {
 133         struct dma_async_tx_descriptor *txdesc = NULL, *rxdesc = NULL;
 134         struct dma_chan *txchan, *rxchan;
 135         struct dma_slave_config txconf, rxconf;
 136         u16 dma_ctrl = 0;
 137
 138         /* 1. setup DMA related registers */
 139         if (cs_change) {
 140                 spi_enable_chip(dws, 0);
 141                 dw_writew(dws, SPIM_DMARDLR, 0xf);
 142                 dw_writew(dws, SPIM_DMATDLR, 0x10);
 143                 if (dws->tx_dma)
 144                         dma_ctrl |= 0x2;
 145                 if (dws->rx_dma)
 146                         dma_ctrl |= 0x1;
 147                 dw_writew(dws, SPIM_DMACR, dma_ctrl);
 148                 spi_enable_chip(dws, 1);
 149         }
 150
 151         dws->dma_chan_done = 0;
 152         txchan = dws->txchan;
 153         rxchan = dws->rxchan;
 154
 155         /* 2. Prepare the TX dma transfer */
 156         txconf.direction = DMA_MEM_TO_DEV;
 157         txconf.dst_addr = dws->dma_addr;
 158         txconf.dst_maxburst = 0x03;//LNW_DMA_MSIZE_16;
 159         txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 160         txconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 161         txconf.device_fc = false;
 162
 163         txchan->device->device_control(txchan, DMA_SLAVE_CONFIG,
 164                                        (unsigned long) &txconf);
 165
 166         memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
 167         dws->tx_sgl.dma_address = dws->tx_dma;
 168         dws->tx_sgl.length = dws->len;
 169
 170         txdesc = dmaengine_prep_slave_sg(txchan,
 171                                 &dws->tx_sgl,
 172                                 1,
 173                                 DMA_MEM_TO_DEV,
 174                                 DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP);
 175         txdesc->callback = dw_spi_dma_done;
 176         txdesc->callback_param = dws;
 177
 178         /* 3. Prepare the RX dma transfer */
 179         rxconf.direction = DMA_DEV_TO_MEM;
 180         rxconf.src_addr = dws->dma_addr;
 181         rxconf.src_maxburst = 0x03; //LNW_DMA_MSIZE_16;
 182         rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 183         rxconf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 184         rxconf.device_fc = false;
 185
 186         rxchan->device->device_control(rxchan, DMA_SLAVE_CONFIG,
 187                                        (unsigned long) &rxconf);
 188
 189         memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
 190         dws->rx_sgl.dma_address = dws->rx_dma;
 191         dws->rx_sgl.length = dws->len;
 192
 193         rxdesc = dmaengine_prep_slave_sg(rxchan,
 194                                 &dws->rx_sgl,
 195                                 1,
 196                                 DMA_DEV_TO_MEM,
 197                                 DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP);
 198         rxdesc->callback = dw_spi_dma_done;
 199         rxdesc->callback_param = dws;
 200
 201         /* rx must be started before tx due to spi instinct */
 202         rxdesc->tx_submit(rxdesc);
 203         txdesc->tx_submit(txdesc);
 204         return 0;
 205 }
 206
 207 static struct dw_spi_dma_ops spi_dma_ops = {
 208         .dma_init       = mid_spi_dma_init,
 209         .dma_exit       = mid_spi_dma_exit,
 210         .dma_transfer   = mid_spi_dma_transfer,
 211 };
 212
 213 int dw_spi_dma_init(struct dw_spi *dws)
 214 {
 215
 216         dws->dma_priv = kzalloc(sizeof(struct spi_dma), GFP_KERNEL);
 217         if (!dws->dma_priv)
 218                 return -ENOMEM;
 219         dws->dma_ops = &spi_dma_ops;
 220         return 0;
 221 }
 222 #endif
 223