1 #ifndef DW_SPI_HEADER_H
2 #define DW_SPI_HEADER_H
5 #include <linux/scatterlist.h>
6 #include <linux/dmaengine.h>
10 #define DBG_SPI(x...) if(atomic_read(&dws->debug_flag) == 1) printk(x)
15 /* SPI register offsets */
16 #define SPIM_CTRLR0 0x0000
17 #define SPIM_CTRLR1 0x0004
18 #define SPIM_SSIENR 0x0008
19 #define SPIM_SER 0x000c
20 #define SPIM_BAUDR 0x0010
21 #define SPIM_TXFTLR 0x0014
22 #define SPIM_RXFTLR 0x0018
23 #define SPIM_TXFLR 0x001c
24 #define SPIM_RXFLR 0x0020
25 #define SPIM_SR 0x0024
26 #define SPIM_IPR 0x0028
27 #define SPIM_IMR 0x002c
28 #define SPIM_ISR 0x0030
29 #define SPIM_RISR 0x0034
30 #define SPIM_ICR 0x0038
31 #define SPIM_DMACR 0x003c
32 #define SPIM_DMATDLR 0x0040
33 #define SPIM_DMARDLR 0x0044
34 #define SPIM_TXDR 0x0400
35 #define SPIM_RXDR 0x0800
37 /* --------Bit fields in CTRLR0--------begin */
39 #define SPI_DFS_OFFSET 0 /* Data Frame Size */
40 #define SPI_DFS_4BIT 0x00
41 #define SPI_DFS_8BIT 0x01
42 #define SPI_DFS_16BIT 0x02
43 #define SPI_DFS_RESV 0x03
45 #define SPI_FRF_OFFSET 16 /* Frame Format */
46 #define SPI_FRF_SPI 0x00 /* motorola spi */
47 #define SPI_FRF_SSP 0x01 /* Texas Instruments SSP*/
48 #define SPI_FRF_MICROWIRE 0x02 /* National Semiconductors Microwire */
49 #define SPI_FRF_RESV 0x03
51 #define SPI_MODE_OFFSET 6 /* SCPH & SCOL */
53 #define SPI_SCPH_OFFSET 6 /* Serial Clock Phase */
54 #define SPI_SCPH_TOGMID 0 /* Serial clock toggles in middle of first data bit */
55 #define SPI_SCPH_TOGSTA 1 /* Serial clock toggles at start of first data bit */
57 #define SPI_SCOL_OFFSET 7 /* Serial Clock Polarity */
59 #define SPI_OPMOD_OFFSET 20
60 #define SPI_OPMOD_MASTER 0
61 #define SPI_OPMOD_SLAVE 1
63 #define SPI_TMOD_OFFSET 18 /* Transfer Mode */
64 //#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
65 #define SPI_TMOD_TR 0x00 /* xmit & recv */
66 #define SPI_TMOD_TO 0x01 /* xmit only */
67 #define SPI_TMOD_RO 0x02 /* recv only */
68 #define SPI_TMOD_RESV 0x03
70 #define SPI_CFS_OFFSET 2 /* Control Frame Size */
72 #define SPI_CSM_OFFSET 8 /* Chip Select Mode */
73 #define SPI_CSM_KEEP 0x00 /* ss_n keep low after every frame data is transferred */
74 #define SPI_CSM_HALF 0x01 /* ss_n be high for half sclk_out cycles after every frame data is transferred */
75 #define SPI_CSM_ONE 0x02 /* ss_n be high for one sclk_out cycle after every frame data is transferred */
77 #define SPI_SSN_DELAY_OFFSET 10
78 #define SPI_SSN_DELAY_HALF 0x00
79 #define SPI_SSN_DELAY_ONE 0x01
81 #define SPI_HALF_WORLD_TX_OFFSET 13
82 #define SPI_HALF_WORLD_ON 0x00
83 #define SPI_HALF_WORLD_OFF 0x01
86 /* --------Bit fields in CTRLR0--------end */
89 /* Bit fields in SR, 7 bits */
90 #define SR_MASK 0x7f /* cover 7 bits */
91 #define SR_BUSY (1 << 0)
92 #define SR_TF_FULL (1 << 1)
93 #define SR_TF_EMPT (1 << 2)
94 #define SR_RF_EMPT (1 << 3)
95 #define SR_RF_FULL (1 << 4)
97 /* Bit fields in ISR, IMR, RISR, 7 bits */
98 #define SPI_INT_TXEI (1 << 0)
99 #define SPI_INT_TXOI (1 << 1)
100 #define SPI_INT_RXUI (1 << 2)
101 #define SPI_INT_RXOI (1 << 3)
102 #define SPI_INT_RXFI (1 << 4)
104 /* Bit fields in DMACR */
105 #define SPI_DMACR_TX_ENABLE (1 << 1)
106 #define SPI_DMACR_RX_ENABLE (1 << 0)
108 /* Bit fields in ICR */
109 #define SPI_CLEAR_INT_ALL (1<< 0)
110 #define SPI_CLEAR_INT_RXUI (1 << 1)
111 #define SPI_CLEAR_INT_RXOI (1 << 2)
112 #define SPI_CLEAR_INT_TXOI (1 << 3)
114 #define SUSPND (1<<0)
115 #define SPIBUSY (1<<1)
116 #define RXBUSY (1<<2)
117 #define TXBUSY (1<<3)
127 struct dw_spi_dma_ops {
128 int (*dma_init)(struct dw_spi *dws);
129 void (*dma_exit)(struct dw_spi *dws);
130 int (*dma_transfer)(struct dw_spi *dws, int cs_change);
134 struct spi_master *master;
135 struct spi_device *cur_dev;
136 struct device *parent_dev;
137 enum dw_ssi_type type;
141 struct clk *pclk_spi;
147 u32 fifo_len; /* depth of the FIFO buffer */
148 u32 max_freq; /* max bus freq supported */
151 u16 num_cs; /* supported slave numbers */
153 /* Driver message queue */
154 struct workqueue_struct *workqueue;
155 struct work_struct pump_messages;
157 struct list_head queue;
161 /* Message Transfer pump */
162 struct tasklet_struct pump_transfers;
164 /* Current message transfer state info */
165 struct spi_message *cur_msg;
166 struct spi_transfer *cur_transfer;
167 struct chip_data *cur_chip;
168 struct chip_data *prev_chip;
179 u8 n_bytes; /* current is a 1/2 bytes op */
180 u8 max_bits_per_word; /* maxim is 16b */
185 dma_addr_t rx_dma_init;
186 dma_addr_t tx_dma_init;
187 dma_cookie_t rx_cookie;
188 dma_cookie_t tx_cookie;
190 struct completion xfer_completion;
191 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
192 void (*cs_control)(struct dw_spi *dws, u32 cs, u8 flag);
196 struct dma_chan *txchan;
197 struct scatterlist tx_sgl;
198 struct dma_chan *rxchan;
199 struct scatterlist rx_sgl;
201 struct device *dma_dev;
202 dma_addr_t tx_dma_addr; /* phy address of the Data register */
203 dma_addr_t rx_dma_addr; /* phy address of the Data register */
204 struct dw_spi_dma_ops *dma_ops;
205 void *dma_priv; /* platform relate info */
207 //struct pci_dev *dmac;
210 /* Bus interface info */
212 #ifdef CONFIG_DEBUG_FS
213 struct dentry *debugfs;
217 static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
219 return __raw_readl(dws->regs + offset);
222 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
224 __raw_writel(val, dws->regs + offset);
227 static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
229 return __raw_readw(dws->regs + offset);
232 static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
234 __raw_writew(val, dws->regs + offset);
237 static inline void spi_enable_chip(struct dw_spi *dws, int enable)
239 dw_writel(dws, SPIM_SSIENR, (enable ? 1 : 0));
242 static inline void spi_set_clk(struct dw_spi *dws, u16 div)
244 dw_writel(dws, SPIM_BAUDR, div);
247 static inline void spi_chip_sel(struct dw_spi *dws, u16 cs)
249 if (cs > dws->num_cs)
253 dws->cs_control(dws, cs, 1);
255 dw_writel(dws, SPIM_SER, 1 << cs);
257 DBG_SPI("%s:cs=%d\n",__func__,cs);
260 static inline void spi_cs_control(struct dw_spi *dws, u32 cs, u8 flag)
263 dw_writel(dws, SPIM_SER, 1 << cs);
265 dw_writel(dws, SPIM_SER, 0);
271 /* Disable IRQ bits */
272 static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
276 new_mask = dw_readl(dws, SPIM_IMR) & ~mask;
277 dw_writel(dws, SPIM_IMR, new_mask);
280 /* Enable IRQ bits */
281 static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
285 new_mask = dw_readl(dws, SPIM_IMR) | mask;
286 dw_writel(dws, SPIM_IMR, new_mask);
290 * Each SPI slave device to work with dw_api controller should
291 * has such a structure claiming its working mode (PIO/DMA etc),
292 * which can be save in the "controller_data" member of the
296 u8 poll_mode; /* 0 for contoller polling mode */
297 u8 type; /* SPI/SSP/Micrwire */
299 void (*cs_control)(struct dw_spi *dws, u32 cs, u8 flag);
302 extern int dw_spi_add_host(struct dw_spi *dws);
303 extern void dw_spi_remove_host(struct dw_spi *dws);
304 extern int dw_spi_suspend_host(struct dw_spi *dws);
305 extern int dw_spi_resume_host(struct dw_spi *dws);
306 extern void dw_spi_xfer_done(struct dw_spi *dws);
308 /* platform related setup */
309 extern int dw_spi_dma_init(struct dw_spi *dws); /* Intel MID platforms */
310 #endif /* SPIM_HEADER_H */