drivers/spi/spi-rockchip-core.c

   1 /*
   2  * Designware SPI core controller driver (refer spi_dw.c)
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #include <linux/dma-mapping.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/highmem.h>
  24 #include <linux/delay.h>
  25 #include <linux/slab.h>
  26 #include <linux/spi/spi.h>
  27 #include <linux/clk.h>
  28
  29
  30 #include "spi-rockchip-core.h"
  31
  32 #ifdef CONFIG_DEBUG_FS
  33 #include <linux/debugfs.h>
  34 #endif
  35
  36 #define START_STATE     ((void *)0)
  37 #define RUNNING_STATE   ((void *)1)
  38 #define DONE_STATE      ((void *)2)
  39 #define ERROR_STATE     ((void *)-1)
  40
  41 #define QUEUE_RUNNING   0
  42 #define QUEUE_STOPPED   1
  43
  44 #define MRST_SPI_DEASSERT       0
  45 #define MRST_SPI_ASSERT         1
  46
  47
  48 /* Slave spi_dev related */
  49 struct chip_data {
  50         u16 cr0;
  51         u8 cs;                  /* chip select pin */
  52         u8 n_bytes;             /* current is a 1/2/4 byte op */
  53         u8 tmode;               /* TR/TO/RO/EEPROM */
  54         u8 type;                /* SPI/SSP/MicroWire */
  55
  56         u8 poll_mode;           /* 1 means use poll mode */
  57
  58         u8 slave_enable;
  59         u32 dma_width;
  60         u32 rx_threshold;
  61         u32 tx_threshold;
  62         u8 enable_dma;
  63         u8 bits_per_word;
  64         u16 clk_div;            /* baud rate divider */
  65         u32 speed_hz;           /* baud rate */
  66         void (*cs_control)(struct dw_spi *dws, u32 cs, u8 flag);
  67 };
  68
  69 #ifdef CONFIG_DEBUG_FS
  70 #define SPI_REGS_BUFSIZE        1024
  71
  72 static ssize_t spi_write_proc_data(struct file *file, const char __user *buffer,
  73                            size_t count, loff_t *data)
  74 {
  75         struct dw_spi *dws;
  76         char *buf;
  77         u32 len = 0;
  78         ssize_t ret;
  79         int reg = 0,value = 0;
  80
  81         dws = file->private_data;
  82
  83         buf = kzalloc(32, GFP_KERNEL);
  84         if (!buf)
  85         return 0;
  86
  87         ret = copy_from_user(buf, buffer, count);
  88         if (ret)
  89         {
  90                 return ret;
  91         }
  92
  93         if((strstr(buf, "debug") != NULL) || (strstr(buf, "DEBUG") != NULL))
  94         {
  95                 atomic_set(&dws->debug_flag, 1);
  96                 kfree(buf);
  97                 printk("%s:open debug\n",__func__);
  98                 return count;
  99         }
 100         else if((strstr(buf, "stop") != NULL) || (strstr(buf, "STOP") != NULL))
 101         {
 102                 atomic_set(&dws->debug_flag, 0);
 103                 printk("%s:close debug\n",__func__);
 104         }
 105         else if((strstr(buf, "=") != NULL))
 106         {
 107                 printk("%s:invalid command\n",__func__);
 108                 return count;
 109         }
 110
 111         sscanf(buf, "0x%x=0x%x", &reg, &value);
 112
 113         if((reg >= SPIM_CTRLR0) && (reg <= SPIM_DMARDLR))
 114         {
 115                 dw_writew(dws, reg, value);
 116                 printk("%s:write data[0x%x] to reg[0x%x] succesfully\n",__func__, value, reg);
 117         }
 118         else
 119         {
 120                 printk("%s:data[0x%x] or reg[0x%x] is out of range\n",__func__, value, reg);
 121         }
 122
 123         kfree(buf);
 124
 125         return count;
 126 }
 127
 128 static ssize_t  spi_show_regs(struct file *file, char __user *user_buf,
 129                                 size_t count, loff_t *ppos)
 130 {
 131         struct dw_spi *dws;
 132         char *buf;
 133         u32 len = 0;
 134         ssize_t ret;
 135
 136         dws = file->private_data;
 137
 138         buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
 139         if (!buf)
 140                 return 0;
 141
 142         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 143                         "MRST SPI0 registers:\n");
 144         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 145                         "=================================\n");
 146         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 147                         "CTRL0: \t\t0x%08x\n", dw_readl(dws, SPIM_CTRLR0));
 148         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 149                         "CTRL1: \t\t0x%08x\n", dw_readl(dws, SPIM_CTRLR1));
 150         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 151                         "SSIENR: \t0x%08x\n", dw_readl(dws, SPIM_SSIENR));
 152         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 153                         "SER: \t\t0x%08x\n", dw_readl(dws, SPIM_SER));
 154         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 155                         "BAUDR: \t\t0x%08x\n", dw_readl(dws, SPIM_BAUDR));
 156         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 157                         "TXFTLR: \t0x%08x\n", dw_readl(dws, SPIM_TXFTLR));
 158         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 159                         "RXFTLR: \t0x%08x\n", dw_readl(dws, SPIM_RXFTLR));
 160         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 161                         "TXFLR: \t\t0x%08x\n", dw_readl(dws, SPIM_TXFLR));
 162         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 163                         "RXFLR: \t\t0x%08x\n", dw_readl(dws, SPIM_RXFLR));
 164         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 165                         "SR: \t\t0x%08x\n", dw_readl(dws, SPIM_SR));
 166         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 167                         "IMR: \t\t0x%08x\n", dw_readl(dws, SPIM_IMR));
 168         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 169                         "ISR: \t\t0x%08x\n", dw_readl(dws, SPIM_ISR));
 170         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 171                         "DMACR: \t\t0x%08x\n", dw_readl(dws, SPIM_DMACR));
 172         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 173                         "DMATDLR: \t0x%08x\n", dw_readl(dws, SPIM_DMATDLR));
 174         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 175                         "DMARDLR: \t0x%08x\n", dw_readl(dws, SPIM_DMARDLR));
 176         len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
 177                         "=================================\n");
 178
 179         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 180         kfree(buf);
 181         return ret;
 182 }
 183
 184 static const struct file_operations spi_regs_ops = {
 185         .owner          = THIS_MODULE,
 186         .open           = simple_open,
 187         .read           = spi_show_regs,
 188         .write          = spi_write_proc_data,
 189         .llseek         = default_llseek,
 190 };
 191
 192 static int spi_debugfs_init(struct dw_spi *dws)
 193 {
 194         dws->debugfs = debugfs_create_dir("spi", NULL);
 195         if (!dws->debugfs)
 196                 return -ENOMEM;
 197
 198         debugfs_create_file("registers", S_IFREG | S_IRUGO,
 199                 dws->debugfs, (void *)dws, &spi_regs_ops);
 200         return 0;
 201 }
 202
 203 static void spi_debugfs_remove(struct dw_spi *dws)
 204 {
 205         if (dws->debugfs)
 206                 debugfs_remove_recursive(dws->debugfs);
 207 }
 208
 209 #else
 210 static inline int spi_debugfs_init(struct dw_spi *dws)
 211 {
 212         return 0;
 213 }
 214
 215 static inline void spi_debugfs_remove(struct dw_spi *dws)
 216 {
 217 }
 218 #endif /* CONFIG_DEBUG_FS */
 219
 220
 221 static void wait_till_not_busy(struct dw_spi *dws)
 222 {
 223         unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
 224         //if spi was slave, it is SR_BUSY always.
 225         if(dws->cur_chip) {
 226                 if(dws->cur_chip->slave_enable == 1)
 227                         return;
 228         }
 229
 230         while (time_before(jiffies, end)) {
 231                 if (!(dw_readw(dws, SPIM_SR) & SR_BUSY))
 232                         return;
 233         }
 234         dev_err(&dws->master->dev,
 235                 "DW SPI: Status keeps busy for 1000us after a read/write!\n");
 236 }
 237
 238
 239 static void flush(struct dw_spi *dws)
 240 {
 241         while (!(dw_readw(dws, SPIM_SR) & SR_RF_EMPT))
 242                 dw_readw(dws, SPIM_RXDR);
 243
 244         wait_till_not_busy(dws);
 245 }
 246
 247
 248 /* Return the max entries we can fill into tx fifo */
 249 static inline u32 tx_max(struct dw_spi *dws)
 250 {
 251         u32 tx_left, tx_room, rxtx_gap;
 252
 253         tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
 254         tx_room = dws->fifo_len - dw_readw(dws, SPIM_TXFLR);
 255
 256         /*
 257          * Another concern is about the tx/rx mismatch, we
 258          * though to use (dws->fifo_len - rxflr - txflr) as
 259          * one maximum value for tx, but it doesn't cover the
 260          * data which is out of tx/rx fifo and inside the
 261          * shift registers. So a control from sw point of
 262          * view is taken.
 263          */
 264         //rxtx_gap =  ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
 265         //              / dws->n_bytes;
 266
 267         return min(tx_left, tx_room);
 268 }
 269
 270 /* Return the max entries we should read out of rx fifo */
 271 static inline u32 rx_max(struct dw_spi *dws)
 272 {
 273         u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
 274
 275         return min(rx_left, (u32)dw_readw(dws, SPIM_RXFLR));
 276 }
 277
 278 static void dw_writer(struct dw_spi *dws)
 279 {
 280         u32 max = tx_max(dws);
 281         u16 txw = 0;
 282
 283         DBG_SPI("%dbyte tx:",dws->n_bytes);
 284         while (max--) {
 285                 /* Set the tx word if the transfer's original "tx" is not null */
 286                 if (dws->tx_end - dws->len) {
 287                         if (dws->n_bytes == 1)
 288                         {
 289                                 txw = *(u8 *)(dws->tx);
 290                                 DBG_SPI("0x%02x,", *(u8 *)(dws->tx));
 291                         }
 292                         else
 293                         {
 294                                 txw = *(u16 *)(dws->tx);
 295                                 DBG_SPI("0x%02x,", *(u16 *)(dws->tx));
 296                         }
 297                 }
 298                 dw_writew(dws, SPIM_TXDR, txw);
 299                 dws->tx += dws->n_bytes;
 300         }
 301
 302         //it is neccessary
 303         wait_till_not_busy(dws);
 304
 305         DBG_SPI("\n");
 306 }
 307
 308 static void dw_reader(struct dw_spi *dws)
 309 {
 310         u32 max = rx_max(dws);
 311         u16 rxw;
 312
 313         DBG_SPI("%dbyte rx:",dws->n_bytes);
 314
 315         while (max--) {
 316                 rxw = dw_readw(dws, SPIM_RXDR);
 317                 /* Care rx only if the transfer's original "rx" is not null */
 318                 if (dws->rx_end - dws->len) {
 319                         if (dws->n_bytes == 1)
 320                         {
 321                                 *(u8 *)(dws->rx) = rxw;
 322                                 DBG_SPI("0x%02x,", *(u8 *)(dws->rx));
 323                         }
 324                         else
 325                         {
 326                                 *(u16 *)(dws->rx) = rxw;
 327                                 DBG_SPI("0x%02x,", *(u16 *)(dws->rx));
 328                         }
 329                 }
 330
 331                 dws->rx += dws->n_bytes;
 332         }
 333
 334         DBG_SPI("\n");
 335 }
 336
 337 static int reader_all(struct dw_spi *dws)
 338 {
 339         u16 rxw;
 340         while (!(dw_readw(dws, SPIM_SR) & SR_RF_EMPT)
 341                 && (dws->rx < dws->rx_end)) {
 342                         dw_reader(dws);
 343                         wait_till_not_busy(dws);
 344                 }
 345
 346         return dws->rx == dws->rx_end;
 347 }
 348
 349
 350 static void *next_transfer(struct dw_spi *dws)
 351 {
 352         struct spi_message *msg = dws->cur_msg;
 353         struct spi_transfer *trans = dws->cur_transfer;
 354
 355         /* Move to next transfer */
 356         if (trans->transfer_list.next != &msg->transfers) {
 357                 dws->cur_transfer =
 358                         list_entry(trans->transfer_list.next,
 359                                         struct spi_transfer,
 360                                         transfer_list);
 361                 return RUNNING_STATE;
 362         } else
 363                 return DONE_STATE;
 364 }
 365
 366 /*
 367  * Note: first step is the protocol driver prepares
 368  * a dma-capable memory, and this func just need translate
 369  * the virt addr to physical
 370  */
 371 static int map_dma_buffers(struct dw_spi *dws)
 372 {
 373         if (!dws->dma_inited
 374                 || !dws->cur_chip->enable_dma
 375                 || !dws->dma_ops)
 376                 return 0;
 377
 378         if (dws->cur_transfer->tx_dma)
 379                 dws->tx_dma = dws->cur_transfer->tx_dma;
 380
 381         if (dws->cur_transfer->rx_dma)
 382                 dws->rx_dma = dws->cur_transfer->rx_dma;
 383
 384         DBG_SPI("%s:line=%d\n",__func__,__LINE__);
 385         return 1;
 386 }
 387
 388 /* Caller already set message->status; dma and pio irqs are blocked */
 389 static void giveback(struct dw_spi *dws)
 390 {
 391         struct spi_transfer *last_transfer;
 392         unsigned long flags;
 393         struct spi_message *msg;
 394         struct spi_message *next_msg;
 395
 396         spin_lock_irqsave(&dws->lock, flags);
 397         msg = dws->cur_msg;
 398         dws->cur_msg = NULL;
 399         dws->cur_transfer = NULL;
 400         dws->prev_chip = dws->cur_chip;
 401         dws->cur_chip = NULL;
 402         dws->dma_mapped = 0;
 403         dws->state = 0;
 404         //queue_work(dws->workqueue, &dws->pump_messages);
 405
 406         /*it is important to close intterrupt*/
 407         spi_mask_intr(dws, 0xff);
 408         //rk29xx_writew(dws, SPIM_DMACR, 0);
 409
 410         spin_unlock_irqrestore(&dws->lock, flags);
 411
 412         last_transfer = list_entry(msg->transfers.prev,
 413                                         struct spi_transfer,
 414                                         transfer_list);
 415
 416         if (!last_transfer->cs_change && dws->cs_control)
 417                 dws->cs_control(dws, msg->spi->chip_select, MRST_SPI_DEASSERT);
 418
 419         msg->state = NULL;
 420
 421         /* get a pointer to the next message, if any */
 422         next_msg = spi_get_next_queued_message(dws->master);
 423
 424         /* see if the next and current messages point
 425         * to the same chip
 426         */
 427         if (next_msg && next_msg->spi != msg->spi)
 428         next_msg = NULL;
 429
 430         spi_finalize_current_message(dws->master);
 431         dws->cur_chip = NULL;
 432
 433
 434         DBG_SPI("%s:line=%d,tx_left=%d\n",__func__,__LINE__, (dws->tx_end - dws->tx) / dws->n_bytes);
 435 }
 436
 437
 438 static void int_error_stop(struct dw_spi *dws, const char *msg)
 439 {
 440         /* Stop the hw */
 441         flush(dws);
 442         spi_enable_chip(dws, 0);
 443
 444         dev_err(&dws->master->dev, "%s\n", msg);
 445         dws->cur_msg->state = ERROR_STATE;
 446         tasklet_schedule(&dws->pump_transfers);
 447         DBG_SPI("%s:line=%d\n",__func__,__LINE__);
 448 }
 449
 450 void dw_spi_xfer_done(struct dw_spi *dws)
 451 {
 452         /* Update total byte transferred return count actual bytes read */
 453         dws->cur_msg->actual_length += dws->len;
 454
 455         /* Move to next transfer */
 456         dws->cur_msg->state = next_transfer(dws);
 457
 458         /* Handle end of message */
 459         if (dws->cur_msg->state == DONE_STATE) {
 460                 dws->cur_msg->status = 0;
 461                 giveback(dws);
 462         } else
 463                 tasklet_schedule(&dws->pump_transfers);
 464
 465         DBG_SPI("%s:line=%d\n",__func__,__LINE__);
 466 }
 467 EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
 468
 469 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
 470 {
 471         u16 irq_status;
 472         u32 int_level = dws->fifo_len / 2;
 473         u32 left;
 474
 475
 476         irq_status = dw_readw(dws, SPIM_ISR) & 0x1f;
 477
 478         DBG_SPI("%s:line=%d,irq_status=0x%x\n",__func__,__LINE__,irq_status);
 479
 480         /* Error handling */
 481         if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
 482                 dw_writew(dws, SPIM_ICR, SPI_CLEAR_INT_TXOI | SPI_CLEAR_INT_RXOI | SPI_CLEAR_INT_RXUI);
 483                 printk("%s:irq_status=0x%x\n",__func__,irq_status);
 484                 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
 485                 return IRQ_HANDLED;
 486         }
 487
 488         if (irq_status & SPI_INT_TXEI)
 489         {
 490                 spi_mask_intr(dws, SPI_INT_TXEI);
 491                 dw_writer(dws);
 492
 493                 if (dws->rx) {
 494                     reader_all(dws);
 495                 }
 496
 497                 /* Re-enable the IRQ if there is still data left to tx */
 498                 if (dws->tx_end > dws->tx)
 499                         spi_umask_intr(dws, SPI_INT_TXEI);
 500                 else
 501                         dw_spi_xfer_done(dws);
 502         }
 503
 504         if (irq_status & SPI_INT_RXFI) {
 505                 spi_mask_intr(dws, SPI_INT_RXFI);
 506
 507                 reader_all(dws);
 508
 509                 /* Re-enable the IRQ if there is still data left to rx */
 510                 if (dws->rx_end > dws->rx) {
 511                         left = ((dws->rx_end - dws->rx) / dws->n_bytes) - 1;
 512                     left = (left > int_level) ? int_level : left;
 513
 514                         dw_writew(dws, SPIM_RXFTLR, left);
 515                         spi_umask_intr(dws, SPI_INT_RXFI);
 516                 }
 517                 else {
 518                         dw_spi_xfer_done(dws);
 519                 }
 520
 521         }
 522
 523         return IRQ_HANDLED;
 524 }
 525
 526
 527 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
 528 {
 529         struct dw_spi *dws = dev_id;
 530         u16 irq_status = dw_readw(dws, SPIM_ISR)&0x3f;
 531
 532         if (!irq_status)
 533                 return IRQ_NONE;
 534
 535         if (!dws->cur_msg) {
 536                 spi_mask_intr(dws, SPI_INT_TXEI);
 537                 return IRQ_HANDLED;
 538         }
 539
 540         return dws->transfer_handler(dws);
 541 }
 542
 543 /* Must be called inside pump_transfers() */
 544 static void poll_transfer(struct dw_spi *dws)
 545 {
 546         DBG_SPI("%s:len=%d\n",__func__, dws->len);
 547
 548         do {
 549                 dw_writer(dws);
 550                 dw_reader(dws);
 551                 cpu_relax();
 552         } while (dws->rx_end > dws->rx);
 553
 554         dw_spi_xfer_done(dws);
 555
 556 }
 557
 558 static void pump_transfers(unsigned long data)
 559 {
 560         struct dw_spi *dws = (struct dw_spi *)data;
 561         struct spi_message *message = NULL;
 562         struct spi_transfer *transfer = NULL;
 563         struct spi_transfer *previous = NULL;
 564         struct spi_device *spi = NULL;
 565         struct chip_data *chip = NULL;
 566         u8 bits = 0;
 567         u8 imask = 0;
 568         u8 cs_change = 0;
 569         u16 txint_level = 0;
 570         u16 rxint_level = 0;
 571         u16 clk_div = 0;
 572         u32 speed = 0;
 573         u32 cr0 = 0;
 574         u16 dma_ctrl = 0;
 575         int ret = 0;
 576
 577
 578         /* Get current state information */
 579         message = dws->cur_msg;
 580         transfer = dws->cur_transfer;
 581         chip = dws->cur_chip;
 582         spi = message->spi;
 583
 584         if (unlikely(!chip->clk_div))
 585                 chip->clk_div = dws->max_freq / chip->speed_hz;
 586
 587         if (message->state == ERROR_STATE) {
 588                 message->status = -EIO;
 589                 goto early_exit;
 590         }
 591
 592         /* Handle end of message */
 593         if (message->state == DONE_STATE) {
 594                 message->status = 0;
 595                 goto early_exit;
 596         }
 597
 598         /* Delay if requested at end of transfer*/
 599         if (message->state == RUNNING_STATE) {
 600                 previous = list_entry(transfer->transfer_list.prev,
 601                                         struct spi_transfer,
 602                                         transfer_list);
 603                 if (previous->delay_usecs)
 604                         udelay(previous->delay_usecs);
 605         }
 606
 607         dws->n_bytes = chip->n_bytes;
 608         dws->dma_width = chip->dma_width;
 609         dws->cs_control = chip->cs_control;
 610
 611         dws->rx_dma = transfer->rx_dma;
 612         dws->tx_dma = transfer->tx_dma;
 613         dws->tx = (void *)transfer->tx_buf;
 614         dws->tx_end = dws->tx + transfer->len;
 615         dws->rx = transfer->rx_buf;
 616         dws->rx_end = dws->rx + transfer->len;
 617         dws->cs_change = transfer->cs_change;
 618         dws->len = dws->cur_transfer->len;
 619         if (chip != dws->prev_chip)
 620                 cs_change = 1;
 621
 622         cr0 = chip->cr0;
 623
 624
 625         DBG_SPI("%s:len=%d\n",__func__,dws->len);
 626
 627         /* Handle per transfer options for bpw and speed */
 628         if (transfer->speed_hz) {
 629                 speed = chip->speed_hz;
 630
 631                 if (transfer->speed_hz != speed) {
 632                         speed = transfer->speed_hz;
 633                         if (speed > dws->max_freq) {
 634                                 printk(KERN_ERR "MRST SPI0: unsupported"
 635                                         "freq: %dHz\n", speed);
 636                                 message->status = -EIO;
 637                                 goto early_exit;
 638                         }
 639
 640                         /* clk_div doesn't support odd number */
 641                         clk_div = dws->max_freq / speed;
 642                         clk_div = (clk_div + 1) & 0xfffe;
 643
 644                         chip->speed_hz = speed;
 645                         chip->clk_div = clk_div;
 646                 }
 647         }
 648         if (transfer->bits_per_word) {
 649                 bits = transfer->bits_per_word;
 650
 651                 switch (bits) {
 652                 case 8:
 653                 case 16:
 654                         dws->n_bytes = dws->dma_width = bits >> 3;
 655                         break;
 656                 default:
 657                         printk(KERN_ERR "MRST SPI0: unsupported bits:"
 658                                 "%db\n", bits);
 659                         message->status = -EIO;
 660                         goto early_exit;
 661                 }
 662
 663                 cr0 =((dws->n_bytes) << SPI_DFS_OFFSET)
 664                         | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)
 665                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)
 666                         | (chip->type << SPI_FRF_OFFSET)
 667                         | (spi->mode << SPI_MODE_OFFSET)
 668                         | (chip->tmode << SPI_TMOD_OFFSET);
 669         }
 670         message->state = RUNNING_STATE;
 671
 672         /*
 673          * Adjust transfer mode if necessary. Requires platform dependent
 674          * chipselect mechanism.
 675          */
 676         if (dws->cs_control) {
 677                 if (dws->rx && dws->tx)
 678                         chip->tmode = SPI_TMOD_TR;
 679                 else if (dws->rx)
 680                         chip->tmode = SPI_TMOD_RO;
 681                 else
 682                         chip->tmode = SPI_TMOD_TO;
 683
 684
 685                 cr0 &= ~(0x3 << SPI_MODE_OFFSET);
 686                 cr0 &= ~(0x3 << SPI_TMOD_OFFSET);
 687                 cr0 &= ~(0x1 << SPI_OPMOD_OFFSET);
 688                 cr0 |= (spi->mode << SPI_MODE_OFFSET);
 689                 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
 690                 cr0 |= ((chip->slave_enable & 1) << SPI_OPMOD_OFFSET);
 691         }
 692
 693         /* Check if current transfer is a DMA transaction */
 694         dws->dma_mapped = map_dma_buffers(dws);
 695
 696         /*
 697          * Interrupt mode
 698          * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
 699          */
 700         if (!dws->dma_mapped && !chip->poll_mode) {
 701                 int templen ;
 702
 703                 if (chip->tmode == SPI_TMOD_RO) {
 704                         templen = dws->len / dws->n_bytes - 1;
 705                         rxint_level = dws->fifo_len / 2;
 706                         rxint_level = (templen > rxint_level) ? rxint_level : templen;
 707                         imask |= SPI_INT_RXFI;
 708                 }
 709                 else {
 710                         templen = dws->len / dws->n_bytes;
 711                         txint_level = dws->fifo_len / 2;
 712                         txint_level = (templen > txint_level) ? txint_level : templen;
 713                         imask |= SPI_INT_TXEI | SPI_INT_TXOI;
 714                 }
 715                 dws->transfer_handler = interrupt_transfer;
 716         }
 717
 718
 719         /*
 720          * Reprogram registers only if
 721          *      1. chip select changes
 722          *      2. clk_div is changed
 723          *      3. control value changes
 724          */
 725         //if (dw_readw(dws, SPIM_CTRLR0) != cr0 || cs_change || clk_div || imask)
 726         if(dws->tx || dws->rx)
 727         {
 728                 spi_enable_chip(dws, 0);
 729                 if (dw_readl(dws, SPIM_CTRLR0) != cr0)
 730                         dw_writel(dws, SPIM_CTRLR0, cr0);
 731
 732                 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
 733                 spi_chip_sel(dws, spi->chip_select);
 734
 735         dw_writew(dws, SPIM_CTRLR1, dws->len-1);
 736
 737                 if (txint_level)
 738                         dw_writew(dws, SPIM_TXFTLR, txint_level);
 739
 740                 if (rxint_level)
 741                 {
 742                         dw_writew(dws, SPIM_RXFTLR, rxint_level);
 743                         DBG_SPI("%s:rxint_level=%d\n",__func__,rxint_level);
 744                 }
 745                 /* Set the interrupt mask, for poll mode just diable all int */
 746                 spi_mask_intr(dws, 0xff);
 747                 if (imask)
 748                         spi_umask_intr(dws, imask);
 749
 750                 /* setup DMA related registers */
 751                 if(dws->dma_mapped)
 752                 {
 753                         /* Set the interrupt mask, for poll mode just diable all int */
 754                         spi_mask_intr(dws, 0xff);
 755                         if(dws->tx)
 756                         {
 757                                 dma_ctrl |= SPI_DMACR_TX_ENABLE;
 758                                 dw_writew(dws, SPIM_DMATDLR, 8);
 759                                 dw_writew(dws, SPIM_CTRLR1, dws->len-1);
 760                         }
 761
 762                         if (dws->rx)
 763                         {
 764                                 dma_ctrl |= SPI_DMACR_RX_ENABLE;
 765                                 dw_writew(dws, SPIM_DMARDLR, 0);
 766                                 dw_writew(dws, SPIM_CTRLR1, dws->len-1);
 767                         }
 768                         dw_writew(dws, SPIM_DMACR, dma_ctrl);
 769
 770                         DBG_SPI("%s:dma_ctrl=0x%x\n",__func__,dw_readw(dws, SPIM_DMACR));
 771
 772                 }
 773
 774                 spi_enable_chip(dws, 1);
 775
 776                 if (cs_change)
 777                         dws->prev_chip = chip;
 778
 779                 DBG_SPI("%s:ctrl0=0x%x\n",__func__,dw_readw(dws, SPIM_CTRLR0));
 780         }
 781
 782         /*dma should be ready before spi_enable_chip*/
 783         if (dws->dma_mapped)
 784         dws->dma_ops->dma_transfer(dws, cs_change);
 785
 786         if (chip->poll_mode)
 787                 poll_transfer(dws);
 788
 789         return;
 790
 791 early_exit:
 792         giveback(dws);
 793         return;
 794 }
 795
 796 static int dw_spi_transfer_one_message(struct spi_master *master,
 797                                            struct spi_message *msg)
 798 {
 799         struct dw_spi *dws = spi_master_get_devdata(master);
 800         int ret = 0;
 801
 802         dws->cur_msg = msg;
 803         /* Initial message state*/
 804         dws->cur_msg->state = START_STATE;
 805         dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
 806                                                 struct spi_transfer,
 807                                                 transfer_list);
 808
 809         /* prepare to setup the SSP, in pump_transfers, using the per
 810          * chip configuration */
 811         dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
 812
 813         dws->dma_mapped = map_dma_buffers(dws);
 814         INIT_COMPLETION(dws->xfer_completion);
 815
 816         /* Mark as busy and launch transfers */
 817         tasklet_schedule(&dws->pump_transfers);
 818
 819         DBG_SPI("%s:line=%d\n",__func__,__LINE__);
 820         if (dws->dma_mapped)
 821         {
 822                 ret = wait_for_completion_timeout(&dws->xfer_completion,
 823                                                         msecs_to_jiffies(2000));
 824                 if(ret == 0)
 825                 {
 826                         dev_err(&dws->master->dev, "dma transfer timeout\n");
 827                         giveback(dws);
 828                         return 0;
 829                 }
 830
 831                 DBG_SPI("%s:wait %d\n",__func__, ret);
 832         }
 833
 834         return 0;
 835 }
 836
 837 static int dw_spi_prepare_transfer(struct spi_master *master)
 838 {
 839         struct dw_spi *dws = spi_master_get_devdata(master);
 840
 841         //pm_runtime_get_sync(&dws->pdev->dev);
 842
 843         DBG_SPI("%s:line=%d\n",__func__,__LINE__);
 844         return 0;
 845 }
 846
 847 static int dw_spi_unprepare_transfer(struct spi_master *master)
 848 {
 849         struct dw_spi *dws = spi_master_get_devdata(master);
 850
 851         /* Disable the SSP now */
 852         //write_SSCR0(read_SSCR0(dws->ioaddr) & ~SSCR0_SSE,
 853         //          dws->ioaddr);
 854
 855         //pm_runtime_mark_last_busy(&dws->pdev->dev);
 856         //pm_runtime_put_autosuspend(&dws->pdev->dev);
 857
 858         DBG_SPI("%s:line=%d\n",__func__,__LINE__);
 859         return 0;
 860 }
 861
 862 /* This may be called twice for each spi dev */
 863 static int dw_spi_setup(struct spi_device *spi)
 864 {
 865         struct dw_spi_chip *chip_info = NULL;
 866         struct chip_data *chip;
 867
 868         if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
 869                 return -EINVAL;
 870
 871         /* Only alloc on first setup */
 872         chip = spi_get_ctldata(spi);
 873         if (!chip) {
 874                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 875                 if (!chip)
 876                         return -ENOMEM;
 877
 878                 chip->cs_control = spi_cs_control;
 879                 chip->enable_dma = 0;
 880         }
 881
 882         /*
 883          * Protocol drivers may change the chip settings, so...
 884          * if chip_info exists, use it
 885          */
 886         chip_info = spi->controller_data;
 887
 888         /* chip_info doesn't always exist */
 889         if (chip_info) {
 890                 if (chip_info->cs_control)
 891                         chip->cs_control = chip_info->cs_control;
 892
 893                 chip->poll_mode = chip_info->poll_mode;
 894                 chip->type = chip_info->type;
 895
 896                 chip->rx_threshold = 0;
 897                 chip->tx_threshold = 0;
 898
 899                 chip->enable_dma = chip_info->enable_dma;
 900         }
 901
 902         if (spi->bits_per_word <= 8) {
 903                 chip->n_bytes = 1;
 904                 chip->dma_width = 1;
 905         } else if (spi->bits_per_word <= 16) {
 906                 chip->n_bytes = 2;
 907                 chip->dma_width = 2;
 908         } else {
 909                 /* Never take >16b case for MRST SPIC */
 910                 dev_err(&spi->dev, "invalid wordsize\n");
 911                 return -EINVAL;
 912         }
 913         chip->bits_per_word = spi->bits_per_word;
 914
 915         if (!spi->max_speed_hz) {
 916                 dev_err(&spi->dev, "No max speed HZ parameter\n");
 917                 return -EINVAL;
 918         }
 919         chip->speed_hz = spi->max_speed_hz;
 920
 921         chip->tmode = 0; /* Tx & Rx */
 922         /* Default SPI mode is SCPOL = 0, SCPH = 0 */
 923         chip->cr0 = ((chip->n_bytes) << SPI_DFS_OFFSET)
 924                     | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)
 925                         | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)
 926                         | (chip->type << SPI_FRF_OFFSET)
 927                         | (spi->mode  << SPI_MODE_OFFSET)
 928                         | (chip->tmode << SPI_TMOD_OFFSET);
 929
 930         spi_set_ctldata(spi, chip);
 931
 932         //printk("%s:line=%d\n",__func__,__LINE__);
 933         return 0;
 934 }
 935
 936 static void dw_spi_cleanup(struct spi_device *spi)
 937 {
 938         struct chip_data *chip = spi_get_ctldata(spi);
 939         kfree(chip);
 940 }
 941
 942
 943 /* Restart the controller, disable all interrupts, clean rx fifo */
 944 static void spi_hw_init(struct dw_spi *dws)
 945 {
 946         spi_enable_chip(dws, 0);
 947         spi_mask_intr(dws, 0xff);
 948
 949         /*
 950          * Try to detect the FIFO depth if not set by interface driver,
 951          * the depth could be from 2 to 32 from HW spec
 952          */
 953         if (!dws->fifo_len) {
 954                 u32 fifo;
 955                 for (fifo = 2; fifo <= 31; fifo++) {
 956                         dw_writew(dws, SPIM_TXFTLR, fifo);
 957                         if (fifo != dw_readw(dws, SPIM_TXFTLR))
 958                                 break;
 959                 }
 960
 961                 dws->fifo_len = (fifo == 31) ? 0 : fifo;
 962                 dw_writew(dws, SPIM_TXFTLR, 0);
 963         }
 964
 965         //spi_enable_chip(dws, 1);
 966         flush(dws);
 967         DBG_SPI("%s:fifo_len=%d\n",__func__, dws->fifo_len);
 968 }
 969
 970 int dw_spi_add_host(struct dw_spi *dws)
 971 {
 972         struct spi_master *master;
 973         int ret;
 974
 975         BUG_ON(dws == NULL);
 976
 977         master = spi_alloc_master(dws->parent_dev, 0);
 978         if (!master) {
 979                 ret = -ENOMEM;
 980                 goto exit;
 981         }
 982
 983         dws->master = master;
 984         dws->type = SSI_MOTO_SPI;
 985         dws->prev_chip = NULL;
 986         dws->dma_inited = 0;
 987         dws->tx_dma_addr = (dma_addr_t)(dws->paddr + SPIM_TXDR);
 988         dws->rx_dma_addr = (dma_addr_t)(dws->paddr + SPIM_RXDR);
 989         snprintf(dws->name, sizeof(dws->name), "dw_spi%d",
 990                         dws->bus_num);
 991
 992         ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED,
 993                         dws->name, dws);
 994         if (ret < 0) {
 995                 dev_err(&master->dev, "can not get IRQ\n");
 996                 goto err_free_master;
 997         }
 998
 999         master->mode_bits = SPI_CPOL | SPI_CPHA;
1000         master->bus_num = dws->bus_num;
1001         master->num_chipselect = dws->num_cs;
1002         master->cleanup = dw_spi_cleanup;
1003         master->setup = dw_spi_setup;
1004         master->transfer_one_message = dw_spi_transfer_one_message;
1005         master->prepare_transfer_hardware = dw_spi_prepare_transfer;
1006         master->unprepare_transfer_hardware = dw_spi_unprepare_transfer;
1007
1008         spin_lock_init(&dws->lock);
1009         tasklet_init(&dws->pump_transfers,
1010                         pump_transfers, (unsigned long)dws);
1011
1012
1013         /* Basic HW init */
1014         spi_hw_init(dws);
1015
1016         if (dws->dma_ops && dws->dma_ops->dma_init) {
1017                 ret = dws->dma_ops->dma_init(dws);
1018                 if (ret) {
1019                         dev_warn(&master->dev, "DMA init failed,ret=%d\n",ret);
1020                         dws->dma_inited = 0;
1021                 }
1022         }
1023
1024         spi_master_set_devdata(master, dws);
1025         ret = spi_register_master(master);
1026         if (ret) {
1027                 dev_err(&master->dev, "problem registering spi master\n");
1028                 goto err_queue_alloc;
1029         }
1030
1031         spi_debugfs_init(dws);
1032
1033
1034         DBG_SPI("%s:bus_num=%d\n",__func__, dws->bus_num);
1035         return 0;
1036
1037 err_queue_alloc:
1038         if (dws->dma_ops && dws->dma_ops->dma_exit)
1039                 dws->dma_ops->dma_exit(dws);
1040 err_diable_hw:
1041         spi_enable_chip(dws, 0);
1042         free_irq(dws->irq, dws);
1043 err_free_master:
1044         spi_master_put(master);
1045 exit:
1046         return ret;
1047 }
1048 EXPORT_SYMBOL_GPL(dw_spi_add_host);
1049
1050 void dw_spi_remove_host(struct dw_spi *dws)
1051 {
1052         int status = 0;
1053
1054         if (!dws)
1055                 return;
1056
1057         spi_debugfs_remove(dws);
1058
1059         if (dws->dma_ops && dws->dma_ops->dma_exit)
1060                 dws->dma_ops->dma_exit(dws);
1061
1062         spi_enable_chip(dws, 0);
1063         /* Disable clk */
1064         spi_set_clk(dws, 0);
1065         free_irq(dws->irq, dws);
1066
1067         /* Disconnect from the SPI framework */
1068         spi_unregister_master(dws->master);
1069
1070
1071         DBG_SPI("%s:bus_num=%d\n",__func__, dws->bus_num);
1072 }
1073 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
1074
1075 int dw_spi_suspend_host(struct dw_spi *dws)
1076 {
1077         int ret = 0;
1078
1079         ret = spi_master_suspend(dws->master);
1080         if (ret != 0)
1081         return ret;
1082
1083         spi_enable_chip(dws, 0);
1084         spi_set_clk(dws, 0);
1085
1086         clk_disable_unprepare(dws->clk_spi);
1087
1088         DBG_SPI("%s:bus_num=%d\n",__func__, dws->bus_num);
1089         return ret;
1090 }
1091 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
1092
1093 int dw_spi_resume_host(struct dw_spi *dws)
1094 {
1095         int ret;
1096
1097         /* Enable the SPI clock */
1098         clk_prepare_enable(dws->clk_spi);
1099
1100         spi_hw_init(dws);
1101
1102         /* Start the queue running */
1103         ret = spi_master_resume(dws->master);
1104         if (ret != 0) {
1105                 printk("%s:problem starting queue (%d)\n", __func__, ret);
1106                 return ret;
1107         }
1108
1109         DBG_SPI("%s:bus_num=%d\n",__func__, dws->bus_num);
1110         return ret;
1111 }
1112 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
1113
1114 MODULE_AUTHOR("Luo Wei <lw@rock-chips.com>");
1115 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
1116 MODULE_LICENSE("GPL v2");