2 * Designware SPI core controller driver (refer spi_dw.c)
4 * Copyright (c) 2009, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/highmem.h>
24 #include <linux/delay.h>
25 #include <linux/slab.h>
26 #include <linux/spi/spi.h>
27 #include <linux/clk.h>
30 #include "spi-rockchip-core.h"
32 #ifdef CONFIG_DEBUG_FS
33 #include <linux/debugfs.h>
36 #define START_STATE ((void *)0)
37 #define RUNNING_STATE ((void *)1)
38 #define DONE_STATE ((void *)2)
39 #define ERROR_STATE ((void *)-1)
41 #define QUEUE_RUNNING 0
42 #define QUEUE_STOPPED 1
44 #define MRST_SPI_DEASSERT 0
45 #define MRST_SPI_ASSERT 1
48 /* Slave spi_dev related */
51 u8 cs; /* chip select pin */
52 u8 n_bytes; /* current is a 1/2/4 byte op */
53 u8 tmode; /* TR/TO/RO/EEPROM */
54 u8 type; /* SPI/SSP/MicroWire */
56 u8 poll_mode; /* 1 means use poll mode */
64 u16 clk_div; /* baud rate divider */
65 u32 speed_hz; /* baud rate */
66 void (*cs_control)(struct dw_spi *dws, u32 cs, u8 flag);
69 #ifdef CONFIG_DEBUG_FS
70 #define SPI_REGS_BUFSIZE 1024
72 static ssize_t spi_write_proc_data(struct file *file, const char __user *buffer,
73 size_t count, loff_t *data)
78 int reg = 0,value = 0;
80 dws = file->private_data;
82 buf = kzalloc(32, GFP_KERNEL);
86 ret = copy_from_user(buf, buffer, count);
92 if((strstr(buf, "debug") != NULL) || (strstr(buf, "DEBUG") != NULL))
94 atomic_set(&dws->debug_flag, 1);
96 printk("%s:open debug\n",__func__);
99 else if((strstr(buf, "stop") != NULL) || (strstr(buf, "STOP") != NULL))
101 atomic_set(&dws->debug_flag, 0);
102 printk("%s:close debug\n",__func__);
104 else if((strstr(buf, "=") != NULL))
106 printk("%s:invalid command\n",__func__);
110 sscanf(buf, "0x%x=0x%x", ®, &value);
112 if((reg >= SPIM_CTRLR0) && (reg <= SPIM_DMARDLR))
114 dw_writew(dws, reg, value);
115 printk("%s:write data[0x%x] to reg[0x%x] succesfully\n",__func__, value, reg);
119 printk("%s:data[0x%x] or reg[0x%x] is out of range\n",__func__, value, reg);
127 static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
128 size_t count, loff_t *ppos)
135 dws = file->private_data;
137 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
141 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
142 "MRST SPI0 registers:\n");
143 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
144 "=================================\n");
145 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
146 "CTRL0: \t\t0x%08x\n", dw_readl(dws, SPIM_CTRLR0));
147 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
148 "CTRL1: \t\t0x%08x\n", dw_readl(dws, SPIM_CTRLR1));
149 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
150 "SSIENR: \t0x%08x\n", dw_readl(dws, SPIM_SSIENR));
151 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
152 "SER: \t\t0x%08x\n", dw_readl(dws, SPIM_SER));
153 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
154 "BAUDR: \t\t0x%08x\n", dw_readl(dws, SPIM_BAUDR));
155 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
156 "TXFTLR: \t0x%08x\n", dw_readl(dws, SPIM_TXFTLR));
157 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
158 "RXFTLR: \t0x%08x\n", dw_readl(dws, SPIM_RXFTLR));
159 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
160 "TXFLR: \t\t0x%08x\n", dw_readl(dws, SPIM_TXFLR));
161 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
162 "RXFLR: \t\t0x%08x\n", dw_readl(dws, SPIM_RXFLR));
163 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
164 "SR: \t\t0x%08x\n", dw_readl(dws, SPIM_SR));
165 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
166 "IMR: \t\t0x%08x\n", dw_readl(dws, SPIM_IMR));
167 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
168 "ISR: \t\t0x%08x\n", dw_readl(dws, SPIM_ISR));
169 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
170 "DMACR: \t\t0x%08x\n", dw_readl(dws, SPIM_DMACR));
171 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
172 "DMATDLR: \t0x%08x\n", dw_readl(dws, SPIM_DMATDLR));
173 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
174 "DMARDLR: \t0x%08x\n", dw_readl(dws, SPIM_DMARDLR));
175 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
176 "=================================\n");
178 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
183 static const struct file_operations spi_regs_ops = {
184 .owner = THIS_MODULE,
186 .read = spi_show_regs,
187 .write = spi_write_proc_data,
188 .llseek = default_llseek,
191 static int spi_debugfs_init(struct dw_spi *dws)
193 dws->debugfs = debugfs_create_dir("spi", NULL);
197 debugfs_create_file("registers", S_IFREG | S_IRUGO,
198 dws->debugfs, (void *)dws, &spi_regs_ops);
202 static void spi_debugfs_remove(struct dw_spi *dws)
205 debugfs_remove_recursive(dws->debugfs);
209 static inline int spi_debugfs_init(struct dw_spi *dws)
214 static inline void spi_debugfs_remove(struct dw_spi *dws)
217 #endif /* CONFIG_DEBUG_FS */
220 static void wait_till_not_busy(struct dw_spi *dws)
222 unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
223 //if spi was slave, it is SR_BUSY always.
225 if(dws->cur_chip->slave_enable == 1)
229 while (time_before(jiffies, end)) {
230 if (!(dw_readw(dws, SPIM_SR) & SR_BUSY))
233 dev_err(&dws->master->dev,
234 "DW SPI: Status keeps busy for 1000us after a read/write!\n");
238 static void flush(struct dw_spi *dws)
240 while (!(dw_readw(dws, SPIM_SR) & SR_RF_EMPT))
241 dw_readw(dws, SPIM_RXDR);
243 wait_till_not_busy(dws);
247 /* Return the max entries we can fill into tx fifo */
248 static inline u32 tx_max(struct dw_spi *dws)
250 u32 tx_left, tx_room;
252 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
253 tx_room = dws->fifo_len - dw_readw(dws, SPIM_TXFLR);
256 * Another concern is about the tx/rx mismatch, we
257 * though to use (dws->fifo_len - rxflr - txflr) as
258 * one maximum value for tx, but it doesn't cover the
259 * data which is out of tx/rx fifo and inside the
260 * shift registers. So a control from sw point of
263 //rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
266 return min(tx_left, tx_room);
269 /* Return the max entries we should read out of rx fifo */
270 static inline u32 rx_max(struct dw_spi *dws)
272 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
274 return min(rx_left, (u32)dw_readw(dws, SPIM_RXFLR));
277 static void dw_writer(struct dw_spi *dws)
279 u32 max = tx_max(dws);
282 DBG_SPI("%dbyte tx:",dws->n_bytes);
284 /* Set the tx word if the transfer's original "tx" is not null */
285 if (dws->tx_end - dws->len) {
286 if (dws->n_bytes == 1)
288 txw = *(u8 *)(dws->tx);
289 DBG_SPI("0x%02x,", *(u8 *)(dws->tx));
293 txw = *(u16 *)(dws->tx);
294 DBG_SPI("0x%02x,", *(u16 *)(dws->tx));
297 dw_writew(dws, SPIM_TXDR, txw);
298 dws->tx += dws->n_bytes;
302 wait_till_not_busy(dws);
307 static void dw_reader(struct dw_spi *dws)
309 u32 max = rx_max(dws);
312 DBG_SPI("%dbyte rx:",dws->n_bytes);
315 rxw = dw_readw(dws, SPIM_RXDR);
316 /* Care rx only if the transfer's original "rx" is not null */
317 if (dws->rx_end - dws->len) {
318 if (dws->n_bytes == 1)
320 *(u8 *)(dws->rx) = rxw;
321 DBG_SPI("0x%02x,", *(u8 *)(dws->rx));
325 *(u16 *)(dws->rx) = rxw;
326 DBG_SPI("0x%02x,", *(u16 *)(dws->rx));
330 dws->rx += dws->n_bytes;
336 static int reader_all(struct dw_spi *dws)
338 while (!(dw_readw(dws, SPIM_SR) & SR_RF_EMPT)
339 && (dws->rx < dws->rx_end)) {
341 wait_till_not_busy(dws);
344 return dws->rx == dws->rx_end;
348 static void *next_transfer(struct dw_spi *dws)
350 struct spi_message *msg = dws->cur_msg;
351 struct spi_transfer *trans = dws->cur_transfer;
353 /* Move to next transfer */
354 if (trans->transfer_list.next != &msg->transfers) {
356 list_entry(trans->transfer_list.next,
359 return RUNNING_STATE;
365 * Note: first step is the protocol driver prepares
366 * a dma-capable memory, and this func just need translate
367 * the virt addr to physical
369 static int map_dma_buffers(struct dw_spi *dws)
372 || !dws->cur_chip->enable_dma
376 if (dws->cur_transfer->tx_dma)
377 dws->tx_dma = dws->cur_transfer->tx_dma;
379 if (dws->cur_transfer->rx_dma)
380 dws->rx_dma = dws->cur_transfer->rx_dma;
382 DBG_SPI("%s:line=%d\n",__func__,__LINE__);
386 /* Caller already set message->status; dma and pio irqs are blocked */
387 static void giveback(struct dw_spi *dws)
389 struct spi_transfer *last_transfer;
391 struct spi_message *msg;
392 struct spi_message *next_msg;
394 spin_lock_irqsave(&dws->lock, flags);
397 dws->cur_transfer = NULL;
398 dws->prev_chip = dws->cur_chip;
399 dws->cur_chip = NULL;
402 //queue_work(dws->workqueue, &dws->pump_messages);
404 /*it is important to close intterrupt*/
405 spi_mask_intr(dws, 0xff);
406 //rk29xx_writew(dws, SPIM_DMACR, 0);
408 spin_unlock_irqrestore(&dws->lock, flags);
410 last_transfer = list_entry(msg->transfers.prev,
414 if (!last_transfer->cs_change && dws->cs_control)
415 dws->cs_control(dws, msg->spi->chip_select, MRST_SPI_DEASSERT);
419 /* get a pointer to the next message, if any */
420 next_msg = spi_get_next_queued_message(dws->master);
422 /* see if the next and current messages point
425 if (next_msg && next_msg->spi != msg->spi)
428 dws->cur_chip = NULL;
429 spi_finalize_current_message(dws->master);
431 DBG_SPI("%s:line=%d,tx_left=%ld\n",__func__,__LINE__, (long)(dws->tx_end - dws->tx) / dws->n_bytes);
435 static void int_error_stop(struct dw_spi *dws, const char *msg)
439 spi_enable_chip(dws, 0);
441 dev_err(&dws->master->dev, "%s\n", msg);
442 dws->cur_msg->state = ERROR_STATE;
443 tasklet_schedule(&dws->pump_transfers);
444 DBG_SPI("%s:line=%d\n",__func__,__LINE__);
447 void dw_spi_xfer_done(struct dw_spi *dws)
449 /* Update total byte transferred return count actual bytes read */
450 dws->cur_msg->actual_length += dws->len;
452 /* Move to next transfer */
453 dws->cur_msg->state = next_transfer(dws);
455 /* Handle end of message */
456 if (dws->cur_msg->state == DONE_STATE) {
457 dws->cur_msg->status = 0;
460 tasklet_schedule(&dws->pump_transfers);
462 DBG_SPI("%s:line=%d\n",__func__,__LINE__);
464 EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
466 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
469 u32 int_level = dws->fifo_len / 2;
473 irq_status = dw_readw(dws, SPIM_ISR) & 0x1f;
475 DBG_SPI("%s:line=%d,irq_status=0x%x\n",__func__,__LINE__,irq_status);
478 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
479 dw_writew(dws, SPIM_ICR, SPI_CLEAR_INT_TXOI | SPI_CLEAR_INT_RXOI | SPI_CLEAR_INT_RXUI);
480 printk("%s:irq_status=0x%x\n",__func__,irq_status);
481 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
485 if (irq_status & SPI_INT_TXEI)
487 spi_mask_intr(dws, SPI_INT_TXEI);
494 /* Re-enable the IRQ if there is still data left to tx */
495 if (dws->tx_end > dws->tx)
496 spi_umask_intr(dws, SPI_INT_TXEI);
498 dw_spi_xfer_done(dws);
501 if (irq_status & SPI_INT_RXFI) {
502 spi_mask_intr(dws, SPI_INT_RXFI);
506 /* Re-enable the IRQ if there is still data left to rx */
507 if (dws->rx_end > dws->rx) {
508 left = ((dws->rx_end - dws->rx) / dws->n_bytes) - 1;
509 left = (left > int_level) ? int_level : left;
511 dw_writew(dws, SPIM_RXFTLR, left);
512 spi_umask_intr(dws, SPI_INT_RXFI);
515 dw_spi_xfer_done(dws);
524 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
526 struct dw_spi *dws = dev_id;
527 u16 irq_status = dw_readw(dws, SPIM_ISR)&0x3f;
533 spi_mask_intr(dws, SPI_INT_TXEI);
537 return dws->transfer_handler(dws);
540 /* Must be called inside pump_transfers() */
541 static void poll_transfer(struct dw_spi *dws)
543 DBG_SPI("%s:len=%ld\n",__func__, (long)dws->len);
549 } while (dws->rx_end > dws->rx);
551 dw_spi_xfer_done(dws);
555 static void pump_transfers(unsigned long data)
557 struct dw_spi *dws = (struct dw_spi *)data;
558 struct spi_message *message = NULL;
559 struct spi_transfer *transfer = NULL;
560 struct spi_transfer *previous = NULL;
561 struct spi_device *spi = NULL;
562 struct chip_data *chip = NULL;
574 /* Get current state information */
575 message = dws->cur_msg;
576 transfer = dws->cur_transfer;
577 chip = dws->cur_chip;
580 if (unlikely(!chip->clk_div))
582 chip->clk_div = dws->max_freq / chip->speed_hz;
583 chip->clk_div = (chip->clk_div + 1) & 0xfffe;
584 chip->speed_hz = dws->max_freq / chip->clk_div;
588 if (message->state == ERROR_STATE) {
589 message->status = -EIO;
593 /* Handle end of message */
594 if (message->state == DONE_STATE) {
599 /* Delay if requested at end of transfer*/
600 if (message->state == RUNNING_STATE) {
601 previous = list_entry(transfer->transfer_list.prev,
604 if (previous->delay_usecs)
605 udelay(previous->delay_usecs);
608 dws->n_bytes = chip->n_bytes;
609 dws->dma_width = chip->dma_width;
610 dws->cs_control = chip->cs_control;
612 dws->rx_dma = transfer->rx_dma;
613 dws->tx_dma = transfer->tx_dma;
614 dws->tx = (void *)transfer->tx_buf;
615 dws->tx_end = dws->tx + transfer->len;
616 dws->rx = transfer->rx_buf;
617 dws->rx_end = dws->rx + transfer->len;
618 dws->cs_change = transfer->cs_change;
619 dws->len = dws->cur_transfer->len;
620 if (chip != dws->prev_chip)
627 /* Handle per transfer options for bpw and speed */
628 if (transfer->speed_hz) {
629 speed = chip->speed_hz;
631 if (transfer->speed_hz != speed) {
632 speed = transfer->speed_hz;
633 if (speed > dws->max_freq) {
634 printk(KERN_ERR "MRST SPI0: unsupported"
635 "freq: %dHz\n", speed);
636 message->status = -EIO;
640 /* clk_div doesn't support odd number */
641 clk_div = dws->max_freq / speed;
642 clk_div = (clk_div + 1) & 0xfffe;
644 chip->speed_hz = dws->max_freq / clk_div;
645 chip->clk_div = clk_div;
648 DBG_SPI("%s:len=%ld,clk_div=%d,speed_hz=%d\n",__func__, (long)dws->len,chip->clk_div,chip->speed_hz);
649 if (transfer->bits_per_word) {
650 bits = transfer->bits_per_word;
655 dws->n_bytes = dws->dma_width = bits >> 3;
658 printk(KERN_ERR "MRST SPI0: unsupported bits:"
660 message->status = -EIO;
664 cr0 =((dws->n_bytes) << SPI_DFS_OFFSET)
665 | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)
666 | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)
667 | (chip->type << SPI_FRF_OFFSET)
668 | (spi->mode << SPI_MODE_OFFSET)
669 | (chip->tmode << SPI_TMOD_OFFSET);
671 message->state = RUNNING_STATE;
674 * Adjust transfer mode if necessary. Requires platform dependent
675 * chipselect mechanism.
677 if (dws->cs_control) {
678 if (dws->rx && dws->tx)
679 chip->tmode = SPI_TMOD_TR;
681 chip->tmode = SPI_TMOD_RO;
683 chip->tmode = SPI_TMOD_TO;
686 cr0 &= ~(0x3 << SPI_MODE_OFFSET);
687 cr0 &= ~(0x3 << SPI_TMOD_OFFSET);
688 cr0 &= ~(0x1 << SPI_OPMOD_OFFSET);
689 cr0 |= (spi->mode << SPI_MODE_OFFSET);
690 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
691 cr0 |= ((chip->slave_enable & 1) << SPI_OPMOD_OFFSET);
694 /* Check if current transfer is a DMA transaction */
695 dws->dma_mapped = map_dma_buffers(dws);
699 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
701 if (!dws->dma_mapped && !chip->poll_mode) {
704 if (chip->tmode == SPI_TMOD_RO) {
705 templen = dws->len / dws->n_bytes - 1;
706 rxint_level = dws->fifo_len / 2;
707 rxint_level = (templen > rxint_level) ? rxint_level : templen;
708 imask |= SPI_INT_RXFI;
711 templen = dws->len / dws->n_bytes;
712 txint_level = dws->fifo_len / 2;
713 txint_level = (templen > txint_level) ? txint_level : templen;
714 imask |= SPI_INT_TXEI | SPI_INT_TXOI;
716 dws->transfer_handler = interrupt_transfer;
720 * Reprogram registers only if
721 * 1. chip select changes
722 * 2. clk_div is changed
723 * 3. control value changes
725 //if (dw_readw(dws, SPIM_CTRLR0) != cr0 || cs_change || clk_div || imask)
726 if(dws->tx || dws->rx)
728 spi_enable_chip(dws, 0);
729 if (dw_readl(dws, SPIM_CTRLR0) != cr0)
730 dw_writel(dws, SPIM_CTRLR0, cr0);
733 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
734 spi_chip_sel(dws, spi->chip_select);
736 dw_writew(dws, SPIM_CTRLR1, dws->len-1);
738 if (txint_level != dw_readl(dws, SPIM_TXFTLR))
739 dw_writew(dws, SPIM_TXFTLR, txint_level);
741 if (rxint_level != dw_readl(dws, SPIM_RXFTLR))
743 dw_writew(dws, SPIM_RXFTLR, rxint_level);
744 DBG_SPI("%s:rxint_level=%d\n",__func__,rxint_level);
747 /* setup DMA related registers */
750 dws->dmatdlr = dws->n_bytes;
751 dws->dmardlr = dws->n_bytes - 1;
752 for(i=dws->n_bytes; i<=dws->fifo_len / 4; i++)
754 if((dws->len / dws->n_bytes) % i == 0)
758 /* Set the interrupt mask, for poll mode just diable all int */
759 spi_mask_intr(dws, 0xff);
762 dma_ctrl |= SPI_DMACR_TX_ENABLE;
763 dw_writew(dws, SPIM_DMATDLR, dws->dmatdlr);
764 dw_writew(dws, SPIM_CTRLR1, dws->len-1);
767 dws->dmardlr = (dws->dmatdlr != dws->n_bytes)?(dws->dmatdlr-1):(dws->n_bytes-1);
771 dma_ctrl |= SPI_DMACR_RX_ENABLE;
772 dw_writew(dws, SPIM_DMARDLR, dws->dmardlr);
773 dw_writew(dws, SPIM_CTRLR1, dws->len-1);
775 dw_writew(dws, SPIM_DMACR, dma_ctrl);
777 DBG_SPI("%s:dma_ctrl=0x%x,dmatdlr=%d,dmardlr=%d\n",__func__,dw_readw(dws, SPIM_DMACR),dws->dmatdlr, dws->dmardlr);
781 if((!dws->dma_mapped) || (dws->dma_mapped && dws->tx))
782 spi_enable_chip(dws, 1);
784 DBG_SPI("%s:ctrl0=0x%x\n",__func__,dw_readw(dws, SPIM_CTRLR0));
786 /* Set the interrupt mask, for poll mode just diable all int */
787 spi_mask_intr(dws, 0xff);
789 spi_umask_intr(dws, imask);
792 dws->prev_chip = chip;
797 printk("%s:warning tx and rx is null\n",__func__);
800 /*dma should be ready before spi_enable_chip*/
802 dws->dma_ops->dma_transfer(dws, cs_change);
814 static int dw_spi_transfer_one_message(struct spi_master *master,
815 struct spi_message *msg)
817 struct dw_spi *dws = spi_master_get_devdata(master);
821 /* Initial message state*/
822 dws->cur_msg->state = START_STATE;
823 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
827 /* prepare to setup the SSP, in pump_transfers, using the per
828 * chip configuration */
829 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
831 dws->dma_mapped = map_dma_buffers(dws);
832 INIT_COMPLETION(dws->xfer_completion);
834 /* Mark as busy and launch transfers */
835 tasklet_schedule(&dws->pump_transfers);
837 DBG_SPI("%s:line=%d\n",__func__,__LINE__);
840 ret = wait_for_completion_timeout(&dws->xfer_completion,
841 msecs_to_jiffies(2000));
844 dev_err(&dws->master->dev, "dma transfer timeout\n");
849 DBG_SPI("%s:wait %d\n",__func__, ret);
855 static int dw_spi_prepare_transfer(struct spi_master *master)
857 struct dw_spi *dws = spi_master_get_devdata(master);
859 //pm_runtime_get_sync(&dws->pdev->dev);
861 DBG_SPI("%s:line=%d\n",__func__,__LINE__);
865 static int dw_spi_unprepare_transfer(struct spi_master *master)
867 struct dw_spi *dws = spi_master_get_devdata(master);
869 /* Disable the SSP now */
870 //write_SSCR0(read_SSCR0(dws->ioaddr) & ~SSCR0_SSE,
873 //pm_runtime_mark_last_busy(&dws->pdev->dev);
874 //pm_runtime_put_autosuspend(&dws->pdev->dev);
876 DBG_SPI("%s:line=%d\n",__func__,__LINE__);
880 /* This may be called twice for each spi dev */
881 static int dw_spi_setup(struct spi_device *spi)
883 struct dw_spi_chip *chip_info = NULL;
884 struct chip_data *chip;
886 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
889 /* Only alloc on first setup */
890 chip = spi_get_ctldata(spi);
892 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
896 chip->cs_control = spi_cs_control;
897 chip->enable_dma = 0;
901 * Protocol drivers may change the chip settings, so...
902 * if chip_info exists, use it
904 chip_info = spi->controller_data;
906 /* chip_info doesn't always exist */
908 if (chip_info->cs_control)
909 chip->cs_control = chip_info->cs_control;
911 chip->poll_mode = chip_info->poll_mode;
912 chip->type = chip_info->type;
914 chip->rx_threshold = 0;
915 chip->tx_threshold = 0;
917 chip->enable_dma = chip_info->enable_dma;
920 if (spi->bits_per_word <= 8) {
923 } else if (spi->bits_per_word <= 16) {
927 /* Never take >16b case for MRST SPIC */
928 dev_err(&spi->dev, "invalid wordsize\n");
931 chip->bits_per_word = spi->bits_per_word;
933 if (!spi->max_speed_hz) {
934 dev_err(&spi->dev, "No max speed HZ parameter\n");
937 chip->speed_hz = spi->max_speed_hz;
939 chip->tmode = 0; /* Tx & Rx */
940 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
941 chip->cr0 = ((chip->n_bytes) << SPI_DFS_OFFSET)
942 | (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)
943 | (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)
944 | (chip->type << SPI_FRF_OFFSET)
945 | (spi->mode << SPI_MODE_OFFSET)
946 | (chip->tmode << SPI_TMOD_OFFSET);
948 spi_set_ctldata(spi, chip);
950 //printk("%s:line=%d\n",__func__,__LINE__);
954 static void dw_spi_cleanup(struct spi_device *spi)
956 struct chip_data *chip = spi_get_ctldata(spi);
961 /* Restart the controller, disable all interrupts, clean rx fifo */
962 static void spi_hw_init(struct dw_spi *dws)
964 spi_enable_chip(dws, 0);
965 spi_mask_intr(dws, 0xff);
968 * Try to detect the FIFO depth if not set by interface driver,
969 * the depth could be from 2 to 32 from HW spec
971 if (!dws->fifo_len) {
973 for (fifo = 2; fifo <= 31; fifo++) {
974 dw_writew(dws, SPIM_TXFTLR, fifo);
975 if (fifo != dw_readw(dws, SPIM_TXFTLR))
979 dws->fifo_len = (fifo == 31) ? 0 : fifo;
980 dw_writew(dws, SPIM_TXFTLR, 0);
983 //spi_enable_chip(dws, 1);
985 DBG_SPI("%s:fifo_len=%d\n",__func__, dws->fifo_len);
988 int dw_spi_add_host(struct dw_spi *dws)
990 struct spi_master *master;
995 master = spi_alloc_master(dws->parent_dev, 0);
1001 dws->master = master;
1002 dws->type = SSI_MOTO_SPI;
1003 dws->prev_chip = NULL;
1004 dws->dma_inited = 0;
1005 dws->tx_dma_addr = (dma_addr_t)(dws->paddr + SPIM_TXDR);
1006 dws->rx_dma_addr = (dma_addr_t)(dws->paddr + SPIM_RXDR);
1007 snprintf(dws->name, sizeof(dws->name), "dw_spi%d",
1010 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED,
1013 dev_err(&master->dev, "can not get IRQ\n");
1014 goto err_free_master;
1017 master->dev.parent = dws->parent_dev;
1018 master->dev.of_node = dws->parent_dev->of_node;
1019 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1020 master->bus_num = dws->bus_num;
1021 master->num_chipselect = dws->num_cs;
1022 master->cleanup = dw_spi_cleanup;
1023 master->setup = dw_spi_setup;
1024 master->transfer_one_message = dw_spi_transfer_one_message;
1025 master->prepare_transfer_hardware = dw_spi_prepare_transfer;
1026 master->unprepare_transfer_hardware = dw_spi_unprepare_transfer;
1028 spin_lock_init(&dws->lock);
1029 tasklet_init(&dws->pump_transfers,
1030 pump_transfers, (unsigned long)dws);
1036 if (dws->dma_ops && dws->dma_ops->dma_init) {
1037 ret = dws->dma_ops->dma_init(dws);
1039 dev_warn(&master->dev, "DMA init failed,ret=%d\n",ret);
1040 dws->dma_inited = 0;
1044 spi_master_set_devdata(master, dws);
1045 ret = spi_register_master(master);
1047 dev_err(&master->dev, "problem registering spi master\n");
1048 goto err_queue_alloc;
1051 spi_debugfs_init(dws);
1054 DBG_SPI("%s:bus_num=%d\n",__func__, dws->bus_num);
1058 if (dws->dma_ops && dws->dma_ops->dma_exit)
1059 dws->dma_ops->dma_exit(dws);
1060 /* err_diable_hw: */
1061 spi_enable_chip(dws, 0);
1062 free_irq(dws->irq, dws);
1064 spi_master_put(master);
1068 EXPORT_SYMBOL_GPL(dw_spi_add_host);
1070 void dw_spi_remove_host(struct dw_spi *dws)
1075 spi_debugfs_remove(dws);
1077 if (dws->dma_ops && dws->dma_ops->dma_exit)
1078 dws->dma_ops->dma_exit(dws);
1080 spi_enable_chip(dws, 0);
1082 spi_set_clk(dws, 0);
1083 free_irq(dws->irq, dws);
1085 /* Disconnect from the SPI framework */
1086 spi_unregister_master(dws->master);
1089 DBG_SPI("%s:bus_num=%d\n",__func__, dws->bus_num);
1091 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
1093 int dw_spi_suspend_host(struct dw_spi *dws)
1097 ret = spi_master_suspend(dws->master);
1101 spi_enable_chip(dws, 0);
1102 spi_set_clk(dws, 0);
1104 clk_disable_unprepare(dws->clk_spi);
1106 DBG_SPI("%s:bus_num=%d\n",__func__, dws->bus_num);
1109 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
1111 int dw_spi_resume_host(struct dw_spi *dws)
1115 /* Enable the SPI clock */
1116 clk_prepare_enable(dws->clk_spi);
1120 /* Start the queue running */
1121 ret = spi_master_resume(dws->master);
1123 printk("%s:problem starting queue (%d)\n", __func__, ret);
1127 DBG_SPI("%s:bus_num=%d\n",__func__, dws->bus_num);
1130 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
1132 MODULE_AUTHOR("Luo Wei <lw@rock-chips.com>");
1133 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
1134 MODULE_LICENSE("GPL v2");