2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/ioport.h>
24 #include <linux/errno.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/spi/pxa2xx_spi.h>
29 #include <linux/spi/spi.h>
30 #include <linux/workqueue.h>
31 #include <linux/delay.h>
32 #include <linux/gpio.h>
33 #include <linux/slab.h>
34 #include <linux/clk.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/acpi.h>
40 #include <asm/delay.h>
42 #include "spi-pxa2xx.h"
44 MODULE_AUTHOR("Stephen Street");
45 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
46 MODULE_LICENSE("GPL");
47 MODULE_ALIAS("platform:pxa2xx-spi");
51 #define TIMOUT_DFLT 1000
54 * for testing SSCR1 changes that require SSP restart, basically
55 * everything except the service and interrupt enables, the pxa270 developer
56 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
57 * list, but the PXA255 dev man says all bits without really meaning the
58 * service and interrupt enables
60 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
61 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
62 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
63 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
64 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
65 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
67 #define LPSS_RX_THRESH_DFLT 64
68 #define LPSS_TX_LOTHRESH_DFLT 160
69 #define LPSS_TX_HITHRESH_DFLT 224
71 /* Offset from drv_data->lpss_base */
73 #define SPI_CS_CONTROL 0x18
74 #define SPI_CS_CONTROL_SW_MODE BIT(0)
75 #define SPI_CS_CONTROL_CS_HIGH BIT(1)
77 static bool is_lpss_ssp(const struct driver_data *drv_data)
79 return drv_data->ssp_type == LPSS_SSP;
83 * Read and write LPSS SSP private registers. Caller must first check that
84 * is_lpss_ssp() returns true before these can be called.
86 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
88 WARN_ON(!drv_data->lpss_base);
89 return readl(drv_data->lpss_base + offset);
92 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
93 unsigned offset, u32 value)
95 WARN_ON(!drv_data->lpss_base);
96 writel(value, drv_data->lpss_base + offset);
100 * lpss_ssp_setup - perform LPSS SSP specific setup
101 * @drv_data: pointer to the driver private data
103 * Perform LPSS SSP specific setup. This function must be called first if
104 * one is going to use LPSS SSP private registers.
106 static void lpss_ssp_setup(struct driver_data *drv_data)
108 unsigned offset = 0x400;
111 if (!is_lpss_ssp(drv_data))
115 * Perform auto-detection of the LPSS SSP private registers. They
116 * can be either at 1k or 2k offset from the base address.
118 orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
120 value = orig | SPI_CS_CONTROL_SW_MODE;
121 writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
122 value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
123 if (value != (orig | SPI_CS_CONTROL_SW_MODE)) {
128 value &= ~SPI_CS_CONTROL_SW_MODE;
129 writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
130 value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
137 /* Now set the LPSS base */
138 drv_data->lpss_base = drv_data->ioaddr + offset;
140 /* Enable software chip select control */
141 value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
142 __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
144 /* Enable multiblock DMA transfers */
145 if (drv_data->master_info->enable_dma)
146 __lpss_ssp_write_priv(drv_data, SSP_REG, 1);
149 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
153 if (!is_lpss_ssp(drv_data))
156 value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL);
158 value &= ~SPI_CS_CONTROL_CS_HIGH;
160 value |= SPI_CS_CONTROL_CS_HIGH;
161 __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
164 static void cs_assert(struct driver_data *drv_data)
166 struct chip_data *chip = drv_data->cur_chip;
168 if (drv_data->ssp_type == CE4100_SSP) {
169 write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
173 if (chip->cs_control) {
174 chip->cs_control(PXA2XX_CS_ASSERT);
178 if (gpio_is_valid(chip->gpio_cs)) {
179 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
183 lpss_ssp_cs_control(drv_data, true);
186 static void cs_deassert(struct driver_data *drv_data)
188 struct chip_data *chip = drv_data->cur_chip;
190 if (drv_data->ssp_type == CE4100_SSP)
193 if (chip->cs_control) {
194 chip->cs_control(PXA2XX_CS_DEASSERT);
198 if (gpio_is_valid(chip->gpio_cs)) {
199 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
203 lpss_ssp_cs_control(drv_data, false);
206 int pxa2xx_spi_flush(struct driver_data *drv_data)
208 unsigned long limit = loops_per_jiffy << 1;
210 void __iomem *reg = drv_data->ioaddr;
213 while (read_SSSR(reg) & SSSR_RNE) {
216 } while ((read_SSSR(reg) & SSSR_BSY) && --limit);
217 write_SSSR_CS(drv_data, SSSR_ROR);
222 static int null_writer(struct driver_data *drv_data)
224 void __iomem *reg = drv_data->ioaddr;
225 u8 n_bytes = drv_data->n_bytes;
227 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
228 || (drv_data->tx == drv_data->tx_end))
232 drv_data->tx += n_bytes;
237 static int null_reader(struct driver_data *drv_data)
239 void __iomem *reg = drv_data->ioaddr;
240 u8 n_bytes = drv_data->n_bytes;
242 while ((read_SSSR(reg) & SSSR_RNE)
243 && (drv_data->rx < drv_data->rx_end)) {
245 drv_data->rx += n_bytes;
248 return drv_data->rx == drv_data->rx_end;
251 static int u8_writer(struct driver_data *drv_data)
253 void __iomem *reg = drv_data->ioaddr;
255 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
256 || (drv_data->tx == drv_data->tx_end))
259 write_SSDR(*(u8 *)(drv_data->tx), reg);
265 static int u8_reader(struct driver_data *drv_data)
267 void __iomem *reg = drv_data->ioaddr;
269 while ((read_SSSR(reg) & SSSR_RNE)
270 && (drv_data->rx < drv_data->rx_end)) {
271 *(u8 *)(drv_data->rx) = read_SSDR(reg);
275 return drv_data->rx == drv_data->rx_end;
278 static int u16_writer(struct driver_data *drv_data)
280 void __iomem *reg = drv_data->ioaddr;
282 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
283 || (drv_data->tx == drv_data->tx_end))
286 write_SSDR(*(u16 *)(drv_data->tx), reg);
292 static int u16_reader(struct driver_data *drv_data)
294 void __iomem *reg = drv_data->ioaddr;
296 while ((read_SSSR(reg) & SSSR_RNE)
297 && (drv_data->rx < drv_data->rx_end)) {
298 *(u16 *)(drv_data->rx) = read_SSDR(reg);
302 return drv_data->rx == drv_data->rx_end;
305 static int u32_writer(struct driver_data *drv_data)
307 void __iomem *reg = drv_data->ioaddr;
309 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
310 || (drv_data->tx == drv_data->tx_end))
313 write_SSDR(*(u32 *)(drv_data->tx), reg);
319 static int u32_reader(struct driver_data *drv_data)
321 void __iomem *reg = drv_data->ioaddr;
323 while ((read_SSSR(reg) & SSSR_RNE)
324 && (drv_data->rx < drv_data->rx_end)) {
325 *(u32 *)(drv_data->rx) = read_SSDR(reg);
329 return drv_data->rx == drv_data->rx_end;
332 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
334 struct spi_message *msg = drv_data->cur_msg;
335 struct spi_transfer *trans = drv_data->cur_transfer;
337 /* Move to next transfer */
338 if (trans->transfer_list.next != &msg->transfers) {
339 drv_data->cur_transfer =
340 list_entry(trans->transfer_list.next,
343 return RUNNING_STATE;
348 /* caller already set message->status; dma and pio irqs are blocked */
349 static void giveback(struct driver_data *drv_data)
351 struct spi_transfer* last_transfer;
352 struct spi_message *msg;
354 msg = drv_data->cur_msg;
355 drv_data->cur_msg = NULL;
356 drv_data->cur_transfer = NULL;
358 last_transfer = list_entry(msg->transfers.prev,
362 /* Delay if requested before any change in chip select */
363 if (last_transfer->delay_usecs)
364 udelay(last_transfer->delay_usecs);
366 /* Drop chip select UNLESS cs_change is true or we are returning
367 * a message with an error, or next message is for another chip
369 if (!last_transfer->cs_change)
370 cs_deassert(drv_data);
372 struct spi_message *next_msg;
374 /* Holding of cs was hinted, but we need to make sure
375 * the next message is for the same chip. Don't waste
376 * time with the following tests unless this was hinted.
378 * We cannot postpone this until pump_messages, because
379 * after calling msg->complete (below) the driver that
380 * sent the current message could be unloaded, which
381 * could invalidate the cs_control() callback...
384 /* get a pointer to the next message, if any */
385 next_msg = spi_get_next_queued_message(drv_data->master);
387 /* see if the next and current messages point
390 if (next_msg && next_msg->spi != msg->spi)
392 if (!next_msg || msg->state == ERROR_STATE)
393 cs_deassert(drv_data);
396 drv_data->cur_chip = NULL;
397 spi_finalize_current_message(drv_data->master);
400 static void reset_sccr1(struct driver_data *drv_data)
402 void __iomem *reg = drv_data->ioaddr;
403 struct chip_data *chip = drv_data->cur_chip;
406 sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1;
407 sccr1_reg &= ~SSCR1_RFT;
408 sccr1_reg |= chip->threshold;
409 write_SSCR1(sccr1_reg, reg);
412 static void int_error_stop(struct driver_data *drv_data, const char* msg)
414 void __iomem *reg = drv_data->ioaddr;
416 /* Stop and reset SSP */
417 write_SSSR_CS(drv_data, drv_data->clear_sr);
418 reset_sccr1(drv_data);
419 if (!pxa25x_ssp_comp(drv_data))
421 pxa2xx_spi_flush(drv_data);
422 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
424 dev_err(&drv_data->pdev->dev, "%s\n", msg);
426 drv_data->cur_msg->state = ERROR_STATE;
427 tasklet_schedule(&drv_data->pump_transfers);
430 static void int_transfer_complete(struct driver_data *drv_data)
432 void __iomem *reg = drv_data->ioaddr;
435 write_SSSR_CS(drv_data, drv_data->clear_sr);
436 reset_sccr1(drv_data);
437 if (!pxa25x_ssp_comp(drv_data))
440 /* Update total byte transferred return count actual bytes read */
441 drv_data->cur_msg->actual_length += drv_data->len -
442 (drv_data->rx_end - drv_data->rx);
444 /* Transfer delays and chip select release are
445 * handled in pump_transfers or giveback
448 /* Move to next transfer */
449 drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
451 /* Schedule transfer tasklet */
452 tasklet_schedule(&drv_data->pump_transfers);
455 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
457 void __iomem *reg = drv_data->ioaddr;
459 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
460 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
462 u32 irq_status = read_SSSR(reg) & irq_mask;
464 if (irq_status & SSSR_ROR) {
465 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
469 if (irq_status & SSSR_TINT) {
470 write_SSSR(SSSR_TINT, reg);
471 if (drv_data->read(drv_data)) {
472 int_transfer_complete(drv_data);
477 /* Drain rx fifo, Fill tx fifo and prevent overruns */
479 if (drv_data->read(drv_data)) {
480 int_transfer_complete(drv_data);
483 } while (drv_data->write(drv_data));
485 if (drv_data->read(drv_data)) {
486 int_transfer_complete(drv_data);
490 if (drv_data->tx == drv_data->tx_end) {
494 sccr1_reg = read_SSCR1(reg);
495 sccr1_reg &= ~SSCR1_TIE;
498 * PXA25x_SSP has no timeout, set up rx threshould for the
499 * remaining RX bytes.
501 if (pxa25x_ssp_comp(drv_data)) {
503 sccr1_reg &= ~SSCR1_RFT;
505 bytes_left = drv_data->rx_end - drv_data->rx;
506 switch (drv_data->n_bytes) {
513 if (bytes_left > RX_THRESH_DFLT)
514 bytes_left = RX_THRESH_DFLT;
516 sccr1_reg |= SSCR1_RxTresh(bytes_left);
518 write_SSCR1(sccr1_reg, reg);
521 /* We did something */
525 static irqreturn_t ssp_int(int irq, void *dev_id)
527 struct driver_data *drv_data = dev_id;
528 void __iomem *reg = drv_data->ioaddr;
530 u32 mask = drv_data->mask_sr;
534 * The IRQ might be shared with other peripherals so we must first
535 * check that are we RPM suspended or not. If we are we assume that
536 * the IRQ was not for us (we shouldn't be RPM suspended when the
537 * interrupt is enabled).
539 if (pm_runtime_suspended(&drv_data->pdev->dev))
542 sccr1_reg = read_SSCR1(reg);
543 status = read_SSSR(reg);
545 /* Ignore possible writes if we don't need to write */
546 if (!(sccr1_reg & SSCR1_TIE))
549 /* Ignore RX timeout interrupt if it is disabled */
550 if (!(sccr1_reg & SSCR1_TINTE))
553 if (!(status & mask))
556 if (!drv_data->cur_msg) {
558 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
559 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
560 if (!pxa25x_ssp_comp(drv_data))
562 write_SSSR_CS(drv_data, drv_data->clear_sr);
564 dev_err(&drv_data->pdev->dev, "bad message state "
565 "in interrupt handler\n");
571 return drv_data->transfer_handler(drv_data);
574 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
576 unsigned long ssp_clk = drv_data->max_clk_rate;
577 const struct ssp_device *ssp = drv_data->ssp;
579 rate = min_t(int, ssp_clk, rate);
581 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
582 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
584 return ((ssp_clk / rate - 1) & 0xfff) << 8;
587 static void pump_transfers(unsigned long data)
589 struct driver_data *drv_data = (struct driver_data *)data;
590 struct spi_message *message = NULL;
591 struct spi_transfer *transfer = NULL;
592 struct spi_transfer *previous = NULL;
593 struct chip_data *chip = NULL;
594 void __iomem *reg = drv_data->ioaddr;
600 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
601 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
603 /* Get current state information */
604 message = drv_data->cur_msg;
605 transfer = drv_data->cur_transfer;
606 chip = drv_data->cur_chip;
608 /* Handle for abort */
609 if (message->state == ERROR_STATE) {
610 message->status = -EIO;
615 /* Handle end of message */
616 if (message->state == DONE_STATE) {
622 /* Delay if requested at end of transfer before CS change */
623 if (message->state == RUNNING_STATE) {
624 previous = list_entry(transfer->transfer_list.prev,
627 if (previous->delay_usecs)
628 udelay(previous->delay_usecs);
630 /* Drop chip select only if cs_change is requested */
631 if (previous->cs_change)
632 cs_deassert(drv_data);
635 /* Check if we can DMA this transfer */
636 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
638 /* reject already-mapped transfers; PIO won't always work */
639 if (message->is_dma_mapped
640 || transfer->rx_dma || transfer->tx_dma) {
641 dev_err(&drv_data->pdev->dev,
642 "pump_transfers: mapped transfer length "
643 "of %u is greater than %d\n",
644 transfer->len, MAX_DMA_LEN);
645 message->status = -EINVAL;
650 /* warn ... we force this to PIO mode */
651 if (printk_ratelimit())
652 dev_warn(&message->spi->dev, "pump_transfers: "
653 "DMA disabled for transfer length %ld "
655 (long)drv_data->len, MAX_DMA_LEN);
658 /* Setup the transfer state based on the type of transfer */
659 if (pxa2xx_spi_flush(drv_data) == 0) {
660 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
661 message->status = -EIO;
665 drv_data->n_bytes = chip->n_bytes;
666 drv_data->tx = (void *)transfer->tx_buf;
667 drv_data->tx_end = drv_data->tx + transfer->len;
668 drv_data->rx = transfer->rx_buf;
669 drv_data->rx_end = drv_data->rx + transfer->len;
670 drv_data->rx_dma = transfer->rx_dma;
671 drv_data->tx_dma = transfer->tx_dma;
672 drv_data->len = transfer->len;
673 drv_data->write = drv_data->tx ? chip->write : null_writer;
674 drv_data->read = drv_data->rx ? chip->read : null_reader;
676 /* Change speed and bit per word on a per transfer */
678 if (transfer->speed_hz || transfer->bits_per_word) {
680 bits = chip->bits_per_word;
681 speed = chip->speed_hz;
683 if (transfer->speed_hz)
684 speed = transfer->speed_hz;
686 if (transfer->bits_per_word)
687 bits = transfer->bits_per_word;
689 clk_div = ssp_get_clk_div(drv_data, speed);
692 drv_data->n_bytes = 1;
693 drv_data->read = drv_data->read != null_reader ?
694 u8_reader : null_reader;
695 drv_data->write = drv_data->write != null_writer ?
696 u8_writer : null_writer;
697 } else if (bits <= 16) {
698 drv_data->n_bytes = 2;
699 drv_data->read = drv_data->read != null_reader ?
700 u16_reader : null_reader;
701 drv_data->write = drv_data->write != null_writer ?
702 u16_writer : null_writer;
703 } else if (bits <= 32) {
704 drv_data->n_bytes = 4;
705 drv_data->read = drv_data->read != null_reader ?
706 u32_reader : null_reader;
707 drv_data->write = drv_data->write != null_writer ?
708 u32_writer : null_writer;
710 /* if bits/word is changed in dma mode, then must check the
711 * thresholds and burst also */
712 if (chip->enable_dma) {
713 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
717 if (printk_ratelimit())
718 dev_warn(&message->spi->dev,
720 "DMA burst size reduced to "
721 "match bits_per_word\n");
726 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
728 | (bits > 16 ? SSCR0_EDSS : 0);
731 message->state = RUNNING_STATE;
733 drv_data->dma_mapped = 0;
734 if (pxa2xx_spi_dma_is_possible(drv_data->len))
735 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
736 if (drv_data->dma_mapped) {
738 /* Ensure we have the correct interrupt handler */
739 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
741 pxa2xx_spi_dma_prepare(drv_data, dma_burst);
743 /* Clear status and start DMA engine */
744 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
745 write_SSSR(drv_data->clear_sr, reg);
747 pxa2xx_spi_dma_start(drv_data);
749 /* Ensure we have the correct interrupt handler */
750 drv_data->transfer_handler = interrupt_transfer;
753 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
754 write_SSSR_CS(drv_data, drv_data->clear_sr);
757 if (is_lpss_ssp(drv_data)) {
758 if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold)
759 write_SSIRF(chip->lpss_rx_threshold, reg);
760 if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold)
761 write_SSITF(chip->lpss_tx_threshold, reg);
764 /* see if we need to reload the config registers */
765 if ((read_SSCR0(reg) != cr0)
766 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
767 (cr1 & SSCR1_CHANGE_MASK)) {
769 /* stop the SSP, and update the other bits */
770 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
771 if (!pxa25x_ssp_comp(drv_data))
772 write_SSTO(chip->timeout, reg);
773 /* first set CR1 without interrupt and service enables */
774 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
775 /* restart the SSP */
776 write_SSCR0(cr0, reg);
779 if (!pxa25x_ssp_comp(drv_data))
780 write_SSTO(chip->timeout, reg);
785 /* after chip select, release the data by enabling service
786 * requests and interrupts, without changing any mode bits */
787 write_SSCR1(cr1, reg);
790 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
791 struct spi_message *msg)
793 struct driver_data *drv_data = spi_master_get_devdata(master);
795 drv_data->cur_msg = msg;
796 /* Initial message state*/
797 drv_data->cur_msg->state = START_STATE;
798 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
802 /* prepare to setup the SSP, in pump_transfers, using the per
803 * chip configuration */
804 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
806 /* Mark as busy and launch transfers */
807 tasklet_schedule(&drv_data->pump_transfers);
811 static int pxa2xx_spi_prepare_transfer(struct spi_master *master)
813 struct driver_data *drv_data = spi_master_get_devdata(master);
815 pm_runtime_get_sync(&drv_data->pdev->dev);
819 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
821 struct driver_data *drv_data = spi_master_get_devdata(master);
823 /* Disable the SSP now */
824 write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE,
827 pm_runtime_mark_last_busy(&drv_data->pdev->dev);
828 pm_runtime_put_autosuspend(&drv_data->pdev->dev);
832 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
833 struct pxa2xx_spi_chip *chip_info)
837 if (chip == NULL || chip_info == NULL)
840 /* NOTE: setup() can be called multiple times, possibly with
841 * different chip_info, release previously requested GPIO
843 if (gpio_is_valid(chip->gpio_cs))
844 gpio_free(chip->gpio_cs);
846 /* If (*cs_control) is provided, ignore GPIO chip select */
847 if (chip_info->cs_control) {
848 chip->cs_control = chip_info->cs_control;
852 if (gpio_is_valid(chip_info->gpio_cs)) {
853 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
855 dev_err(&spi->dev, "failed to request chip select "
856 "GPIO%d\n", chip_info->gpio_cs);
860 chip->gpio_cs = chip_info->gpio_cs;
861 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
863 err = gpio_direction_output(chip->gpio_cs,
864 !chip->gpio_cs_inverted);
870 static int setup(struct spi_device *spi)
872 struct pxa2xx_spi_chip *chip_info = NULL;
873 struct chip_data *chip;
874 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
875 unsigned int clk_div;
876 uint tx_thres, tx_hi_thres, rx_thres;
878 if (is_lpss_ssp(drv_data)) {
879 tx_thres = LPSS_TX_LOTHRESH_DFLT;
880 tx_hi_thres = LPSS_TX_HITHRESH_DFLT;
881 rx_thres = LPSS_RX_THRESH_DFLT;
883 tx_thres = TX_THRESH_DFLT;
885 rx_thres = RX_THRESH_DFLT;
888 if (!pxa25x_ssp_comp(drv_data)
889 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
890 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
891 "b/w not 4-32 for type non-PXA25x_SSP\n",
892 drv_data->ssp_type, spi->bits_per_word);
894 } else if (pxa25x_ssp_comp(drv_data)
895 && (spi->bits_per_word < 4
896 || spi->bits_per_word > 16)) {
897 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
898 "b/w not 4-16 for type PXA25x_SSP\n",
899 drv_data->ssp_type, spi->bits_per_word);
903 /* Only alloc on first setup */
904 chip = spi_get_ctldata(spi);
906 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
909 "failed setup: can't allocate chip data\n");
913 if (drv_data->ssp_type == CE4100_SSP) {
914 if (spi->chip_select > 4) {
915 dev_err(&spi->dev, "failed setup: "
916 "cs number must not be > 4.\n");
921 chip->frm = spi->chip_select;
924 chip->enable_dma = 0;
925 chip->timeout = TIMOUT_DFLT;
928 /* protocol drivers may change the chip settings, so...
929 * if chip_info exists, use it */
930 chip_info = spi->controller_data;
932 /* chip_info isn't always needed */
935 if (chip_info->timeout)
936 chip->timeout = chip_info->timeout;
937 if (chip_info->tx_threshold)
938 tx_thres = chip_info->tx_threshold;
939 if (chip_info->tx_hi_threshold)
940 tx_hi_thres = chip_info->tx_hi_threshold;
941 if (chip_info->rx_threshold)
942 rx_thres = chip_info->rx_threshold;
943 chip->enable_dma = drv_data->master_info->enable_dma;
944 chip->dma_threshold = 0;
945 if (chip_info->enable_loopback)
946 chip->cr1 = SSCR1_LBM;
947 } else if (ACPI_HANDLE(&spi->dev)) {
949 * Slave devices enumerated from ACPI namespace don't
950 * usually have chip_info but we still might want to use
953 chip->enable_dma = drv_data->master_info->enable_dma;
956 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
957 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
959 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
960 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
961 | SSITF_TxHiThresh(tx_hi_thres);
963 /* set dma burst and threshold outside of chip_info path so that if
964 * chip_info goes away after setting chip->enable_dma, the
965 * burst and threshold can still respond to changes in bits_per_word */
966 if (chip->enable_dma) {
967 /* set up legal burst and threshold for dma */
968 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
970 &chip->dma_burst_size,
971 &chip->dma_threshold)) {
972 dev_warn(&spi->dev, "in setup: DMA burst size reduced "
973 "to match bits_per_word\n");
977 clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz);
978 chip->speed_hz = spi->max_speed_hz;
982 | SSCR0_DataSize(spi->bits_per_word > 16 ?
983 spi->bits_per_word - 16 : spi->bits_per_word)
985 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
986 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
987 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
988 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
990 if (spi->mode & SPI_LOOP)
991 chip->cr1 |= SSCR1_LBM;
993 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
994 if (!pxa25x_ssp_comp(drv_data))
995 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
996 drv_data->max_clk_rate
997 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
998 chip->enable_dma ? "DMA" : "PIO");
1000 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1001 drv_data->max_clk_rate / 2
1002 / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1003 chip->enable_dma ? "DMA" : "PIO");
1005 if (spi->bits_per_word <= 8) {
1007 chip->read = u8_reader;
1008 chip->write = u8_writer;
1009 } else if (spi->bits_per_word <= 16) {
1011 chip->read = u16_reader;
1012 chip->write = u16_writer;
1013 } else if (spi->bits_per_word <= 32) {
1014 chip->cr0 |= SSCR0_EDSS;
1016 chip->read = u32_reader;
1017 chip->write = u32_writer;
1019 dev_err(&spi->dev, "invalid wordsize\n");
1022 chip->bits_per_word = spi->bits_per_word;
1024 spi_set_ctldata(spi, chip);
1026 if (drv_data->ssp_type == CE4100_SSP)
1029 return setup_cs(spi, chip, chip_info);
1032 static void cleanup(struct spi_device *spi)
1034 struct chip_data *chip = spi_get_ctldata(spi);
1035 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1040 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1041 gpio_free(chip->gpio_cs);
1047 static int pxa2xx_spi_acpi_add_dma(struct acpi_resource *res, void *data)
1049 struct pxa2xx_spi_master *pdata = data;
1051 if (res->type == ACPI_RESOURCE_TYPE_FIXED_DMA) {
1052 const struct acpi_resource_fixed_dma *dma;
1054 dma = &res->data.fixed_dma;
1055 if (pdata->tx_slave_id < 0) {
1056 pdata->tx_slave_id = dma->request_lines;
1057 pdata->tx_chan_id = dma->channels;
1058 } else if (pdata->rx_slave_id < 0) {
1059 pdata->rx_slave_id = dma->request_lines;
1060 pdata->rx_chan_id = dma->channels;
1064 /* Tell the ACPI core to skip this resource */
1068 static struct pxa2xx_spi_master *
1069 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1071 struct pxa2xx_spi_master *pdata;
1072 struct list_head resource_list;
1073 struct acpi_device *adev;
1074 struct ssp_device *ssp;
1075 struct resource *res;
1078 if (!ACPI_HANDLE(&pdev->dev) ||
1079 acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
1082 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1085 "failed to allocate memory for platform data\n");
1089 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1095 ssp->phys_base = res->start;
1096 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1097 if (IS_ERR(ssp->mmio_base))
1098 return PTR_ERR(ssp->mmio_base);
1100 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1101 ssp->irq = platform_get_irq(pdev, 0);
1102 ssp->type = LPSS_SSP;
1106 if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid))
1107 ssp->port_id = devid;
1109 pdata->num_chipselect = 1;
1110 pdata->rx_slave_id = -1;
1111 pdata->tx_slave_id = -1;
1113 INIT_LIST_HEAD(&resource_list);
1114 acpi_dev_get_resources(adev, &resource_list, pxa2xx_spi_acpi_add_dma,
1116 acpi_dev_free_resource_list(&resource_list);
1118 pdata->enable_dma = pdata->rx_slave_id >= 0 && pdata->tx_slave_id >= 0;
1123 static struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1128 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1130 static inline struct pxa2xx_spi_master *
1131 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1137 static int pxa2xx_spi_probe(struct platform_device *pdev)
1139 struct device *dev = &pdev->dev;
1140 struct pxa2xx_spi_master *platform_info;
1141 struct spi_master *master;
1142 struct driver_data *drv_data;
1143 struct ssp_device *ssp;
1146 platform_info = dev_get_platdata(dev);
1147 if (!platform_info) {
1148 platform_info = pxa2xx_spi_acpi_get_pdata(pdev);
1149 if (!platform_info) {
1150 dev_err(&pdev->dev, "missing platform data\n");
1155 ssp = pxa_ssp_request(pdev->id, pdev->name);
1157 ssp = &platform_info->ssp;
1159 if (!ssp->mmio_base) {
1160 dev_err(&pdev->dev, "failed to get ssp\n");
1164 /* Allocate master with space for drv_data and null dma buffer */
1165 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1167 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1171 drv_data = spi_master_get_devdata(master);
1172 drv_data->master = master;
1173 drv_data->master_info = platform_info;
1174 drv_data->pdev = pdev;
1175 drv_data->ssp = ssp;
1177 master->dev.parent = &pdev->dev;
1178 master->dev.of_node = pdev->dev.of_node;
1179 /* the spi->mode bits understood by this driver: */
1180 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1182 master->bus_num = ssp->port_id;
1183 master->num_chipselect = platform_info->num_chipselect;
1184 master->dma_alignment = DMA_ALIGNMENT;
1185 master->cleanup = cleanup;
1186 master->setup = setup;
1187 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1188 master->prepare_transfer_hardware = pxa2xx_spi_prepare_transfer;
1189 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1191 drv_data->ssp_type = ssp->type;
1192 drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT);
1194 drv_data->ioaddr = ssp->mmio_base;
1195 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1196 if (pxa25x_ssp_comp(drv_data)) {
1197 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1198 drv_data->dma_cr1 = 0;
1199 drv_data->clear_sr = SSSR_ROR;
1200 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1202 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1203 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1204 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1205 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1208 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1211 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1212 goto out_error_master_alloc;
1215 /* Setup DMA if requested */
1216 drv_data->tx_channel = -1;
1217 drv_data->rx_channel = -1;
1218 if (platform_info->enable_dma) {
1219 status = pxa2xx_spi_dma_setup(drv_data);
1221 dev_warn(dev, "failed to setup DMA, using PIO\n");
1222 platform_info->enable_dma = false;
1226 /* Enable SOC clock */
1227 clk_prepare_enable(ssp->clk);
1229 drv_data->max_clk_rate = clk_get_rate(ssp->clk);
1231 /* Load default SSP configuration */
1232 write_SSCR0(0, drv_data->ioaddr);
1233 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1234 SSCR1_TxTresh(TX_THRESH_DFLT),
1236 write_SSCR0(SSCR0_SCR(2)
1238 | SSCR0_DataSize(8),
1240 if (!pxa25x_ssp_comp(drv_data))
1241 write_SSTO(0, drv_data->ioaddr);
1242 write_SSPSP(0, drv_data->ioaddr);
1244 lpss_ssp_setup(drv_data);
1246 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1247 (unsigned long)drv_data);
1249 /* Register with the SPI framework */
1250 platform_set_drvdata(pdev, drv_data);
1251 status = spi_register_master(master);
1253 dev_err(&pdev->dev, "problem registering spi master\n");
1254 goto out_error_clock_enabled;
1257 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1258 pm_runtime_use_autosuspend(&pdev->dev);
1259 pm_runtime_set_active(&pdev->dev);
1260 pm_runtime_enable(&pdev->dev);
1264 out_error_clock_enabled:
1265 clk_disable_unprepare(ssp->clk);
1266 pxa2xx_spi_dma_release(drv_data);
1267 free_irq(ssp->irq, drv_data);
1269 out_error_master_alloc:
1270 spi_master_put(master);
1275 static int pxa2xx_spi_remove(struct platform_device *pdev)
1277 struct driver_data *drv_data = platform_get_drvdata(pdev);
1278 struct ssp_device *ssp;
1282 ssp = drv_data->ssp;
1284 pm_runtime_get_sync(&pdev->dev);
1286 /* Disable the SSP at the peripheral and SOC level */
1287 write_SSCR0(0, drv_data->ioaddr);
1288 clk_disable_unprepare(ssp->clk);
1291 if (drv_data->master_info->enable_dma)
1292 pxa2xx_spi_dma_release(drv_data);
1294 pm_runtime_put_noidle(&pdev->dev);
1295 pm_runtime_disable(&pdev->dev);
1298 free_irq(ssp->irq, drv_data);
1303 /* Disconnect from the SPI framework */
1304 spi_unregister_master(drv_data->master);
1306 /* Prevent double remove */
1307 platform_set_drvdata(pdev, NULL);
1312 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1316 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1317 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1321 static int pxa2xx_spi_suspend(struct device *dev)
1323 struct driver_data *drv_data = dev_get_drvdata(dev);
1324 struct ssp_device *ssp = drv_data->ssp;
1327 status = spi_master_suspend(drv_data->master);
1330 write_SSCR0(0, drv_data->ioaddr);
1332 if (!pm_runtime_suspended(dev))
1333 clk_disable_unprepare(ssp->clk);
1338 static int pxa2xx_spi_resume(struct device *dev)
1340 struct driver_data *drv_data = dev_get_drvdata(dev);
1341 struct ssp_device *ssp = drv_data->ssp;
1344 pxa2xx_spi_dma_resume(drv_data);
1346 /* Enable the SSP clock */
1347 if (!pm_runtime_suspended(dev))
1348 clk_prepare_enable(ssp->clk);
1350 /* Start the queue running */
1351 status = spi_master_resume(drv_data->master);
1353 dev_err(dev, "problem starting queue (%d)\n", status);
1361 #ifdef CONFIG_PM_RUNTIME
1362 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1364 struct driver_data *drv_data = dev_get_drvdata(dev);
1366 clk_disable_unprepare(drv_data->ssp->clk);
1370 static int pxa2xx_spi_runtime_resume(struct device *dev)
1372 struct driver_data *drv_data = dev_get_drvdata(dev);
1374 clk_prepare_enable(drv_data->ssp->clk);
1379 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1380 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1381 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1382 pxa2xx_spi_runtime_resume, NULL)
1385 static struct platform_driver driver = {
1387 .name = "pxa2xx-spi",
1388 .owner = THIS_MODULE,
1389 .pm = &pxa2xx_spi_pm_ops,
1390 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1392 .probe = pxa2xx_spi_probe,
1393 .remove = pxa2xx_spi_remove,
1394 .shutdown = pxa2xx_spi_shutdown,
1397 static int __init pxa2xx_spi_init(void)
1399 return platform_driver_register(&driver);
1401 subsys_initcall(pxa2xx_spi_init);
1403 static void __exit pxa2xx_spi_exit(void)
1405 platform_driver_unregister(&driver);
1407 module_exit(pxa2xx_spi_exit);